170c6cce0SQiao Zhou /*
270c6cce0SQiao Zhou * Base driver for Marvell 88PM805
370c6cce0SQiao Zhou *
470c6cce0SQiao Zhou * Copyright (C) 2012 Marvell International Ltd.
570c6cce0SQiao Zhou * Haojian Zhuang <haojian.zhuang@marvell.com>
670c6cce0SQiao Zhou * Joseph(Yossi) Hanin <yhanin@marvell.com>
770c6cce0SQiao Zhou * Qiao Zhou <zhouqiao@marvell.com>
870c6cce0SQiao Zhou *
970c6cce0SQiao Zhou * This file is subject to the terms and conditions of the GNU General
1070c6cce0SQiao Zhou * Public License. See the file "COPYING" in the main directory of this
1170c6cce0SQiao Zhou * archive for more details.
1270c6cce0SQiao Zhou *
1370c6cce0SQiao Zhou * This program is distributed in the hope that it will be useful,
1470c6cce0SQiao Zhou * but WITHOUT ANY WARRANTY; without even the implied warranty of
1570c6cce0SQiao Zhou * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1670c6cce0SQiao Zhou * GNU General Public License for more details.
1770c6cce0SQiao Zhou *
1870c6cce0SQiao Zhou * You should have received a copy of the GNU General Public License
1970c6cce0SQiao Zhou * along with this program; if not, write to the Free Software
2070c6cce0SQiao Zhou * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2170c6cce0SQiao Zhou */
2270c6cce0SQiao Zhou
2370c6cce0SQiao Zhou #include <linux/kernel.h>
2470c6cce0SQiao Zhou #include <linux/module.h>
2570c6cce0SQiao Zhou #include <linux/i2c.h>
2670c6cce0SQiao Zhou #include <linux/irq.h>
2770c6cce0SQiao Zhou #include <linux/mfd/core.h>
2870c6cce0SQiao Zhou #include <linux/mfd/88pm80x.h>
2970c6cce0SQiao Zhou #include <linux/slab.h>
3070c6cce0SQiao Zhou #include <linux/delay.h>
3170c6cce0SQiao Zhou
3270c6cce0SQiao Zhou static const struct i2c_device_id pm80x_id_table[] = {
3303dcc544SChao Xie {"88PM805", 0},
3431b3ffbdSSamuel Ortiz {} /* NULL terminated */
3570c6cce0SQiao Zhou };
3670c6cce0SQiao Zhou MODULE_DEVICE_TABLE(i2c, pm80x_id_table);
3770c6cce0SQiao Zhou
3870c6cce0SQiao Zhou /* Interrupt Number in 88PM805 */
3970c6cce0SQiao Zhou enum {
4070c6cce0SQiao Zhou PM805_IRQ_LDO_OFF, /*0 */
4170c6cce0SQiao Zhou PM805_IRQ_SRC_DPLL_LOCK, /*1 */
4270c6cce0SQiao Zhou PM805_IRQ_CLIP_FAULT,
4370c6cce0SQiao Zhou PM805_IRQ_MIC_CONFLICT,
4470c6cce0SQiao Zhou PM805_IRQ_HP2_SHRT,
4570c6cce0SQiao Zhou PM805_IRQ_HP1_SHRT, /*5 */
4670c6cce0SQiao Zhou PM805_IRQ_FINE_PLL_FAULT,
4770c6cce0SQiao Zhou PM805_IRQ_RAW_PLL_FAULT,
4870c6cce0SQiao Zhou PM805_IRQ_VOLP_BTN_DET,
4970c6cce0SQiao Zhou PM805_IRQ_VOLM_BTN_DET,
5070c6cce0SQiao Zhou PM805_IRQ_SHRT_BTN_DET, /*10 */
5170c6cce0SQiao Zhou PM805_IRQ_MIC_DET, /*11 */
5270c6cce0SQiao Zhou
5370c6cce0SQiao Zhou PM805_MAX_IRQ,
5470c6cce0SQiao Zhou };
5570c6cce0SQiao Zhou
5670c6cce0SQiao Zhou static struct resource codec_resources[] = {
5770c6cce0SQiao Zhou /* Headset microphone insertion or removal */
58ba4672adSZhen Lei DEFINE_RES_IRQ_NAMED(PM805_IRQ_MIC_DET, "micin"),
59ba4672adSZhen Lei
6070c6cce0SQiao Zhou /* Audio short HP1 */
61ba4672adSZhen Lei DEFINE_RES_IRQ_NAMED(PM805_IRQ_HP1_SHRT, "audio-short1"),
62ba4672adSZhen Lei
6370c6cce0SQiao Zhou /* Audio short HP2 */
64ba4672adSZhen Lei DEFINE_RES_IRQ_NAMED(PM805_IRQ_HP2_SHRT, "audio-short2"),
6570c6cce0SQiao Zhou };
6670c6cce0SQiao Zhou
6704e02417SGeert Uytterhoeven static const struct mfd_cell codec_devs[] = {
6870c6cce0SQiao Zhou {
6970c6cce0SQiao Zhou .name = "88pm80x-codec",
7070c6cce0SQiao Zhou .num_resources = ARRAY_SIZE(codec_resources),
7170c6cce0SQiao Zhou .resources = &codec_resources[0],
7270c6cce0SQiao Zhou .id = -1,
7370c6cce0SQiao Zhou },
7470c6cce0SQiao Zhou };
7570c6cce0SQiao Zhou
7670c6cce0SQiao Zhou static struct regmap_irq pm805_irqs[] = {
7770c6cce0SQiao Zhou /* INT0 */
7870c6cce0SQiao Zhou [PM805_IRQ_LDO_OFF] = {
7970c6cce0SQiao Zhou .mask = PM805_INT1_HP1_SHRT,
8070c6cce0SQiao Zhou },
8170c6cce0SQiao Zhou [PM805_IRQ_SRC_DPLL_LOCK] = {
8270c6cce0SQiao Zhou .mask = PM805_INT1_HP2_SHRT,
8370c6cce0SQiao Zhou },
8470c6cce0SQiao Zhou [PM805_IRQ_CLIP_FAULT] = {
8570c6cce0SQiao Zhou .mask = PM805_INT1_MIC_CONFLICT,
8670c6cce0SQiao Zhou },
8770c6cce0SQiao Zhou [PM805_IRQ_MIC_CONFLICT] = {
8870c6cce0SQiao Zhou .mask = PM805_INT1_CLIP_FAULT,
8970c6cce0SQiao Zhou },
9070c6cce0SQiao Zhou [PM805_IRQ_HP2_SHRT] = {
9170c6cce0SQiao Zhou .mask = PM805_INT1_LDO_OFF,
9270c6cce0SQiao Zhou },
9370c6cce0SQiao Zhou [PM805_IRQ_HP1_SHRT] = {
9470c6cce0SQiao Zhou .mask = PM805_INT1_SRC_DPLL_LOCK,
9570c6cce0SQiao Zhou },
9670c6cce0SQiao Zhou /* INT1 */
9770c6cce0SQiao Zhou [PM805_IRQ_FINE_PLL_FAULT] = {
9870c6cce0SQiao Zhou .reg_offset = 1,
9970c6cce0SQiao Zhou .mask = PM805_INT2_MIC_DET,
10070c6cce0SQiao Zhou },
10170c6cce0SQiao Zhou [PM805_IRQ_RAW_PLL_FAULT] = {
10270c6cce0SQiao Zhou .reg_offset = 1,
10370c6cce0SQiao Zhou .mask = PM805_INT2_SHRT_BTN_DET,
10470c6cce0SQiao Zhou },
10570c6cce0SQiao Zhou [PM805_IRQ_VOLP_BTN_DET] = {
10670c6cce0SQiao Zhou .reg_offset = 1,
10770c6cce0SQiao Zhou .mask = PM805_INT2_VOLM_BTN_DET,
10870c6cce0SQiao Zhou },
10970c6cce0SQiao Zhou [PM805_IRQ_VOLM_BTN_DET] = {
11070c6cce0SQiao Zhou .reg_offset = 1,
11170c6cce0SQiao Zhou .mask = PM805_INT2_VOLP_BTN_DET,
11270c6cce0SQiao Zhou },
11370c6cce0SQiao Zhou [PM805_IRQ_SHRT_BTN_DET] = {
11470c6cce0SQiao Zhou .reg_offset = 1,
11570c6cce0SQiao Zhou .mask = PM805_INT2_RAW_PLL_FAULT,
11670c6cce0SQiao Zhou },
11770c6cce0SQiao Zhou [PM805_IRQ_MIC_DET] = {
11870c6cce0SQiao Zhou .reg_offset = 1,
11970c6cce0SQiao Zhou .mask = PM805_INT2_FINE_PLL_FAULT,
12070c6cce0SQiao Zhou },
12170c6cce0SQiao Zhou };
12270c6cce0SQiao Zhou
device_irq_init_805(struct pm80x_chip * chip)123f791be49SBill Pemberton static int device_irq_init_805(struct pm80x_chip *chip)
12470c6cce0SQiao Zhou {
12570c6cce0SQiao Zhou struct regmap *map = chip->regmap;
1261ef5677eSYi Zhang unsigned long flags = IRQF_ONESHOT;
12770c6cce0SQiao Zhou int data, mask, ret = -EINVAL;
12870c6cce0SQiao Zhou
12970c6cce0SQiao Zhou if (!map || !chip->irq) {
13070c6cce0SQiao Zhou dev_err(chip->dev, "incorrect parameters\n");
13170c6cce0SQiao Zhou return -EINVAL;
13270c6cce0SQiao Zhou }
13370c6cce0SQiao Zhou
13470c6cce0SQiao Zhou /*
13570c6cce0SQiao Zhou * irq_mode defines the way of clearing interrupt. it's read-clear by
13670c6cce0SQiao Zhou * default.
13770c6cce0SQiao Zhou */
13870c6cce0SQiao Zhou mask =
13970c6cce0SQiao Zhou PM805_STATUS0_INT_CLEAR | PM805_STATUS0_INV_INT |
14070c6cce0SQiao Zhou PM800_STATUS0_INT_MASK;
14170c6cce0SQiao Zhou
14270c6cce0SQiao Zhou data = PM805_STATUS0_INT_CLEAR;
14370c6cce0SQiao Zhou ret = regmap_update_bits(map, PM805_INT_STATUS0, mask, data);
14470c6cce0SQiao Zhou /*
14570c6cce0SQiao Zhou * PM805_INT_STATUS is under 32K clock domain, so need to
14670c6cce0SQiao Zhou * add proper delay before the next I2C register access.
14770c6cce0SQiao Zhou */
148dc543929SLee Jones usleep_range(1000, 3000);
14970c6cce0SQiao Zhou
15070c6cce0SQiao Zhou if (ret < 0)
15170c6cce0SQiao Zhou goto out;
15270c6cce0SQiao Zhou
15370c6cce0SQiao Zhou ret =
15470c6cce0SQiao Zhou regmap_add_irq_chip(chip->regmap, chip->irq, flags, -1,
15570c6cce0SQiao Zhou chip->regmap_irq_chip, &chip->irq_data);
15670c6cce0SQiao Zhou
15770c6cce0SQiao Zhou out:
15870c6cce0SQiao Zhou return ret;
15970c6cce0SQiao Zhou }
16070c6cce0SQiao Zhou
device_irq_exit_805(struct pm80x_chip * chip)16170c6cce0SQiao Zhou static void device_irq_exit_805(struct pm80x_chip *chip)
16270c6cce0SQiao Zhou {
16370c6cce0SQiao Zhou regmap_del_irq_chip(chip->irq, chip->irq_data);
16470c6cce0SQiao Zhou }
16570c6cce0SQiao Zhou
16670c6cce0SQiao Zhou static struct regmap_irq_chip pm805_irq_chip = {
16770c6cce0SQiao Zhou .name = "88pm805",
16870c6cce0SQiao Zhou .irqs = pm805_irqs,
16970c6cce0SQiao Zhou .num_irqs = ARRAY_SIZE(pm805_irqs),
17070c6cce0SQiao Zhou
17170c6cce0SQiao Zhou .num_regs = 2,
17270c6cce0SQiao Zhou .status_base = PM805_INT_STATUS1,
17370c6cce0SQiao Zhou .mask_base = PM805_INT_MASK1,
17470c6cce0SQiao Zhou .ack_base = PM805_INT_STATUS1,
17570c6cce0SQiao Zhou };
17670c6cce0SQiao Zhou
device_805_init(struct pm80x_chip * chip)177f791be49SBill Pemberton static int device_805_init(struct pm80x_chip *chip)
17870c6cce0SQiao Zhou {
17970c6cce0SQiao Zhou int ret = 0;
18070c6cce0SQiao Zhou struct regmap *map = chip->regmap;
18170c6cce0SQiao Zhou
18270c6cce0SQiao Zhou if (!map) {
18370c6cce0SQiao Zhou dev_err(chip->dev, "regmap is invalid\n");
18470c6cce0SQiao Zhou return -EINVAL;
18570c6cce0SQiao Zhou }
18670c6cce0SQiao Zhou
18770c6cce0SQiao Zhou chip->regmap_irq_chip = &pm805_irq_chip;
18870c6cce0SQiao Zhou
18970c6cce0SQiao Zhou ret = device_irq_init_805(chip);
19070c6cce0SQiao Zhou if (ret < 0) {
19170c6cce0SQiao Zhou dev_err(chip->dev, "Failed to init pm805 irq!\n");
19270c6cce0SQiao Zhou goto out_irq_init;
19370c6cce0SQiao Zhou }
19470c6cce0SQiao Zhou
19570c6cce0SQiao Zhou ret = mfd_add_devices(chip->dev, 0, &codec_devs[0],
1960848c94fSMark Brown ARRAY_SIZE(codec_devs), &codec_resources[0], 0,
1970848c94fSMark Brown NULL);
19870c6cce0SQiao Zhou if (ret < 0) {
19970c6cce0SQiao Zhou dev_err(chip->dev, "Failed to add codec subdev\n");
20070c6cce0SQiao Zhou goto out_codec;
20170c6cce0SQiao Zhou } else
20270c6cce0SQiao Zhou dev_info(chip->dev, "[%s]:Added mfd codec_devs\n", __func__);
20370c6cce0SQiao Zhou
20470c6cce0SQiao Zhou return 0;
20570c6cce0SQiao Zhou
20670c6cce0SQiao Zhou out_codec:
20770c6cce0SQiao Zhou device_irq_exit_805(chip);
20870c6cce0SQiao Zhou out_irq_init:
20970c6cce0SQiao Zhou return ret;
21070c6cce0SQiao Zhou }
21170c6cce0SQiao Zhou
pm805_probe(struct i2c_client * client)21261d1be25SUwe Kleine-König static int pm805_probe(struct i2c_client *client)
21370c6cce0SQiao Zhou {
21470c6cce0SQiao Zhou int ret = 0;
21570c6cce0SQiao Zhou struct pm80x_chip *chip;
216334a41ceSJingoo Han struct pm80x_platform_data *pdata = dev_get_platdata(&client->dev);
21770c6cce0SQiao Zhou
21803dcc544SChao Xie ret = pm80x_init(client);
21970c6cce0SQiao Zhou if (ret) {
22070c6cce0SQiao Zhou dev_err(&client->dev, "pm805_init fail!\n");
22170c6cce0SQiao Zhou goto out_init;
22270c6cce0SQiao Zhou }
22370c6cce0SQiao Zhou
22470c6cce0SQiao Zhou chip = i2c_get_clientdata(client);
22570c6cce0SQiao Zhou
22670c6cce0SQiao Zhou ret = device_805_init(chip);
22770c6cce0SQiao Zhou if (ret) {
22803dcc544SChao Xie dev_err(chip->dev, "Failed to initialize 88pm805 devices\n");
22970c6cce0SQiao Zhou goto err_805_init;
23070c6cce0SQiao Zhou }
23170c6cce0SQiao Zhou
2322b274fe5SChao Xie if (pdata && pdata->plat_config)
23370c6cce0SQiao Zhou pdata->plat_config(chip, pdata);
23470c6cce0SQiao Zhou
23570c6cce0SQiao Zhou err_805_init:
236306df798SYi Zhang pm80x_deinit();
23770c6cce0SQiao Zhou out_init:
23870c6cce0SQiao Zhou return ret;
23970c6cce0SQiao Zhou }
24070c6cce0SQiao Zhou
pm805_remove(struct i2c_client * client)241ed5c2f5fSUwe Kleine-König static void pm805_remove(struct i2c_client *client)
24270c6cce0SQiao Zhou {
24370c6cce0SQiao Zhou struct pm80x_chip *chip = i2c_get_clientdata(client);
24470c6cce0SQiao Zhou
24570c6cce0SQiao Zhou mfd_remove_devices(chip->dev);
24670c6cce0SQiao Zhou device_irq_exit_805(chip);
24770c6cce0SQiao Zhou
248306df798SYi Zhang pm80x_deinit();
24970c6cce0SQiao Zhou }
25070c6cce0SQiao Zhou
25170c6cce0SQiao Zhou static struct i2c_driver pm805_driver = {
25270c6cce0SQiao Zhou .driver = {
25346223a19SChao Xie .name = "88PM805",
25419755a0aSPaul Cercueil .pm = pm_sleep_ptr(&pm80x_pm_ops),
25570c6cce0SQiao Zhou },
256*9816d859SUwe Kleine-König .probe = pm805_probe,
25784449216SBill Pemberton .remove = pm805_remove,
25870c6cce0SQiao Zhou .id_table = pm80x_id_table,
25970c6cce0SQiao Zhou };
26070c6cce0SQiao Zhou
pm805_i2c_init(void)26170c6cce0SQiao Zhou static int __init pm805_i2c_init(void)
26270c6cce0SQiao Zhou {
26370c6cce0SQiao Zhou return i2c_add_driver(&pm805_driver);
26470c6cce0SQiao Zhou }
26570c6cce0SQiao Zhou subsys_initcall(pm805_i2c_init);
26670c6cce0SQiao Zhou
pm805_i2c_exit(void)26770c6cce0SQiao Zhou static void __exit pm805_i2c_exit(void)
26870c6cce0SQiao Zhou {
26970c6cce0SQiao Zhou i2c_del_driver(&pm805_driver);
27070c6cce0SQiao Zhou }
27170c6cce0SQiao Zhou module_exit(pm805_i2c_exit);
27270c6cce0SQiao Zhou
27370c6cce0SQiao Zhou MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM805");
27470c6cce0SQiao Zhou MODULE_AUTHOR("Qiao Zhou <zhouqiao@marvell.com>");
27570c6cce0SQiao Zhou MODULE_LICENSE("GPL");
276