1 /* 2 * linux/drivers/message/fusion/mptbase.c 3 * This is the Fusion MPT base driver which supports multiple 4 * (SCSI + LAN) specialized protocol drivers. 5 * For use with LSI PCI chip/adapter(s) 6 * running LSI Fusion MPT (Message Passing Technology) firmware. 7 * 8 * Copyright (c) 1999-2008 LSI Corporation 9 * (mailto:DL-MPTFusionLinux@lsi.com) 10 * 11 */ 12 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 13 /* 14 This program is free software; you can redistribute it and/or modify 15 it under the terms of the GNU General Public License as published by 16 the Free Software Foundation; version 2 of the License. 17 18 This program is distributed in the hope that it will be useful, 19 but WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 GNU General Public License for more details. 22 23 NO WARRANTY 24 THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR 25 CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT 26 LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, 27 MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is 28 solely responsible for determining the appropriateness of using and 29 distributing the Program and assumes all risks associated with its 30 exercise of rights under this Agreement, including but not limited to 31 the risks and costs of program errors, damage to or loss of data, 32 programs or equipment, and unavailability or interruption of operations. 33 34 DISCLAIMER OF LIABILITY 35 NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY 36 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND 38 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 39 TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 40 USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED 41 HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES 42 43 You should have received a copy of the GNU General Public License 44 along with this program; if not, write to the Free Software 45 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 46 */ 47 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 48 49 #include <linux/kernel.h> 50 #include <linux/module.h> 51 #include <linux/errno.h> 52 #include <linux/init.h> 53 #include <linux/seq_file.h> 54 #include <linux/slab.h> 55 #include <linux/types.h> 56 #include <linux/pci.h> 57 #include <linux/kdev_t.h> 58 #include <linux/blkdev.h> 59 #include <linux/delay.h> 60 #include <linux/interrupt.h> 61 #include <linux/dma-mapping.h> 62 #include <linux/kthread.h> 63 #include <scsi/scsi_host.h> 64 65 #include "mptbase.h" 66 #include "lsi/mpi_log_fc.h" 67 68 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 69 #define my_NAME "Fusion MPT base driver" 70 #define my_VERSION MPT_LINUX_VERSION_COMMON 71 #define MYNAM "mptbase" 72 73 MODULE_AUTHOR(MODULEAUTHOR); 74 MODULE_DESCRIPTION(my_NAME); 75 MODULE_LICENSE("GPL"); 76 MODULE_VERSION(my_VERSION); 77 78 /* 79 * cmd line parameters 80 */ 81 82 static int mpt_msi_enable_spi; 83 module_param(mpt_msi_enable_spi, int, 0); 84 MODULE_PARM_DESC(mpt_msi_enable_spi, 85 " Enable MSI Support for SPI controllers (default=0)"); 86 87 static int mpt_msi_enable_fc; 88 module_param(mpt_msi_enable_fc, int, 0); 89 MODULE_PARM_DESC(mpt_msi_enable_fc, 90 " Enable MSI Support for FC controllers (default=0)"); 91 92 static int mpt_msi_enable_sas; 93 module_param(mpt_msi_enable_sas, int, 0); 94 MODULE_PARM_DESC(mpt_msi_enable_sas, 95 " Enable MSI Support for SAS controllers (default=0)"); 96 97 static int mpt_channel_mapping; 98 module_param(mpt_channel_mapping, int, 0); 99 MODULE_PARM_DESC(mpt_channel_mapping, " Mapping id's to channels (default=0)"); 100 101 static int mpt_debug_level; 102 static int mpt_set_debug_level(const char *val, const struct kernel_param *kp); 103 module_param_call(mpt_debug_level, mpt_set_debug_level, param_get_int, 104 &mpt_debug_level, 0600); 105 MODULE_PARM_DESC(mpt_debug_level, 106 " debug level - refer to mptdebug.h - (default=0)"); 107 108 int mpt_fwfault_debug; 109 EXPORT_SYMBOL(mpt_fwfault_debug); 110 module_param(mpt_fwfault_debug, int, 0600); 111 MODULE_PARM_DESC(mpt_fwfault_debug, 112 "Enable detection of Firmware fault and halt Firmware on fault - (default=0)"); 113 114 static char MptCallbacksName[MPT_MAX_PROTOCOL_DRIVERS] 115 [MPT_MAX_CALLBACKNAME_LEN+1]; 116 117 #ifdef MFCNT 118 static int mfcounter = 0; 119 #define PRINT_MF_COUNT 20000 120 #endif 121 122 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 123 /* 124 * Public data... 125 */ 126 127 #define WHOINIT_UNKNOWN 0xAA 128 129 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 130 /* 131 * Private data... 132 */ 133 /* Adapter link list */ 134 LIST_HEAD(ioc_list); 135 /* Callback lookup table */ 136 static MPT_CALLBACK MptCallbacks[MPT_MAX_PROTOCOL_DRIVERS]; 137 /* Protocol driver class lookup table */ 138 static int MptDriverClass[MPT_MAX_PROTOCOL_DRIVERS]; 139 /* Event handler lookup table */ 140 static MPT_EVHANDLER MptEvHandlers[MPT_MAX_PROTOCOL_DRIVERS]; 141 /* Reset handler lookup table */ 142 static MPT_RESETHANDLER MptResetHandlers[MPT_MAX_PROTOCOL_DRIVERS]; 143 static struct mpt_pci_driver *MptDeviceDriverHandlers[MPT_MAX_PROTOCOL_DRIVERS]; 144 145 #ifdef CONFIG_PROC_FS 146 static struct proc_dir_entry *mpt_proc_root_dir; 147 #endif 148 149 /* 150 * Driver Callback Index's 151 */ 152 static u8 mpt_base_index = MPT_MAX_PROTOCOL_DRIVERS; 153 static u8 last_drv_idx; 154 155 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 156 /* 157 * Forward protos... 158 */ 159 static irqreturn_t mpt_interrupt(int irq, void *bus_id); 160 static int mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, 161 MPT_FRAME_HDR *reply); 162 static int mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, 163 u32 *req, int replyBytes, u16 *u16reply, int maxwait, 164 int sleepFlag); 165 static int mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag); 166 static void mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev); 167 static void mpt_adapter_disable(MPT_ADAPTER *ioc); 168 static void mpt_adapter_dispose(MPT_ADAPTER *ioc); 169 170 static void MptDisplayIocCapabilities(MPT_ADAPTER *ioc); 171 static int MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag); 172 static int GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason); 173 static int GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag); 174 static int SendIocInit(MPT_ADAPTER *ioc, int sleepFlag); 175 static int SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag); 176 static int mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag); 177 static int mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag); 178 static int mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag); 179 static int KickStart(MPT_ADAPTER *ioc, int ignore, int sleepFlag); 180 static int SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag); 181 static int PrimeIocFifos(MPT_ADAPTER *ioc); 182 static int WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag); 183 static int WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag); 184 static int WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag); 185 static int GetLanConfigPages(MPT_ADAPTER *ioc); 186 static int GetIoUnitPage2(MPT_ADAPTER *ioc); 187 int mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode); 188 static int mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum); 189 static int mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum); 190 static void mpt_read_ioc_pg_1(MPT_ADAPTER *ioc); 191 static void mpt_read_ioc_pg_4(MPT_ADAPTER *ioc); 192 static void mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc); 193 static int SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch, 194 int sleepFlag); 195 static int SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp); 196 static int mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag); 197 static int mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init); 198 199 #ifdef CONFIG_PROC_FS 200 static int mpt_summary_proc_show(struct seq_file *m, void *v); 201 static int mpt_version_proc_show(struct seq_file *m, void *v); 202 static int mpt_iocinfo_proc_show(struct seq_file *m, void *v); 203 #endif 204 static void mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc); 205 206 static int ProcessEventNotification(MPT_ADAPTER *ioc, 207 EventNotificationReply_t *evReply, int *evHandlers); 208 static void mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf); 209 static void mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info); 210 static void mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info); 211 static void mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info , u8 cb_idx); 212 static int mpt_read_ioc_pg_3(MPT_ADAPTER *ioc); 213 static void mpt_inactive_raid_list_free(MPT_ADAPTER *ioc); 214 215 /* module entry point */ 216 static int __init fusion_init (void); 217 static void __exit fusion_exit (void); 218 219 #define CHIPREG_READ32(addr) readl_relaxed(addr) 220 #define CHIPREG_READ32_dmasync(addr) readl(addr) 221 #define CHIPREG_WRITE32(addr,val) writel(val, addr) 222 #define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr) 223 #define CHIPREG_PIO_READ32(addr) inl((unsigned long)addr) 224 225 static void 226 pci_disable_io_access(struct pci_dev *pdev) 227 { 228 u16 command_reg; 229 230 pci_read_config_word(pdev, PCI_COMMAND, &command_reg); 231 command_reg &= ~1; 232 pci_write_config_word(pdev, PCI_COMMAND, command_reg); 233 } 234 235 static void 236 pci_enable_io_access(struct pci_dev *pdev) 237 { 238 u16 command_reg; 239 240 pci_read_config_word(pdev, PCI_COMMAND, &command_reg); 241 command_reg |= 1; 242 pci_write_config_word(pdev, PCI_COMMAND, command_reg); 243 } 244 245 static int mpt_set_debug_level(const char *val, const struct kernel_param *kp) 246 { 247 int ret = param_set_int(val, kp); 248 MPT_ADAPTER *ioc; 249 250 if (ret) 251 return ret; 252 253 list_for_each_entry(ioc, &ioc_list, list) 254 ioc->debug_level = mpt_debug_level; 255 return 0; 256 } 257 258 /** 259 * mpt_get_cb_idx - obtain cb_idx for registered driver 260 * @dclass: class driver enum 261 * 262 * Returns cb_idx, or zero means it wasn't found 263 **/ 264 static u8 265 mpt_get_cb_idx(MPT_DRIVER_CLASS dclass) 266 { 267 u8 cb_idx; 268 269 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) 270 if (MptDriverClass[cb_idx] == dclass) 271 return cb_idx; 272 return 0; 273 } 274 275 /** 276 * mpt_is_discovery_complete - determine if discovery has completed 277 * @ioc: per adatper instance 278 * 279 * Returns 1 when discovery completed, else zero. 280 */ 281 static int 282 mpt_is_discovery_complete(MPT_ADAPTER *ioc) 283 { 284 ConfigExtendedPageHeader_t hdr; 285 CONFIGPARMS cfg; 286 SasIOUnitPage0_t *buffer; 287 dma_addr_t dma_handle; 288 int rc = 0; 289 290 memset(&hdr, 0, sizeof(ConfigExtendedPageHeader_t)); 291 memset(&cfg, 0, sizeof(CONFIGPARMS)); 292 hdr.PageVersion = MPI_SASIOUNITPAGE0_PAGEVERSION; 293 hdr.PageType = MPI_CONFIG_PAGETYPE_EXTENDED; 294 hdr.ExtPageType = MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT; 295 cfg.cfghdr.ehdr = &hdr; 296 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 297 298 if ((mpt_config(ioc, &cfg))) 299 goto out; 300 if (!hdr.ExtPageLength) 301 goto out; 302 303 buffer = pci_alloc_consistent(ioc->pcidev, hdr.ExtPageLength * 4, 304 &dma_handle); 305 if (!buffer) 306 goto out; 307 308 cfg.physAddr = dma_handle; 309 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 310 311 if ((mpt_config(ioc, &cfg))) 312 goto out_free_consistent; 313 314 if (!(buffer->PhyData[0].PortFlags & 315 MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS)) 316 rc = 1; 317 318 out_free_consistent: 319 pci_free_consistent(ioc->pcidev, hdr.ExtPageLength * 4, 320 buffer, dma_handle); 321 out: 322 return rc; 323 } 324 325 326 /** 327 * mpt_remove_dead_ioc_func - kthread context to remove dead ioc 328 * @arg: input argument, used to derive ioc 329 * 330 * Return 0 if controller is removed from pci subsystem. 331 * Return -1 for other case. 332 */ 333 static int mpt_remove_dead_ioc_func(void *arg) 334 { 335 MPT_ADAPTER *ioc = (MPT_ADAPTER *)arg; 336 struct pci_dev *pdev; 337 338 if (!ioc) 339 return -1; 340 341 pdev = ioc->pcidev; 342 if (!pdev) 343 return -1; 344 345 pci_stop_and_remove_bus_device_locked(pdev); 346 return 0; 347 } 348 349 350 351 /** 352 * mpt_fault_reset_work - work performed on workq after ioc fault 353 * @work: input argument, used to derive ioc 354 * 355 **/ 356 static void 357 mpt_fault_reset_work(struct work_struct *work) 358 { 359 MPT_ADAPTER *ioc = 360 container_of(work, MPT_ADAPTER, fault_reset_work.work); 361 u32 ioc_raw_state; 362 int rc; 363 unsigned long flags; 364 MPT_SCSI_HOST *hd; 365 struct task_struct *p; 366 367 if (ioc->ioc_reset_in_progress || !ioc->active) 368 goto out; 369 370 371 ioc_raw_state = mpt_GetIocState(ioc, 0); 372 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_MASK) { 373 printk(MYIOC_s_INFO_FMT "%s: IOC is non-operational !!!!\n", 374 ioc->name, __func__); 375 376 /* 377 * Call mptscsih_flush_pending_cmds callback so that we 378 * flush all pending commands back to OS. 379 * This call is required to aovid deadlock at block layer. 380 * Dead IOC will fail to do diag reset,and this call is safe 381 * since dead ioc will never return any command back from HW. 382 */ 383 hd = shost_priv(ioc->sh); 384 ioc->schedule_dead_ioc_flush_running_cmds(hd); 385 386 /*Remove the Dead Host */ 387 p = kthread_run(mpt_remove_dead_ioc_func, ioc, 388 "mpt_dead_ioc_%d", ioc->id); 389 if (IS_ERR(p)) { 390 printk(MYIOC_s_ERR_FMT 391 "%s: Running mpt_dead_ioc thread failed !\n", 392 ioc->name, __func__); 393 } else { 394 printk(MYIOC_s_WARN_FMT 395 "%s: Running mpt_dead_ioc thread success !\n", 396 ioc->name, __func__); 397 } 398 return; /* don't rearm timer */ 399 } 400 401 if ((ioc_raw_state & MPI_IOC_STATE_MASK) 402 == MPI_IOC_STATE_FAULT) { 403 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state (%04xh)!!!\n", 404 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK); 405 printk(MYIOC_s_WARN_FMT "Issuing HardReset from %s!!\n", 406 ioc->name, __func__); 407 rc = mpt_HardResetHandler(ioc, CAN_SLEEP); 408 printk(MYIOC_s_WARN_FMT "%s: HardReset: %s\n", ioc->name, 409 __func__, (rc == 0) ? "success" : "failed"); 410 ioc_raw_state = mpt_GetIocState(ioc, 0); 411 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) 412 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state after " 413 "reset (%04xh)\n", ioc->name, ioc_raw_state & 414 MPI_DOORBELL_DATA_MASK); 415 } else if (ioc->bus_type == SAS && ioc->sas_discovery_quiesce_io) { 416 if ((mpt_is_discovery_complete(ioc))) { 417 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "clearing " 418 "discovery_quiesce_io flag\n", ioc->name)); 419 ioc->sas_discovery_quiesce_io = 0; 420 } 421 } 422 423 out: 424 /* 425 * Take turns polling alternate controller 426 */ 427 if (ioc->alt_ioc) 428 ioc = ioc->alt_ioc; 429 430 /* rearm the timer */ 431 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 432 if (ioc->reset_work_q) 433 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work, 434 msecs_to_jiffies(MPT_POLLING_INTERVAL)); 435 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 436 } 437 438 439 /* 440 * Process turbo (context) reply... 441 */ 442 static void 443 mpt_turbo_reply(MPT_ADAPTER *ioc, u32 pa) 444 { 445 MPT_FRAME_HDR *mf = NULL; 446 MPT_FRAME_HDR *mr = NULL; 447 u16 req_idx = 0; 448 u8 cb_idx; 449 450 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got TURBO reply req_idx=%08x\n", 451 ioc->name, pa)); 452 453 switch (pa >> MPI_CONTEXT_REPLY_TYPE_SHIFT) { 454 case MPI_CONTEXT_REPLY_TYPE_SCSI_INIT: 455 req_idx = pa & 0x0000FFFF; 456 cb_idx = (pa & 0x00FF0000) >> 16; 457 mf = MPT_INDEX_2_MFPTR(ioc, req_idx); 458 break; 459 case MPI_CONTEXT_REPLY_TYPE_LAN: 460 cb_idx = mpt_get_cb_idx(MPTLAN_DRIVER); 461 /* 462 * Blind set of mf to NULL here was fatal 463 * after lan_reply says "freeme" 464 * Fix sort of combined with an optimization here; 465 * added explicit check for case where lan_reply 466 * was just returning 1 and doing nothing else. 467 * For this case skip the callback, but set up 468 * proper mf value first here:-) 469 */ 470 if ((pa & 0x58000000) == 0x58000000) { 471 req_idx = pa & 0x0000FFFF; 472 mf = MPT_INDEX_2_MFPTR(ioc, req_idx); 473 mpt_free_msg_frame(ioc, mf); 474 mb(); 475 return; 476 } 477 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa); 478 break; 479 case MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET: 480 cb_idx = mpt_get_cb_idx(MPTSTM_DRIVER); 481 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa); 482 break; 483 default: 484 cb_idx = 0; 485 BUG(); 486 } 487 488 /* Check for (valid) IO callback! */ 489 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS || 490 MptCallbacks[cb_idx] == NULL) { 491 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n", 492 __func__, ioc->name, cb_idx); 493 goto out; 494 } 495 496 if (MptCallbacks[cb_idx](ioc, mf, mr)) 497 mpt_free_msg_frame(ioc, mf); 498 out: 499 mb(); 500 } 501 502 static void 503 mpt_reply(MPT_ADAPTER *ioc, u32 pa) 504 { 505 MPT_FRAME_HDR *mf; 506 MPT_FRAME_HDR *mr; 507 u16 req_idx; 508 u8 cb_idx; 509 int freeme; 510 511 u32 reply_dma_low; 512 u16 ioc_stat; 513 514 /* non-TURBO reply! Hmmm, something may be up... 515 * Newest turbo reply mechanism; get address 516 * via left shift 1 (get rid of MPI_ADDRESS_REPLY_A_BIT)! 517 */ 518 519 /* Map DMA address of reply header to cpu address. 520 * pa is 32 bits - but the dma address may be 32 or 64 bits 521 * get offset based only only the low addresses 522 */ 523 524 reply_dma_low = (pa <<= 1); 525 mr = (MPT_FRAME_HDR *)((u8 *)ioc->reply_frames + 526 (reply_dma_low - ioc->reply_frames_low_dma)); 527 528 req_idx = le16_to_cpu(mr->u.frame.hwhdr.msgctxu.fld.req_idx); 529 cb_idx = mr->u.frame.hwhdr.msgctxu.fld.cb_idx; 530 mf = MPT_INDEX_2_MFPTR(ioc, req_idx); 531 532 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got non-TURBO reply=%p req_idx=%x cb_idx=%x Function=%x\n", 533 ioc->name, mr, req_idx, cb_idx, mr->u.hdr.Function)); 534 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mr); 535 536 /* Check/log IOC log info 537 */ 538 ioc_stat = le16_to_cpu(mr->u.reply.IOCStatus); 539 if (ioc_stat & MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 540 u32 log_info = le32_to_cpu(mr->u.reply.IOCLogInfo); 541 if (ioc->bus_type == FC) 542 mpt_fc_log_info(ioc, log_info); 543 else if (ioc->bus_type == SPI) 544 mpt_spi_log_info(ioc, log_info); 545 else if (ioc->bus_type == SAS) 546 mpt_sas_log_info(ioc, log_info, cb_idx); 547 } 548 549 if (ioc_stat & MPI_IOCSTATUS_MASK) 550 mpt_iocstatus_info(ioc, (u32)ioc_stat, mf); 551 552 /* Check for (valid) IO callback! */ 553 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS || 554 MptCallbacks[cb_idx] == NULL) { 555 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n", 556 __func__, ioc->name, cb_idx); 557 freeme = 0; 558 goto out; 559 } 560 561 freeme = MptCallbacks[cb_idx](ioc, mf, mr); 562 563 out: 564 /* Flush (non-TURBO) reply with a WRITE! */ 565 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, pa); 566 567 if (freeme) 568 mpt_free_msg_frame(ioc, mf); 569 mb(); 570 } 571 572 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 573 /** 574 * mpt_interrupt - MPT adapter (IOC) specific interrupt handler. 575 * @irq: irq number (not used) 576 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure 577 * 578 * This routine is registered via the request_irq() kernel API call, 579 * and handles all interrupts generated from a specific MPT adapter 580 * (also referred to as a IO Controller or IOC). 581 * This routine must clear the interrupt from the adapter and does 582 * so by reading the reply FIFO. Multiple replies may be processed 583 * per single call to this routine. 584 * 585 * This routine handles register-level access of the adapter but 586 * dispatches (calls) a protocol-specific callback routine to handle 587 * the protocol-specific details of the MPT request completion. 588 */ 589 static irqreturn_t 590 mpt_interrupt(int irq, void *bus_id) 591 { 592 MPT_ADAPTER *ioc = bus_id; 593 u32 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo); 594 595 if (pa == 0xFFFFFFFF) 596 return IRQ_NONE; 597 598 /* 599 * Drain the reply FIFO! 600 */ 601 do { 602 if (pa & MPI_ADDRESS_REPLY_A_BIT) 603 mpt_reply(ioc, pa); 604 else 605 mpt_turbo_reply(ioc, pa); 606 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo); 607 } while (pa != 0xFFFFFFFF); 608 609 return IRQ_HANDLED; 610 } 611 612 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 613 /** 614 * mptbase_reply - MPT base driver's callback routine 615 * @ioc: Pointer to MPT_ADAPTER structure 616 * @req: Pointer to original MPT request frame 617 * @reply: Pointer to MPT reply frame (NULL if TurboReply) 618 * 619 * MPT base driver's callback routine; all base driver 620 * "internal" request/reply processing is routed here. 621 * Currently used for EventNotification and EventAck handling. 622 * 623 * Returns 1 indicating original alloc'd request frame ptr 624 * should be freed, or 0 if it shouldn't. 625 */ 626 static int 627 mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, MPT_FRAME_HDR *reply) 628 { 629 EventNotificationReply_t *pEventReply; 630 u8 event; 631 int evHandlers; 632 int freereq = 1; 633 634 switch (reply->u.hdr.Function) { 635 case MPI_FUNCTION_EVENT_NOTIFICATION: 636 pEventReply = (EventNotificationReply_t *)reply; 637 evHandlers = 0; 638 ProcessEventNotification(ioc, pEventReply, &evHandlers); 639 event = le32_to_cpu(pEventReply->Event) & 0xFF; 640 if (pEventReply->MsgFlags & MPI_MSGFLAGS_CONTINUATION_REPLY) 641 freereq = 0; 642 if (event != MPI_EVENT_EVENT_CHANGE) 643 break; 644 fallthrough; 645 case MPI_FUNCTION_CONFIG: 646 case MPI_FUNCTION_SAS_IO_UNIT_CONTROL: 647 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_COMMAND_GOOD; 648 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_RF_VALID; 649 memcpy(ioc->mptbase_cmds.reply, reply, 650 min(MPT_DEFAULT_FRAME_SIZE, 651 4 * reply->u.reply.MsgLength)); 652 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) { 653 ioc->mptbase_cmds.status &= ~MPT_MGMT_STATUS_PENDING; 654 complete(&ioc->mptbase_cmds.done); 655 } else 656 freereq = 0; 657 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_FREE_MF) 658 freereq = 1; 659 break; 660 case MPI_FUNCTION_EVENT_ACK: 661 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT 662 "EventAck reply received\n", ioc->name)); 663 break; 664 default: 665 printk(MYIOC_s_ERR_FMT 666 "Unexpected msg function (=%02Xh) reply received!\n", 667 ioc->name, reply->u.hdr.Function); 668 break; 669 } 670 671 /* 672 * Conditionally tell caller to free the original 673 * EventNotification/EventAck/unexpected request frame! 674 */ 675 return freereq; 676 } 677 678 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 679 /** 680 * mpt_register - Register protocol-specific main callback handler. 681 * @cbfunc: callback function pointer 682 * @dclass: Protocol driver's class (%MPT_DRIVER_CLASS enum value) 683 * @func_name: call function's name 684 * 685 * This routine is called by a protocol-specific driver (SCSI host, 686 * LAN, SCSI target) to register its reply callback routine. Each 687 * protocol-specific driver must do this before it will be able to 688 * use any IOC resources, such as obtaining request frames. 689 * 690 * NOTES: The SCSI protocol driver currently calls this routine thrice 691 * in order to register separate callbacks; one for "normal" SCSI IO; 692 * one for MptScsiTaskMgmt requests; one for Scan/DV requests. 693 * 694 * Returns u8 valued "handle" in the range (and S.O.D. order) 695 * {N,...,7,6,5,...,1} if successful. 696 * A return value of MPT_MAX_PROTOCOL_DRIVERS (including zero!) should be 697 * considered an error by the caller. 698 */ 699 u8 700 mpt_register(MPT_CALLBACK cbfunc, MPT_DRIVER_CLASS dclass, char *func_name) 701 { 702 u8 cb_idx; 703 last_drv_idx = MPT_MAX_PROTOCOL_DRIVERS; 704 705 /* 706 * Search for empty callback slot in this order: {N,...,7,6,5,...,1} 707 * (slot/handle 0 is reserved!) 708 */ 709 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 710 if (MptCallbacks[cb_idx] == NULL) { 711 MptCallbacks[cb_idx] = cbfunc; 712 MptDriverClass[cb_idx] = dclass; 713 MptEvHandlers[cb_idx] = NULL; 714 last_drv_idx = cb_idx; 715 strlcpy(MptCallbacksName[cb_idx], func_name, 716 MPT_MAX_CALLBACKNAME_LEN+1); 717 break; 718 } 719 } 720 721 return last_drv_idx; 722 } 723 724 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 725 /** 726 * mpt_deregister - Deregister a protocol drivers resources. 727 * @cb_idx: previously registered callback handle 728 * 729 * Each protocol-specific driver should call this routine when its 730 * module is unloaded. 731 */ 732 void 733 mpt_deregister(u8 cb_idx) 734 { 735 if (cb_idx && (cb_idx < MPT_MAX_PROTOCOL_DRIVERS)) { 736 MptCallbacks[cb_idx] = NULL; 737 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER; 738 MptEvHandlers[cb_idx] = NULL; 739 740 last_drv_idx++; 741 } 742 } 743 744 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 745 /** 746 * mpt_event_register - Register protocol-specific event callback handler. 747 * @cb_idx: previously registered (via mpt_register) callback handle 748 * @ev_cbfunc: callback function 749 * 750 * This routine can be called by one or more protocol-specific drivers 751 * if/when they choose to be notified of MPT events. 752 * 753 * Returns 0 for success. 754 */ 755 int 756 mpt_event_register(u8 cb_idx, MPT_EVHANDLER ev_cbfunc) 757 { 758 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 759 return -1; 760 761 MptEvHandlers[cb_idx] = ev_cbfunc; 762 return 0; 763 } 764 765 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 766 /** 767 * mpt_event_deregister - Deregister protocol-specific event callback handler 768 * @cb_idx: previously registered callback handle 769 * 770 * Each protocol-specific driver should call this routine 771 * when it does not (or can no longer) handle events, 772 * or when its module is unloaded. 773 */ 774 void 775 mpt_event_deregister(u8 cb_idx) 776 { 777 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 778 return; 779 780 MptEvHandlers[cb_idx] = NULL; 781 } 782 783 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 784 /** 785 * mpt_reset_register - Register protocol-specific IOC reset handler. 786 * @cb_idx: previously registered (via mpt_register) callback handle 787 * @reset_func: reset function 788 * 789 * This routine can be called by one or more protocol-specific drivers 790 * if/when they choose to be notified of IOC resets. 791 * 792 * Returns 0 for success. 793 */ 794 int 795 mpt_reset_register(u8 cb_idx, MPT_RESETHANDLER reset_func) 796 { 797 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 798 return -1; 799 800 MptResetHandlers[cb_idx] = reset_func; 801 return 0; 802 } 803 804 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 805 /** 806 * mpt_reset_deregister - Deregister protocol-specific IOC reset handler. 807 * @cb_idx: previously registered callback handle 808 * 809 * Each protocol-specific driver should call this routine 810 * when it does not (or can no longer) handle IOC reset handling, 811 * or when its module is unloaded. 812 */ 813 void 814 mpt_reset_deregister(u8 cb_idx) 815 { 816 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 817 return; 818 819 MptResetHandlers[cb_idx] = NULL; 820 } 821 822 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 823 /** 824 * mpt_device_driver_register - Register device driver hooks 825 * @dd_cbfunc: driver callbacks struct 826 * @cb_idx: MPT protocol driver index 827 */ 828 int 829 mpt_device_driver_register(struct mpt_pci_driver * dd_cbfunc, u8 cb_idx) 830 { 831 MPT_ADAPTER *ioc; 832 const struct pci_device_id *id; 833 834 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 835 return -EINVAL; 836 837 MptDeviceDriverHandlers[cb_idx] = dd_cbfunc; 838 839 /* call per pci device probe entry point */ 840 list_for_each_entry(ioc, &ioc_list, list) { 841 id = ioc->pcidev->driver ? 842 ioc->pcidev->driver->id_table : NULL; 843 if (dd_cbfunc->probe) 844 dd_cbfunc->probe(ioc->pcidev, id); 845 } 846 847 return 0; 848 } 849 850 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 851 /** 852 * mpt_device_driver_deregister - DeRegister device driver hooks 853 * @cb_idx: MPT protocol driver index 854 */ 855 void 856 mpt_device_driver_deregister(u8 cb_idx) 857 { 858 struct mpt_pci_driver *dd_cbfunc; 859 MPT_ADAPTER *ioc; 860 861 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 862 return; 863 864 dd_cbfunc = MptDeviceDriverHandlers[cb_idx]; 865 866 list_for_each_entry(ioc, &ioc_list, list) { 867 if (dd_cbfunc->remove) 868 dd_cbfunc->remove(ioc->pcidev); 869 } 870 871 MptDeviceDriverHandlers[cb_idx] = NULL; 872 } 873 874 875 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 876 /** 877 * mpt_get_msg_frame - Obtain an MPT request frame from the pool 878 * @cb_idx: Handle of registered MPT protocol driver 879 * @ioc: Pointer to MPT adapter structure 880 * 881 * Obtain an MPT request frame from the pool (of 1024) that are 882 * allocated per MPT adapter. 883 * 884 * Returns pointer to a MPT request frame or %NULL if none are available 885 * or IOC is not active. 886 */ 887 MPT_FRAME_HDR* 888 mpt_get_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc) 889 { 890 MPT_FRAME_HDR *mf; 891 unsigned long flags; 892 u16 req_idx; /* Request index */ 893 894 /* validate handle and ioc identifier */ 895 896 #ifdef MFCNT 897 if (!ioc->active) 898 printk(MYIOC_s_WARN_FMT "IOC Not Active! mpt_get_msg_frame " 899 "returning NULL!\n", ioc->name); 900 #endif 901 902 /* If interrupts are not attached, do not return a request frame */ 903 if (!ioc->active) 904 return NULL; 905 906 spin_lock_irqsave(&ioc->FreeQlock, flags); 907 if (!list_empty(&ioc->FreeQ)) { 908 int req_offset; 909 910 mf = list_entry(ioc->FreeQ.next, MPT_FRAME_HDR, 911 u.frame.linkage.list); 912 list_del(&mf->u.frame.linkage.list); 913 mf->u.frame.linkage.arg1 = 0; 914 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */ 915 req_offset = (u8 *)mf - (u8 *)ioc->req_frames; 916 /* u16! */ 917 req_idx = req_offset / ioc->req_sz; 918 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx); 919 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0; 920 /* Default, will be changed if necessary in SG generation */ 921 ioc->RequestNB[req_idx] = ioc->NB_for_64_byte_frame; 922 #ifdef MFCNT 923 ioc->mfcnt++; 924 #endif 925 } 926 else 927 mf = NULL; 928 spin_unlock_irqrestore(&ioc->FreeQlock, flags); 929 930 #ifdef MFCNT 931 if (mf == NULL) 932 printk(MYIOC_s_WARN_FMT "IOC Active. No free Msg Frames! " 933 "Count 0x%x Max 0x%x\n", ioc->name, ioc->mfcnt, 934 ioc->req_depth); 935 mfcounter++; 936 if (mfcounter == PRINT_MF_COUNT) 937 printk(MYIOC_s_INFO_FMT "MF Count 0x%x Max 0x%x \n", ioc->name, 938 ioc->mfcnt, ioc->req_depth); 939 #endif 940 941 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_get_msg_frame(%d,%d), got mf=%p\n", 942 ioc->name, cb_idx, ioc->id, mf)); 943 return mf; 944 } 945 946 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 947 /** 948 * mpt_put_msg_frame - Send a protocol-specific MPT request frame to an IOC 949 * @cb_idx: Handle of registered MPT protocol driver 950 * @ioc: Pointer to MPT adapter structure 951 * @mf: Pointer to MPT request frame 952 * 953 * This routine posts an MPT request frame to the request post FIFO of a 954 * specific MPT adapter. 955 */ 956 void 957 mpt_put_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf) 958 { 959 u32 mf_dma_addr; 960 int req_offset; 961 u16 req_idx; /* Request index */ 962 963 /* ensure values are reset properly! */ 964 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */ 965 req_offset = (u8 *)mf - (u8 *)ioc->req_frames; 966 /* u16! */ 967 req_idx = req_offset / ioc->req_sz; 968 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx); 969 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0; 970 971 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf); 972 973 mf_dma_addr = (ioc->req_frames_low_dma + req_offset) | ioc->RequestNB[req_idx]; 974 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d " 975 "RequestNB=%x\n", ioc->name, mf_dma_addr, req_idx, 976 ioc->RequestNB[req_idx])); 977 CHIPREG_WRITE32(&ioc->chip->RequestFifo, mf_dma_addr); 978 } 979 980 /** 981 * mpt_put_msg_frame_hi_pri - Send a hi-pri protocol-specific MPT request frame 982 * @cb_idx: Handle of registered MPT protocol driver 983 * @ioc: Pointer to MPT adapter structure 984 * @mf: Pointer to MPT request frame 985 * 986 * Send a protocol-specific MPT request frame to an IOC using 987 * hi-priority request queue. 988 * 989 * This routine posts an MPT request frame to the request post FIFO of a 990 * specific MPT adapter. 991 **/ 992 void 993 mpt_put_msg_frame_hi_pri(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf) 994 { 995 u32 mf_dma_addr; 996 int req_offset; 997 u16 req_idx; /* Request index */ 998 999 /* ensure values are reset properly! */ 1000 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; 1001 req_offset = (u8 *)mf - (u8 *)ioc->req_frames; 1002 req_idx = req_offset / ioc->req_sz; 1003 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx); 1004 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0; 1005 1006 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf); 1007 1008 mf_dma_addr = (ioc->req_frames_low_dma + req_offset); 1009 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d\n", 1010 ioc->name, mf_dma_addr, req_idx)); 1011 CHIPREG_WRITE32(&ioc->chip->RequestHiPriFifo, mf_dma_addr); 1012 } 1013 1014 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1015 /** 1016 * mpt_free_msg_frame - Place MPT request frame back on FreeQ. 1017 * @ioc: Pointer to MPT adapter structure 1018 * @mf: Pointer to MPT request frame 1019 * 1020 * This routine places a MPT request frame back on the MPT adapter's 1021 * FreeQ. 1022 */ 1023 void 1024 mpt_free_msg_frame(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf) 1025 { 1026 unsigned long flags; 1027 1028 /* Put Request back on FreeQ! */ 1029 spin_lock_irqsave(&ioc->FreeQlock, flags); 1030 if (cpu_to_le32(mf->u.frame.linkage.arg1) == 0xdeadbeaf) 1031 goto out; 1032 /* signature to know if this mf is freed */ 1033 mf->u.frame.linkage.arg1 = cpu_to_le32(0xdeadbeaf); 1034 list_add(&mf->u.frame.linkage.list, &ioc->FreeQ); 1035 #ifdef MFCNT 1036 ioc->mfcnt--; 1037 #endif 1038 out: 1039 spin_unlock_irqrestore(&ioc->FreeQlock, flags); 1040 } 1041 1042 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1043 /** 1044 * mpt_add_sge - Place a simple 32 bit SGE at address pAddr. 1045 * @pAddr: virtual address for SGE 1046 * @flagslength: SGE flags and data transfer length 1047 * @dma_addr: Physical address 1048 * 1049 * This routine places a MPT request frame back on the MPT adapter's 1050 * FreeQ. 1051 */ 1052 static void 1053 mpt_add_sge(void *pAddr, u32 flagslength, dma_addr_t dma_addr) 1054 { 1055 SGESimple32_t *pSge = (SGESimple32_t *) pAddr; 1056 pSge->FlagsLength = cpu_to_le32(flagslength); 1057 pSge->Address = cpu_to_le32(dma_addr); 1058 } 1059 1060 /** 1061 * mpt_add_sge_64bit - Place a simple 64 bit SGE at address pAddr. 1062 * @pAddr: virtual address for SGE 1063 * @flagslength: SGE flags and data transfer length 1064 * @dma_addr: Physical address 1065 * 1066 * This routine places a MPT request frame back on the MPT adapter's 1067 * FreeQ. 1068 **/ 1069 static void 1070 mpt_add_sge_64bit(void *pAddr, u32 flagslength, dma_addr_t dma_addr) 1071 { 1072 SGESimple64_t *pSge = (SGESimple64_t *) pAddr; 1073 pSge->Address.Low = cpu_to_le32 1074 (lower_32_bits(dma_addr)); 1075 pSge->Address.High = cpu_to_le32 1076 (upper_32_bits(dma_addr)); 1077 pSge->FlagsLength = cpu_to_le32 1078 ((flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING)); 1079 } 1080 1081 /** 1082 * mpt_add_sge_64bit_1078 - Place a simple 64 bit SGE at address pAddr (1078 workaround). 1083 * @pAddr: virtual address for SGE 1084 * @flagslength: SGE flags and data transfer length 1085 * @dma_addr: Physical address 1086 * 1087 * This routine places a MPT request frame back on the MPT adapter's 1088 * FreeQ. 1089 **/ 1090 static void 1091 mpt_add_sge_64bit_1078(void *pAddr, u32 flagslength, dma_addr_t dma_addr) 1092 { 1093 SGESimple64_t *pSge = (SGESimple64_t *) pAddr; 1094 u32 tmp; 1095 1096 pSge->Address.Low = cpu_to_le32 1097 (lower_32_bits(dma_addr)); 1098 tmp = (u32)(upper_32_bits(dma_addr)); 1099 1100 /* 1101 * 1078 errata workaround for the 36GB limitation 1102 */ 1103 if ((((u64)dma_addr + MPI_SGE_LENGTH(flagslength)) >> 32) == 9) { 1104 flagslength |= 1105 MPI_SGE_SET_FLAGS(MPI_SGE_FLAGS_LOCAL_ADDRESS); 1106 tmp |= (1<<31); 1107 if (mpt_debug_level & MPT_DEBUG_36GB_MEM) 1108 printk(KERN_DEBUG "1078 P0M2 addressing for " 1109 "addr = 0x%llx len = %d\n", 1110 (unsigned long long)dma_addr, 1111 MPI_SGE_LENGTH(flagslength)); 1112 } 1113 1114 pSge->Address.High = cpu_to_le32(tmp); 1115 pSge->FlagsLength = cpu_to_le32( 1116 (flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING)); 1117 } 1118 1119 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1120 /** 1121 * mpt_add_chain - Place a 32 bit chain SGE at address pAddr. 1122 * @pAddr: virtual address for SGE 1123 * @next: nextChainOffset value (u32's) 1124 * @length: length of next SGL segment 1125 * @dma_addr: Physical address 1126 * 1127 */ 1128 static void 1129 mpt_add_chain(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr) 1130 { 1131 SGEChain32_t *pChain = (SGEChain32_t *) pAddr; 1132 1133 pChain->Length = cpu_to_le16(length); 1134 pChain->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT; 1135 pChain->NextChainOffset = next; 1136 pChain->Address = cpu_to_le32(dma_addr); 1137 } 1138 1139 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1140 /** 1141 * mpt_add_chain_64bit - Place a 64 bit chain SGE at address pAddr. 1142 * @pAddr: virtual address for SGE 1143 * @next: nextChainOffset value (u32's) 1144 * @length: length of next SGL segment 1145 * @dma_addr: Physical address 1146 * 1147 */ 1148 static void 1149 mpt_add_chain_64bit(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr) 1150 { 1151 SGEChain64_t *pChain = (SGEChain64_t *) pAddr; 1152 u32 tmp = dma_addr & 0xFFFFFFFF; 1153 1154 pChain->Length = cpu_to_le16(length); 1155 pChain->Flags = (MPI_SGE_FLAGS_CHAIN_ELEMENT | 1156 MPI_SGE_FLAGS_64_BIT_ADDRESSING); 1157 1158 pChain->NextChainOffset = next; 1159 1160 pChain->Address.Low = cpu_to_le32(tmp); 1161 tmp = (u32)(upper_32_bits(dma_addr)); 1162 pChain->Address.High = cpu_to_le32(tmp); 1163 } 1164 1165 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1166 /** 1167 * mpt_send_handshake_request - Send MPT request via doorbell handshake method. 1168 * @cb_idx: Handle of registered MPT protocol driver 1169 * @ioc: Pointer to MPT adapter structure 1170 * @reqBytes: Size of the request in bytes 1171 * @req: Pointer to MPT request frame 1172 * @sleepFlag: Use schedule if CAN_SLEEP else use udelay. 1173 * 1174 * This routine is used exclusively to send MptScsiTaskMgmt 1175 * requests since they are required to be sent via doorbell handshake. 1176 * 1177 * NOTE: It is the callers responsibility to byte-swap fields in the 1178 * request which are greater than 1 byte in size. 1179 * 1180 * Returns 0 for success, non-zero for failure. 1181 */ 1182 int 1183 mpt_send_handshake_request(u8 cb_idx, MPT_ADAPTER *ioc, int reqBytes, u32 *req, int sleepFlag) 1184 { 1185 int r = 0; 1186 u8 *req_as_bytes; 1187 int ii; 1188 1189 /* State is known to be good upon entering 1190 * this function so issue the bus reset 1191 * request. 1192 */ 1193 1194 /* 1195 * Emulate what mpt_put_msg_frame() does /wrt to sanity 1196 * setting cb_idx/req_idx. But ONLY if this request 1197 * is in proper (pre-alloc'd) request buffer range... 1198 */ 1199 ii = MFPTR_2_MPT_INDEX(ioc,(MPT_FRAME_HDR*)req); 1200 if (reqBytes >= 12 && ii >= 0 && ii < ioc->req_depth) { 1201 MPT_FRAME_HDR *mf = (MPT_FRAME_HDR*)req; 1202 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(ii); 1203 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; 1204 } 1205 1206 /* Make sure there are no doorbells */ 1207 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1208 1209 CHIPREG_WRITE32(&ioc->chip->Doorbell, 1210 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) | 1211 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT))); 1212 1213 /* Wait for IOC doorbell int */ 1214 if ((ii = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) { 1215 return ii; 1216 } 1217 1218 /* Read doorbell and check for active bit */ 1219 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE)) 1220 return -5; 1221 1222 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_send_handshake_request start, WaitCnt=%d\n", 1223 ioc->name, ii)); 1224 1225 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1226 1227 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) { 1228 return -2; 1229 } 1230 1231 /* Send request via doorbell handshake */ 1232 req_as_bytes = (u8 *) req; 1233 for (ii = 0; ii < reqBytes/4; ii++) { 1234 u32 word; 1235 1236 word = ((req_as_bytes[(ii*4) + 0] << 0) | 1237 (req_as_bytes[(ii*4) + 1] << 8) | 1238 (req_as_bytes[(ii*4) + 2] << 16) | 1239 (req_as_bytes[(ii*4) + 3] << 24)); 1240 CHIPREG_WRITE32(&ioc->chip->Doorbell, word); 1241 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) { 1242 r = -3; 1243 break; 1244 } 1245 } 1246 1247 if (r >= 0 && WaitForDoorbellInt(ioc, 10, sleepFlag) >= 0) 1248 r = 0; 1249 else 1250 r = -4; 1251 1252 /* Make sure there are no doorbells */ 1253 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1254 1255 return r; 1256 } 1257 1258 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1259 /** 1260 * mpt_host_page_access_control - control the IOC's Host Page Buffer access 1261 * @ioc: Pointer to MPT adapter structure 1262 * @access_control_value: define bits below 1263 * @sleepFlag: Specifies whether the process can sleep 1264 * 1265 * Provides mechanism for the host driver to control the IOC's 1266 * Host Page Buffer access. 1267 * 1268 * Access Control Value - bits[15:12] 1269 * 0h Reserved 1270 * 1h Enable Access { MPI_DB_HPBAC_ENABLE_ACCESS } 1271 * 2h Disable Access { MPI_DB_HPBAC_DISABLE_ACCESS } 1272 * 3h Free Buffer { MPI_DB_HPBAC_FREE_BUFFER } 1273 * 1274 * Returns 0 for success, non-zero for failure. 1275 */ 1276 1277 static int 1278 mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag) 1279 { 1280 int r = 0; 1281 1282 /* return if in use */ 1283 if (CHIPREG_READ32(&ioc->chip->Doorbell) 1284 & MPI_DOORBELL_ACTIVE) 1285 return -1; 1286 1287 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1288 1289 CHIPREG_WRITE32(&ioc->chip->Doorbell, 1290 ((MPI_FUNCTION_HOST_PAGEBUF_ACCESS_CONTROL 1291 <<MPI_DOORBELL_FUNCTION_SHIFT) | 1292 (access_control_value<<12))); 1293 1294 /* Wait for IOC to clear Doorbell Status bit */ 1295 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) { 1296 return -2; 1297 }else 1298 return 0; 1299 } 1300 1301 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1302 /** 1303 * mpt_host_page_alloc - allocate system memory for the fw 1304 * @ioc: Pointer to pointer to IOC adapter 1305 * @ioc_init: Pointer to ioc init config page 1306 * 1307 * If we already allocated memory in past, then resend the same pointer. 1308 * Returns 0 for success, non-zero for failure. 1309 */ 1310 static int 1311 mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init) 1312 { 1313 char *psge; 1314 int flags_length; 1315 u32 host_page_buffer_sz=0; 1316 1317 if(!ioc->HostPageBuffer) { 1318 1319 host_page_buffer_sz = 1320 le32_to_cpu(ioc->facts.HostPageBufferSGE.FlagsLength) & 0xFFFFFF; 1321 1322 if(!host_page_buffer_sz) 1323 return 0; /* fw doesn't need any host buffers */ 1324 1325 /* spin till we get enough memory */ 1326 while (host_page_buffer_sz > 0) { 1327 ioc->HostPageBuffer = 1328 dma_alloc_coherent(&ioc->pcidev->dev, 1329 host_page_buffer_sz, 1330 &ioc->HostPageBuffer_dma, 1331 GFP_KERNEL); 1332 if (ioc->HostPageBuffer) { 1333 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 1334 "host_page_buffer @ %p, dma @ %x, sz=%d bytes\n", 1335 ioc->name, ioc->HostPageBuffer, 1336 (u32)ioc->HostPageBuffer_dma, 1337 host_page_buffer_sz)); 1338 ioc->alloc_total += host_page_buffer_sz; 1339 ioc->HostPageBuffer_sz = host_page_buffer_sz; 1340 break; 1341 } 1342 1343 host_page_buffer_sz -= (4*1024); 1344 } 1345 } 1346 1347 if(!ioc->HostPageBuffer) { 1348 printk(MYIOC_s_ERR_FMT 1349 "Failed to alloc memory for host_page_buffer!\n", 1350 ioc->name); 1351 return -999; 1352 } 1353 1354 psge = (char *)&ioc_init->HostPageBufferSGE; 1355 flags_length = MPI_SGE_FLAGS_SIMPLE_ELEMENT | 1356 MPI_SGE_FLAGS_SYSTEM_ADDRESS | 1357 MPI_SGE_FLAGS_HOST_TO_IOC | 1358 MPI_SGE_FLAGS_END_OF_BUFFER; 1359 flags_length = flags_length << MPI_SGE_FLAGS_SHIFT; 1360 flags_length |= ioc->HostPageBuffer_sz; 1361 ioc->add_sge(psge, flags_length, ioc->HostPageBuffer_dma); 1362 ioc->facts.HostPageBufferSGE = ioc_init->HostPageBufferSGE; 1363 1364 return 0; 1365 } 1366 1367 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1368 /** 1369 * mpt_verify_adapter - Given IOC identifier, set pointer to its adapter structure. 1370 * @iocid: IOC unique identifier (integer) 1371 * @iocpp: Pointer to pointer to IOC adapter 1372 * 1373 * Given a unique IOC identifier, set pointer to the associated MPT 1374 * adapter structure. 1375 * 1376 * Returns iocid and sets iocpp if iocid is found. 1377 * Returns -1 if iocid is not found. 1378 */ 1379 int 1380 mpt_verify_adapter(int iocid, MPT_ADAPTER **iocpp) 1381 { 1382 MPT_ADAPTER *ioc; 1383 1384 list_for_each_entry(ioc,&ioc_list,list) { 1385 if (ioc->id == iocid) { 1386 *iocpp =ioc; 1387 return iocid; 1388 } 1389 } 1390 1391 *iocpp = NULL; 1392 return -1; 1393 } 1394 1395 /** 1396 * mpt_get_product_name - returns product string 1397 * @vendor: pci vendor id 1398 * @device: pci device id 1399 * @revision: pci revision id 1400 * 1401 * Returns product string displayed when driver loads, 1402 * in /proc/mpt/summary and /sysfs/class/scsi_host/host<X>/version_product 1403 * 1404 **/ 1405 static const char* 1406 mpt_get_product_name(u16 vendor, u16 device, u8 revision) 1407 { 1408 char *product_str = NULL; 1409 1410 if (vendor == PCI_VENDOR_ID_BROCADE) { 1411 switch (device) 1412 { 1413 case MPI_MANUFACTPAGE_DEVICEID_FC949E: 1414 switch (revision) 1415 { 1416 case 0x00: 1417 product_str = "BRE040 A0"; 1418 break; 1419 case 0x01: 1420 product_str = "BRE040 A1"; 1421 break; 1422 default: 1423 product_str = "BRE040"; 1424 break; 1425 } 1426 break; 1427 } 1428 goto out; 1429 } 1430 1431 switch (device) 1432 { 1433 case MPI_MANUFACTPAGE_DEVICEID_FC909: 1434 product_str = "LSIFC909 B1"; 1435 break; 1436 case MPI_MANUFACTPAGE_DEVICEID_FC919: 1437 product_str = "LSIFC919 B0"; 1438 break; 1439 case MPI_MANUFACTPAGE_DEVICEID_FC929: 1440 product_str = "LSIFC929 B0"; 1441 break; 1442 case MPI_MANUFACTPAGE_DEVICEID_FC919X: 1443 if (revision < 0x80) 1444 product_str = "LSIFC919X A0"; 1445 else 1446 product_str = "LSIFC919XL A1"; 1447 break; 1448 case MPI_MANUFACTPAGE_DEVICEID_FC929X: 1449 if (revision < 0x80) 1450 product_str = "LSIFC929X A0"; 1451 else 1452 product_str = "LSIFC929XL A1"; 1453 break; 1454 case MPI_MANUFACTPAGE_DEVICEID_FC939X: 1455 product_str = "LSIFC939X A1"; 1456 break; 1457 case MPI_MANUFACTPAGE_DEVICEID_FC949X: 1458 product_str = "LSIFC949X A1"; 1459 break; 1460 case MPI_MANUFACTPAGE_DEVICEID_FC949E: 1461 switch (revision) 1462 { 1463 case 0x00: 1464 product_str = "LSIFC949E A0"; 1465 break; 1466 case 0x01: 1467 product_str = "LSIFC949E A1"; 1468 break; 1469 default: 1470 product_str = "LSIFC949E"; 1471 break; 1472 } 1473 break; 1474 case MPI_MANUFACTPAGE_DEVID_53C1030: 1475 switch (revision) 1476 { 1477 case 0x00: 1478 product_str = "LSI53C1030 A0"; 1479 break; 1480 case 0x01: 1481 product_str = "LSI53C1030 B0"; 1482 break; 1483 case 0x03: 1484 product_str = "LSI53C1030 B1"; 1485 break; 1486 case 0x07: 1487 product_str = "LSI53C1030 B2"; 1488 break; 1489 case 0x08: 1490 product_str = "LSI53C1030 C0"; 1491 break; 1492 case 0x80: 1493 product_str = "LSI53C1030T A0"; 1494 break; 1495 case 0x83: 1496 product_str = "LSI53C1030T A2"; 1497 break; 1498 case 0x87: 1499 product_str = "LSI53C1030T A3"; 1500 break; 1501 case 0xc1: 1502 product_str = "LSI53C1020A A1"; 1503 break; 1504 default: 1505 product_str = "LSI53C1030"; 1506 break; 1507 } 1508 break; 1509 case MPI_MANUFACTPAGE_DEVID_1030_53C1035: 1510 switch (revision) 1511 { 1512 case 0x03: 1513 product_str = "LSI53C1035 A2"; 1514 break; 1515 case 0x04: 1516 product_str = "LSI53C1035 B0"; 1517 break; 1518 default: 1519 product_str = "LSI53C1035"; 1520 break; 1521 } 1522 break; 1523 case MPI_MANUFACTPAGE_DEVID_SAS1064: 1524 switch (revision) 1525 { 1526 case 0x00: 1527 product_str = "LSISAS1064 A1"; 1528 break; 1529 case 0x01: 1530 product_str = "LSISAS1064 A2"; 1531 break; 1532 case 0x02: 1533 product_str = "LSISAS1064 A3"; 1534 break; 1535 case 0x03: 1536 product_str = "LSISAS1064 A4"; 1537 break; 1538 default: 1539 product_str = "LSISAS1064"; 1540 break; 1541 } 1542 break; 1543 case MPI_MANUFACTPAGE_DEVID_SAS1064E: 1544 switch (revision) 1545 { 1546 case 0x00: 1547 product_str = "LSISAS1064E A0"; 1548 break; 1549 case 0x01: 1550 product_str = "LSISAS1064E B0"; 1551 break; 1552 case 0x02: 1553 product_str = "LSISAS1064E B1"; 1554 break; 1555 case 0x04: 1556 product_str = "LSISAS1064E B2"; 1557 break; 1558 case 0x08: 1559 product_str = "LSISAS1064E B3"; 1560 break; 1561 default: 1562 product_str = "LSISAS1064E"; 1563 break; 1564 } 1565 break; 1566 case MPI_MANUFACTPAGE_DEVID_SAS1068: 1567 switch (revision) 1568 { 1569 case 0x00: 1570 product_str = "LSISAS1068 A0"; 1571 break; 1572 case 0x01: 1573 product_str = "LSISAS1068 B0"; 1574 break; 1575 case 0x02: 1576 product_str = "LSISAS1068 B1"; 1577 break; 1578 default: 1579 product_str = "LSISAS1068"; 1580 break; 1581 } 1582 break; 1583 case MPI_MANUFACTPAGE_DEVID_SAS1068E: 1584 switch (revision) 1585 { 1586 case 0x00: 1587 product_str = "LSISAS1068E A0"; 1588 break; 1589 case 0x01: 1590 product_str = "LSISAS1068E B0"; 1591 break; 1592 case 0x02: 1593 product_str = "LSISAS1068E B1"; 1594 break; 1595 case 0x04: 1596 product_str = "LSISAS1068E B2"; 1597 break; 1598 case 0x08: 1599 product_str = "LSISAS1068E B3"; 1600 break; 1601 default: 1602 product_str = "LSISAS1068E"; 1603 break; 1604 } 1605 break; 1606 case MPI_MANUFACTPAGE_DEVID_SAS1078: 1607 switch (revision) 1608 { 1609 case 0x00: 1610 product_str = "LSISAS1078 A0"; 1611 break; 1612 case 0x01: 1613 product_str = "LSISAS1078 B0"; 1614 break; 1615 case 0x02: 1616 product_str = "LSISAS1078 C0"; 1617 break; 1618 case 0x03: 1619 product_str = "LSISAS1078 C1"; 1620 break; 1621 case 0x04: 1622 product_str = "LSISAS1078 C2"; 1623 break; 1624 default: 1625 product_str = "LSISAS1078"; 1626 break; 1627 } 1628 break; 1629 } 1630 1631 out: 1632 return product_str; 1633 } 1634 1635 /** 1636 * mpt_mapresources - map in memory mapped io 1637 * @ioc: Pointer to pointer to IOC adapter 1638 * 1639 **/ 1640 static int 1641 mpt_mapresources(MPT_ADAPTER *ioc) 1642 { 1643 u8 __iomem *mem; 1644 int ii; 1645 resource_size_t mem_phys; 1646 unsigned long port; 1647 u32 msize; 1648 u32 psize; 1649 int r = -ENODEV; 1650 struct pci_dev *pdev; 1651 1652 pdev = ioc->pcidev; 1653 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 1654 if (pci_enable_device_mem(pdev)) { 1655 printk(MYIOC_s_ERR_FMT "pci_enable_device_mem() " 1656 "failed\n", ioc->name); 1657 return r; 1658 } 1659 if (pci_request_selected_regions(pdev, ioc->bars, "mpt")) { 1660 printk(MYIOC_s_ERR_FMT "pci_request_selected_regions() with " 1661 "MEM failed\n", ioc->name); 1662 goto out_pci_disable_device; 1663 } 1664 1665 if (sizeof(dma_addr_t) > 4) { 1666 const uint64_t required_mask = dma_get_required_mask 1667 (&pdev->dev); 1668 if (required_mask > DMA_BIT_MASK(32) 1669 && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) 1670 && !pci_set_consistent_dma_mask(pdev, 1671 DMA_BIT_MASK(64))) { 1672 ioc->dma_mask = DMA_BIT_MASK(64); 1673 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 1674 ": 64 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", 1675 ioc->name)); 1676 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) 1677 && !pci_set_consistent_dma_mask(pdev, 1678 DMA_BIT_MASK(32))) { 1679 ioc->dma_mask = DMA_BIT_MASK(32); 1680 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 1681 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", 1682 ioc->name)); 1683 } else { 1684 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n", 1685 ioc->name, pci_name(pdev)); 1686 goto out_pci_release_region; 1687 } 1688 } else { 1689 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) 1690 && !pci_set_consistent_dma_mask(pdev, 1691 DMA_BIT_MASK(32))) { 1692 ioc->dma_mask = DMA_BIT_MASK(32); 1693 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 1694 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", 1695 ioc->name)); 1696 } else { 1697 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n", 1698 ioc->name, pci_name(pdev)); 1699 goto out_pci_release_region; 1700 } 1701 } 1702 1703 mem_phys = msize = 0; 1704 port = psize = 0; 1705 for (ii = 0; ii < DEVICE_COUNT_RESOURCE; ii++) { 1706 if (pci_resource_flags(pdev, ii) & PCI_BASE_ADDRESS_SPACE_IO) { 1707 if (psize) 1708 continue; 1709 /* Get I/O space! */ 1710 port = pci_resource_start(pdev, ii); 1711 psize = pci_resource_len(pdev, ii); 1712 } else { 1713 if (msize) 1714 continue; 1715 /* Get memmap */ 1716 mem_phys = pci_resource_start(pdev, ii); 1717 msize = pci_resource_len(pdev, ii); 1718 } 1719 } 1720 ioc->mem_size = msize; 1721 1722 mem = NULL; 1723 /* Get logical ptr for PciMem0 space */ 1724 /*mem = ioremap(mem_phys, msize);*/ 1725 mem = ioremap(mem_phys, msize); 1726 if (mem == NULL) { 1727 printk(MYIOC_s_ERR_FMT ": ERROR - Unable to map adapter" 1728 " memory!\n", ioc->name); 1729 r = -EINVAL; 1730 goto out_pci_release_region; 1731 } 1732 ioc->memmap = mem; 1733 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "mem = %p, mem_phys = %llx\n", 1734 ioc->name, mem, (unsigned long long)mem_phys)); 1735 1736 ioc->mem_phys = mem_phys; 1737 ioc->chip = (SYSIF_REGS __iomem *)mem; 1738 1739 /* Save Port IO values in case we need to do downloadboot */ 1740 ioc->pio_mem_phys = port; 1741 ioc->pio_chip = (SYSIF_REGS __iomem *)port; 1742 1743 return 0; 1744 1745 out_pci_release_region: 1746 pci_release_selected_regions(pdev, ioc->bars); 1747 out_pci_disable_device: 1748 pci_disable_device(pdev); 1749 return r; 1750 } 1751 1752 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1753 /** 1754 * mpt_attach - Install a PCI intelligent MPT adapter. 1755 * @pdev: Pointer to pci_dev structure 1756 * @id: PCI device ID information 1757 * 1758 * This routine performs all the steps necessary to bring the IOC of 1759 * a MPT adapter to a OPERATIONAL state. This includes registering 1760 * memory regions, registering the interrupt, and allocating request 1761 * and reply memory pools. 1762 * 1763 * This routine also pre-fetches the LAN MAC address of a Fibre Channel 1764 * MPT adapter. 1765 * 1766 * Returns 0 for success, non-zero for failure. 1767 * 1768 * TODO: Add support for polled controllers 1769 */ 1770 int 1771 mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id) 1772 { 1773 MPT_ADAPTER *ioc; 1774 u8 cb_idx; 1775 int r = -ENODEV; 1776 u8 pcixcmd; 1777 static int mpt_ids = 0; 1778 #ifdef CONFIG_PROC_FS 1779 struct proc_dir_entry *dent; 1780 #endif 1781 1782 ioc = kzalloc(sizeof(MPT_ADAPTER), GFP_KERNEL); 1783 if (ioc == NULL) { 1784 printk(KERN_ERR MYNAM ": ERROR - Insufficient memory to add adapter!\n"); 1785 return -ENOMEM; 1786 } 1787 1788 ioc->id = mpt_ids++; 1789 sprintf(ioc->name, "ioc%d", ioc->id); 1790 dinitprintk(ioc, printk(KERN_WARNING MYNAM ": mpt_adapter_install\n")); 1791 1792 /* 1793 * set initial debug level 1794 * (refer to mptdebug.h) 1795 * 1796 */ 1797 ioc->debug_level = mpt_debug_level; 1798 if (mpt_debug_level) 1799 printk(KERN_INFO "mpt_debug_level=%xh\n", mpt_debug_level); 1800 1801 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": mpt_adapter_install\n", ioc->name)); 1802 1803 ioc->pcidev = pdev; 1804 if (mpt_mapresources(ioc)) { 1805 goto out_free_ioc; 1806 } 1807 1808 /* 1809 * Setting up proper handlers for scatter gather handling 1810 */ 1811 if (ioc->dma_mask == DMA_BIT_MASK(64)) { 1812 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) 1813 ioc->add_sge = &mpt_add_sge_64bit_1078; 1814 else 1815 ioc->add_sge = &mpt_add_sge_64bit; 1816 ioc->add_chain = &mpt_add_chain_64bit; 1817 ioc->sg_addr_size = 8; 1818 } else { 1819 ioc->add_sge = &mpt_add_sge; 1820 ioc->add_chain = &mpt_add_chain; 1821 ioc->sg_addr_size = 4; 1822 } 1823 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size; 1824 1825 ioc->alloc_total = sizeof(MPT_ADAPTER); 1826 ioc->req_sz = MPT_DEFAULT_FRAME_SIZE; /* avoid div by zero! */ 1827 ioc->reply_sz = MPT_REPLY_FRAME_SIZE; 1828 1829 1830 spin_lock_init(&ioc->taskmgmt_lock); 1831 mutex_init(&ioc->internal_cmds.mutex); 1832 init_completion(&ioc->internal_cmds.done); 1833 mutex_init(&ioc->mptbase_cmds.mutex); 1834 init_completion(&ioc->mptbase_cmds.done); 1835 mutex_init(&ioc->taskmgmt_cmds.mutex); 1836 init_completion(&ioc->taskmgmt_cmds.done); 1837 1838 /* Initialize the event logging. 1839 */ 1840 ioc->eventTypes = 0; /* None */ 1841 ioc->eventContext = 0; 1842 ioc->eventLogSize = 0; 1843 ioc->events = NULL; 1844 1845 #ifdef MFCNT 1846 ioc->mfcnt = 0; 1847 #endif 1848 1849 ioc->sh = NULL; 1850 ioc->cached_fw = NULL; 1851 1852 /* Initialize SCSI Config Data structure 1853 */ 1854 memset(&ioc->spi_data, 0, sizeof(SpiCfgData)); 1855 1856 /* Initialize the fc rport list head. 1857 */ 1858 INIT_LIST_HEAD(&ioc->fc_rports); 1859 1860 /* Find lookup slot. */ 1861 INIT_LIST_HEAD(&ioc->list); 1862 1863 1864 /* Initialize workqueue */ 1865 INIT_DELAYED_WORK(&ioc->fault_reset_work, mpt_fault_reset_work); 1866 1867 snprintf(ioc->reset_work_q_name, MPT_KOBJ_NAME_LEN, 1868 "mpt_poll_%d", ioc->id); 1869 ioc->reset_work_q = alloc_workqueue(ioc->reset_work_q_name, 1870 WQ_MEM_RECLAIM, 0); 1871 if (!ioc->reset_work_q) { 1872 printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n", 1873 ioc->name); 1874 r = -ENOMEM; 1875 goto out_unmap_resources; 1876 } 1877 1878 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "facts @ %p, pfacts[0] @ %p\n", 1879 ioc->name, &ioc->facts, &ioc->pfacts[0])); 1880 1881 ioc->prod_name = mpt_get_product_name(pdev->vendor, pdev->device, 1882 pdev->revision); 1883 1884 switch (pdev->device) 1885 { 1886 case MPI_MANUFACTPAGE_DEVICEID_FC939X: 1887 case MPI_MANUFACTPAGE_DEVICEID_FC949X: 1888 ioc->errata_flag_1064 = 1; 1889 fallthrough; 1890 case MPI_MANUFACTPAGE_DEVICEID_FC909: 1891 case MPI_MANUFACTPAGE_DEVICEID_FC929: 1892 case MPI_MANUFACTPAGE_DEVICEID_FC919: 1893 case MPI_MANUFACTPAGE_DEVICEID_FC949E: 1894 ioc->bus_type = FC; 1895 break; 1896 1897 case MPI_MANUFACTPAGE_DEVICEID_FC929X: 1898 if (pdev->revision < XL_929) { 1899 /* 929X Chip Fix. Set Split transactions level 1900 * for PCIX. Set MOST bits to zero. 1901 */ 1902 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1903 pcixcmd &= 0x8F; 1904 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1905 } else { 1906 /* 929XL Chip Fix. Set MMRBC to 0x08. 1907 */ 1908 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1909 pcixcmd |= 0x08; 1910 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1911 } 1912 ioc->bus_type = FC; 1913 break; 1914 1915 case MPI_MANUFACTPAGE_DEVICEID_FC919X: 1916 /* 919X Chip Fix. Set Split transactions level 1917 * for PCIX. Set MOST bits to zero. 1918 */ 1919 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1920 pcixcmd &= 0x8F; 1921 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1922 ioc->bus_type = FC; 1923 break; 1924 1925 case MPI_MANUFACTPAGE_DEVID_53C1030: 1926 /* 1030 Chip Fix. Disable Split transactions 1927 * for PCIX. Set MOST bits to zero if Rev < C0( = 8). 1928 */ 1929 if (pdev->revision < C0_1030) { 1930 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1931 pcixcmd &= 0x8F; 1932 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1933 } 1934 fallthrough; 1935 1936 case MPI_MANUFACTPAGE_DEVID_1030_53C1035: 1937 ioc->bus_type = SPI; 1938 break; 1939 1940 case MPI_MANUFACTPAGE_DEVID_SAS1064: 1941 case MPI_MANUFACTPAGE_DEVID_SAS1068: 1942 ioc->errata_flag_1064 = 1; 1943 ioc->bus_type = SAS; 1944 break; 1945 1946 case MPI_MANUFACTPAGE_DEVID_SAS1064E: 1947 case MPI_MANUFACTPAGE_DEVID_SAS1068E: 1948 case MPI_MANUFACTPAGE_DEVID_SAS1078: 1949 ioc->bus_type = SAS; 1950 break; 1951 } 1952 1953 1954 switch (ioc->bus_type) { 1955 1956 case SAS: 1957 ioc->msi_enable = mpt_msi_enable_sas; 1958 break; 1959 1960 case SPI: 1961 ioc->msi_enable = mpt_msi_enable_spi; 1962 break; 1963 1964 case FC: 1965 ioc->msi_enable = mpt_msi_enable_fc; 1966 break; 1967 1968 default: 1969 ioc->msi_enable = 0; 1970 break; 1971 } 1972 1973 ioc->fw_events_off = 1; 1974 1975 if (ioc->errata_flag_1064) 1976 pci_disable_io_access(pdev); 1977 1978 spin_lock_init(&ioc->FreeQlock); 1979 1980 /* Disable all! */ 1981 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 1982 ioc->active = 0; 1983 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1984 1985 /* Set IOC ptr in the pcidev's driver data. */ 1986 pci_set_drvdata(ioc->pcidev, ioc); 1987 1988 /* Set lookup ptr. */ 1989 list_add_tail(&ioc->list, &ioc_list); 1990 1991 /* Check for "bound ports" (929, 929X, 1030, 1035) to reduce redundant resets. 1992 */ 1993 mpt_detect_bound_ports(ioc, pdev); 1994 1995 INIT_LIST_HEAD(&ioc->fw_event_list); 1996 spin_lock_init(&ioc->fw_event_lock); 1997 snprintf(ioc->fw_event_q_name, MPT_KOBJ_NAME_LEN, "mpt/%d", ioc->id); 1998 ioc->fw_event_q = alloc_workqueue(ioc->fw_event_q_name, 1999 WQ_MEM_RECLAIM, 0); 2000 if (!ioc->fw_event_q) { 2001 printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n", 2002 ioc->name); 2003 r = -ENOMEM; 2004 goto out_remove_ioc; 2005 } 2006 2007 if ((r = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP, 2008 CAN_SLEEP)) != 0){ 2009 printk(MYIOC_s_ERR_FMT "didn't initialize properly! (%d)\n", 2010 ioc->name, r); 2011 2012 destroy_workqueue(ioc->fw_event_q); 2013 ioc->fw_event_q = NULL; 2014 2015 list_del(&ioc->list); 2016 if (ioc->alt_ioc) 2017 ioc->alt_ioc->alt_ioc = NULL; 2018 iounmap(ioc->memmap); 2019 if (pci_is_enabled(pdev)) 2020 pci_disable_device(pdev); 2021 if (r != -5) 2022 pci_release_selected_regions(pdev, ioc->bars); 2023 2024 destroy_workqueue(ioc->reset_work_q); 2025 ioc->reset_work_q = NULL; 2026 2027 kfree(ioc); 2028 return r; 2029 } 2030 2031 /* call per device driver probe entry point */ 2032 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) { 2033 if(MptDeviceDriverHandlers[cb_idx] && 2034 MptDeviceDriverHandlers[cb_idx]->probe) { 2035 MptDeviceDriverHandlers[cb_idx]->probe(pdev,id); 2036 } 2037 } 2038 2039 #ifdef CONFIG_PROC_FS 2040 /* 2041 * Create "/proc/mpt/iocN" subdirectory entry for each MPT adapter. 2042 */ 2043 dent = proc_mkdir(ioc->name, mpt_proc_root_dir); 2044 if (dent) { 2045 proc_create_single_data("info", S_IRUGO, dent, 2046 mpt_iocinfo_proc_show, ioc); 2047 proc_create_single_data("summary", S_IRUGO, dent, 2048 mpt_summary_proc_show, ioc); 2049 } 2050 #endif 2051 2052 if (!ioc->alt_ioc) 2053 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work, 2054 msecs_to_jiffies(MPT_POLLING_INTERVAL)); 2055 2056 return 0; 2057 2058 out_remove_ioc: 2059 list_del(&ioc->list); 2060 if (ioc->alt_ioc) 2061 ioc->alt_ioc->alt_ioc = NULL; 2062 2063 destroy_workqueue(ioc->reset_work_q); 2064 ioc->reset_work_q = NULL; 2065 2066 out_unmap_resources: 2067 iounmap(ioc->memmap); 2068 pci_disable_device(pdev); 2069 pci_release_selected_regions(pdev, ioc->bars); 2070 2071 out_free_ioc: 2072 kfree(ioc); 2073 2074 return r; 2075 } 2076 2077 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2078 /** 2079 * mpt_detach - Remove a PCI intelligent MPT adapter. 2080 * @pdev: Pointer to pci_dev structure 2081 */ 2082 2083 void 2084 mpt_detach(struct pci_dev *pdev) 2085 { 2086 MPT_ADAPTER *ioc = pci_get_drvdata(pdev); 2087 char pname[64]; 2088 u8 cb_idx; 2089 unsigned long flags; 2090 struct workqueue_struct *wq; 2091 2092 /* 2093 * Stop polling ioc for fault condition 2094 */ 2095 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 2096 wq = ioc->reset_work_q; 2097 ioc->reset_work_q = NULL; 2098 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 2099 cancel_delayed_work(&ioc->fault_reset_work); 2100 destroy_workqueue(wq); 2101 2102 spin_lock_irqsave(&ioc->fw_event_lock, flags); 2103 wq = ioc->fw_event_q; 2104 ioc->fw_event_q = NULL; 2105 spin_unlock_irqrestore(&ioc->fw_event_lock, flags); 2106 destroy_workqueue(wq); 2107 2108 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/summary", ioc->name); 2109 remove_proc_entry(pname, NULL); 2110 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/info", ioc->name); 2111 remove_proc_entry(pname, NULL); 2112 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s", ioc->name); 2113 remove_proc_entry(pname, NULL); 2114 2115 /* call per device driver remove entry point */ 2116 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) { 2117 if(MptDeviceDriverHandlers[cb_idx] && 2118 MptDeviceDriverHandlers[cb_idx]->remove) { 2119 MptDeviceDriverHandlers[cb_idx]->remove(pdev); 2120 } 2121 } 2122 2123 /* Disable interrupts! */ 2124 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 2125 2126 ioc->active = 0; 2127 synchronize_irq(pdev->irq); 2128 2129 /* Clear any lingering interrupt */ 2130 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 2131 2132 CHIPREG_READ32(&ioc->chip->IntStatus); 2133 2134 mpt_adapter_dispose(ioc); 2135 2136 } 2137 2138 /************************************************************************** 2139 * Power Management 2140 */ 2141 #ifdef CONFIG_PM 2142 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2143 /** 2144 * mpt_suspend - Fusion MPT base driver suspend routine. 2145 * @pdev: Pointer to pci_dev structure 2146 * @state: new state to enter 2147 */ 2148 int 2149 mpt_suspend(struct pci_dev *pdev, pm_message_t state) 2150 { 2151 u32 device_state; 2152 MPT_ADAPTER *ioc = pci_get_drvdata(pdev); 2153 2154 device_state = pci_choose_state(pdev, state); 2155 printk(MYIOC_s_INFO_FMT "pci-suspend: pdev=0x%p, slot=%s, Entering " 2156 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev), 2157 device_state); 2158 2159 /* put ioc into READY_STATE */ 2160 if (SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, CAN_SLEEP)) { 2161 printk(MYIOC_s_ERR_FMT 2162 "pci-suspend: IOC msg unit reset failed!\n", ioc->name); 2163 } 2164 2165 /* disable interrupts */ 2166 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 2167 ioc->active = 0; 2168 2169 /* Clear any lingering interrupt */ 2170 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 2171 2172 free_irq(ioc->pci_irq, ioc); 2173 if (ioc->msi_enable) 2174 pci_disable_msi(ioc->pcidev); 2175 ioc->pci_irq = -1; 2176 pci_save_state(pdev); 2177 pci_disable_device(pdev); 2178 pci_release_selected_regions(pdev, ioc->bars); 2179 pci_set_power_state(pdev, device_state); 2180 return 0; 2181 } 2182 2183 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2184 /** 2185 * mpt_resume - Fusion MPT base driver resume routine. 2186 * @pdev: Pointer to pci_dev structure 2187 */ 2188 int 2189 mpt_resume(struct pci_dev *pdev) 2190 { 2191 MPT_ADAPTER *ioc = pci_get_drvdata(pdev); 2192 u32 device_state = pdev->current_state; 2193 int recovery_state; 2194 int err; 2195 2196 printk(MYIOC_s_INFO_FMT "pci-resume: pdev=0x%p, slot=%s, Previous " 2197 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev), 2198 device_state); 2199 2200 pci_set_power_state(pdev, PCI_D0); 2201 pci_enable_wake(pdev, PCI_D0, 0); 2202 pci_restore_state(pdev); 2203 ioc->pcidev = pdev; 2204 err = mpt_mapresources(ioc); 2205 if (err) 2206 return err; 2207 2208 if (ioc->dma_mask == DMA_BIT_MASK(64)) { 2209 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) 2210 ioc->add_sge = &mpt_add_sge_64bit_1078; 2211 else 2212 ioc->add_sge = &mpt_add_sge_64bit; 2213 ioc->add_chain = &mpt_add_chain_64bit; 2214 ioc->sg_addr_size = 8; 2215 } else { 2216 2217 ioc->add_sge = &mpt_add_sge; 2218 ioc->add_chain = &mpt_add_chain; 2219 ioc->sg_addr_size = 4; 2220 } 2221 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size; 2222 2223 printk(MYIOC_s_INFO_FMT "pci-resume: ioc-state=0x%x,doorbell=0x%x\n", 2224 ioc->name, (mpt_GetIocState(ioc, 1) >> MPI_IOC_STATE_SHIFT), 2225 CHIPREG_READ32(&ioc->chip->Doorbell)); 2226 2227 /* 2228 * Errata workaround for SAS pci express: 2229 * Upon returning to the D0 state, the contents of the doorbell will be 2230 * stale data, and this will incorrectly signal to the host driver that 2231 * the firmware is ready to process mpt commands. The workaround is 2232 * to issue a diagnostic reset. 2233 */ 2234 if (ioc->bus_type == SAS && (pdev->device == 2235 MPI_MANUFACTPAGE_DEVID_SAS1068E || pdev->device == 2236 MPI_MANUFACTPAGE_DEVID_SAS1064E)) { 2237 if (KickStart(ioc, 1, CAN_SLEEP) < 0) { 2238 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover\n", 2239 ioc->name); 2240 goto out; 2241 } 2242 } 2243 2244 /* bring ioc to operational state */ 2245 printk(MYIOC_s_INFO_FMT "Sending mpt_do_ioc_recovery\n", ioc->name); 2246 recovery_state = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP, 2247 CAN_SLEEP); 2248 if (recovery_state != 0) 2249 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover, " 2250 "error:[%x]\n", ioc->name, recovery_state); 2251 else 2252 printk(MYIOC_s_INFO_FMT 2253 "pci-resume: success\n", ioc->name); 2254 out: 2255 return 0; 2256 2257 } 2258 #endif 2259 2260 static int 2261 mpt_signal_reset(u8 index, MPT_ADAPTER *ioc, int reset_phase) 2262 { 2263 if ((MptDriverClass[index] == MPTSPI_DRIVER && 2264 ioc->bus_type != SPI) || 2265 (MptDriverClass[index] == MPTFC_DRIVER && 2266 ioc->bus_type != FC) || 2267 (MptDriverClass[index] == MPTSAS_DRIVER && 2268 ioc->bus_type != SAS)) 2269 /* make sure we only call the relevant reset handler 2270 * for the bus */ 2271 return 0; 2272 return (MptResetHandlers[index])(ioc, reset_phase); 2273 } 2274 2275 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2276 /** 2277 * mpt_do_ioc_recovery - Initialize or recover MPT adapter. 2278 * @ioc: Pointer to MPT adapter structure 2279 * @reason: Event word / reason 2280 * @sleepFlag: Use schedule if CAN_SLEEP else use udelay. 2281 * 2282 * This routine performs all the steps necessary to bring the IOC 2283 * to a OPERATIONAL state. 2284 * 2285 * This routine also pre-fetches the LAN MAC address of a Fibre Channel 2286 * MPT adapter. 2287 * 2288 * Returns: 2289 * 0 for success 2290 * -1 if failed to get board READY 2291 * -2 if READY but IOCFacts Failed 2292 * -3 if READY but PrimeIOCFifos Failed 2293 * -4 if READY but IOCInit Failed 2294 * -5 if failed to enable_device and/or request_selected_regions 2295 * -6 if failed to upload firmware 2296 */ 2297 static int 2298 mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag) 2299 { 2300 int hard_reset_done = 0; 2301 int alt_ioc_ready = 0; 2302 int hard; 2303 int rc=0; 2304 int ii; 2305 int ret = 0; 2306 int reset_alt_ioc_active = 0; 2307 int irq_allocated = 0; 2308 u8 *a; 2309 2310 printk(MYIOC_s_INFO_FMT "Initiating %s\n", ioc->name, 2311 reason == MPT_HOSTEVENT_IOC_BRINGUP ? "bringup" : "recovery"); 2312 2313 /* Disable reply interrupts (also blocks FreeQ) */ 2314 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 2315 ioc->active = 0; 2316 2317 if (ioc->alt_ioc) { 2318 if (ioc->alt_ioc->active || 2319 reason == MPT_HOSTEVENT_IOC_RECOVER) { 2320 reset_alt_ioc_active = 1; 2321 /* Disable alt-IOC's reply interrupts 2322 * (and FreeQ) for a bit 2323 **/ 2324 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, 2325 0xFFFFFFFF); 2326 ioc->alt_ioc->active = 0; 2327 } 2328 } 2329 2330 hard = 1; 2331 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) 2332 hard = 0; 2333 2334 if ((hard_reset_done = MakeIocReady(ioc, hard, sleepFlag)) < 0) { 2335 if (hard_reset_done == -4) { 2336 printk(MYIOC_s_WARN_FMT "Owned by PEER..skipping!\n", 2337 ioc->name); 2338 2339 if (reset_alt_ioc_active && ioc->alt_ioc) { 2340 /* (re)Enable alt-IOC! (reply interrupt, FreeQ) */ 2341 dprintk(ioc, printk(MYIOC_s_INFO_FMT 2342 "alt_ioc reply irq re-enabled\n", ioc->alt_ioc->name)); 2343 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, MPI_HIM_DIM); 2344 ioc->alt_ioc->active = 1; 2345 } 2346 2347 } else { 2348 printk(MYIOC_s_WARN_FMT 2349 "NOT READY WARNING!\n", ioc->name); 2350 } 2351 ret = -1; 2352 goto out; 2353 } 2354 2355 /* hard_reset_done = 0 if a soft reset was performed 2356 * and 1 if a hard reset was performed. 2357 */ 2358 if (hard_reset_done && reset_alt_ioc_active && ioc->alt_ioc) { 2359 if ((rc = MakeIocReady(ioc->alt_ioc, 0, sleepFlag)) == 0) 2360 alt_ioc_ready = 1; 2361 else 2362 printk(MYIOC_s_WARN_FMT 2363 ": alt-ioc Not ready WARNING!\n", 2364 ioc->alt_ioc->name); 2365 } 2366 2367 for (ii=0; ii<5; ii++) { 2368 /* Get IOC facts! Allow 5 retries */ 2369 if ((rc = GetIocFacts(ioc, sleepFlag, reason)) == 0) 2370 break; 2371 } 2372 2373 2374 if (ii == 5) { 2375 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2376 "Retry IocFacts failed rc=%x\n", ioc->name, rc)); 2377 ret = -2; 2378 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) { 2379 MptDisplayIocCapabilities(ioc); 2380 } 2381 2382 if (alt_ioc_ready) { 2383 if ((rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason)) != 0) { 2384 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2385 "Initial Alt IocFacts failed rc=%x\n", 2386 ioc->name, rc)); 2387 /* Retry - alt IOC was initialized once 2388 */ 2389 rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason); 2390 } 2391 if (rc) { 2392 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2393 "Retry Alt IocFacts failed rc=%x\n", ioc->name, rc)); 2394 alt_ioc_ready = 0; 2395 reset_alt_ioc_active = 0; 2396 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) { 2397 MptDisplayIocCapabilities(ioc->alt_ioc); 2398 } 2399 } 2400 2401 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP) && 2402 (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)) { 2403 pci_release_selected_regions(ioc->pcidev, ioc->bars); 2404 ioc->bars = pci_select_bars(ioc->pcidev, IORESOURCE_MEM | 2405 IORESOURCE_IO); 2406 if (pci_enable_device(ioc->pcidev)) 2407 return -5; 2408 if (pci_request_selected_regions(ioc->pcidev, ioc->bars, 2409 "mpt")) 2410 return -5; 2411 } 2412 2413 /* 2414 * Device is reset now. It must have de-asserted the interrupt line 2415 * (if it was asserted) and it should be safe to register for the 2416 * interrupt now. 2417 */ 2418 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) { 2419 ioc->pci_irq = -1; 2420 if (ioc->pcidev->irq) { 2421 if (ioc->msi_enable && !pci_enable_msi(ioc->pcidev)) 2422 printk(MYIOC_s_INFO_FMT "PCI-MSI enabled\n", 2423 ioc->name); 2424 else 2425 ioc->msi_enable = 0; 2426 rc = request_irq(ioc->pcidev->irq, mpt_interrupt, 2427 IRQF_SHARED, ioc->name, ioc); 2428 if (rc < 0) { 2429 printk(MYIOC_s_ERR_FMT "Unable to allocate " 2430 "interrupt %d!\n", 2431 ioc->name, ioc->pcidev->irq); 2432 if (ioc->msi_enable) 2433 pci_disable_msi(ioc->pcidev); 2434 ret = -EBUSY; 2435 goto out; 2436 } 2437 irq_allocated = 1; 2438 ioc->pci_irq = ioc->pcidev->irq; 2439 pci_set_master(ioc->pcidev); /* ?? */ 2440 pci_set_drvdata(ioc->pcidev, ioc); 2441 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 2442 "installed at interrupt %d\n", ioc->name, 2443 ioc->pcidev->irq)); 2444 } 2445 } 2446 2447 /* Prime reply & request queues! 2448 * (mucho alloc's) Must be done prior to 2449 * init as upper addresses are needed for init. 2450 * If fails, continue with alt-ioc processing 2451 */ 2452 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "PrimeIocFifos\n", 2453 ioc->name)); 2454 if ((ret == 0) && ((rc = PrimeIocFifos(ioc)) != 0)) 2455 ret = -3; 2456 2457 /* May need to check/upload firmware & data here! 2458 * If fails, continue with alt-ioc processing 2459 */ 2460 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "SendIocInit\n", 2461 ioc->name)); 2462 if ((ret == 0) && ((rc = SendIocInit(ioc, sleepFlag)) != 0)) 2463 ret = -4; 2464 // NEW! 2465 if (alt_ioc_ready && ((rc = PrimeIocFifos(ioc->alt_ioc)) != 0)) { 2466 printk(MYIOC_s_WARN_FMT 2467 ": alt-ioc (%d) FIFO mgmt alloc WARNING!\n", 2468 ioc->alt_ioc->name, rc); 2469 alt_ioc_ready = 0; 2470 reset_alt_ioc_active = 0; 2471 } 2472 2473 if (alt_ioc_ready) { 2474 if ((rc = SendIocInit(ioc->alt_ioc, sleepFlag)) != 0) { 2475 alt_ioc_ready = 0; 2476 reset_alt_ioc_active = 0; 2477 printk(MYIOC_s_WARN_FMT 2478 ": alt-ioc: (%d) init failure WARNING!\n", 2479 ioc->alt_ioc->name, rc); 2480 } 2481 } 2482 2483 if (reason == MPT_HOSTEVENT_IOC_BRINGUP){ 2484 if (ioc->upload_fw) { 2485 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2486 "firmware upload required!\n", ioc->name)); 2487 2488 /* Controller is not operational, cannot do upload 2489 */ 2490 if (ret == 0) { 2491 rc = mpt_do_upload(ioc, sleepFlag); 2492 if (rc == 0) { 2493 if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) { 2494 /* 2495 * Maintain only one pointer to FW memory 2496 * so there will not be two attempt to 2497 * downloadboot onboard dual function 2498 * chips (mpt_adapter_disable, 2499 * mpt_diag_reset) 2500 */ 2501 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2502 "mpt_upload: alt_%s has cached_fw=%p \n", 2503 ioc->name, ioc->alt_ioc->name, ioc->alt_ioc->cached_fw)); 2504 ioc->cached_fw = NULL; 2505 } 2506 } else { 2507 printk(MYIOC_s_WARN_FMT 2508 "firmware upload failure!\n", ioc->name); 2509 ret = -6; 2510 } 2511 } 2512 } 2513 } 2514 2515 /* Enable MPT base driver management of EventNotification 2516 * and EventAck handling. 2517 */ 2518 if ((ret == 0) && (!ioc->facts.EventState)) { 2519 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 2520 "SendEventNotification\n", 2521 ioc->name)); 2522 ret = SendEventNotification(ioc, 1, sleepFlag); /* 1=Enable */ 2523 } 2524 2525 if (ioc->alt_ioc && alt_ioc_ready && !ioc->alt_ioc->facts.EventState) 2526 rc = SendEventNotification(ioc->alt_ioc, 1, sleepFlag); 2527 2528 if (ret == 0) { 2529 /* Enable! (reply interrupt) */ 2530 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM); 2531 ioc->active = 1; 2532 } 2533 if (rc == 0) { /* alt ioc */ 2534 if (reset_alt_ioc_active && ioc->alt_ioc) { 2535 /* (re)Enable alt-IOC! (reply interrupt) */ 2536 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "alt-ioc" 2537 "reply irq re-enabled\n", 2538 ioc->alt_ioc->name)); 2539 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, 2540 MPI_HIM_DIM); 2541 ioc->alt_ioc->active = 1; 2542 } 2543 } 2544 2545 2546 /* Add additional "reason" check before call to GetLanConfigPages 2547 * (combined with GetIoUnitPage2 call). This prevents a somewhat 2548 * recursive scenario; GetLanConfigPages times out, timer expired 2549 * routine calls HardResetHandler, which calls into here again, 2550 * and we try GetLanConfigPages again... 2551 */ 2552 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) { 2553 2554 /* 2555 * Initialize link list for inactive raid volumes. 2556 */ 2557 mutex_init(&ioc->raid_data.inactive_list_mutex); 2558 INIT_LIST_HEAD(&ioc->raid_data.inactive_list); 2559 2560 switch (ioc->bus_type) { 2561 2562 case SAS: 2563 /* clear persistency table */ 2564 if(ioc->facts.IOCExceptions & 2565 MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL) { 2566 ret = mptbase_sas_persist_operation(ioc, 2567 MPI_SAS_OP_CLEAR_NOT_PRESENT); 2568 if(ret != 0) 2569 goto out; 2570 } 2571 2572 /* Find IM volumes 2573 */ 2574 mpt_findImVolumes(ioc); 2575 2576 /* Check, and possibly reset, the coalescing value 2577 */ 2578 mpt_read_ioc_pg_1(ioc); 2579 2580 break; 2581 2582 case FC: 2583 if ((ioc->pfacts[0].ProtocolFlags & 2584 MPI_PORTFACTS_PROTOCOL_LAN) && 2585 (ioc->lan_cnfg_page0.Header.PageLength == 0)) { 2586 /* 2587 * Pre-fetch the ports LAN MAC address! 2588 * (LANPage1_t stuff) 2589 */ 2590 (void) GetLanConfigPages(ioc); 2591 a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow; 2592 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2593 "LanAddr = %pMR\n", ioc->name, a)); 2594 } 2595 break; 2596 2597 case SPI: 2598 /* Get NVRAM and adapter maximums from SPP 0 and 2 2599 */ 2600 mpt_GetScsiPortSettings(ioc, 0); 2601 2602 /* Get version and length of SDP 1 2603 */ 2604 mpt_readScsiDevicePageHeaders(ioc, 0); 2605 2606 /* Find IM volumes 2607 */ 2608 if (ioc->facts.MsgVersion >= MPI_VERSION_01_02) 2609 mpt_findImVolumes(ioc); 2610 2611 /* Check, and possibly reset, the coalescing value 2612 */ 2613 mpt_read_ioc_pg_1(ioc); 2614 2615 mpt_read_ioc_pg_4(ioc); 2616 2617 break; 2618 } 2619 2620 GetIoUnitPage2(ioc); 2621 mpt_get_manufacturing_pg_0(ioc); 2622 } 2623 2624 out: 2625 if ((ret != 0) && irq_allocated) { 2626 free_irq(ioc->pci_irq, ioc); 2627 if (ioc->msi_enable) 2628 pci_disable_msi(ioc->pcidev); 2629 } 2630 return ret; 2631 } 2632 2633 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2634 /** 2635 * mpt_detect_bound_ports - Search for matching PCI bus/dev_function 2636 * @ioc: Pointer to MPT adapter structure 2637 * @pdev: Pointer to (struct pci_dev) structure 2638 * 2639 * Search for PCI bus/dev_function which matches 2640 * PCI bus/dev_function (+/-1) for newly discovered 929, 2641 * 929X, 1030 or 1035. 2642 * 2643 * If match on PCI dev_function +/-1 is found, bind the two MPT adapters 2644 * using alt_ioc pointer fields in their %MPT_ADAPTER structures. 2645 */ 2646 static void 2647 mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev) 2648 { 2649 struct pci_dev *peer=NULL; 2650 unsigned int slot = PCI_SLOT(pdev->devfn); 2651 unsigned int func = PCI_FUNC(pdev->devfn); 2652 MPT_ADAPTER *ioc_srch; 2653 2654 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "PCI device %s devfn=%x/%x," 2655 " searching for devfn match on %x or %x\n", 2656 ioc->name, pci_name(pdev), pdev->bus->number, 2657 pdev->devfn, func-1, func+1)); 2658 2659 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func-1)); 2660 if (!peer) { 2661 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func+1)); 2662 if (!peer) 2663 return; 2664 } 2665 2666 list_for_each_entry(ioc_srch, &ioc_list, list) { 2667 struct pci_dev *_pcidev = ioc_srch->pcidev; 2668 if (_pcidev == peer) { 2669 /* Paranoia checks */ 2670 if (ioc->alt_ioc != NULL) { 2671 printk(MYIOC_s_WARN_FMT 2672 "Oops, already bound (%s <==> %s)!\n", 2673 ioc->name, ioc->name, ioc->alt_ioc->name); 2674 break; 2675 } else if (ioc_srch->alt_ioc != NULL) { 2676 printk(MYIOC_s_WARN_FMT 2677 "Oops, already bound (%s <==> %s)!\n", 2678 ioc_srch->name, ioc_srch->name, 2679 ioc_srch->alt_ioc->name); 2680 break; 2681 } 2682 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2683 "FOUND! binding %s <==> %s\n", 2684 ioc->name, ioc->name, ioc_srch->name)); 2685 ioc_srch->alt_ioc = ioc; 2686 ioc->alt_ioc = ioc_srch; 2687 } 2688 } 2689 pci_dev_put(peer); 2690 } 2691 2692 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2693 /** 2694 * mpt_adapter_disable - Disable misbehaving MPT adapter. 2695 * @ioc: Pointer to MPT adapter structure 2696 */ 2697 static void 2698 mpt_adapter_disable(MPT_ADAPTER *ioc) 2699 { 2700 int sz; 2701 int ret; 2702 2703 if (ioc->cached_fw != NULL) { 2704 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2705 "%s: Pushing FW onto adapter\n", __func__, ioc->name)); 2706 if ((ret = mpt_downloadboot(ioc, (MpiFwHeader_t *) 2707 ioc->cached_fw, CAN_SLEEP)) < 0) { 2708 printk(MYIOC_s_WARN_FMT 2709 ": firmware downloadboot failure (%d)!\n", 2710 ioc->name, ret); 2711 } 2712 } 2713 2714 /* 2715 * Put the controller into ready state (if its not already) 2716 */ 2717 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) { 2718 if (!SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, 2719 CAN_SLEEP)) { 2720 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) 2721 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit " 2722 "reset failed to put ioc in ready state!\n", 2723 ioc->name, __func__); 2724 } else 2725 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit reset " 2726 "failed!\n", ioc->name, __func__); 2727 } 2728 2729 2730 /* Disable adapter interrupts! */ 2731 synchronize_irq(ioc->pcidev->irq); 2732 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 2733 ioc->active = 0; 2734 2735 /* Clear any lingering interrupt */ 2736 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 2737 CHIPREG_READ32(&ioc->chip->IntStatus); 2738 2739 if (ioc->alloc != NULL) { 2740 sz = ioc->alloc_sz; 2741 dexitprintk(ioc, printk(MYIOC_s_INFO_FMT "free @ %p, sz=%d bytes\n", 2742 ioc->name, ioc->alloc, ioc->alloc_sz)); 2743 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->alloc, 2744 ioc->alloc_dma); 2745 ioc->reply_frames = NULL; 2746 ioc->req_frames = NULL; 2747 ioc->alloc = NULL; 2748 ioc->alloc_total -= sz; 2749 } 2750 2751 if (ioc->sense_buf_pool != NULL) { 2752 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC); 2753 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->sense_buf_pool, 2754 ioc->sense_buf_pool_dma); 2755 ioc->sense_buf_pool = NULL; 2756 ioc->alloc_total -= sz; 2757 } 2758 2759 if (ioc->events != NULL){ 2760 sz = MPTCTL_EVENT_LOG_SIZE * sizeof(MPT_IOCTL_EVENTS); 2761 kfree(ioc->events); 2762 ioc->events = NULL; 2763 ioc->alloc_total -= sz; 2764 } 2765 2766 mpt_free_fw_memory(ioc); 2767 2768 kfree(ioc->spi_data.nvram); 2769 mpt_inactive_raid_list_free(ioc); 2770 kfree(ioc->raid_data.pIocPg2); 2771 kfree(ioc->raid_data.pIocPg3); 2772 ioc->spi_data.nvram = NULL; 2773 ioc->raid_data.pIocPg3 = NULL; 2774 2775 if (ioc->spi_data.pIocPg4 != NULL) { 2776 sz = ioc->spi_data.IocPg4Sz; 2777 pci_free_consistent(ioc->pcidev, sz, 2778 ioc->spi_data.pIocPg4, 2779 ioc->spi_data.IocPg4_dma); 2780 ioc->spi_data.pIocPg4 = NULL; 2781 ioc->alloc_total -= sz; 2782 } 2783 2784 if (ioc->ReqToChain != NULL) { 2785 kfree(ioc->ReqToChain); 2786 kfree(ioc->RequestNB); 2787 ioc->ReqToChain = NULL; 2788 } 2789 2790 kfree(ioc->ChainToChain); 2791 ioc->ChainToChain = NULL; 2792 2793 if (ioc->HostPageBuffer != NULL) { 2794 if((ret = mpt_host_page_access_control(ioc, 2795 MPI_DB_HPBAC_FREE_BUFFER, NO_SLEEP)) != 0) { 2796 printk(MYIOC_s_ERR_FMT 2797 ": %s: host page buffers free failed (%d)!\n", 2798 ioc->name, __func__, ret); 2799 } 2800 dexitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2801 "HostPageBuffer free @ %p, sz=%d bytes\n", 2802 ioc->name, ioc->HostPageBuffer, 2803 ioc->HostPageBuffer_sz)); 2804 dma_free_coherent(&ioc->pcidev->dev, ioc->HostPageBuffer_sz, 2805 ioc->HostPageBuffer, ioc->HostPageBuffer_dma); 2806 ioc->HostPageBuffer = NULL; 2807 ioc->HostPageBuffer_sz = 0; 2808 ioc->alloc_total -= ioc->HostPageBuffer_sz; 2809 } 2810 2811 pci_set_drvdata(ioc->pcidev, NULL); 2812 } 2813 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2814 /** 2815 * mpt_adapter_dispose - Free all resources associated with an MPT adapter 2816 * @ioc: Pointer to MPT adapter structure 2817 * 2818 * This routine unregisters h/w resources and frees all alloc'd memory 2819 * associated with a MPT adapter structure. 2820 */ 2821 static void 2822 mpt_adapter_dispose(MPT_ADAPTER *ioc) 2823 { 2824 int sz_first, sz_last; 2825 2826 if (ioc == NULL) 2827 return; 2828 2829 sz_first = ioc->alloc_total; 2830 2831 mpt_adapter_disable(ioc); 2832 2833 if (ioc->pci_irq != -1) { 2834 free_irq(ioc->pci_irq, ioc); 2835 if (ioc->msi_enable) 2836 pci_disable_msi(ioc->pcidev); 2837 ioc->pci_irq = -1; 2838 } 2839 2840 if (ioc->memmap != NULL) { 2841 iounmap(ioc->memmap); 2842 ioc->memmap = NULL; 2843 } 2844 2845 pci_disable_device(ioc->pcidev); 2846 pci_release_selected_regions(ioc->pcidev, ioc->bars); 2847 2848 /* Zap the adapter lookup ptr! */ 2849 list_del(&ioc->list); 2850 2851 sz_last = ioc->alloc_total; 2852 dprintk(ioc, printk(MYIOC_s_INFO_FMT "free'd %d of %d bytes\n", 2853 ioc->name, sz_first-sz_last+(int)sizeof(*ioc), sz_first)); 2854 2855 if (ioc->alt_ioc) 2856 ioc->alt_ioc->alt_ioc = NULL; 2857 2858 kfree(ioc); 2859 } 2860 2861 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2862 /** 2863 * MptDisplayIocCapabilities - Disply IOC's capabilities. 2864 * @ioc: Pointer to MPT adapter structure 2865 */ 2866 static void 2867 MptDisplayIocCapabilities(MPT_ADAPTER *ioc) 2868 { 2869 int i = 0; 2870 2871 printk(KERN_INFO "%s: ", ioc->name); 2872 if (ioc->prod_name) 2873 pr_cont("%s: ", ioc->prod_name); 2874 pr_cont("Capabilities={"); 2875 2876 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR) { 2877 pr_cont("Initiator"); 2878 i++; 2879 } 2880 2881 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) { 2882 pr_cont("%sTarget", i ? "," : ""); 2883 i++; 2884 } 2885 2886 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) { 2887 pr_cont("%sLAN", i ? "," : ""); 2888 i++; 2889 } 2890 2891 #if 0 2892 /* 2893 * This would probably evoke more questions than it's worth 2894 */ 2895 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) { 2896 pr_cont("%sLogBusAddr", i ? "," : ""); 2897 i++; 2898 } 2899 #endif 2900 2901 pr_cont("}\n"); 2902 } 2903 2904 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2905 /** 2906 * MakeIocReady - Get IOC to a READY state, using KickStart if needed. 2907 * @ioc: Pointer to MPT_ADAPTER structure 2908 * @force: Force hard KickStart of IOC 2909 * @sleepFlag: Specifies whether the process can sleep 2910 * 2911 * Returns: 2912 * 1 - DIAG reset and READY 2913 * 0 - READY initially OR soft reset and READY 2914 * -1 - Any failure on KickStart 2915 * -2 - Msg Unit Reset Failed 2916 * -3 - IO Unit Reset Failed 2917 * -4 - IOC owned by a PEER 2918 */ 2919 static int 2920 MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag) 2921 { 2922 u32 ioc_state; 2923 int statefault = 0; 2924 int cntdn; 2925 int hard_reset_done = 0; 2926 int r; 2927 int ii; 2928 int whoinit; 2929 2930 /* Get current [raw] IOC state */ 2931 ioc_state = mpt_GetIocState(ioc, 0); 2932 dhsprintk(ioc, printk(MYIOC_s_INFO_FMT "MakeIocReady [raw] state=%08x\n", ioc->name, ioc_state)); 2933 2934 /* 2935 * Check to see if IOC got left/stuck in doorbell handshake 2936 * grip of death. If so, hard reset the IOC. 2937 */ 2938 if (ioc_state & MPI_DOORBELL_ACTIVE) { 2939 statefault = 1; 2940 printk(MYIOC_s_WARN_FMT "Unexpected doorbell active!\n", 2941 ioc->name); 2942 } 2943 2944 /* Is it already READY? */ 2945 if (!statefault && 2946 ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_READY)) { 2947 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 2948 "IOC is in READY state\n", ioc->name)); 2949 return 0; 2950 } 2951 2952 /* 2953 * Check to see if IOC is in FAULT state. 2954 */ 2955 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) { 2956 statefault = 2; 2957 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state!!!\n", 2958 ioc->name); 2959 printk(MYIOC_s_WARN_FMT " FAULT code = %04xh\n", 2960 ioc->name, ioc_state & MPI_DOORBELL_DATA_MASK); 2961 } 2962 2963 /* 2964 * Hmmm... Did it get left operational? 2965 */ 2966 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_OPERATIONAL) { 2967 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOC operational unexpected\n", 2968 ioc->name)); 2969 2970 /* Check WhoInit. 2971 * If PCI Peer, exit. 2972 * Else, if no fault conditions are present, issue a MessageUnitReset 2973 * Else, fall through to KickStart case 2974 */ 2975 whoinit = (ioc_state & MPI_DOORBELL_WHO_INIT_MASK) >> MPI_DOORBELL_WHO_INIT_SHIFT; 2976 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 2977 "whoinit 0x%x statefault %d force %d\n", 2978 ioc->name, whoinit, statefault, force)); 2979 if (whoinit == MPI_WHOINIT_PCI_PEER) 2980 return -4; 2981 else { 2982 if ((statefault == 0 ) && (force == 0)) { 2983 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) == 0) 2984 return 0; 2985 } 2986 statefault = 3; 2987 } 2988 } 2989 2990 hard_reset_done = KickStart(ioc, statefault||force, sleepFlag); 2991 if (hard_reset_done < 0) 2992 return -1; 2993 2994 /* 2995 * Loop here waiting for IOC to come READY. 2996 */ 2997 ii = 0; 2998 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 5; /* 5 seconds */ 2999 3000 while ((ioc_state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) { 3001 if (ioc_state == MPI_IOC_STATE_OPERATIONAL) { 3002 /* 3003 * BIOS or previous driver load left IOC in OP state. 3004 * Reset messaging FIFOs. 3005 */ 3006 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) != 0) { 3007 printk(MYIOC_s_ERR_FMT "IOC msg unit reset failed!\n", ioc->name); 3008 return -2; 3009 } 3010 } else if (ioc_state == MPI_IOC_STATE_RESET) { 3011 /* 3012 * Something is wrong. Try to get IOC back 3013 * to a known state. 3014 */ 3015 if ((r = SendIocReset(ioc, MPI_FUNCTION_IO_UNIT_RESET, sleepFlag)) != 0) { 3016 printk(MYIOC_s_ERR_FMT "IO unit reset failed!\n", ioc->name); 3017 return -3; 3018 } 3019 } 3020 3021 ii++; cntdn--; 3022 if (!cntdn) { 3023 printk(MYIOC_s_ERR_FMT 3024 "Wait IOC_READY state (0x%x) timeout(%d)!\n", 3025 ioc->name, ioc_state, (int)((ii+5)/HZ)); 3026 return -ETIME; 3027 } 3028 3029 if (sleepFlag == CAN_SLEEP) { 3030 msleep(1); 3031 } else { 3032 mdelay (1); /* 1 msec delay */ 3033 } 3034 3035 } 3036 3037 if (statefault < 3) { 3038 printk(MYIOC_s_INFO_FMT "Recovered from %s\n", ioc->name, 3039 statefault == 1 ? "stuck handshake" : "IOC FAULT"); 3040 } 3041 3042 return hard_reset_done; 3043 } 3044 3045 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3046 /** 3047 * mpt_GetIocState - Get the current state of a MPT adapter. 3048 * @ioc: Pointer to MPT_ADAPTER structure 3049 * @cooked: Request raw or cooked IOC state 3050 * 3051 * Returns all IOC Doorbell register bits if cooked==0, else just the 3052 * Doorbell bits in MPI_IOC_STATE_MASK. 3053 */ 3054 u32 3055 mpt_GetIocState(MPT_ADAPTER *ioc, int cooked) 3056 { 3057 u32 s, sc; 3058 3059 /* Get! */ 3060 s = CHIPREG_READ32(&ioc->chip->Doorbell); 3061 sc = s & MPI_IOC_STATE_MASK; 3062 3063 /* Save! */ 3064 ioc->last_state = sc; 3065 3066 return cooked ? sc : s; 3067 } 3068 3069 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3070 /** 3071 * GetIocFacts - Send IOCFacts request to MPT adapter. 3072 * @ioc: Pointer to MPT_ADAPTER structure 3073 * @sleepFlag: Specifies whether the process can sleep 3074 * @reason: If recovery, only update facts. 3075 * 3076 * Returns 0 for success, non-zero for failure. 3077 */ 3078 static int 3079 GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason) 3080 { 3081 IOCFacts_t get_facts; 3082 IOCFactsReply_t *facts; 3083 int r; 3084 int req_sz; 3085 int reply_sz; 3086 int sz; 3087 u32 vv; 3088 u8 shiftFactor=1; 3089 3090 /* IOC *must* NOT be in RESET state! */ 3091 if (ioc->last_state == MPI_IOC_STATE_RESET) { 3092 printk(KERN_ERR MYNAM 3093 ": ERROR - Can't get IOCFacts, %s NOT READY! (%08x)\n", 3094 ioc->name, ioc->last_state); 3095 return -44; 3096 } 3097 3098 facts = &ioc->facts; 3099 3100 /* Destination (reply area)... */ 3101 reply_sz = sizeof(*facts); 3102 memset(facts, 0, reply_sz); 3103 3104 /* Request area (get_facts on the stack right now!) */ 3105 req_sz = sizeof(get_facts); 3106 memset(&get_facts, 0, req_sz); 3107 3108 get_facts.Function = MPI_FUNCTION_IOC_FACTS; 3109 /* Assert: All other get_facts fields are zero! */ 3110 3111 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3112 "Sending get IocFacts request req_sz=%d reply_sz=%d\n", 3113 ioc->name, req_sz, reply_sz)); 3114 3115 /* No non-zero fields in the get_facts request are greater than 3116 * 1 byte in size, so we can just fire it off as is. 3117 */ 3118 r = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_facts, 3119 reply_sz, (u16*)facts, 5 /*seconds*/, sleepFlag); 3120 if (r != 0) 3121 return r; 3122 3123 /* 3124 * Now byte swap (GRRR) the necessary fields before any further 3125 * inspection of reply contents. 3126 * 3127 * But need to do some sanity checks on MsgLength (byte) field 3128 * to make sure we don't zero IOC's req_sz! 3129 */ 3130 /* Did we get a valid reply? */ 3131 if (facts->MsgLength > offsetof(IOCFactsReply_t, RequestFrameSize)/sizeof(u32)) { 3132 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) { 3133 /* 3134 * If not been here, done that, save off first WhoInit value 3135 */ 3136 if (ioc->FirstWhoInit == WHOINIT_UNKNOWN) 3137 ioc->FirstWhoInit = facts->WhoInit; 3138 } 3139 3140 facts->MsgVersion = le16_to_cpu(facts->MsgVersion); 3141 facts->MsgContext = le32_to_cpu(facts->MsgContext); 3142 facts->IOCExceptions = le16_to_cpu(facts->IOCExceptions); 3143 facts->IOCStatus = le16_to_cpu(facts->IOCStatus); 3144 facts->IOCLogInfo = le32_to_cpu(facts->IOCLogInfo); 3145 /* CHECKME! IOCStatus, IOCLogInfo */ 3146 3147 facts->ReplyQueueDepth = le16_to_cpu(facts->ReplyQueueDepth); 3148 facts->RequestFrameSize = le16_to_cpu(facts->RequestFrameSize); 3149 3150 /* 3151 * FC f/w version changed between 1.1 and 1.2 3152 * Old: u16{Major(4),Minor(4),SubMinor(8)} 3153 * New: u32{Major(8),Minor(8),Unit(8),Dev(8)} 3154 */ 3155 if (facts->MsgVersion < MPI_VERSION_01_02) { 3156 /* 3157 * Handle old FC f/w style, convert to new... 3158 */ 3159 u16 oldv = le16_to_cpu(facts->Reserved_0101_FWVersion); 3160 facts->FWVersion.Word = 3161 ((oldv<<12) & 0xFF000000) | 3162 ((oldv<<8) & 0x000FFF00); 3163 } else 3164 facts->FWVersion.Word = le32_to_cpu(facts->FWVersion.Word); 3165 3166 facts->ProductID = le16_to_cpu(facts->ProductID); 3167 3168 if ((ioc->facts.ProductID & MPI_FW_HEADER_PID_PROD_MASK) 3169 > MPI_FW_HEADER_PID_PROD_TARGET_SCSI) 3170 ioc->ir_firmware = 1; 3171 3172 facts->CurrentHostMfaHighAddr = 3173 le32_to_cpu(facts->CurrentHostMfaHighAddr); 3174 facts->GlobalCredits = le16_to_cpu(facts->GlobalCredits); 3175 facts->CurrentSenseBufferHighAddr = 3176 le32_to_cpu(facts->CurrentSenseBufferHighAddr); 3177 facts->CurReplyFrameSize = 3178 le16_to_cpu(facts->CurReplyFrameSize); 3179 facts->IOCCapabilities = le32_to_cpu(facts->IOCCapabilities); 3180 3181 /* 3182 * Handle NEW (!) IOCFactsReply fields in MPI-1.01.xx 3183 * Older MPI-1.00.xx struct had 13 dwords, and enlarged 3184 * to 14 in MPI-1.01.0x. 3185 */ 3186 if (facts->MsgLength >= (offsetof(IOCFactsReply_t,FWImageSize) + 7)/4 && 3187 facts->MsgVersion > MPI_VERSION_01_00) { 3188 facts->FWImageSize = le32_to_cpu(facts->FWImageSize); 3189 } 3190 3191 facts->FWImageSize = ALIGN(facts->FWImageSize, 4); 3192 3193 if (!facts->RequestFrameSize) { 3194 /* Something is wrong! */ 3195 printk(MYIOC_s_ERR_FMT "IOC reported invalid 0 request size!\n", 3196 ioc->name); 3197 return -55; 3198 } 3199 3200 r = sz = facts->BlockSize; 3201 vv = ((63 / (sz * 4)) + 1) & 0x03; 3202 ioc->NB_for_64_byte_frame = vv; 3203 while ( sz ) 3204 { 3205 shiftFactor++; 3206 sz = sz >> 1; 3207 } 3208 ioc->NBShiftFactor = shiftFactor; 3209 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3210 "NB_for_64_byte_frame=%x NBShiftFactor=%x BlockSize=%x\n", 3211 ioc->name, vv, shiftFactor, r)); 3212 3213 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) { 3214 /* 3215 * Set values for this IOC's request & reply frame sizes, 3216 * and request & reply queue depths... 3217 */ 3218 ioc->req_sz = min(MPT_DEFAULT_FRAME_SIZE, facts->RequestFrameSize * 4); 3219 ioc->req_depth = min_t(int, MPT_MAX_REQ_DEPTH, facts->GlobalCredits); 3220 ioc->reply_sz = MPT_REPLY_FRAME_SIZE; 3221 ioc->reply_depth = min_t(int, MPT_DEFAULT_REPLY_DEPTH, facts->ReplyQueueDepth); 3222 3223 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "reply_sz=%3d, reply_depth=%4d\n", 3224 ioc->name, ioc->reply_sz, ioc->reply_depth)); 3225 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "req_sz =%3d, req_depth =%4d\n", 3226 ioc->name, ioc->req_sz, ioc->req_depth)); 3227 3228 /* Get port facts! */ 3229 if ( (r = GetPortFacts(ioc, 0, sleepFlag)) != 0 ) 3230 return r; 3231 } 3232 } else { 3233 printk(MYIOC_s_ERR_FMT 3234 "Invalid IOC facts reply, msgLength=%d offsetof=%zd!\n", 3235 ioc->name, facts->MsgLength, (offsetof(IOCFactsReply_t, 3236 RequestFrameSize)/sizeof(u32))); 3237 return -66; 3238 } 3239 3240 return 0; 3241 } 3242 3243 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3244 /** 3245 * GetPortFacts - Send PortFacts request to MPT adapter. 3246 * @ioc: Pointer to MPT_ADAPTER structure 3247 * @portnum: Port number 3248 * @sleepFlag: Specifies whether the process can sleep 3249 * 3250 * Returns 0 for success, non-zero for failure. 3251 */ 3252 static int 3253 GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag) 3254 { 3255 PortFacts_t get_pfacts; 3256 PortFactsReply_t *pfacts; 3257 int ii; 3258 int req_sz; 3259 int reply_sz; 3260 int max_id; 3261 3262 /* IOC *must* NOT be in RESET state! */ 3263 if (ioc->last_state == MPI_IOC_STATE_RESET) { 3264 printk(MYIOC_s_ERR_FMT "Can't get PortFacts NOT READY! (%08x)\n", 3265 ioc->name, ioc->last_state ); 3266 return -4; 3267 } 3268 3269 pfacts = &ioc->pfacts[portnum]; 3270 3271 /* Destination (reply area)... */ 3272 reply_sz = sizeof(*pfacts); 3273 memset(pfacts, 0, reply_sz); 3274 3275 /* Request area (get_pfacts on the stack right now!) */ 3276 req_sz = sizeof(get_pfacts); 3277 memset(&get_pfacts, 0, req_sz); 3278 3279 get_pfacts.Function = MPI_FUNCTION_PORT_FACTS; 3280 get_pfacts.PortNumber = portnum; 3281 /* Assert: All other get_pfacts fields are zero! */ 3282 3283 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending get PortFacts(%d) request\n", 3284 ioc->name, portnum)); 3285 3286 /* No non-zero fields in the get_pfacts request are greater than 3287 * 1 byte in size, so we can just fire it off as is. 3288 */ 3289 ii = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_pfacts, 3290 reply_sz, (u16*)pfacts, 5 /*seconds*/, sleepFlag); 3291 if (ii != 0) 3292 return ii; 3293 3294 /* Did we get a valid reply? */ 3295 3296 /* Now byte swap the necessary fields in the response. */ 3297 pfacts->MsgContext = le32_to_cpu(pfacts->MsgContext); 3298 pfacts->IOCStatus = le16_to_cpu(pfacts->IOCStatus); 3299 pfacts->IOCLogInfo = le32_to_cpu(pfacts->IOCLogInfo); 3300 pfacts->MaxDevices = le16_to_cpu(pfacts->MaxDevices); 3301 pfacts->PortSCSIID = le16_to_cpu(pfacts->PortSCSIID); 3302 pfacts->ProtocolFlags = le16_to_cpu(pfacts->ProtocolFlags); 3303 pfacts->MaxPostedCmdBuffers = le16_to_cpu(pfacts->MaxPostedCmdBuffers); 3304 pfacts->MaxPersistentIDs = le16_to_cpu(pfacts->MaxPersistentIDs); 3305 pfacts->MaxLanBuckets = le16_to_cpu(pfacts->MaxLanBuckets); 3306 3307 max_id = (ioc->bus_type == SAS) ? pfacts->PortSCSIID : 3308 pfacts->MaxDevices; 3309 ioc->devices_per_bus = (max_id > 255) ? 256 : max_id; 3310 ioc->number_of_buses = (ioc->devices_per_bus < 256) ? 1 : max_id/256; 3311 3312 /* 3313 * Place all the devices on channels 3314 * 3315 * (for debuging) 3316 */ 3317 if (mpt_channel_mapping) { 3318 ioc->devices_per_bus = 1; 3319 ioc->number_of_buses = (max_id > 255) ? 255 : max_id; 3320 } 3321 3322 return 0; 3323 } 3324 3325 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3326 /** 3327 * SendIocInit - Send IOCInit request to MPT adapter. 3328 * @ioc: Pointer to MPT_ADAPTER structure 3329 * @sleepFlag: Specifies whether the process can sleep 3330 * 3331 * Send IOCInit followed by PortEnable to bring IOC to OPERATIONAL state. 3332 * 3333 * Returns 0 for success, non-zero for failure. 3334 */ 3335 static int 3336 SendIocInit(MPT_ADAPTER *ioc, int sleepFlag) 3337 { 3338 IOCInit_t ioc_init; 3339 MPIDefaultReply_t init_reply; 3340 u32 state; 3341 int r; 3342 int count; 3343 int cntdn; 3344 3345 memset(&ioc_init, 0, sizeof(ioc_init)); 3346 memset(&init_reply, 0, sizeof(init_reply)); 3347 3348 ioc_init.WhoInit = MPI_WHOINIT_HOST_DRIVER; 3349 ioc_init.Function = MPI_FUNCTION_IOC_INIT; 3350 3351 /* If we are in a recovery mode and we uploaded the FW image, 3352 * then this pointer is not NULL. Skip the upload a second time. 3353 * Set this flag if cached_fw set for either IOC. 3354 */ 3355 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT) 3356 ioc->upload_fw = 1; 3357 else 3358 ioc->upload_fw = 0; 3359 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "upload_fw %d facts.Flags=%x\n", 3360 ioc->name, ioc->upload_fw, ioc->facts.Flags)); 3361 3362 ioc_init.MaxDevices = (U8)ioc->devices_per_bus; 3363 ioc_init.MaxBuses = (U8)ioc->number_of_buses; 3364 3365 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "facts.MsgVersion=%x\n", 3366 ioc->name, ioc->facts.MsgVersion)); 3367 if (ioc->facts.MsgVersion >= MPI_VERSION_01_05) { 3368 // set MsgVersion and HeaderVersion host driver was built with 3369 ioc_init.MsgVersion = cpu_to_le16(MPI_VERSION); 3370 ioc_init.HeaderVersion = cpu_to_le16(MPI_HEADER_VERSION); 3371 3372 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT) { 3373 ioc_init.HostPageBufferSGE = ioc->facts.HostPageBufferSGE; 3374 } else if(mpt_host_page_alloc(ioc, &ioc_init)) 3375 return -99; 3376 } 3377 ioc_init.ReplyFrameSize = cpu_to_le16(ioc->reply_sz); /* in BYTES */ 3378 3379 if (ioc->sg_addr_size == sizeof(u64)) { 3380 /* Save the upper 32-bits of the request 3381 * (reply) and sense buffers. 3382 */ 3383 ioc_init.HostMfaHighAddr = cpu_to_le32((u32)((u64)ioc->alloc_dma >> 32)); 3384 ioc_init.SenseBufferHighAddr = cpu_to_le32((u32)((u64)ioc->sense_buf_pool_dma >> 32)); 3385 } else { 3386 /* Force 32-bit addressing */ 3387 ioc_init.HostMfaHighAddr = cpu_to_le32(0); 3388 ioc_init.SenseBufferHighAddr = cpu_to_le32(0); 3389 } 3390 3391 ioc->facts.CurrentHostMfaHighAddr = ioc_init.HostMfaHighAddr; 3392 ioc->facts.CurrentSenseBufferHighAddr = ioc_init.SenseBufferHighAddr; 3393 ioc->facts.MaxDevices = ioc_init.MaxDevices; 3394 ioc->facts.MaxBuses = ioc_init.MaxBuses; 3395 3396 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOCInit (req @ %p)\n", 3397 ioc->name, &ioc_init)); 3398 3399 r = mpt_handshake_req_reply_wait(ioc, sizeof(IOCInit_t), (u32*)&ioc_init, 3400 sizeof(MPIDefaultReply_t), (u16*)&init_reply, 10 /*seconds*/, sleepFlag); 3401 if (r != 0) { 3402 printk(MYIOC_s_ERR_FMT "Sending IOCInit failed(%d)!\n",ioc->name, r); 3403 return r; 3404 } 3405 3406 /* No need to byte swap the multibyte fields in the reply 3407 * since we don't even look at its contents. 3408 */ 3409 3410 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending PortEnable (req @ %p)\n", 3411 ioc->name, &ioc_init)); 3412 3413 if ((r = SendPortEnable(ioc, 0, sleepFlag)) != 0) { 3414 printk(MYIOC_s_ERR_FMT "Sending PortEnable failed(%d)!\n",ioc->name, r); 3415 return r; 3416 } 3417 3418 /* YIKES! SUPER IMPORTANT!!! 3419 * Poll IocState until _OPERATIONAL while IOC is doing 3420 * LoopInit and TargetDiscovery! 3421 */ 3422 count = 0; 3423 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 60; /* 60 seconds */ 3424 state = mpt_GetIocState(ioc, 1); 3425 while (state != MPI_IOC_STATE_OPERATIONAL && --cntdn) { 3426 if (sleepFlag == CAN_SLEEP) { 3427 msleep(1); 3428 } else { 3429 mdelay(1); 3430 } 3431 3432 if (!cntdn) { 3433 printk(MYIOC_s_ERR_FMT "Wait IOC_OP state timeout(%d)!\n", 3434 ioc->name, (int)((count+5)/HZ)); 3435 return -9; 3436 } 3437 3438 state = mpt_GetIocState(ioc, 1); 3439 count++; 3440 } 3441 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wait IOC_OPERATIONAL state (cnt=%d)\n", 3442 ioc->name, count)); 3443 3444 ioc->aen_event_read_flag=0; 3445 return r; 3446 } 3447 3448 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3449 /** 3450 * SendPortEnable - Send PortEnable request to MPT adapter port. 3451 * @ioc: Pointer to MPT_ADAPTER structure 3452 * @portnum: Port number to enable 3453 * @sleepFlag: Specifies whether the process can sleep 3454 * 3455 * Send PortEnable to bring IOC to OPERATIONAL state. 3456 * 3457 * Returns 0 for success, non-zero for failure. 3458 */ 3459 static int 3460 SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag) 3461 { 3462 PortEnable_t port_enable; 3463 MPIDefaultReply_t reply_buf; 3464 int rc; 3465 int req_sz; 3466 int reply_sz; 3467 3468 /* Destination... */ 3469 reply_sz = sizeof(MPIDefaultReply_t); 3470 memset(&reply_buf, 0, reply_sz); 3471 3472 req_sz = sizeof(PortEnable_t); 3473 memset(&port_enable, 0, req_sz); 3474 3475 port_enable.Function = MPI_FUNCTION_PORT_ENABLE; 3476 port_enable.PortNumber = portnum; 3477 /* port_enable.ChainOffset = 0; */ 3478 /* port_enable.MsgFlags = 0; */ 3479 /* port_enable.MsgContext = 0; */ 3480 3481 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending Port(%d)Enable (req @ %p)\n", 3482 ioc->name, portnum, &port_enable)); 3483 3484 /* RAID FW may take a long time to enable 3485 */ 3486 if (ioc->ir_firmware || ioc->bus_type == SAS) { 3487 rc = mpt_handshake_req_reply_wait(ioc, req_sz, 3488 (u32*)&port_enable, reply_sz, (u16*)&reply_buf, 3489 300 /*seconds*/, sleepFlag); 3490 } else { 3491 rc = mpt_handshake_req_reply_wait(ioc, req_sz, 3492 (u32*)&port_enable, reply_sz, (u16*)&reply_buf, 3493 30 /*seconds*/, sleepFlag); 3494 } 3495 return rc; 3496 } 3497 3498 /** 3499 * mpt_alloc_fw_memory - allocate firmware memory 3500 * @ioc: Pointer to MPT_ADAPTER structure 3501 * @size: total FW bytes 3502 * 3503 * If memory has already been allocated, the same (cached) value 3504 * is returned. 3505 * 3506 * Return 0 if successful, or non-zero for failure 3507 **/ 3508 int 3509 mpt_alloc_fw_memory(MPT_ADAPTER *ioc, int size) 3510 { 3511 int rc; 3512 3513 if (ioc->cached_fw) { 3514 rc = 0; /* use already allocated memory */ 3515 goto out; 3516 } 3517 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) { 3518 ioc->cached_fw = ioc->alt_ioc->cached_fw; /* use alt_ioc's memory */ 3519 ioc->cached_fw_dma = ioc->alt_ioc->cached_fw_dma; 3520 rc = 0; 3521 goto out; 3522 } 3523 ioc->cached_fw = pci_alloc_consistent(ioc->pcidev, size, &ioc->cached_fw_dma); 3524 if (!ioc->cached_fw) { 3525 printk(MYIOC_s_ERR_FMT "Unable to allocate memory for the cached firmware image!\n", 3526 ioc->name); 3527 rc = -1; 3528 } else { 3529 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Image @ %p[%p], sz=%d[%x] bytes\n", 3530 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, size, size)); 3531 ioc->alloc_total += size; 3532 rc = 0; 3533 } 3534 out: 3535 return rc; 3536 } 3537 3538 /** 3539 * mpt_free_fw_memory - free firmware memory 3540 * @ioc: Pointer to MPT_ADAPTER structure 3541 * 3542 * If alt_img is NULL, delete from ioc structure. 3543 * Else, delete a secondary image in same format. 3544 **/ 3545 void 3546 mpt_free_fw_memory(MPT_ADAPTER *ioc) 3547 { 3548 int sz; 3549 3550 if (!ioc->cached_fw) 3551 return; 3552 3553 sz = ioc->facts.FWImageSize; 3554 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "free_fw_memory: FW Image @ %p[%p], sz=%d[%x] bytes\n", 3555 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz)); 3556 pci_free_consistent(ioc->pcidev, sz, ioc->cached_fw, ioc->cached_fw_dma); 3557 ioc->alloc_total -= sz; 3558 ioc->cached_fw = NULL; 3559 } 3560 3561 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3562 /** 3563 * mpt_do_upload - Construct and Send FWUpload request to MPT adapter port. 3564 * @ioc: Pointer to MPT_ADAPTER structure 3565 * @sleepFlag: Specifies whether the process can sleep 3566 * 3567 * Returns 0 for success, >0 for handshake failure 3568 * <0 for fw upload failure. 3569 * 3570 * Remark: If bound IOC and a successful FWUpload was performed 3571 * on the bound IOC, the second image is discarded 3572 * and memory is free'd. Both channels must upload to prevent 3573 * IOC from running in degraded mode. 3574 */ 3575 static int 3576 mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag) 3577 { 3578 u8 reply[sizeof(FWUploadReply_t)]; 3579 FWUpload_t *prequest; 3580 FWUploadReply_t *preply; 3581 FWUploadTCSGE_t *ptcsge; 3582 u32 flagsLength; 3583 int ii, sz, reply_sz; 3584 int cmdStatus; 3585 int request_size; 3586 /* If the image size is 0, we are done. 3587 */ 3588 if ((sz = ioc->facts.FWImageSize) == 0) 3589 return 0; 3590 3591 if (mpt_alloc_fw_memory(ioc, ioc->facts.FWImageSize) != 0) 3592 return -ENOMEM; 3593 3594 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": FW Image @ %p[%p], sz=%d[%x] bytes\n", 3595 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz)); 3596 3597 prequest = (sleepFlag == NO_SLEEP) ? kzalloc(ioc->req_sz, GFP_ATOMIC) : 3598 kzalloc(ioc->req_sz, GFP_KERNEL); 3599 if (!prequest) { 3600 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed " 3601 "while allocating memory \n", ioc->name)); 3602 mpt_free_fw_memory(ioc); 3603 return -ENOMEM; 3604 } 3605 3606 preply = (FWUploadReply_t *)&reply; 3607 3608 reply_sz = sizeof(reply); 3609 memset(preply, 0, reply_sz); 3610 3611 prequest->ImageType = MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM; 3612 prequest->Function = MPI_FUNCTION_FW_UPLOAD; 3613 3614 ptcsge = (FWUploadTCSGE_t *) &prequest->SGL; 3615 ptcsge->DetailsLength = 12; 3616 ptcsge->Flags = MPI_SGE_FLAGS_TRANSACTION_ELEMENT; 3617 ptcsge->ImageSize = cpu_to_le32(sz); 3618 ptcsge++; 3619 3620 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ | sz; 3621 ioc->add_sge((char *)ptcsge, flagsLength, ioc->cached_fw_dma); 3622 request_size = offsetof(FWUpload_t, SGL) + sizeof(FWUploadTCSGE_t) + 3623 ioc->SGE_size; 3624 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending FW Upload " 3625 " (req @ %p) fw_size=%d mf_request_size=%d\n", ioc->name, prequest, 3626 ioc->facts.FWImageSize, request_size)); 3627 DBG_DUMP_FW_REQUEST_FRAME(ioc, (u32 *)prequest); 3628 3629 ii = mpt_handshake_req_reply_wait(ioc, request_size, (u32 *)prequest, 3630 reply_sz, (u16 *)preply, 65 /*seconds*/, sleepFlag); 3631 3632 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Upload completed " 3633 "rc=%x \n", ioc->name, ii)); 3634 3635 cmdStatus = -EFAULT; 3636 if (ii == 0) { 3637 /* Handshake transfer was complete and successful. 3638 * Check the Reply Frame. 3639 */ 3640 int status; 3641 status = le16_to_cpu(preply->IOCStatus) & 3642 MPI_IOCSTATUS_MASK; 3643 if (status == MPI_IOCSTATUS_SUCCESS && 3644 ioc->facts.FWImageSize == 3645 le32_to_cpu(preply->ActualImageSize)) 3646 cmdStatus = 0; 3647 } 3648 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": do_upload cmdStatus=%d \n", 3649 ioc->name, cmdStatus)); 3650 3651 3652 if (cmdStatus) { 3653 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed, " 3654 "freeing image \n", ioc->name)); 3655 mpt_free_fw_memory(ioc); 3656 } 3657 kfree(prequest); 3658 3659 return cmdStatus; 3660 } 3661 3662 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3663 /** 3664 * mpt_downloadboot - DownloadBoot code 3665 * @ioc: Pointer to MPT_ADAPTER structure 3666 * @pFwHeader: Pointer to firmware header info 3667 * @sleepFlag: Specifies whether the process can sleep 3668 * 3669 * FwDownloadBoot requires Programmed IO access. 3670 * 3671 * Returns 0 for success 3672 * -1 FW Image size is 0 3673 * -2 No valid cached_fw Pointer 3674 * <0 for fw upload failure. 3675 */ 3676 static int 3677 mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag) 3678 { 3679 MpiExtImageHeader_t *pExtImage; 3680 u32 fwSize; 3681 u32 diag0val; 3682 int count; 3683 u32 *ptrFw; 3684 u32 diagRwData; 3685 u32 nextImage; 3686 u32 load_addr; 3687 u32 ioc_state=0; 3688 3689 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot: fw size 0x%x (%d), FW Ptr %p\n", 3690 ioc->name, pFwHeader->ImageSize, pFwHeader->ImageSize, pFwHeader)); 3691 3692 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 3693 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); 3694 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE); 3695 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE); 3696 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE); 3697 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); 3698 3699 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM)); 3700 3701 /* wait 1 msec */ 3702 if (sleepFlag == CAN_SLEEP) { 3703 msleep(1); 3704 } else { 3705 mdelay (1); 3706 } 3707 3708 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 3709 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER); 3710 3711 for (count = 0; count < 30; count ++) { 3712 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 3713 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) { 3714 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RESET_ADAPTER cleared, count=%d\n", 3715 ioc->name, count)); 3716 break; 3717 } 3718 /* wait .1 sec */ 3719 if (sleepFlag == CAN_SLEEP) { 3720 msleep (100); 3721 } else { 3722 mdelay (100); 3723 } 3724 } 3725 3726 if ( count == 30 ) { 3727 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot failed! " 3728 "Unable to get MPI_DIAG_DRWE mode, diag0val=%x\n", 3729 ioc->name, diag0val)); 3730 return -3; 3731 } 3732 3733 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 3734 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); 3735 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE); 3736 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE); 3737 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE); 3738 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); 3739 3740 /* Set the DiagRwEn and Disable ARM bits */ 3741 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_RW_ENABLE | MPI_DIAG_DISABLE_ARM)); 3742 3743 fwSize = (pFwHeader->ImageSize + 3)/4; 3744 ptrFw = (u32 *) pFwHeader; 3745 3746 /* Write the LoadStartAddress to the DiagRw Address Register 3747 * using Programmed IO 3748 */ 3749 if (ioc->errata_flag_1064) 3750 pci_enable_io_access(ioc->pcidev); 3751 3752 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress); 3753 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "LoadStart addr written 0x%x \n", 3754 ioc->name, pFwHeader->LoadStartAddress)); 3755 3756 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write FW Image: 0x%x bytes @ %p\n", 3757 ioc->name, fwSize*4, ptrFw)); 3758 while (fwSize--) { 3759 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++); 3760 } 3761 3762 nextImage = pFwHeader->NextImageHeaderOffset; 3763 while (nextImage) { 3764 pExtImage = (MpiExtImageHeader_t *) ((char *)pFwHeader + nextImage); 3765 3766 load_addr = pExtImage->LoadStartAddress; 3767 3768 fwSize = (pExtImage->ImageSize + 3) >> 2; 3769 ptrFw = (u32 *)pExtImage; 3770 3771 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write Ext Image: 0x%x (%d) bytes @ %p load_addr=%x\n", 3772 ioc->name, fwSize*4, fwSize*4, ptrFw, load_addr)); 3773 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, load_addr); 3774 3775 while (fwSize--) { 3776 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++); 3777 } 3778 nextImage = pExtImage->NextImageHeaderOffset; 3779 } 3780 3781 /* Write the IopResetVectorRegAddr */ 3782 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Addr=%x! \n", ioc->name, pFwHeader->IopResetRegAddr)); 3783 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->IopResetRegAddr); 3784 3785 /* Write the IopResetVectorValue */ 3786 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Value=%x! \n", ioc->name, pFwHeader->IopResetVectorValue)); 3787 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, pFwHeader->IopResetVectorValue); 3788 3789 /* Clear the internal flash bad bit - autoincrementing register, 3790 * so must do two writes. 3791 */ 3792 if (ioc->bus_type == SPI) { 3793 /* 3794 * 1030 and 1035 H/W errata, workaround to access 3795 * the ClearFlashBadSignatureBit 3796 */ 3797 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000); 3798 diagRwData = CHIPREG_PIO_READ32(&ioc->pio_chip->DiagRwData); 3799 diagRwData |= 0x40000000; 3800 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000); 3801 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData); 3802 3803 } else /* if((ioc->bus_type == SAS) || (ioc->bus_type == FC)) */ { 3804 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 3805 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | 3806 MPI_DIAG_CLEAR_FLASH_BAD_SIG); 3807 3808 /* wait 1 msec */ 3809 if (sleepFlag == CAN_SLEEP) { 3810 msleep (1); 3811 } else { 3812 mdelay (1); 3813 } 3814 } 3815 3816 if (ioc->errata_flag_1064) 3817 pci_disable_io_access(ioc->pcidev); 3818 3819 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 3820 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot diag0val=%x, " 3821 "turning off PREVENT_IOC_BOOT, DISABLE_ARM, RW_ENABLE\n", 3822 ioc->name, diag0val)); 3823 diag0val &= ~(MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM | MPI_DIAG_RW_ENABLE); 3824 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot now diag0val=%x\n", 3825 ioc->name, diag0val)); 3826 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val); 3827 3828 /* Write 0xFF to reset the sequencer */ 3829 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 3830 3831 if (ioc->bus_type == SAS) { 3832 ioc_state = mpt_GetIocState(ioc, 0); 3833 if ( (GetIocFacts(ioc, sleepFlag, 3834 MPT_HOSTEVENT_IOC_BRINGUP)) != 0 ) { 3835 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "GetIocFacts failed: IocState=%x\n", 3836 ioc->name, ioc_state)); 3837 return -EFAULT; 3838 } 3839 } 3840 3841 for (count=0; count<HZ*20; count++) { 3842 if ((ioc_state = mpt_GetIocState(ioc, 0)) & MPI_IOC_STATE_READY) { 3843 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3844 "downloadboot successful! (count=%d) IocState=%x\n", 3845 ioc->name, count, ioc_state)); 3846 if (ioc->bus_type == SAS) { 3847 return 0; 3848 } 3849 if ((SendIocInit(ioc, sleepFlag)) != 0) { 3850 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3851 "downloadboot: SendIocInit failed\n", 3852 ioc->name)); 3853 return -EFAULT; 3854 } 3855 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3856 "downloadboot: SendIocInit successful\n", 3857 ioc->name)); 3858 return 0; 3859 } 3860 if (sleepFlag == CAN_SLEEP) { 3861 msleep (10); 3862 } else { 3863 mdelay (10); 3864 } 3865 } 3866 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3867 "downloadboot failed! IocState=%x\n",ioc->name, ioc_state)); 3868 return -EFAULT; 3869 } 3870 3871 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3872 /** 3873 * KickStart - Perform hard reset of MPT adapter. 3874 * @ioc: Pointer to MPT_ADAPTER structure 3875 * @force: Force hard reset 3876 * @sleepFlag: Specifies whether the process can sleep 3877 * 3878 * This routine places MPT adapter in diagnostic mode via the 3879 * WriteSequence register, and then performs a hard reset of adapter 3880 * via the Diagnostic register. 3881 * 3882 * Inputs: sleepflag - CAN_SLEEP (non-interrupt thread) 3883 * or NO_SLEEP (interrupt thread, use mdelay) 3884 * force - 1 if doorbell active, board fault state 3885 * board operational, IOC_RECOVERY or 3886 * IOC_BRINGUP and there is an alt_ioc. 3887 * 0 else 3888 * 3889 * Returns: 3890 * 1 - hard reset, READY 3891 * 0 - no reset due to History bit, READY 3892 * -1 - no reset due to History bit but not READY 3893 * OR reset but failed to come READY 3894 * -2 - no reset, could not enter DIAG mode 3895 * -3 - reset but bad FW bit 3896 */ 3897 static int 3898 KickStart(MPT_ADAPTER *ioc, int force, int sleepFlag) 3899 { 3900 int hard_reset_done = 0; 3901 u32 ioc_state=0; 3902 int cnt,cntdn; 3903 3904 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStarting!\n", ioc->name)); 3905 if (ioc->bus_type == SPI) { 3906 /* Always issue a Msg Unit Reset first. This will clear some 3907 * SCSI bus hang conditions. 3908 */ 3909 SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag); 3910 3911 if (sleepFlag == CAN_SLEEP) { 3912 msleep (1000); 3913 } else { 3914 mdelay (1000); 3915 } 3916 } 3917 3918 hard_reset_done = mpt_diag_reset(ioc, force, sleepFlag); 3919 if (hard_reset_done < 0) 3920 return hard_reset_done; 3921 3922 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset successful!\n", 3923 ioc->name)); 3924 3925 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 2; /* 2 seconds */ 3926 for (cnt=0; cnt<cntdn; cnt++) { 3927 ioc_state = mpt_GetIocState(ioc, 1); 3928 if ((ioc_state == MPI_IOC_STATE_READY) || (ioc_state == MPI_IOC_STATE_OPERATIONAL)) { 3929 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStart successful! (cnt=%d)\n", 3930 ioc->name, cnt)); 3931 return hard_reset_done; 3932 } 3933 if (sleepFlag == CAN_SLEEP) { 3934 msleep (10); 3935 } else { 3936 mdelay (10); 3937 } 3938 } 3939 3940 dinitprintk(ioc, printk(MYIOC_s_ERR_FMT "Failed to come READY after reset! IocState=%x\n", 3941 ioc->name, mpt_GetIocState(ioc, 0))); 3942 return -1; 3943 } 3944 3945 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3946 /** 3947 * mpt_diag_reset - Perform hard reset of the adapter. 3948 * @ioc: Pointer to MPT_ADAPTER structure 3949 * @ignore: Set if to honor and clear to ignore 3950 * the reset history bit 3951 * @sleepFlag: CAN_SLEEP if called in a non-interrupt thread, 3952 * else set to NO_SLEEP (use mdelay instead) 3953 * 3954 * This routine places the adapter in diagnostic mode via the 3955 * WriteSequence register and then performs a hard reset of adapter 3956 * via the Diagnostic register. Adapter should be in ready state 3957 * upon successful completion. 3958 * 3959 * Returns: 1 hard reset successful 3960 * 0 no reset performed because reset history bit set 3961 * -2 enabling diagnostic mode failed 3962 * -3 diagnostic reset failed 3963 */ 3964 static int 3965 mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag) 3966 { 3967 u32 diag0val; 3968 u32 doorbell; 3969 int hard_reset_done = 0; 3970 int count = 0; 3971 u32 diag1val = 0; 3972 MpiFwHeader_t *cached_fw; /* Pointer to FW */ 3973 u8 cb_idx; 3974 3975 /* Clear any existing interrupts */ 3976 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 3977 3978 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) { 3979 3980 if (!ignore) 3981 return 0; 3982 3983 drsprintk(ioc, printk(MYIOC_s_WARN_FMT "%s: Doorbell=%p; 1078 reset " 3984 "address=%p\n", ioc->name, __func__, 3985 &ioc->chip->Doorbell, &ioc->chip->Reset_1078)); 3986 CHIPREG_WRITE32(&ioc->chip->Reset_1078, 0x07); 3987 if (sleepFlag == CAN_SLEEP) 3988 msleep(1); 3989 else 3990 mdelay(1); 3991 3992 /* 3993 * Call each currently registered protocol IOC reset handler 3994 * with pre-reset indication. 3995 * NOTE: If we're doing _IOC_BRINGUP, there can be no 3996 * MptResetHandlers[] registered yet. 3997 */ 3998 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 3999 if (MptResetHandlers[cb_idx]) 4000 (*(MptResetHandlers[cb_idx]))(ioc, 4001 MPT_IOC_PRE_RESET); 4002 } 4003 4004 for (count = 0; count < 60; count ++) { 4005 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell); 4006 doorbell &= MPI_IOC_STATE_MASK; 4007 4008 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4009 "looking for READY STATE: doorbell=%x" 4010 " count=%d\n", 4011 ioc->name, doorbell, count)); 4012 4013 if (doorbell == MPI_IOC_STATE_READY) { 4014 return 1; 4015 } 4016 4017 /* wait 1 sec */ 4018 if (sleepFlag == CAN_SLEEP) 4019 msleep(1000); 4020 else 4021 mdelay(1000); 4022 } 4023 return -1; 4024 } 4025 4026 /* Use "Diagnostic reset" method! (only thing available!) */ 4027 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4028 4029 if (ioc->debug_level & MPT_DEBUG) { 4030 if (ioc->alt_ioc) 4031 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); 4032 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG1: diag0=%08x, diag1=%08x\n", 4033 ioc->name, diag0val, diag1val)); 4034 } 4035 4036 /* Do the reset if we are told to ignore the reset history 4037 * or if the reset history is 0 4038 */ 4039 if (ignore || !(diag0val & MPI_DIAG_RESET_HISTORY)) { 4040 while ((diag0val & MPI_DIAG_DRWE) == 0) { 4041 /* Write magic sequence to WriteSequence register 4042 * Loop until in diagnostic mode 4043 */ 4044 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 4045 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); 4046 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE); 4047 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE); 4048 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE); 4049 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); 4050 4051 /* wait 100 msec */ 4052 if (sleepFlag == CAN_SLEEP) { 4053 msleep (100); 4054 } else { 4055 mdelay (100); 4056 } 4057 4058 count++; 4059 if (count > 20) { 4060 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n", 4061 ioc->name, diag0val); 4062 return -2; 4063 4064 } 4065 4066 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4067 4068 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wrote magic DiagWriteEn sequence (%x)\n", 4069 ioc->name, diag0val)); 4070 } 4071 4072 if (ioc->debug_level & MPT_DEBUG) { 4073 if (ioc->alt_ioc) 4074 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); 4075 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG2: diag0=%08x, diag1=%08x\n", 4076 ioc->name, diag0val, diag1val)); 4077 } 4078 /* 4079 * Disable the ARM (Bug fix) 4080 * 4081 */ 4082 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_DISABLE_ARM); 4083 mdelay(1); 4084 4085 /* 4086 * Now hit the reset bit in the Diagnostic register 4087 * (THE BIG HAMMER!) (Clears DRWE bit). 4088 */ 4089 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER); 4090 hard_reset_done = 1; 4091 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset performed\n", 4092 ioc->name)); 4093 4094 /* 4095 * Call each currently registered protocol IOC reset handler 4096 * with pre-reset indication. 4097 * NOTE: If we're doing _IOC_BRINGUP, there can be no 4098 * MptResetHandlers[] registered yet. 4099 */ 4100 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 4101 if (MptResetHandlers[cb_idx]) { 4102 mpt_signal_reset(cb_idx, 4103 ioc, MPT_IOC_PRE_RESET); 4104 if (ioc->alt_ioc) { 4105 mpt_signal_reset(cb_idx, 4106 ioc->alt_ioc, MPT_IOC_PRE_RESET); 4107 } 4108 } 4109 } 4110 4111 if (ioc->cached_fw) 4112 cached_fw = (MpiFwHeader_t *)ioc->cached_fw; 4113 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) 4114 cached_fw = (MpiFwHeader_t *)ioc->alt_ioc->cached_fw; 4115 else 4116 cached_fw = NULL; 4117 if (cached_fw) { 4118 /* If the DownloadBoot operation fails, the 4119 * IOC will be left unusable. This is a fatal error 4120 * case. _diag_reset will return < 0 4121 */ 4122 for (count = 0; count < 30; count ++) { 4123 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4124 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) { 4125 break; 4126 } 4127 4128 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "cached_fw: diag0val=%x count=%d\n", 4129 ioc->name, diag0val, count)); 4130 /* wait 1 sec */ 4131 if (sleepFlag == CAN_SLEEP) { 4132 msleep (1000); 4133 } else { 4134 mdelay (1000); 4135 } 4136 } 4137 if ((count = mpt_downloadboot(ioc, cached_fw, sleepFlag)) < 0) { 4138 printk(MYIOC_s_WARN_FMT 4139 "firmware downloadboot failure (%d)!\n", ioc->name, count); 4140 } 4141 4142 } else { 4143 /* Wait for FW to reload and for board 4144 * to go to the READY state. 4145 * Maximum wait is 60 seconds. 4146 * If fail, no error will check again 4147 * with calling program. 4148 */ 4149 for (count = 0; count < 60; count ++) { 4150 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell); 4151 doorbell &= MPI_IOC_STATE_MASK; 4152 4153 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4154 "looking for READY STATE: doorbell=%x" 4155 " count=%d\n", ioc->name, doorbell, count)); 4156 4157 if (doorbell == MPI_IOC_STATE_READY) { 4158 break; 4159 } 4160 4161 /* wait 1 sec */ 4162 if (sleepFlag == CAN_SLEEP) { 4163 msleep (1000); 4164 } else { 4165 mdelay (1000); 4166 } 4167 } 4168 4169 if (doorbell != MPI_IOC_STATE_READY) 4170 printk(MYIOC_s_ERR_FMT "Failed to come READY " 4171 "after reset! IocState=%x", ioc->name, 4172 doorbell); 4173 } 4174 } 4175 4176 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4177 if (ioc->debug_level & MPT_DEBUG) { 4178 if (ioc->alt_ioc) 4179 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); 4180 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG3: diag0=%08x, diag1=%08x\n", 4181 ioc->name, diag0val, diag1val)); 4182 } 4183 4184 /* Clear RESET_HISTORY bit! Place board in the 4185 * diagnostic mode to update the diag register. 4186 */ 4187 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4188 count = 0; 4189 while ((diag0val & MPI_DIAG_DRWE) == 0) { 4190 /* Write magic sequence to WriteSequence register 4191 * Loop until in diagnostic mode 4192 */ 4193 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 4194 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); 4195 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE); 4196 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE); 4197 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE); 4198 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); 4199 4200 /* wait 100 msec */ 4201 if (sleepFlag == CAN_SLEEP) { 4202 msleep (100); 4203 } else { 4204 mdelay (100); 4205 } 4206 4207 count++; 4208 if (count > 20) { 4209 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n", 4210 ioc->name, diag0val); 4211 break; 4212 } 4213 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4214 } 4215 diag0val &= ~MPI_DIAG_RESET_HISTORY; 4216 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val); 4217 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4218 if (diag0val & MPI_DIAG_RESET_HISTORY) { 4219 printk(MYIOC_s_WARN_FMT "ResetHistory bit failed to clear!\n", 4220 ioc->name); 4221 } 4222 4223 /* Disable Diagnostic Mode 4224 */ 4225 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFFFFFFFF); 4226 4227 /* Check FW reload status flags. 4228 */ 4229 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4230 if (diag0val & (MPI_DIAG_FLASH_BAD_SIG | MPI_DIAG_RESET_ADAPTER | MPI_DIAG_DISABLE_ARM)) { 4231 printk(MYIOC_s_ERR_FMT "Diagnostic reset FAILED! (%02xh)\n", 4232 ioc->name, diag0val); 4233 return -3; 4234 } 4235 4236 if (ioc->debug_level & MPT_DEBUG) { 4237 if (ioc->alt_ioc) 4238 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); 4239 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG4: diag0=%08x, diag1=%08x\n", 4240 ioc->name, diag0val, diag1val)); 4241 } 4242 4243 /* 4244 * Reset flag that says we've enabled event notification 4245 */ 4246 ioc->facts.EventState = 0; 4247 4248 if (ioc->alt_ioc) 4249 ioc->alt_ioc->facts.EventState = 0; 4250 4251 return hard_reset_done; 4252 } 4253 4254 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4255 /** 4256 * SendIocReset - Send IOCReset request to MPT adapter. 4257 * @ioc: Pointer to MPT_ADAPTER structure 4258 * @reset_type: reset type, expected values are 4259 * %MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET or %MPI_FUNCTION_IO_UNIT_RESET 4260 * @sleepFlag: Specifies whether the process can sleep 4261 * 4262 * Send IOCReset request to the MPT adapter. 4263 * 4264 * Returns 0 for success, non-zero for failure. 4265 */ 4266 static int 4267 SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag) 4268 { 4269 int r; 4270 u32 state; 4271 int cntdn, count; 4272 4273 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOC reset(0x%02x)!\n", 4274 ioc->name, reset_type)); 4275 CHIPREG_WRITE32(&ioc->chip->Doorbell, reset_type<<MPI_DOORBELL_FUNCTION_SHIFT); 4276 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) 4277 return r; 4278 4279 /* FW ACK'd request, wait for READY state 4280 */ 4281 count = 0; 4282 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 15; /* 15 seconds */ 4283 4284 while ((state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) { 4285 cntdn--; 4286 count++; 4287 if (!cntdn) { 4288 if (sleepFlag != CAN_SLEEP) 4289 count *= 10; 4290 4291 printk(MYIOC_s_ERR_FMT 4292 "Wait IOC_READY state (0x%x) timeout(%d)!\n", 4293 ioc->name, state, (int)((count+5)/HZ)); 4294 return -ETIME; 4295 } 4296 4297 if (sleepFlag == CAN_SLEEP) { 4298 msleep(1); 4299 } else { 4300 mdelay (1); /* 1 msec delay */ 4301 } 4302 } 4303 4304 /* TODO! 4305 * Cleanup all event stuff for this IOC; re-issue EventNotification 4306 * request if needed. 4307 */ 4308 if (ioc->facts.Function) 4309 ioc->facts.EventState = 0; 4310 4311 return 0; 4312 } 4313 4314 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4315 /** 4316 * initChainBuffers - Allocate memory for and initialize chain buffers 4317 * @ioc: Pointer to MPT_ADAPTER structure 4318 * 4319 * Allocates memory for and initializes chain buffers, 4320 * chain buffer control arrays and spinlock. 4321 */ 4322 static int 4323 initChainBuffers(MPT_ADAPTER *ioc) 4324 { 4325 u8 *mem; 4326 int sz, ii, num_chain; 4327 int scale, num_sge, numSGE; 4328 4329 /* ReqToChain size must equal the req_depth 4330 * index = req_idx 4331 */ 4332 if (ioc->ReqToChain == NULL) { 4333 sz = ioc->req_depth * sizeof(int); 4334 mem = kmalloc(sz, GFP_ATOMIC); 4335 if (mem == NULL) 4336 return -1; 4337 4338 ioc->ReqToChain = (int *) mem; 4339 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReqToChain alloc @ %p, sz=%d bytes\n", 4340 ioc->name, mem, sz)); 4341 mem = kmalloc(sz, GFP_ATOMIC); 4342 if (mem == NULL) 4343 return -1; 4344 4345 ioc->RequestNB = (int *) mem; 4346 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestNB alloc @ %p, sz=%d bytes\n", 4347 ioc->name, mem, sz)); 4348 } 4349 for (ii = 0; ii < ioc->req_depth; ii++) { 4350 ioc->ReqToChain[ii] = MPT_HOST_NO_CHAIN; 4351 } 4352 4353 /* ChainToChain size must equal the total number 4354 * of chain buffers to be allocated. 4355 * index = chain_idx 4356 * 4357 * Calculate the number of chain buffers needed(plus 1) per I/O 4358 * then multiply the maximum number of simultaneous cmds 4359 * 4360 * num_sge = num sge in request frame + last chain buffer 4361 * scale = num sge per chain buffer if no chain element 4362 */ 4363 scale = ioc->req_sz / ioc->SGE_size; 4364 if (ioc->sg_addr_size == sizeof(u64)) 4365 num_sge = scale + (ioc->req_sz - 60) / ioc->SGE_size; 4366 else 4367 num_sge = 1 + scale + (ioc->req_sz - 64) / ioc->SGE_size; 4368 4369 if (ioc->sg_addr_size == sizeof(u64)) { 4370 numSGE = (scale - 1) * (ioc->facts.MaxChainDepth-1) + scale + 4371 (ioc->req_sz - 60) / ioc->SGE_size; 4372 } else { 4373 numSGE = 1 + (scale - 1) * (ioc->facts.MaxChainDepth-1) + 4374 scale + (ioc->req_sz - 64) / ioc->SGE_size; 4375 } 4376 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "num_sge=%d numSGE=%d\n", 4377 ioc->name, num_sge, numSGE)); 4378 4379 if (ioc->bus_type == FC) { 4380 if (numSGE > MPT_SCSI_FC_SG_DEPTH) 4381 numSGE = MPT_SCSI_FC_SG_DEPTH; 4382 } else { 4383 if (numSGE > MPT_SCSI_SG_DEPTH) 4384 numSGE = MPT_SCSI_SG_DEPTH; 4385 } 4386 4387 num_chain = 1; 4388 while (numSGE - num_sge > 0) { 4389 num_chain++; 4390 num_sge += (scale - 1); 4391 } 4392 num_chain++; 4393 4394 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Now numSGE=%d num_sge=%d num_chain=%d\n", 4395 ioc->name, numSGE, num_sge, num_chain)); 4396 4397 if (ioc->bus_type == SPI) 4398 num_chain *= MPT_SCSI_CAN_QUEUE; 4399 else if (ioc->bus_type == SAS) 4400 num_chain *= MPT_SAS_CAN_QUEUE; 4401 else 4402 num_chain *= MPT_FC_CAN_QUEUE; 4403 4404 ioc->num_chain = num_chain; 4405 4406 sz = num_chain * sizeof(int); 4407 if (ioc->ChainToChain == NULL) { 4408 mem = kmalloc(sz, GFP_ATOMIC); 4409 if (mem == NULL) 4410 return -1; 4411 4412 ioc->ChainToChain = (int *) mem; 4413 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainToChain alloc @ %p, sz=%d bytes\n", 4414 ioc->name, mem, sz)); 4415 } else { 4416 mem = (u8 *) ioc->ChainToChain; 4417 } 4418 memset(mem, 0xFF, sz); 4419 return num_chain; 4420 } 4421 4422 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4423 /** 4424 * PrimeIocFifos - Initialize IOC request and reply FIFOs. 4425 * @ioc: Pointer to MPT_ADAPTER structure 4426 * 4427 * This routine allocates memory for the MPT reply and request frame 4428 * pools (if necessary), and primes the IOC reply FIFO with 4429 * reply frames. 4430 * 4431 * Returns 0 for success, non-zero for failure. 4432 */ 4433 static int 4434 PrimeIocFifos(MPT_ADAPTER *ioc) 4435 { 4436 MPT_FRAME_HDR *mf; 4437 unsigned long flags; 4438 dma_addr_t alloc_dma; 4439 u8 *mem; 4440 int i, reply_sz, sz, total_size, num_chain; 4441 u64 dma_mask; 4442 4443 dma_mask = 0; 4444 4445 /* Prime reply FIFO... */ 4446 4447 if (ioc->reply_frames == NULL) { 4448 if ( (num_chain = initChainBuffers(ioc)) < 0) 4449 return -1; 4450 /* 4451 * 1078 errata workaround for the 36GB limitation 4452 */ 4453 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078 && 4454 ioc->dma_mask > DMA_BIT_MASK(35)) { 4455 if (!pci_set_dma_mask(ioc->pcidev, DMA_BIT_MASK(32)) 4456 && !pci_set_consistent_dma_mask(ioc->pcidev, 4457 DMA_BIT_MASK(32))) { 4458 dma_mask = DMA_BIT_MASK(35); 4459 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4460 "setting 35 bit addressing for " 4461 "Request/Reply/Chain and Sense Buffers\n", 4462 ioc->name)); 4463 } else { 4464 /*Reseting DMA mask to 64 bit*/ 4465 pci_set_dma_mask(ioc->pcidev, 4466 DMA_BIT_MASK(64)); 4467 pci_set_consistent_dma_mask(ioc->pcidev, 4468 DMA_BIT_MASK(64)); 4469 4470 printk(MYIOC_s_ERR_FMT 4471 "failed setting 35 bit addressing for " 4472 "Request/Reply/Chain and Sense Buffers\n", 4473 ioc->name); 4474 return -1; 4475 } 4476 } 4477 4478 total_size = reply_sz = (ioc->reply_sz * ioc->reply_depth); 4479 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d bytes, ReplyDepth=%d\n", 4480 ioc->name, ioc->reply_sz, ioc->reply_depth)); 4481 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d[%x] bytes\n", 4482 ioc->name, reply_sz, reply_sz)); 4483 4484 sz = (ioc->req_sz * ioc->req_depth); 4485 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d bytes, RequestDepth=%d\n", 4486 ioc->name, ioc->req_sz, ioc->req_depth)); 4487 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d[%x] bytes\n", 4488 ioc->name, sz, sz)); 4489 total_size += sz; 4490 4491 sz = num_chain * ioc->req_sz; /* chain buffer pool size */ 4492 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d bytes, ChainDepth=%d\n", 4493 ioc->name, ioc->req_sz, num_chain)); 4494 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d[%x] bytes num_chain=%d\n", 4495 ioc->name, sz, sz, num_chain)); 4496 4497 total_size += sz; 4498 mem = dma_alloc_coherent(&ioc->pcidev->dev, total_size, 4499 &alloc_dma, GFP_KERNEL); 4500 if (mem == NULL) { 4501 printk(MYIOC_s_ERR_FMT "Unable to allocate Reply, Request, Chain Buffers!\n", 4502 ioc->name); 4503 goto out_fail; 4504 } 4505 4506 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Total alloc @ %p[%p], sz=%d[%x] bytes\n", 4507 ioc->name, mem, (void *)(ulong)alloc_dma, total_size, total_size)); 4508 4509 memset(mem, 0, total_size); 4510 ioc->alloc_total += total_size; 4511 ioc->alloc = mem; 4512 ioc->alloc_dma = alloc_dma; 4513 ioc->alloc_sz = total_size; 4514 ioc->reply_frames = (MPT_FRAME_HDR *) mem; 4515 ioc->reply_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF); 4516 4517 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n", 4518 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma)); 4519 4520 alloc_dma += reply_sz; 4521 mem += reply_sz; 4522 4523 /* Request FIFO - WE manage this! */ 4524 4525 ioc->req_frames = (MPT_FRAME_HDR *) mem; 4526 ioc->req_frames_dma = alloc_dma; 4527 4528 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffers @ %p[%p]\n", 4529 ioc->name, mem, (void *)(ulong)alloc_dma)); 4530 4531 ioc->req_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF); 4532 4533 for (i = 0; i < ioc->req_depth; i++) { 4534 alloc_dma += ioc->req_sz; 4535 mem += ioc->req_sz; 4536 } 4537 4538 ioc->ChainBuffer = mem; 4539 ioc->ChainBufferDMA = alloc_dma; 4540 4541 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffers @ %p(%p)\n", 4542 ioc->name, ioc->ChainBuffer, (void *)(ulong)ioc->ChainBufferDMA)); 4543 4544 /* Initialize the free chain Q. 4545 */ 4546 4547 INIT_LIST_HEAD(&ioc->FreeChainQ); 4548 4549 /* Post the chain buffers to the FreeChainQ. 4550 */ 4551 mem = (u8 *)ioc->ChainBuffer; 4552 for (i=0; i < num_chain; i++) { 4553 mf = (MPT_FRAME_HDR *) mem; 4554 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeChainQ); 4555 mem += ioc->req_sz; 4556 } 4557 4558 /* Initialize Request frames linked list 4559 */ 4560 alloc_dma = ioc->req_frames_dma; 4561 mem = (u8 *) ioc->req_frames; 4562 4563 spin_lock_irqsave(&ioc->FreeQlock, flags); 4564 INIT_LIST_HEAD(&ioc->FreeQ); 4565 for (i = 0; i < ioc->req_depth; i++) { 4566 mf = (MPT_FRAME_HDR *) mem; 4567 4568 /* Queue REQUESTs *internally*! */ 4569 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeQ); 4570 4571 mem += ioc->req_sz; 4572 } 4573 spin_unlock_irqrestore(&ioc->FreeQlock, flags); 4574 4575 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC); 4576 ioc->sense_buf_pool = dma_alloc_coherent(&ioc->pcidev->dev, sz, 4577 &ioc->sense_buf_pool_dma, GFP_KERNEL); 4578 if (ioc->sense_buf_pool == NULL) { 4579 printk(MYIOC_s_ERR_FMT "Unable to allocate Sense Buffers!\n", 4580 ioc->name); 4581 goto out_fail; 4582 } 4583 4584 ioc->sense_buf_low_dma = (u32) (ioc->sense_buf_pool_dma & 0xFFFFFFFF); 4585 ioc->alloc_total += sz; 4586 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SenseBuffers @ %p[%p]\n", 4587 ioc->name, ioc->sense_buf_pool, (void *)(ulong)ioc->sense_buf_pool_dma)); 4588 4589 } 4590 4591 /* Post Reply frames to FIFO 4592 */ 4593 alloc_dma = ioc->alloc_dma; 4594 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n", 4595 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma)); 4596 4597 for (i = 0; i < ioc->reply_depth; i++) { 4598 /* Write each address to the IOC! */ 4599 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, alloc_dma); 4600 alloc_dma += ioc->reply_sz; 4601 } 4602 4603 if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev, 4604 ioc->dma_mask) && !pci_set_consistent_dma_mask(ioc->pcidev, 4605 ioc->dma_mask)) 4606 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4607 "restoring 64 bit addressing\n", ioc->name)); 4608 4609 return 0; 4610 4611 out_fail: 4612 4613 if (ioc->alloc != NULL) { 4614 sz = ioc->alloc_sz; 4615 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->alloc, 4616 ioc->alloc_dma); 4617 ioc->reply_frames = NULL; 4618 ioc->req_frames = NULL; 4619 ioc->alloc_total -= sz; 4620 } 4621 if (ioc->sense_buf_pool != NULL) { 4622 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC); 4623 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->sense_buf_pool, 4624 ioc->sense_buf_pool_dma); 4625 ioc->sense_buf_pool = NULL; 4626 } 4627 4628 if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev, 4629 DMA_BIT_MASK(64)) && !pci_set_consistent_dma_mask(ioc->pcidev, 4630 DMA_BIT_MASK(64))) 4631 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4632 "restoring 64 bit addressing\n", ioc->name)); 4633 4634 return -1; 4635 } 4636 4637 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4638 /** 4639 * mpt_handshake_req_reply_wait - Send MPT request to and receive reply 4640 * from IOC via doorbell handshake method. 4641 * @ioc: Pointer to MPT_ADAPTER structure 4642 * @reqBytes: Size of the request in bytes 4643 * @req: Pointer to MPT request frame 4644 * @replyBytes: Expected size of the reply in bytes 4645 * @u16reply: Pointer to area where reply should be written 4646 * @maxwait: Max wait time for a reply (in seconds) 4647 * @sleepFlag: Specifies whether the process can sleep 4648 * 4649 * NOTES: It is the callers responsibility to byte-swap fields in the 4650 * request which are greater than 1 byte in size. It is also the 4651 * callers responsibility to byte-swap response fields which are 4652 * greater than 1 byte in size. 4653 * 4654 * Returns 0 for success, non-zero for failure. 4655 */ 4656 static int 4657 mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, u32 *req, 4658 int replyBytes, u16 *u16reply, int maxwait, int sleepFlag) 4659 { 4660 MPIDefaultReply_t *mptReply; 4661 int failcnt = 0; 4662 int t; 4663 4664 /* 4665 * Get ready to cache a handshake reply 4666 */ 4667 ioc->hs_reply_idx = 0; 4668 mptReply = (MPIDefaultReply_t *) ioc->hs_reply; 4669 mptReply->MsgLength = 0; 4670 4671 /* 4672 * Make sure there are no doorbells (WRITE 0 to IntStatus reg), 4673 * then tell IOC that we want to handshake a request of N words. 4674 * (WRITE u32val to Doorbell reg). 4675 */ 4676 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4677 CHIPREG_WRITE32(&ioc->chip->Doorbell, 4678 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) | 4679 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT))); 4680 4681 /* 4682 * Wait for IOC's doorbell handshake int 4683 */ 4684 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) 4685 failcnt++; 4686 4687 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request start reqBytes=%d, WaitCnt=%d%s\n", 4688 ioc->name, reqBytes, t, failcnt ? " - MISSING DOORBELL HANDSHAKE!" : "")); 4689 4690 /* Read doorbell and check for active bit */ 4691 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE)) 4692 return -1; 4693 4694 /* 4695 * Clear doorbell int (WRITE 0 to IntStatus reg), 4696 * then wait for IOC to ACKnowledge that it's ready for 4697 * our handshake request. 4698 */ 4699 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4700 if (!failcnt && (t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) 4701 failcnt++; 4702 4703 if (!failcnt) { 4704 int ii; 4705 u8 *req_as_bytes = (u8 *) req; 4706 4707 /* 4708 * Stuff request words via doorbell handshake, 4709 * with ACK from IOC for each. 4710 */ 4711 for (ii = 0; !failcnt && ii < reqBytes/4; ii++) { 4712 u32 word = ((req_as_bytes[(ii*4) + 0] << 0) | 4713 (req_as_bytes[(ii*4) + 1] << 8) | 4714 (req_as_bytes[(ii*4) + 2] << 16) | 4715 (req_as_bytes[(ii*4) + 3] << 24)); 4716 4717 CHIPREG_WRITE32(&ioc->chip->Doorbell, word); 4718 if ((t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) 4719 failcnt++; 4720 } 4721 4722 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Handshake request frame (@%p) header\n", ioc->name, req)); 4723 DBG_DUMP_REQUEST_FRAME_HDR(ioc, (u32 *)req); 4724 4725 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request post done, WaitCnt=%d%s\n", 4726 ioc->name, t, failcnt ? " - MISSING DOORBELL ACK!" : "")); 4727 4728 /* 4729 * Wait for completion of doorbell handshake reply from the IOC 4730 */ 4731 if (!failcnt && (t = WaitForDoorbellReply(ioc, maxwait, sleepFlag)) < 0) 4732 failcnt++; 4733 4734 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake reply count=%d%s\n", 4735 ioc->name, t, failcnt ? " - MISSING DOORBELL REPLY!" : "")); 4736 4737 /* 4738 * Copy out the cached reply... 4739 */ 4740 for (ii=0; ii < min(replyBytes/2,mptReply->MsgLength*2); ii++) 4741 u16reply[ii] = ioc->hs_reply[ii]; 4742 } else { 4743 return -99; 4744 } 4745 4746 return -failcnt; 4747 } 4748 4749 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4750 /** 4751 * WaitForDoorbellAck - Wait for IOC doorbell handshake acknowledge 4752 * @ioc: Pointer to MPT_ADAPTER structure 4753 * @howlong: How long to wait (in seconds) 4754 * @sleepFlag: Specifies whether the process can sleep 4755 * 4756 * This routine waits (up to ~2 seconds max) for IOC doorbell 4757 * handshake ACKnowledge, indicated by the IOP_DOORBELL_STATUS 4758 * bit in its IntStatus register being clear. 4759 * 4760 * Returns a negative value on failure, else wait loop count. 4761 */ 4762 static int 4763 WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag) 4764 { 4765 int cntdn; 4766 int count = 0; 4767 u32 intstat=0; 4768 4769 cntdn = 1000 * howlong; 4770 4771 if (sleepFlag == CAN_SLEEP) { 4772 while (--cntdn) { 4773 msleep (1); 4774 intstat = CHIPREG_READ32(&ioc->chip->IntStatus); 4775 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS)) 4776 break; 4777 count++; 4778 } 4779 } else { 4780 while (--cntdn) { 4781 udelay (1000); 4782 intstat = CHIPREG_READ32(&ioc->chip->IntStatus); 4783 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS)) 4784 break; 4785 count++; 4786 } 4787 } 4788 4789 if (cntdn) { 4790 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell ACK (count=%d)\n", 4791 ioc->name, count)); 4792 return count; 4793 } 4794 4795 printk(MYIOC_s_ERR_FMT "Doorbell ACK timeout (count=%d), IntStatus=%x!\n", 4796 ioc->name, count, intstat); 4797 return -1; 4798 } 4799 4800 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4801 /** 4802 * WaitForDoorbellInt - Wait for IOC to set its doorbell interrupt bit 4803 * @ioc: Pointer to MPT_ADAPTER structure 4804 * @howlong: How long to wait (in seconds) 4805 * @sleepFlag: Specifies whether the process can sleep 4806 * 4807 * This routine waits (up to ~2 seconds max) for IOC doorbell interrupt 4808 * (MPI_HIS_DOORBELL_INTERRUPT) to be set in the IntStatus register. 4809 * 4810 * Returns a negative value on failure, else wait loop count. 4811 */ 4812 static int 4813 WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag) 4814 { 4815 int cntdn; 4816 int count = 0; 4817 u32 intstat=0; 4818 4819 cntdn = 1000 * howlong; 4820 if (sleepFlag == CAN_SLEEP) { 4821 while (--cntdn) { 4822 intstat = CHIPREG_READ32(&ioc->chip->IntStatus); 4823 if (intstat & MPI_HIS_DOORBELL_INTERRUPT) 4824 break; 4825 msleep(1); 4826 count++; 4827 } 4828 } else { 4829 while (--cntdn) { 4830 intstat = CHIPREG_READ32(&ioc->chip->IntStatus); 4831 if (intstat & MPI_HIS_DOORBELL_INTERRUPT) 4832 break; 4833 udelay (1000); 4834 count++; 4835 } 4836 } 4837 4838 if (cntdn) { 4839 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell INT (cnt=%d) howlong=%d\n", 4840 ioc->name, count, howlong)); 4841 return count; 4842 } 4843 4844 printk(MYIOC_s_ERR_FMT "Doorbell INT timeout (count=%d), IntStatus=%x!\n", 4845 ioc->name, count, intstat); 4846 return -1; 4847 } 4848 4849 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4850 /** 4851 * WaitForDoorbellReply - Wait for and capture an IOC handshake reply. 4852 * @ioc: Pointer to MPT_ADAPTER structure 4853 * @howlong: How long to wait (in seconds) 4854 * @sleepFlag: Specifies whether the process can sleep 4855 * 4856 * This routine polls the IOC for a handshake reply, 16 bits at a time. 4857 * Reply is cached to IOC private area large enough to hold a maximum 4858 * of 128 bytes of reply data. 4859 * 4860 * Returns a negative value on failure, else size of reply in WORDS. 4861 */ 4862 static int 4863 WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag) 4864 { 4865 int u16cnt = 0; 4866 int failcnt = 0; 4867 int t; 4868 u16 *hs_reply = ioc->hs_reply; 4869 volatile MPIDefaultReply_t *mptReply = (MPIDefaultReply_t *) ioc->hs_reply; 4870 u16 hword; 4871 4872 hs_reply[0] = hs_reply[1] = hs_reply[7] = 0; 4873 4874 /* 4875 * Get first two u16's so we can look at IOC's intended reply MsgLength 4876 */ 4877 u16cnt=0; 4878 if ((t = WaitForDoorbellInt(ioc, howlong, sleepFlag)) < 0) { 4879 failcnt++; 4880 } else { 4881 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF); 4882 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4883 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) 4884 failcnt++; 4885 else { 4886 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF); 4887 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4888 } 4889 } 4890 4891 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitCnt=%d First handshake reply word=%08x%s\n", 4892 ioc->name, t, le32_to_cpu(*(u32 *)hs_reply), 4893 failcnt ? " - MISSING DOORBELL HANDSHAKE!" : "")); 4894 4895 /* 4896 * If no error (and IOC said MsgLength is > 0), piece together 4897 * reply 16 bits at a time. 4898 */ 4899 for (u16cnt=2; !failcnt && u16cnt < (2 * mptReply->MsgLength); u16cnt++) { 4900 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) 4901 failcnt++; 4902 hword = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF); 4903 /* don't overflow our IOC hs_reply[] buffer! */ 4904 if (u16cnt < ARRAY_SIZE(ioc->hs_reply)) 4905 hs_reply[u16cnt] = hword; 4906 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4907 } 4908 4909 if (!failcnt && (t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) 4910 failcnt++; 4911 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4912 4913 if (failcnt) { 4914 printk(MYIOC_s_ERR_FMT "Handshake reply failure!\n", 4915 ioc->name); 4916 return -failcnt; 4917 } 4918 #if 0 4919 else if (u16cnt != (2 * mptReply->MsgLength)) { 4920 return -101; 4921 } 4922 else if ((mptReply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { 4923 return -102; 4924 } 4925 #endif 4926 4927 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got Handshake reply:\n", ioc->name)); 4928 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mptReply); 4929 4930 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell REPLY WaitCnt=%d (sz=%d)\n", 4931 ioc->name, t, u16cnt/2)); 4932 return u16cnt/2; 4933 } 4934 4935 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4936 /** 4937 * GetLanConfigPages - Fetch LANConfig pages. 4938 * @ioc: Pointer to MPT_ADAPTER structure 4939 * 4940 * Return: 0 for success 4941 * -ENOMEM if no memory available 4942 * -EPERM if not allowed due to ISR context 4943 * -EAGAIN if no msg frames currently available 4944 * -EFAULT for non-successful reply or no reply (timeout) 4945 */ 4946 static int 4947 GetLanConfigPages(MPT_ADAPTER *ioc) 4948 { 4949 ConfigPageHeader_t hdr; 4950 CONFIGPARMS cfg; 4951 LANPage0_t *ppage0_alloc; 4952 dma_addr_t page0_dma; 4953 LANPage1_t *ppage1_alloc; 4954 dma_addr_t page1_dma; 4955 int rc = 0; 4956 int data_sz; 4957 int copy_sz; 4958 4959 /* Get LAN Page 0 header */ 4960 hdr.PageVersion = 0; 4961 hdr.PageLength = 0; 4962 hdr.PageNumber = 0; 4963 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN; 4964 cfg.cfghdr.hdr = &hdr; 4965 cfg.physAddr = -1; 4966 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 4967 cfg.dir = 0; 4968 cfg.pageAddr = 0; 4969 cfg.timeout = 0; 4970 4971 if ((rc = mpt_config(ioc, &cfg)) != 0) 4972 return rc; 4973 4974 if (hdr.PageLength > 0) { 4975 data_sz = hdr.PageLength * 4; 4976 ppage0_alloc = pci_alloc_consistent(ioc->pcidev, data_sz, &page0_dma); 4977 rc = -ENOMEM; 4978 if (ppage0_alloc) { 4979 memset((u8 *)ppage0_alloc, 0, data_sz); 4980 cfg.physAddr = page0_dma; 4981 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 4982 4983 if ((rc = mpt_config(ioc, &cfg)) == 0) { 4984 /* save the data */ 4985 copy_sz = min_t(int, sizeof(LANPage0_t), data_sz); 4986 memcpy(&ioc->lan_cnfg_page0, ppage0_alloc, copy_sz); 4987 4988 } 4989 4990 pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage0_alloc, page0_dma); 4991 4992 /* FIXME! 4993 * Normalize endianness of structure data, 4994 * by byte-swapping all > 1 byte fields! 4995 */ 4996 4997 } 4998 4999 if (rc) 5000 return rc; 5001 } 5002 5003 /* Get LAN Page 1 header */ 5004 hdr.PageVersion = 0; 5005 hdr.PageLength = 0; 5006 hdr.PageNumber = 1; 5007 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN; 5008 cfg.cfghdr.hdr = &hdr; 5009 cfg.physAddr = -1; 5010 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5011 cfg.dir = 0; 5012 cfg.pageAddr = 0; 5013 5014 if ((rc = mpt_config(ioc, &cfg)) != 0) 5015 return rc; 5016 5017 if (hdr.PageLength == 0) 5018 return 0; 5019 5020 data_sz = hdr.PageLength * 4; 5021 rc = -ENOMEM; 5022 ppage1_alloc = pci_alloc_consistent(ioc->pcidev, data_sz, &page1_dma); 5023 if (ppage1_alloc) { 5024 memset((u8 *)ppage1_alloc, 0, data_sz); 5025 cfg.physAddr = page1_dma; 5026 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5027 5028 if ((rc = mpt_config(ioc, &cfg)) == 0) { 5029 /* save the data */ 5030 copy_sz = min_t(int, sizeof(LANPage1_t), data_sz); 5031 memcpy(&ioc->lan_cnfg_page1, ppage1_alloc, copy_sz); 5032 } 5033 5034 pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage1_alloc, page1_dma); 5035 5036 /* FIXME! 5037 * Normalize endianness of structure data, 5038 * by byte-swapping all > 1 byte fields! 5039 */ 5040 5041 } 5042 5043 return rc; 5044 } 5045 5046 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5047 /** 5048 * mptbase_sas_persist_operation - Perform operation on SAS Persistent Table 5049 * @ioc: Pointer to MPT_ADAPTER structure 5050 * @persist_opcode: see below 5051 * 5052 * =============================== ====================================== 5053 * MPI_SAS_OP_CLEAR_NOT_PRESENT Free all persist TargetID mappings for 5054 * devices not currently present. 5055 * MPI_SAS_OP_CLEAR_ALL_PERSISTENT Clear al persist TargetID mappings 5056 * =============================== ====================================== 5057 * 5058 * NOTE: Don't use not this function during interrupt time. 5059 * 5060 * Returns 0 for success, non-zero error 5061 */ 5062 5063 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5064 int 5065 mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode) 5066 { 5067 SasIoUnitControlRequest_t *sasIoUnitCntrReq; 5068 SasIoUnitControlReply_t *sasIoUnitCntrReply; 5069 MPT_FRAME_HDR *mf = NULL; 5070 MPIHeader_t *mpi_hdr; 5071 int ret = 0; 5072 unsigned long timeleft; 5073 5074 mutex_lock(&ioc->mptbase_cmds.mutex); 5075 5076 /* init the internal cmd struct */ 5077 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE); 5078 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status) 5079 5080 /* insure garbage is not sent to fw */ 5081 switch(persist_opcode) { 5082 5083 case MPI_SAS_OP_CLEAR_NOT_PRESENT: 5084 case MPI_SAS_OP_CLEAR_ALL_PERSISTENT: 5085 break; 5086 5087 default: 5088 ret = -1; 5089 goto out; 5090 } 5091 5092 printk(KERN_DEBUG "%s: persist_opcode=%x\n", 5093 __func__, persist_opcode); 5094 5095 /* Get a MF for this command. 5096 */ 5097 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) { 5098 printk(KERN_DEBUG "%s: no msg frames!\n", __func__); 5099 ret = -1; 5100 goto out; 5101 } 5102 5103 mpi_hdr = (MPIHeader_t *) mf; 5104 sasIoUnitCntrReq = (SasIoUnitControlRequest_t *)mf; 5105 memset(sasIoUnitCntrReq,0,sizeof(SasIoUnitControlRequest_t)); 5106 sasIoUnitCntrReq->Function = MPI_FUNCTION_SAS_IO_UNIT_CONTROL; 5107 sasIoUnitCntrReq->MsgContext = mpi_hdr->MsgContext; 5108 sasIoUnitCntrReq->Operation = persist_opcode; 5109 5110 mpt_put_msg_frame(mpt_base_index, ioc, mf); 5111 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, 10*HZ); 5112 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { 5113 ret = -ETIME; 5114 printk(KERN_DEBUG "%s: failed\n", __func__); 5115 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) 5116 goto out; 5117 if (!timeleft) { 5118 printk(MYIOC_s_WARN_FMT 5119 "Issuing Reset from %s!!, doorbell=0x%08x\n", 5120 ioc->name, __func__, mpt_GetIocState(ioc, 0)); 5121 mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP); 5122 mpt_free_msg_frame(ioc, mf); 5123 } 5124 goto out; 5125 } 5126 5127 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) { 5128 ret = -1; 5129 goto out; 5130 } 5131 5132 sasIoUnitCntrReply = 5133 (SasIoUnitControlReply_t *)ioc->mptbase_cmds.reply; 5134 if (le16_to_cpu(sasIoUnitCntrReply->IOCStatus) != MPI_IOCSTATUS_SUCCESS) { 5135 printk(KERN_DEBUG "%s: IOCStatus=0x%X IOCLogInfo=0x%X\n", 5136 __func__, sasIoUnitCntrReply->IOCStatus, 5137 sasIoUnitCntrReply->IOCLogInfo); 5138 printk(KERN_DEBUG "%s: failed\n", __func__); 5139 ret = -1; 5140 } else 5141 printk(KERN_DEBUG "%s: success\n", __func__); 5142 out: 5143 5144 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status) 5145 mutex_unlock(&ioc->mptbase_cmds.mutex); 5146 return ret; 5147 } 5148 5149 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5150 5151 static void 5152 mptbase_raid_process_event_data(MPT_ADAPTER *ioc, 5153 MpiEventDataRaid_t * pRaidEventData) 5154 { 5155 int volume; 5156 int reason; 5157 int disk; 5158 int status; 5159 int flags; 5160 int state; 5161 5162 volume = pRaidEventData->VolumeID; 5163 reason = pRaidEventData->ReasonCode; 5164 disk = pRaidEventData->PhysDiskNum; 5165 status = le32_to_cpu(pRaidEventData->SettingsStatus); 5166 flags = (status >> 0) & 0xff; 5167 state = (status >> 8) & 0xff; 5168 5169 if (reason == MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED) { 5170 return; 5171 } 5172 5173 if ((reason >= MPI_EVENT_RAID_RC_PHYSDISK_CREATED && 5174 reason <= MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED) || 5175 (reason == MPI_EVENT_RAID_RC_SMART_DATA)) { 5176 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for PhysDisk %d id=%d\n", 5177 ioc->name, disk, volume); 5178 } else { 5179 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for VolumeID %d\n", 5180 ioc->name, volume); 5181 } 5182 5183 switch(reason) { 5184 case MPI_EVENT_RAID_RC_VOLUME_CREATED: 5185 printk(MYIOC_s_INFO_FMT " volume has been created\n", 5186 ioc->name); 5187 break; 5188 5189 case MPI_EVENT_RAID_RC_VOLUME_DELETED: 5190 5191 printk(MYIOC_s_INFO_FMT " volume has been deleted\n", 5192 ioc->name); 5193 break; 5194 5195 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED: 5196 printk(MYIOC_s_INFO_FMT " volume settings have been changed\n", 5197 ioc->name); 5198 break; 5199 5200 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED: 5201 printk(MYIOC_s_INFO_FMT " volume is now %s%s%s%s\n", 5202 ioc->name, 5203 state == MPI_RAIDVOL0_STATUS_STATE_OPTIMAL 5204 ? "optimal" 5205 : state == MPI_RAIDVOL0_STATUS_STATE_DEGRADED 5206 ? "degraded" 5207 : state == MPI_RAIDVOL0_STATUS_STATE_FAILED 5208 ? "failed" 5209 : "state unknown", 5210 flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED 5211 ? ", enabled" : "", 5212 flags & MPI_RAIDVOL0_STATUS_FLAG_QUIESCED 5213 ? ", quiesced" : "", 5214 flags & MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS 5215 ? ", resync in progress" : "" ); 5216 break; 5217 5218 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED: 5219 printk(MYIOC_s_INFO_FMT " volume membership of PhysDisk %d has changed\n", 5220 ioc->name, disk); 5221 break; 5222 5223 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED: 5224 printk(MYIOC_s_INFO_FMT " PhysDisk has been created\n", 5225 ioc->name); 5226 break; 5227 5228 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED: 5229 printk(MYIOC_s_INFO_FMT " PhysDisk has been deleted\n", 5230 ioc->name); 5231 break; 5232 5233 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED: 5234 printk(MYIOC_s_INFO_FMT " PhysDisk settings have been changed\n", 5235 ioc->name); 5236 break; 5237 5238 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED: 5239 printk(MYIOC_s_INFO_FMT " PhysDisk is now %s%s%s\n", 5240 ioc->name, 5241 state == MPI_PHYSDISK0_STATUS_ONLINE 5242 ? "online" 5243 : state == MPI_PHYSDISK0_STATUS_MISSING 5244 ? "missing" 5245 : state == MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE 5246 ? "not compatible" 5247 : state == MPI_PHYSDISK0_STATUS_FAILED 5248 ? "failed" 5249 : state == MPI_PHYSDISK0_STATUS_INITIALIZING 5250 ? "initializing" 5251 : state == MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED 5252 ? "offline requested" 5253 : state == MPI_PHYSDISK0_STATUS_FAILED_REQUESTED 5254 ? "failed requested" 5255 : state == MPI_PHYSDISK0_STATUS_OTHER_OFFLINE 5256 ? "offline" 5257 : "state unknown", 5258 flags & MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC 5259 ? ", out of sync" : "", 5260 flags & MPI_PHYSDISK0_STATUS_FLAG_QUIESCED 5261 ? ", quiesced" : "" ); 5262 break; 5263 5264 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED: 5265 printk(MYIOC_s_INFO_FMT " Domain Validation needed for PhysDisk %d\n", 5266 ioc->name, disk); 5267 break; 5268 5269 case MPI_EVENT_RAID_RC_SMART_DATA: 5270 printk(MYIOC_s_INFO_FMT " SMART data received, ASC/ASCQ = %02xh/%02xh\n", 5271 ioc->name, pRaidEventData->ASC, pRaidEventData->ASCQ); 5272 break; 5273 5274 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED: 5275 printk(MYIOC_s_INFO_FMT " replacement of PhysDisk %d has started\n", 5276 ioc->name, disk); 5277 break; 5278 } 5279 } 5280 5281 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5282 /** 5283 * GetIoUnitPage2 - Retrieve BIOS version and boot order information. 5284 * @ioc: Pointer to MPT_ADAPTER structure 5285 * 5286 * Returns: 0 for success 5287 * -ENOMEM if no memory available 5288 * -EPERM if not allowed due to ISR context 5289 * -EAGAIN if no msg frames currently available 5290 * -EFAULT for non-successful reply or no reply (timeout) 5291 */ 5292 static int 5293 GetIoUnitPage2(MPT_ADAPTER *ioc) 5294 { 5295 ConfigPageHeader_t hdr; 5296 CONFIGPARMS cfg; 5297 IOUnitPage2_t *ppage_alloc; 5298 dma_addr_t page_dma; 5299 int data_sz; 5300 int rc; 5301 5302 /* Get the page header */ 5303 hdr.PageVersion = 0; 5304 hdr.PageLength = 0; 5305 hdr.PageNumber = 2; 5306 hdr.PageType = MPI_CONFIG_PAGETYPE_IO_UNIT; 5307 cfg.cfghdr.hdr = &hdr; 5308 cfg.physAddr = -1; 5309 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5310 cfg.dir = 0; 5311 cfg.pageAddr = 0; 5312 cfg.timeout = 0; 5313 5314 if ((rc = mpt_config(ioc, &cfg)) != 0) 5315 return rc; 5316 5317 if (hdr.PageLength == 0) 5318 return 0; 5319 5320 /* Read the config page */ 5321 data_sz = hdr.PageLength * 4; 5322 rc = -ENOMEM; 5323 ppage_alloc = pci_alloc_consistent(ioc->pcidev, data_sz, &page_dma); 5324 if (ppage_alloc) { 5325 memset((u8 *)ppage_alloc, 0, data_sz); 5326 cfg.physAddr = page_dma; 5327 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5328 5329 /* If Good, save data */ 5330 if ((rc = mpt_config(ioc, &cfg)) == 0) 5331 ioc->biosVersion = le32_to_cpu(ppage_alloc->BiosVersion); 5332 5333 pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage_alloc, page_dma); 5334 } 5335 5336 return rc; 5337 } 5338 5339 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5340 /** 5341 * mpt_GetScsiPortSettings - read SCSI Port Page 0 and 2 5342 * @ioc: Pointer to a Adapter Strucutre 5343 * @portnum: IOC port number 5344 * 5345 * Return: -EFAULT if read of config page header fails 5346 * or if no nvram 5347 * If read of SCSI Port Page 0 fails, 5348 * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF) 5349 * Adapter settings: async, narrow 5350 * Return 1 5351 * If read of SCSI Port Page 2 fails, 5352 * Adapter settings valid 5353 * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF) 5354 * Return 1 5355 * Else 5356 * Both valid 5357 * Return 0 5358 * CHECK - what type of locking mechanisms should be used???? 5359 */ 5360 static int 5361 mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum) 5362 { 5363 u8 *pbuf; 5364 dma_addr_t buf_dma; 5365 CONFIGPARMS cfg; 5366 ConfigPageHeader_t header; 5367 int ii; 5368 int data, rc = 0; 5369 5370 /* Allocate memory 5371 */ 5372 if (!ioc->spi_data.nvram) { 5373 int sz; 5374 u8 *mem; 5375 sz = MPT_MAX_SCSI_DEVICES * sizeof(int); 5376 mem = kmalloc(sz, GFP_ATOMIC); 5377 if (mem == NULL) 5378 return -EFAULT; 5379 5380 ioc->spi_data.nvram = (int *) mem; 5381 5382 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SCSI device NVRAM settings @ %p, sz=%d\n", 5383 ioc->name, ioc->spi_data.nvram, sz)); 5384 } 5385 5386 /* Invalidate NVRAM information 5387 */ 5388 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) { 5389 ioc->spi_data.nvram[ii] = MPT_HOST_NVRAM_INVALID; 5390 } 5391 5392 /* Read SPP0 header, allocate memory, then read page. 5393 */ 5394 header.PageVersion = 0; 5395 header.PageLength = 0; 5396 header.PageNumber = 0; 5397 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT; 5398 cfg.cfghdr.hdr = &header; 5399 cfg.physAddr = -1; 5400 cfg.pageAddr = portnum; 5401 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5402 cfg.dir = 0; 5403 cfg.timeout = 0; /* use default */ 5404 if (mpt_config(ioc, &cfg) != 0) 5405 return -EFAULT; 5406 5407 if (header.PageLength > 0) { 5408 pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma); 5409 if (pbuf) { 5410 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5411 cfg.physAddr = buf_dma; 5412 if (mpt_config(ioc, &cfg) != 0) { 5413 ioc->spi_data.maxBusWidth = MPT_NARROW; 5414 ioc->spi_data.maxSyncOffset = 0; 5415 ioc->spi_data.minSyncFactor = MPT_ASYNC; 5416 ioc->spi_data.busType = MPT_HOST_BUS_UNKNOWN; 5417 rc = 1; 5418 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT 5419 "Unable to read PortPage0 minSyncFactor=%x\n", 5420 ioc->name, ioc->spi_data.minSyncFactor)); 5421 } else { 5422 /* Save the Port Page 0 data 5423 */ 5424 SCSIPortPage0_t *pPP0 = (SCSIPortPage0_t *) pbuf; 5425 pPP0->Capabilities = le32_to_cpu(pPP0->Capabilities); 5426 pPP0->PhysicalInterface = le32_to_cpu(pPP0->PhysicalInterface); 5427 5428 if ( (pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_QAS) == 0 ) { 5429 ioc->spi_data.noQas |= MPT_TARGET_NO_NEGO_QAS; 5430 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT 5431 "noQas due to Capabilities=%x\n", 5432 ioc->name, pPP0->Capabilities)); 5433 } 5434 ioc->spi_data.maxBusWidth = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_WIDE ? 1 : 0; 5435 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK; 5436 if (data) { 5437 ioc->spi_data.maxSyncOffset = (u8) (data >> 16); 5438 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK; 5439 ioc->spi_data.minSyncFactor = (u8) (data >> 8); 5440 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT 5441 "PortPage0 minSyncFactor=%x\n", 5442 ioc->name, ioc->spi_data.minSyncFactor)); 5443 } else { 5444 ioc->spi_data.maxSyncOffset = 0; 5445 ioc->spi_data.minSyncFactor = MPT_ASYNC; 5446 } 5447 5448 ioc->spi_data.busType = pPP0->PhysicalInterface & MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK; 5449 5450 /* Update the minSyncFactor based on bus type. 5451 */ 5452 if ((ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD) || 5453 (ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE)) { 5454 5455 if (ioc->spi_data.minSyncFactor < MPT_ULTRA) { 5456 ioc->spi_data.minSyncFactor = MPT_ULTRA; 5457 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT 5458 "HVD or SE detected, minSyncFactor=%x\n", 5459 ioc->name, ioc->spi_data.minSyncFactor)); 5460 } 5461 } 5462 } 5463 if (pbuf) { 5464 pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma); 5465 } 5466 } 5467 } 5468 5469 /* SCSI Port Page 2 - Read the header then the page. 5470 */ 5471 header.PageVersion = 0; 5472 header.PageLength = 0; 5473 header.PageNumber = 2; 5474 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT; 5475 cfg.cfghdr.hdr = &header; 5476 cfg.physAddr = -1; 5477 cfg.pageAddr = portnum; 5478 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5479 cfg.dir = 0; 5480 if (mpt_config(ioc, &cfg) != 0) 5481 return -EFAULT; 5482 5483 if (header.PageLength > 0) { 5484 /* Allocate memory and read SCSI Port Page 2 5485 */ 5486 pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma); 5487 if (pbuf) { 5488 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_NVRAM; 5489 cfg.physAddr = buf_dma; 5490 if (mpt_config(ioc, &cfg) != 0) { 5491 /* Nvram data is left with INVALID mark 5492 */ 5493 rc = 1; 5494 } else if (ioc->pcidev->vendor == PCI_VENDOR_ID_ATTO) { 5495 5496 /* This is an ATTO adapter, read Page2 accordingly 5497 */ 5498 ATTO_SCSIPortPage2_t *pPP2 = (ATTO_SCSIPortPage2_t *) pbuf; 5499 ATTODeviceInfo_t *pdevice = NULL; 5500 u16 ATTOFlags; 5501 5502 /* Save the Port Page 2 data 5503 * (reformat into a 32bit quantity) 5504 */ 5505 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) { 5506 pdevice = &pPP2->DeviceSettings[ii]; 5507 ATTOFlags = le16_to_cpu(pdevice->ATTOFlags); 5508 data = 0; 5509 5510 /* Translate ATTO device flags to LSI format 5511 */ 5512 if (ATTOFlags & ATTOFLAG_DISC) 5513 data |= (MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE); 5514 if (ATTOFlags & ATTOFLAG_ID_ENB) 5515 data |= (MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE); 5516 if (ATTOFlags & ATTOFLAG_LUN_ENB) 5517 data |= (MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE); 5518 if (ATTOFlags & ATTOFLAG_TAGGED) 5519 data |= (MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE); 5520 if (!(ATTOFlags & ATTOFLAG_WIDE_ENB)) 5521 data |= (MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE); 5522 5523 data = (data << 16) | (pdevice->Period << 8) | 10; 5524 ioc->spi_data.nvram[ii] = data; 5525 } 5526 } else { 5527 SCSIPortPage2_t *pPP2 = (SCSIPortPage2_t *) pbuf; 5528 MpiDeviceInfo_t *pdevice = NULL; 5529 5530 /* 5531 * Save "Set to Avoid SCSI Bus Resets" flag 5532 */ 5533 ioc->spi_data.bus_reset = 5534 (le32_to_cpu(pPP2->PortFlags) & 5535 MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET) ? 5536 0 : 1 ; 5537 5538 /* Save the Port Page 2 data 5539 * (reformat into a 32bit quantity) 5540 */ 5541 data = le32_to_cpu(pPP2->PortFlags) & MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK; 5542 ioc->spi_data.PortFlags = data; 5543 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) { 5544 pdevice = &pPP2->DeviceSettings[ii]; 5545 data = (le16_to_cpu(pdevice->DeviceFlags) << 16) | 5546 (pdevice->SyncFactor << 8) | pdevice->Timeout; 5547 ioc->spi_data.nvram[ii] = data; 5548 } 5549 } 5550 5551 pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma); 5552 } 5553 } 5554 5555 /* Update Adapter limits with those from NVRAM 5556 * Comment: Don't need to do this. Target performance 5557 * parameters will never exceed the adapters limits. 5558 */ 5559 5560 return rc; 5561 } 5562 5563 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5564 /** 5565 * mpt_readScsiDevicePageHeaders - save version and length of SDP1 5566 * @ioc: Pointer to a Adapter Strucutre 5567 * @portnum: IOC port number 5568 * 5569 * Return: -EFAULT if read of config page header fails 5570 * or 0 if success. 5571 */ 5572 static int 5573 mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum) 5574 { 5575 CONFIGPARMS cfg; 5576 ConfigPageHeader_t header; 5577 5578 /* Read the SCSI Device Page 1 header 5579 */ 5580 header.PageVersion = 0; 5581 header.PageLength = 0; 5582 header.PageNumber = 1; 5583 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE; 5584 cfg.cfghdr.hdr = &header; 5585 cfg.physAddr = -1; 5586 cfg.pageAddr = portnum; 5587 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5588 cfg.dir = 0; 5589 cfg.timeout = 0; 5590 if (mpt_config(ioc, &cfg) != 0) 5591 return -EFAULT; 5592 5593 ioc->spi_data.sdp1version = cfg.cfghdr.hdr->PageVersion; 5594 ioc->spi_data.sdp1length = cfg.cfghdr.hdr->PageLength; 5595 5596 header.PageVersion = 0; 5597 header.PageLength = 0; 5598 header.PageNumber = 0; 5599 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE; 5600 if (mpt_config(ioc, &cfg) != 0) 5601 return -EFAULT; 5602 5603 ioc->spi_data.sdp0version = cfg.cfghdr.hdr->PageVersion; 5604 ioc->spi_data.sdp0length = cfg.cfghdr.hdr->PageLength; 5605 5606 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 0: version %d length %d\n", 5607 ioc->name, ioc->spi_data.sdp0version, ioc->spi_data.sdp0length)); 5608 5609 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 1: version %d length %d\n", 5610 ioc->name, ioc->spi_data.sdp1version, ioc->spi_data.sdp1length)); 5611 return 0; 5612 } 5613 5614 /** 5615 * mpt_inactive_raid_list_free - This clears this link list. 5616 * @ioc : pointer to per adapter structure 5617 **/ 5618 static void 5619 mpt_inactive_raid_list_free(MPT_ADAPTER *ioc) 5620 { 5621 struct inactive_raid_component_info *component_info, *pNext; 5622 5623 if (list_empty(&ioc->raid_data.inactive_list)) 5624 return; 5625 5626 mutex_lock(&ioc->raid_data.inactive_list_mutex); 5627 list_for_each_entry_safe(component_info, pNext, 5628 &ioc->raid_data.inactive_list, list) { 5629 list_del(&component_info->list); 5630 kfree(component_info); 5631 } 5632 mutex_unlock(&ioc->raid_data.inactive_list_mutex); 5633 } 5634 5635 /** 5636 * mpt_inactive_raid_volumes - sets up link list of phy_disk_nums for devices belonging in an inactive volume 5637 * 5638 * @ioc : pointer to per adapter structure 5639 * @channel : volume channel 5640 * @id : volume target id 5641 **/ 5642 static void 5643 mpt_inactive_raid_volumes(MPT_ADAPTER *ioc, u8 channel, u8 id) 5644 { 5645 CONFIGPARMS cfg; 5646 ConfigPageHeader_t hdr; 5647 dma_addr_t dma_handle; 5648 pRaidVolumePage0_t buffer = NULL; 5649 int i; 5650 RaidPhysDiskPage0_t phys_disk; 5651 struct inactive_raid_component_info *component_info; 5652 int handle_inactive_volumes; 5653 5654 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 5655 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 5656 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_VOLUME; 5657 cfg.pageAddr = (channel << 8) + id; 5658 cfg.cfghdr.hdr = &hdr; 5659 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5660 5661 if (mpt_config(ioc, &cfg) != 0) 5662 goto out; 5663 5664 if (!hdr.PageLength) 5665 goto out; 5666 5667 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, 5668 &dma_handle); 5669 5670 if (!buffer) 5671 goto out; 5672 5673 cfg.physAddr = dma_handle; 5674 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5675 5676 if (mpt_config(ioc, &cfg) != 0) 5677 goto out; 5678 5679 if (!buffer->NumPhysDisks) 5680 goto out; 5681 5682 handle_inactive_volumes = 5683 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE || 5684 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED) == 0 || 5685 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_FAILED || 5686 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_MISSING) ? 1 : 0; 5687 5688 if (!handle_inactive_volumes) 5689 goto out; 5690 5691 mutex_lock(&ioc->raid_data.inactive_list_mutex); 5692 for (i = 0; i < buffer->NumPhysDisks; i++) { 5693 if(mpt_raid_phys_disk_pg0(ioc, 5694 buffer->PhysDisk[i].PhysDiskNum, &phys_disk) != 0) 5695 continue; 5696 5697 if ((component_info = kmalloc(sizeof (*component_info), 5698 GFP_KERNEL)) == NULL) 5699 continue; 5700 5701 component_info->volumeID = id; 5702 component_info->volumeBus = channel; 5703 component_info->d.PhysDiskNum = phys_disk.PhysDiskNum; 5704 component_info->d.PhysDiskBus = phys_disk.PhysDiskBus; 5705 component_info->d.PhysDiskID = phys_disk.PhysDiskID; 5706 component_info->d.PhysDiskIOC = phys_disk.PhysDiskIOC; 5707 5708 list_add_tail(&component_info->list, 5709 &ioc->raid_data.inactive_list); 5710 } 5711 mutex_unlock(&ioc->raid_data.inactive_list_mutex); 5712 5713 out: 5714 if (buffer) 5715 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer, 5716 dma_handle); 5717 } 5718 5719 /** 5720 * mpt_raid_phys_disk_pg0 - returns phys disk page zero 5721 * @ioc: Pointer to a Adapter Structure 5722 * @phys_disk_num: io unit unique phys disk num generated by the ioc 5723 * @phys_disk: requested payload data returned 5724 * 5725 * Return: 5726 * 0 on success 5727 * -EFAULT if read of config page header fails or data pointer not NULL 5728 * -ENOMEM if pci_alloc failed 5729 **/ 5730 int 5731 mpt_raid_phys_disk_pg0(MPT_ADAPTER *ioc, u8 phys_disk_num, 5732 RaidPhysDiskPage0_t *phys_disk) 5733 { 5734 CONFIGPARMS cfg; 5735 ConfigPageHeader_t hdr; 5736 dma_addr_t dma_handle; 5737 pRaidPhysDiskPage0_t buffer = NULL; 5738 int rc; 5739 5740 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 5741 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 5742 memset(phys_disk, 0, sizeof(RaidPhysDiskPage0_t)); 5743 5744 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE0_PAGEVERSION; 5745 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK; 5746 cfg.cfghdr.hdr = &hdr; 5747 cfg.physAddr = -1; 5748 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5749 5750 if (mpt_config(ioc, &cfg) != 0) { 5751 rc = -EFAULT; 5752 goto out; 5753 } 5754 5755 if (!hdr.PageLength) { 5756 rc = -EFAULT; 5757 goto out; 5758 } 5759 5760 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, 5761 &dma_handle); 5762 5763 if (!buffer) { 5764 rc = -ENOMEM; 5765 goto out; 5766 } 5767 5768 cfg.physAddr = dma_handle; 5769 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5770 cfg.pageAddr = phys_disk_num; 5771 5772 if (mpt_config(ioc, &cfg) != 0) { 5773 rc = -EFAULT; 5774 goto out; 5775 } 5776 5777 rc = 0; 5778 memcpy(phys_disk, buffer, sizeof(*buffer)); 5779 phys_disk->MaxLBA = le32_to_cpu(buffer->MaxLBA); 5780 5781 out: 5782 5783 if (buffer) 5784 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer, 5785 dma_handle); 5786 5787 return rc; 5788 } 5789 5790 /** 5791 * mpt_raid_phys_disk_get_num_paths - returns number paths associated to this phys_num 5792 * @ioc: Pointer to a Adapter Structure 5793 * @phys_disk_num: io unit unique phys disk num generated by the ioc 5794 * 5795 * Return: 5796 * returns number paths 5797 **/ 5798 int 5799 mpt_raid_phys_disk_get_num_paths(MPT_ADAPTER *ioc, u8 phys_disk_num) 5800 { 5801 CONFIGPARMS cfg; 5802 ConfigPageHeader_t hdr; 5803 dma_addr_t dma_handle; 5804 pRaidPhysDiskPage1_t buffer = NULL; 5805 int rc; 5806 5807 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 5808 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 5809 5810 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION; 5811 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK; 5812 hdr.PageNumber = 1; 5813 cfg.cfghdr.hdr = &hdr; 5814 cfg.physAddr = -1; 5815 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5816 5817 if (mpt_config(ioc, &cfg) != 0) { 5818 rc = 0; 5819 goto out; 5820 } 5821 5822 if (!hdr.PageLength) { 5823 rc = 0; 5824 goto out; 5825 } 5826 5827 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, 5828 &dma_handle); 5829 5830 if (!buffer) { 5831 rc = 0; 5832 goto out; 5833 } 5834 5835 cfg.physAddr = dma_handle; 5836 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5837 cfg.pageAddr = phys_disk_num; 5838 5839 if (mpt_config(ioc, &cfg) != 0) { 5840 rc = 0; 5841 goto out; 5842 } 5843 5844 rc = buffer->NumPhysDiskPaths; 5845 out: 5846 5847 if (buffer) 5848 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer, 5849 dma_handle); 5850 5851 return rc; 5852 } 5853 EXPORT_SYMBOL(mpt_raid_phys_disk_get_num_paths); 5854 5855 /** 5856 * mpt_raid_phys_disk_pg1 - returns phys disk page 1 5857 * @ioc: Pointer to a Adapter Structure 5858 * @phys_disk_num: io unit unique phys disk num generated by the ioc 5859 * @phys_disk: requested payload data returned 5860 * 5861 * Return: 5862 * 0 on success 5863 * -EFAULT if read of config page header fails or data pointer not NULL 5864 * -ENOMEM if pci_alloc failed 5865 **/ 5866 int 5867 mpt_raid_phys_disk_pg1(MPT_ADAPTER *ioc, u8 phys_disk_num, 5868 RaidPhysDiskPage1_t *phys_disk) 5869 { 5870 CONFIGPARMS cfg; 5871 ConfigPageHeader_t hdr; 5872 dma_addr_t dma_handle; 5873 pRaidPhysDiskPage1_t buffer = NULL; 5874 int rc; 5875 int i; 5876 __le64 sas_address; 5877 5878 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 5879 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 5880 rc = 0; 5881 5882 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION; 5883 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK; 5884 hdr.PageNumber = 1; 5885 cfg.cfghdr.hdr = &hdr; 5886 cfg.physAddr = -1; 5887 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5888 5889 if (mpt_config(ioc, &cfg) != 0) { 5890 rc = -EFAULT; 5891 goto out; 5892 } 5893 5894 if (!hdr.PageLength) { 5895 rc = -EFAULT; 5896 goto out; 5897 } 5898 5899 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, 5900 &dma_handle); 5901 5902 if (!buffer) { 5903 rc = -ENOMEM; 5904 goto out; 5905 } 5906 5907 cfg.physAddr = dma_handle; 5908 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5909 cfg.pageAddr = phys_disk_num; 5910 5911 if (mpt_config(ioc, &cfg) != 0) { 5912 rc = -EFAULT; 5913 goto out; 5914 } 5915 5916 phys_disk->NumPhysDiskPaths = buffer->NumPhysDiskPaths; 5917 phys_disk->PhysDiskNum = phys_disk_num; 5918 for (i = 0; i < phys_disk->NumPhysDiskPaths; i++) { 5919 phys_disk->Path[i].PhysDiskID = buffer->Path[i].PhysDiskID; 5920 phys_disk->Path[i].PhysDiskBus = buffer->Path[i].PhysDiskBus; 5921 phys_disk->Path[i].OwnerIdentifier = 5922 buffer->Path[i].OwnerIdentifier; 5923 phys_disk->Path[i].Flags = le16_to_cpu(buffer->Path[i].Flags); 5924 memcpy(&sas_address, &buffer->Path[i].WWID, sizeof(__le64)); 5925 sas_address = le64_to_cpu(sas_address); 5926 memcpy(&phys_disk->Path[i].WWID, &sas_address, sizeof(__le64)); 5927 memcpy(&sas_address, 5928 &buffer->Path[i].OwnerWWID, sizeof(__le64)); 5929 sas_address = le64_to_cpu(sas_address); 5930 memcpy(&phys_disk->Path[i].OwnerWWID, 5931 &sas_address, sizeof(__le64)); 5932 } 5933 5934 out: 5935 5936 if (buffer) 5937 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer, 5938 dma_handle); 5939 5940 return rc; 5941 } 5942 EXPORT_SYMBOL(mpt_raid_phys_disk_pg1); 5943 5944 5945 /** 5946 * mpt_findImVolumes - Identify IDs of hidden disks and RAID Volumes 5947 * @ioc: Pointer to a Adapter Strucutre 5948 * 5949 * Return: 5950 * 0 on success 5951 * -EFAULT if read of config page header fails or data pointer not NULL 5952 * -ENOMEM if pci_alloc failed 5953 **/ 5954 int 5955 mpt_findImVolumes(MPT_ADAPTER *ioc) 5956 { 5957 IOCPage2_t *pIoc2; 5958 u8 *mem; 5959 dma_addr_t ioc2_dma; 5960 CONFIGPARMS cfg; 5961 ConfigPageHeader_t header; 5962 int rc = 0; 5963 int iocpage2sz; 5964 int i; 5965 5966 if (!ioc->ir_firmware) 5967 return 0; 5968 5969 /* Free the old page 5970 */ 5971 kfree(ioc->raid_data.pIocPg2); 5972 ioc->raid_data.pIocPg2 = NULL; 5973 mpt_inactive_raid_list_free(ioc); 5974 5975 /* Read IOCP2 header then the page. 5976 */ 5977 header.PageVersion = 0; 5978 header.PageLength = 0; 5979 header.PageNumber = 2; 5980 header.PageType = MPI_CONFIG_PAGETYPE_IOC; 5981 cfg.cfghdr.hdr = &header; 5982 cfg.physAddr = -1; 5983 cfg.pageAddr = 0; 5984 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5985 cfg.dir = 0; 5986 cfg.timeout = 0; 5987 if (mpt_config(ioc, &cfg) != 0) 5988 return -EFAULT; 5989 5990 if (header.PageLength == 0) 5991 return -EFAULT; 5992 5993 iocpage2sz = header.PageLength * 4; 5994 pIoc2 = pci_alloc_consistent(ioc->pcidev, iocpage2sz, &ioc2_dma); 5995 if (!pIoc2) 5996 return -ENOMEM; 5997 5998 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5999 cfg.physAddr = ioc2_dma; 6000 if (mpt_config(ioc, &cfg) != 0) 6001 goto out; 6002 6003 mem = kmemdup(pIoc2, iocpage2sz, GFP_KERNEL); 6004 if (!mem) { 6005 rc = -ENOMEM; 6006 goto out; 6007 } 6008 6009 ioc->raid_data.pIocPg2 = (IOCPage2_t *) mem; 6010 6011 mpt_read_ioc_pg_3(ioc); 6012 6013 for (i = 0; i < pIoc2->NumActiveVolumes ; i++) 6014 mpt_inactive_raid_volumes(ioc, 6015 pIoc2->RaidVolume[i].VolumeBus, 6016 pIoc2->RaidVolume[i].VolumeID); 6017 6018 out: 6019 pci_free_consistent(ioc->pcidev, iocpage2sz, pIoc2, ioc2_dma); 6020 6021 return rc; 6022 } 6023 6024 static int 6025 mpt_read_ioc_pg_3(MPT_ADAPTER *ioc) 6026 { 6027 IOCPage3_t *pIoc3; 6028 u8 *mem; 6029 CONFIGPARMS cfg; 6030 ConfigPageHeader_t header; 6031 dma_addr_t ioc3_dma; 6032 int iocpage3sz = 0; 6033 6034 /* Free the old page 6035 */ 6036 kfree(ioc->raid_data.pIocPg3); 6037 ioc->raid_data.pIocPg3 = NULL; 6038 6039 /* There is at least one physical disk. 6040 * Read and save IOC Page 3 6041 */ 6042 header.PageVersion = 0; 6043 header.PageLength = 0; 6044 header.PageNumber = 3; 6045 header.PageType = MPI_CONFIG_PAGETYPE_IOC; 6046 cfg.cfghdr.hdr = &header; 6047 cfg.physAddr = -1; 6048 cfg.pageAddr = 0; 6049 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 6050 cfg.dir = 0; 6051 cfg.timeout = 0; 6052 if (mpt_config(ioc, &cfg) != 0) 6053 return 0; 6054 6055 if (header.PageLength == 0) 6056 return 0; 6057 6058 /* Read Header good, alloc memory 6059 */ 6060 iocpage3sz = header.PageLength * 4; 6061 pIoc3 = pci_alloc_consistent(ioc->pcidev, iocpage3sz, &ioc3_dma); 6062 if (!pIoc3) 6063 return 0; 6064 6065 /* Read the Page and save the data 6066 * into malloc'd memory. 6067 */ 6068 cfg.physAddr = ioc3_dma; 6069 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 6070 if (mpt_config(ioc, &cfg) == 0) { 6071 mem = kmalloc(iocpage3sz, GFP_KERNEL); 6072 if (mem) { 6073 memcpy(mem, (u8 *)pIoc3, iocpage3sz); 6074 ioc->raid_data.pIocPg3 = (IOCPage3_t *) mem; 6075 } 6076 } 6077 6078 pci_free_consistent(ioc->pcidev, iocpage3sz, pIoc3, ioc3_dma); 6079 6080 return 0; 6081 } 6082 6083 static void 6084 mpt_read_ioc_pg_4(MPT_ADAPTER *ioc) 6085 { 6086 IOCPage4_t *pIoc4; 6087 CONFIGPARMS cfg; 6088 ConfigPageHeader_t header; 6089 dma_addr_t ioc4_dma; 6090 int iocpage4sz; 6091 6092 /* Read and save IOC Page 4 6093 */ 6094 header.PageVersion = 0; 6095 header.PageLength = 0; 6096 header.PageNumber = 4; 6097 header.PageType = MPI_CONFIG_PAGETYPE_IOC; 6098 cfg.cfghdr.hdr = &header; 6099 cfg.physAddr = -1; 6100 cfg.pageAddr = 0; 6101 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 6102 cfg.dir = 0; 6103 cfg.timeout = 0; 6104 if (mpt_config(ioc, &cfg) != 0) 6105 return; 6106 6107 if (header.PageLength == 0) 6108 return; 6109 6110 if ( (pIoc4 = ioc->spi_data.pIocPg4) == NULL ) { 6111 iocpage4sz = (header.PageLength + 4) * 4; /* Allow 4 additional SEP's */ 6112 pIoc4 = pci_alloc_consistent(ioc->pcidev, iocpage4sz, &ioc4_dma); 6113 if (!pIoc4) 6114 return; 6115 ioc->alloc_total += iocpage4sz; 6116 } else { 6117 ioc4_dma = ioc->spi_data.IocPg4_dma; 6118 iocpage4sz = ioc->spi_data.IocPg4Sz; 6119 } 6120 6121 /* Read the Page into dma memory. 6122 */ 6123 cfg.physAddr = ioc4_dma; 6124 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 6125 if (mpt_config(ioc, &cfg) == 0) { 6126 ioc->spi_data.pIocPg4 = (IOCPage4_t *) pIoc4; 6127 ioc->spi_data.IocPg4_dma = ioc4_dma; 6128 ioc->spi_data.IocPg4Sz = iocpage4sz; 6129 } else { 6130 pci_free_consistent(ioc->pcidev, iocpage4sz, pIoc4, ioc4_dma); 6131 ioc->spi_data.pIocPg4 = NULL; 6132 ioc->alloc_total -= iocpage4sz; 6133 } 6134 } 6135 6136 static void 6137 mpt_read_ioc_pg_1(MPT_ADAPTER *ioc) 6138 { 6139 IOCPage1_t *pIoc1; 6140 CONFIGPARMS cfg; 6141 ConfigPageHeader_t header; 6142 dma_addr_t ioc1_dma; 6143 int iocpage1sz = 0; 6144 u32 tmp; 6145 6146 /* Check the Coalescing Timeout in IOC Page 1 6147 */ 6148 header.PageVersion = 0; 6149 header.PageLength = 0; 6150 header.PageNumber = 1; 6151 header.PageType = MPI_CONFIG_PAGETYPE_IOC; 6152 cfg.cfghdr.hdr = &header; 6153 cfg.physAddr = -1; 6154 cfg.pageAddr = 0; 6155 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 6156 cfg.dir = 0; 6157 cfg.timeout = 0; 6158 if (mpt_config(ioc, &cfg) != 0) 6159 return; 6160 6161 if (header.PageLength == 0) 6162 return; 6163 6164 /* Read Header good, alloc memory 6165 */ 6166 iocpage1sz = header.PageLength * 4; 6167 pIoc1 = pci_alloc_consistent(ioc->pcidev, iocpage1sz, &ioc1_dma); 6168 if (!pIoc1) 6169 return; 6170 6171 /* Read the Page and check coalescing timeout 6172 */ 6173 cfg.physAddr = ioc1_dma; 6174 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 6175 if (mpt_config(ioc, &cfg) == 0) { 6176 6177 tmp = le32_to_cpu(pIoc1->Flags) & MPI_IOCPAGE1_REPLY_COALESCING; 6178 if (tmp == MPI_IOCPAGE1_REPLY_COALESCING) { 6179 tmp = le32_to_cpu(pIoc1->CoalescingTimeout); 6180 6181 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Coalescing Enabled Timeout = %d\n", 6182 ioc->name, tmp)); 6183 6184 if (tmp > MPT_COALESCING_TIMEOUT) { 6185 pIoc1->CoalescingTimeout = cpu_to_le32(MPT_COALESCING_TIMEOUT); 6186 6187 /* Write NVRAM and current 6188 */ 6189 cfg.dir = 1; 6190 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT; 6191 if (mpt_config(ioc, &cfg) == 0) { 6192 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Reset Current Coalescing Timeout to = %d\n", 6193 ioc->name, MPT_COALESCING_TIMEOUT)); 6194 6195 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM; 6196 if (mpt_config(ioc, &cfg) == 0) { 6197 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6198 "Reset NVRAM Coalescing Timeout to = %d\n", 6199 ioc->name, MPT_COALESCING_TIMEOUT)); 6200 } else { 6201 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6202 "Reset NVRAM Coalescing Timeout Failed\n", 6203 ioc->name)); 6204 } 6205 6206 } else { 6207 dprintk(ioc, printk(MYIOC_s_WARN_FMT 6208 "Reset of Current Coalescing Timeout Failed!\n", 6209 ioc->name)); 6210 } 6211 } 6212 6213 } else { 6214 dprintk(ioc, printk(MYIOC_s_WARN_FMT "Coalescing Disabled\n", ioc->name)); 6215 } 6216 } 6217 6218 pci_free_consistent(ioc->pcidev, iocpage1sz, pIoc1, ioc1_dma); 6219 6220 return; 6221 } 6222 6223 static void 6224 mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc) 6225 { 6226 CONFIGPARMS cfg; 6227 ConfigPageHeader_t hdr; 6228 dma_addr_t buf_dma; 6229 ManufacturingPage0_t *pbuf = NULL; 6230 6231 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 6232 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 6233 6234 hdr.PageType = MPI_CONFIG_PAGETYPE_MANUFACTURING; 6235 cfg.cfghdr.hdr = &hdr; 6236 cfg.physAddr = -1; 6237 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 6238 cfg.timeout = 10; 6239 6240 if (mpt_config(ioc, &cfg) != 0) 6241 goto out; 6242 6243 if (!cfg.cfghdr.hdr->PageLength) 6244 goto out; 6245 6246 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 6247 pbuf = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, &buf_dma); 6248 if (!pbuf) 6249 goto out; 6250 6251 cfg.physAddr = buf_dma; 6252 6253 if (mpt_config(ioc, &cfg) != 0) 6254 goto out; 6255 6256 memcpy(ioc->board_name, pbuf->BoardName, sizeof(ioc->board_name)); 6257 memcpy(ioc->board_assembly, pbuf->BoardAssembly, sizeof(ioc->board_assembly)); 6258 memcpy(ioc->board_tracer, pbuf->BoardTracerNumber, sizeof(ioc->board_tracer)); 6259 6260 out: 6261 6262 if (pbuf) 6263 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, pbuf, buf_dma); 6264 } 6265 6266 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6267 /** 6268 * SendEventNotification - Send EventNotification (on or off) request to adapter 6269 * @ioc: Pointer to MPT_ADAPTER structure 6270 * @EvSwitch: Event switch flags 6271 * @sleepFlag: Specifies whether the process can sleep 6272 */ 6273 static int 6274 SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch, int sleepFlag) 6275 { 6276 EventNotification_t evn; 6277 MPIDefaultReply_t reply_buf; 6278 6279 memset(&evn, 0, sizeof(EventNotification_t)); 6280 memset(&reply_buf, 0, sizeof(MPIDefaultReply_t)); 6281 6282 evn.Function = MPI_FUNCTION_EVENT_NOTIFICATION; 6283 evn.Switch = EvSwitch; 6284 evn.MsgContext = cpu_to_le32(mpt_base_index << 16); 6285 6286 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6287 "Sending EventNotification (%d) request %p\n", 6288 ioc->name, EvSwitch, &evn)); 6289 6290 return mpt_handshake_req_reply_wait(ioc, sizeof(EventNotification_t), 6291 (u32 *)&evn, sizeof(MPIDefaultReply_t), (u16 *)&reply_buf, 30, 6292 sleepFlag); 6293 } 6294 6295 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6296 /** 6297 * SendEventAck - Send EventAck request to MPT adapter. 6298 * @ioc: Pointer to MPT_ADAPTER structure 6299 * @evnp: Pointer to original EventNotification request 6300 */ 6301 static int 6302 SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp) 6303 { 6304 EventAck_t *pAck; 6305 6306 if ((pAck = (EventAck_t *) mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) { 6307 dfailprintk(ioc, printk(MYIOC_s_WARN_FMT "%s, no msg frames!!\n", 6308 ioc->name, __func__)); 6309 return -1; 6310 } 6311 6312 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending EventAck\n", ioc->name)); 6313 6314 pAck->Function = MPI_FUNCTION_EVENT_ACK; 6315 pAck->ChainOffset = 0; 6316 pAck->Reserved[0] = pAck->Reserved[1] = 0; 6317 pAck->MsgFlags = 0; 6318 pAck->Reserved1[0] = pAck->Reserved1[1] = pAck->Reserved1[2] = 0; 6319 pAck->Event = evnp->Event; 6320 pAck->EventContext = evnp->EventContext; 6321 6322 mpt_put_msg_frame(mpt_base_index, ioc, (MPT_FRAME_HDR *)pAck); 6323 6324 return 0; 6325 } 6326 6327 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6328 /** 6329 * mpt_config - Generic function to issue config message 6330 * @ioc: Pointer to an adapter structure 6331 * @pCfg: Pointer to a configuration structure. Struct contains 6332 * action, page address, direction, physical address 6333 * and pointer to a configuration page header 6334 * Page header is updated. 6335 * 6336 * Returns 0 for success 6337 * -EAGAIN if no msg frames currently available 6338 * -EFAULT for non-successful reply or no reply (timeout) 6339 */ 6340 int 6341 mpt_config(MPT_ADAPTER *ioc, CONFIGPARMS *pCfg) 6342 { 6343 Config_t *pReq; 6344 ConfigReply_t *pReply; 6345 ConfigExtendedPageHeader_t *pExtHdr = NULL; 6346 MPT_FRAME_HDR *mf; 6347 int ii; 6348 int flagsLength; 6349 long timeout; 6350 int ret; 6351 u8 page_type = 0, extend_page; 6352 unsigned long timeleft; 6353 unsigned long flags; 6354 u8 issue_hard_reset = 0; 6355 u8 retry_count = 0; 6356 6357 might_sleep(); 6358 6359 /* don't send a config page during diag reset */ 6360 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6361 if (ioc->ioc_reset_in_progress) { 6362 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6363 "%s: busy with host reset\n", ioc->name, __func__)); 6364 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6365 return -EBUSY; 6366 } 6367 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6368 6369 /* don't send if no chance of success */ 6370 if (!ioc->active || 6371 mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_OPERATIONAL) { 6372 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6373 "%s: ioc not operational, %d, %xh\n", 6374 ioc->name, __func__, ioc->active, 6375 mpt_GetIocState(ioc, 0))); 6376 return -EFAULT; 6377 } 6378 6379 retry_config: 6380 mutex_lock(&ioc->mptbase_cmds.mutex); 6381 /* init the internal cmd struct */ 6382 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE); 6383 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status) 6384 6385 /* Get and Populate a free Frame 6386 */ 6387 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) { 6388 dcprintk(ioc, printk(MYIOC_s_WARN_FMT 6389 "mpt_config: no msg frames!\n", ioc->name)); 6390 ret = -EAGAIN; 6391 goto out; 6392 } 6393 6394 pReq = (Config_t *)mf; 6395 pReq->Action = pCfg->action; 6396 pReq->Reserved = 0; 6397 pReq->ChainOffset = 0; 6398 pReq->Function = MPI_FUNCTION_CONFIG; 6399 6400 /* Assume page type is not extended and clear "reserved" fields. */ 6401 pReq->ExtPageLength = 0; 6402 pReq->ExtPageType = 0; 6403 pReq->MsgFlags = 0; 6404 6405 for (ii=0; ii < 8; ii++) 6406 pReq->Reserved2[ii] = 0; 6407 6408 pReq->Header.PageVersion = pCfg->cfghdr.hdr->PageVersion; 6409 pReq->Header.PageLength = pCfg->cfghdr.hdr->PageLength; 6410 pReq->Header.PageNumber = pCfg->cfghdr.hdr->PageNumber; 6411 pReq->Header.PageType = (pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK); 6412 6413 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == MPI_CONFIG_PAGETYPE_EXTENDED) { 6414 pExtHdr = (ConfigExtendedPageHeader_t *)pCfg->cfghdr.ehdr; 6415 pReq->ExtPageLength = cpu_to_le16(pExtHdr->ExtPageLength); 6416 pReq->ExtPageType = pExtHdr->ExtPageType; 6417 pReq->Header.PageType = MPI_CONFIG_PAGETYPE_EXTENDED; 6418 6419 /* Page Length must be treated as a reserved field for the 6420 * extended header. 6421 */ 6422 pReq->Header.PageLength = 0; 6423 } 6424 6425 pReq->PageAddress = cpu_to_le32(pCfg->pageAddr); 6426 6427 /* Add a SGE to the config request. 6428 */ 6429 if (pCfg->dir) 6430 flagsLength = MPT_SGE_FLAGS_SSIMPLE_WRITE; 6431 else 6432 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ; 6433 6434 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == 6435 MPI_CONFIG_PAGETYPE_EXTENDED) { 6436 flagsLength |= pExtHdr->ExtPageLength * 4; 6437 page_type = pReq->ExtPageType; 6438 extend_page = 1; 6439 } else { 6440 flagsLength |= pCfg->cfghdr.hdr->PageLength * 4; 6441 page_type = pReq->Header.PageType; 6442 extend_page = 0; 6443 } 6444 6445 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6446 "Sending Config request type 0x%x, page 0x%x and action %d\n", 6447 ioc->name, page_type, pReq->Header.PageNumber, pReq->Action)); 6448 6449 ioc->add_sge((char *)&pReq->PageBufferSGE, flagsLength, pCfg->physAddr); 6450 timeout = (pCfg->timeout < 15) ? HZ*15 : HZ*pCfg->timeout; 6451 mpt_put_msg_frame(mpt_base_index, ioc, mf); 6452 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, 6453 timeout); 6454 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { 6455 ret = -ETIME; 6456 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6457 "Failed Sending Config request type 0x%x, page 0x%x," 6458 " action %d, status %xh, time left %ld\n\n", 6459 ioc->name, page_type, pReq->Header.PageNumber, 6460 pReq->Action, ioc->mptbase_cmds.status, timeleft)); 6461 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) 6462 goto out; 6463 if (!timeleft) { 6464 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6465 if (ioc->ioc_reset_in_progress) { 6466 spin_unlock_irqrestore(&ioc->taskmgmt_lock, 6467 flags); 6468 printk(MYIOC_s_INFO_FMT "%s: host reset in" 6469 " progress mpt_config timed out.!!\n", 6470 __func__, ioc->name); 6471 mutex_unlock(&ioc->mptbase_cmds.mutex); 6472 return -EFAULT; 6473 } 6474 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6475 issue_hard_reset = 1; 6476 } 6477 goto out; 6478 } 6479 6480 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) { 6481 ret = -1; 6482 goto out; 6483 } 6484 pReply = (ConfigReply_t *)ioc->mptbase_cmds.reply; 6485 ret = le16_to_cpu(pReply->IOCStatus) & MPI_IOCSTATUS_MASK; 6486 if (ret == MPI_IOCSTATUS_SUCCESS) { 6487 if (extend_page) { 6488 pCfg->cfghdr.ehdr->ExtPageLength = 6489 le16_to_cpu(pReply->ExtPageLength); 6490 pCfg->cfghdr.ehdr->ExtPageType = 6491 pReply->ExtPageType; 6492 } 6493 pCfg->cfghdr.hdr->PageVersion = pReply->Header.PageVersion; 6494 pCfg->cfghdr.hdr->PageLength = pReply->Header.PageLength; 6495 pCfg->cfghdr.hdr->PageNumber = pReply->Header.PageNumber; 6496 pCfg->cfghdr.hdr->PageType = pReply->Header.PageType; 6497 6498 } 6499 6500 if (retry_count) 6501 printk(MYIOC_s_INFO_FMT "Retry completed " 6502 "ret=0x%x timeleft=%ld\n", 6503 ioc->name, ret, timeleft); 6504 6505 dcprintk(ioc, printk(KERN_DEBUG "IOCStatus=%04xh, IOCLogInfo=%08xh\n", 6506 ret, le32_to_cpu(pReply->IOCLogInfo))); 6507 6508 out: 6509 6510 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status) 6511 mutex_unlock(&ioc->mptbase_cmds.mutex); 6512 if (issue_hard_reset) { 6513 issue_hard_reset = 0; 6514 printk(MYIOC_s_WARN_FMT 6515 "Issuing Reset from %s!!, doorbell=0x%08x\n", 6516 ioc->name, __func__, mpt_GetIocState(ioc, 0)); 6517 if (retry_count == 0) { 6518 if (mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP) != 0) 6519 retry_count++; 6520 } else 6521 mpt_HardResetHandler(ioc, CAN_SLEEP); 6522 6523 mpt_free_msg_frame(ioc, mf); 6524 /* attempt one retry for a timed out command */ 6525 if (retry_count < 2) { 6526 printk(MYIOC_s_INFO_FMT 6527 "Attempting Retry Config request" 6528 " type 0x%x, page 0x%x," 6529 " action %d\n", ioc->name, page_type, 6530 pCfg->cfghdr.hdr->PageNumber, pCfg->action); 6531 retry_count++; 6532 goto retry_config; 6533 } 6534 } 6535 return ret; 6536 6537 } 6538 6539 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6540 /** 6541 * mpt_ioc_reset - Base cleanup for hard reset 6542 * @ioc: Pointer to the adapter structure 6543 * @reset_phase: Indicates pre- or post-reset functionality 6544 * 6545 * Remark: Frees resources with internally generated commands. 6546 */ 6547 static int 6548 mpt_ioc_reset(MPT_ADAPTER *ioc, int reset_phase) 6549 { 6550 switch (reset_phase) { 6551 case MPT_IOC_SETUP_RESET: 6552 ioc->taskmgmt_quiesce_io = 1; 6553 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6554 "%s: MPT_IOC_SETUP_RESET\n", ioc->name, __func__)); 6555 break; 6556 case MPT_IOC_PRE_RESET: 6557 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6558 "%s: MPT_IOC_PRE_RESET\n", ioc->name, __func__)); 6559 break; 6560 case MPT_IOC_POST_RESET: 6561 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6562 "%s: MPT_IOC_POST_RESET\n", ioc->name, __func__)); 6563 /* wake up mptbase_cmds */ 6564 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) { 6565 ioc->mptbase_cmds.status |= 6566 MPT_MGMT_STATUS_DID_IOCRESET; 6567 complete(&ioc->mptbase_cmds.done); 6568 } 6569 /* wake up taskmgmt_cmds */ 6570 if (ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_PENDING) { 6571 ioc->taskmgmt_cmds.status |= 6572 MPT_MGMT_STATUS_DID_IOCRESET; 6573 complete(&ioc->taskmgmt_cmds.done); 6574 } 6575 break; 6576 default: 6577 break; 6578 } 6579 6580 return 1; /* currently means nothing really */ 6581 } 6582 6583 6584 #ifdef CONFIG_PROC_FS /* { */ 6585 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6586 /* 6587 * procfs (%MPT_PROCFS_MPTBASEDIR/...) support stuff... 6588 */ 6589 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6590 /** 6591 * procmpt_create - Create %MPT_PROCFS_MPTBASEDIR entries. 6592 * 6593 * Returns 0 for success, non-zero for failure. 6594 */ 6595 static int 6596 procmpt_create(void) 6597 { 6598 mpt_proc_root_dir = proc_mkdir(MPT_PROCFS_MPTBASEDIR, NULL); 6599 if (mpt_proc_root_dir == NULL) 6600 return -ENOTDIR; 6601 6602 proc_create_single("summary", S_IRUGO, mpt_proc_root_dir, 6603 mpt_summary_proc_show); 6604 proc_create_single("version", S_IRUGO, mpt_proc_root_dir, 6605 mpt_version_proc_show); 6606 return 0; 6607 } 6608 6609 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6610 /** 6611 * procmpt_destroy - Tear down %MPT_PROCFS_MPTBASEDIR entries. 6612 * 6613 * Returns 0 for success, non-zero for failure. 6614 */ 6615 static void 6616 procmpt_destroy(void) 6617 { 6618 remove_proc_entry("version", mpt_proc_root_dir); 6619 remove_proc_entry("summary", mpt_proc_root_dir); 6620 remove_proc_entry(MPT_PROCFS_MPTBASEDIR, NULL); 6621 } 6622 6623 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6624 /* 6625 * Handles read request from /proc/mpt/summary or /proc/mpt/iocN/summary. 6626 */ 6627 static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan); 6628 6629 static int mpt_summary_proc_show(struct seq_file *m, void *v) 6630 { 6631 MPT_ADAPTER *ioc = m->private; 6632 6633 if (ioc) { 6634 seq_mpt_print_ioc_summary(ioc, m, 1); 6635 } else { 6636 list_for_each_entry(ioc, &ioc_list, list) { 6637 seq_mpt_print_ioc_summary(ioc, m, 1); 6638 } 6639 } 6640 6641 return 0; 6642 } 6643 6644 static int mpt_version_proc_show(struct seq_file *m, void *v) 6645 { 6646 u8 cb_idx; 6647 int scsi, fc, sas, lan, ctl, targ, dmp; 6648 char *drvname; 6649 6650 seq_printf(m, "%s-%s\n", "mptlinux", MPT_LINUX_VERSION_COMMON); 6651 seq_printf(m, " Fusion MPT base driver\n"); 6652 6653 scsi = fc = sas = lan = ctl = targ = dmp = 0; 6654 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 6655 drvname = NULL; 6656 if (MptCallbacks[cb_idx]) { 6657 switch (MptDriverClass[cb_idx]) { 6658 case MPTSPI_DRIVER: 6659 if (!scsi++) drvname = "SPI host"; 6660 break; 6661 case MPTFC_DRIVER: 6662 if (!fc++) drvname = "FC host"; 6663 break; 6664 case MPTSAS_DRIVER: 6665 if (!sas++) drvname = "SAS host"; 6666 break; 6667 case MPTLAN_DRIVER: 6668 if (!lan++) drvname = "LAN"; 6669 break; 6670 case MPTSTM_DRIVER: 6671 if (!targ++) drvname = "SCSI target"; 6672 break; 6673 case MPTCTL_DRIVER: 6674 if (!ctl++) drvname = "ioctl"; 6675 break; 6676 } 6677 6678 if (drvname) 6679 seq_printf(m, " Fusion MPT %s driver\n", drvname); 6680 } 6681 } 6682 6683 return 0; 6684 } 6685 6686 static int mpt_iocinfo_proc_show(struct seq_file *m, void *v) 6687 { 6688 MPT_ADAPTER *ioc = m->private; 6689 char expVer[32]; 6690 int sz; 6691 int p; 6692 6693 mpt_get_fw_exp_ver(expVer, ioc); 6694 6695 seq_printf(m, "%s:", ioc->name); 6696 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT) 6697 seq_printf(m, " (f/w download boot flag set)"); 6698 // if (ioc->facts.IOCExceptions & MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL) 6699 // seq_printf(m, " CONFIG_CHECKSUM_FAIL!"); 6700 6701 seq_printf(m, "\n ProductID = 0x%04x (%s)\n", 6702 ioc->facts.ProductID, 6703 ioc->prod_name); 6704 seq_printf(m, " FWVersion = 0x%08x%s", ioc->facts.FWVersion.Word, expVer); 6705 if (ioc->facts.FWImageSize) 6706 seq_printf(m, " (fw_size=%d)", ioc->facts.FWImageSize); 6707 seq_printf(m, "\n MsgVersion = 0x%04x\n", ioc->facts.MsgVersion); 6708 seq_printf(m, " FirstWhoInit = 0x%02x\n", ioc->FirstWhoInit); 6709 seq_printf(m, " EventState = 0x%02x\n", ioc->facts.EventState); 6710 6711 seq_printf(m, " CurrentHostMfaHighAddr = 0x%08x\n", 6712 ioc->facts.CurrentHostMfaHighAddr); 6713 seq_printf(m, " CurrentSenseBufferHighAddr = 0x%08x\n", 6714 ioc->facts.CurrentSenseBufferHighAddr); 6715 6716 seq_printf(m, " MaxChainDepth = 0x%02x frames\n", ioc->facts.MaxChainDepth); 6717 seq_printf(m, " MinBlockSize = 0x%02x bytes\n", 4*ioc->facts.BlockSize); 6718 6719 seq_printf(m, " RequestFrames @ 0x%p (Dma @ 0x%p)\n", 6720 (void *)ioc->req_frames, (void *)(ulong)ioc->req_frames_dma); 6721 /* 6722 * Rounding UP to nearest 4-kB boundary here... 6723 */ 6724 sz = (ioc->req_sz * ioc->req_depth) + 128; 6725 sz = ((sz + 0x1000UL - 1UL) / 0x1000) * 0x1000; 6726 seq_printf(m, " {CurReqSz=%d} x {CurReqDepth=%d} = %d bytes ^= 0x%x\n", 6727 ioc->req_sz, ioc->req_depth, ioc->req_sz*ioc->req_depth, sz); 6728 seq_printf(m, " {MaxReqSz=%d} {MaxReqDepth=%d}\n", 6729 4*ioc->facts.RequestFrameSize, 6730 ioc->facts.GlobalCredits); 6731 6732 seq_printf(m, " Frames @ 0x%p (Dma @ 0x%p)\n", 6733 (void *)ioc->alloc, (void *)(ulong)ioc->alloc_dma); 6734 sz = (ioc->reply_sz * ioc->reply_depth) + 128; 6735 seq_printf(m, " {CurRepSz=%d} x {CurRepDepth=%d} = %d bytes ^= 0x%x\n", 6736 ioc->reply_sz, ioc->reply_depth, ioc->reply_sz*ioc->reply_depth, sz); 6737 seq_printf(m, " {MaxRepSz=%d} {MaxRepDepth=%d}\n", 6738 ioc->facts.CurReplyFrameSize, 6739 ioc->facts.ReplyQueueDepth); 6740 6741 seq_printf(m, " MaxDevices = %d\n", 6742 (ioc->facts.MaxDevices==0) ? 255 : ioc->facts.MaxDevices); 6743 seq_printf(m, " MaxBuses = %d\n", ioc->facts.MaxBuses); 6744 6745 /* per-port info */ 6746 for (p=0; p < ioc->facts.NumberOfPorts; p++) { 6747 seq_printf(m, " PortNumber = %d (of %d)\n", 6748 p+1, 6749 ioc->facts.NumberOfPorts); 6750 if (ioc->bus_type == FC) { 6751 if (ioc->pfacts[p].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) { 6752 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow; 6753 seq_printf(m, " LanAddr = %pMR\n", a); 6754 } 6755 seq_printf(m, " WWN = %08X%08X:%08X%08X\n", 6756 ioc->fc_port_page0[p].WWNN.High, 6757 ioc->fc_port_page0[p].WWNN.Low, 6758 ioc->fc_port_page0[p].WWPN.High, 6759 ioc->fc_port_page0[p].WWPN.Low); 6760 } 6761 } 6762 6763 return 0; 6764 } 6765 #endif /* CONFIG_PROC_FS } */ 6766 6767 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6768 static void 6769 mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc) 6770 { 6771 buf[0] ='\0'; 6772 if ((ioc->facts.FWVersion.Word >> 24) == 0x0E) { 6773 sprintf(buf, " (Exp %02d%02d)", 6774 (ioc->facts.FWVersion.Word >> 16) & 0x00FF, /* Month */ 6775 (ioc->facts.FWVersion.Word >> 8) & 0x1F); /* Day */ 6776 6777 /* insider hack! */ 6778 if ((ioc->facts.FWVersion.Word >> 8) & 0x80) 6779 strcat(buf, " [MDBG]"); 6780 } 6781 } 6782 6783 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6784 /** 6785 * mpt_print_ioc_summary - Write ASCII summary of IOC to a buffer. 6786 * @ioc: Pointer to MPT_ADAPTER structure 6787 * @buffer: Pointer to buffer where IOC summary info should be written 6788 * @size: Pointer to number of bytes we wrote (set by this routine) 6789 * @len: Offset at which to start writing in buffer 6790 * @showlan: Display LAN stuff? 6791 * 6792 * This routine writes (english readable) ASCII text, which represents 6793 * a summary of IOC information, to a buffer. 6794 */ 6795 void 6796 mpt_print_ioc_summary(MPT_ADAPTER *ioc, char *buffer, int *size, int len, int showlan) 6797 { 6798 char expVer[32]; 6799 int y; 6800 6801 mpt_get_fw_exp_ver(expVer, ioc); 6802 6803 /* 6804 * Shorter summary of attached ioc's... 6805 */ 6806 y = sprintf(buffer+len, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d", 6807 ioc->name, 6808 ioc->prod_name, 6809 MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */ 6810 ioc->facts.FWVersion.Word, 6811 expVer, 6812 ioc->facts.NumberOfPorts, 6813 ioc->req_depth); 6814 6815 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) { 6816 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow; 6817 y += sprintf(buffer+len+y, ", LanAddr=%pMR", a); 6818 } 6819 6820 y += sprintf(buffer+len+y, ", IRQ=%d", ioc->pci_irq); 6821 6822 if (!ioc->active) 6823 y += sprintf(buffer+len+y, " (disabled)"); 6824 6825 y += sprintf(buffer+len+y, "\n"); 6826 6827 *size = y; 6828 } 6829 6830 #ifdef CONFIG_PROC_FS 6831 static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan) 6832 { 6833 char expVer[32]; 6834 6835 mpt_get_fw_exp_ver(expVer, ioc); 6836 6837 /* 6838 * Shorter summary of attached ioc's... 6839 */ 6840 seq_printf(m, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d", 6841 ioc->name, 6842 ioc->prod_name, 6843 MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */ 6844 ioc->facts.FWVersion.Word, 6845 expVer, 6846 ioc->facts.NumberOfPorts, 6847 ioc->req_depth); 6848 6849 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) { 6850 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow; 6851 seq_printf(m, ", LanAddr=%pMR", a); 6852 } 6853 6854 seq_printf(m, ", IRQ=%d", ioc->pci_irq); 6855 6856 if (!ioc->active) 6857 seq_printf(m, " (disabled)"); 6858 6859 seq_putc(m, '\n'); 6860 } 6861 #endif 6862 6863 /** 6864 * mpt_set_taskmgmt_in_progress_flag - set flags associated with task management 6865 * @ioc: Pointer to MPT_ADAPTER structure 6866 * 6867 * Returns 0 for SUCCESS or -1 if FAILED. 6868 * 6869 * If -1 is return, then it was not possible to set the flags 6870 **/ 6871 int 6872 mpt_set_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc) 6873 { 6874 unsigned long flags; 6875 int retval; 6876 6877 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6878 if (ioc->ioc_reset_in_progress || ioc->taskmgmt_in_progress || 6879 (ioc->alt_ioc && ioc->alt_ioc->taskmgmt_in_progress)) { 6880 retval = -1; 6881 goto out; 6882 } 6883 retval = 0; 6884 ioc->taskmgmt_in_progress = 1; 6885 ioc->taskmgmt_quiesce_io = 1; 6886 if (ioc->alt_ioc) { 6887 ioc->alt_ioc->taskmgmt_in_progress = 1; 6888 ioc->alt_ioc->taskmgmt_quiesce_io = 1; 6889 } 6890 out: 6891 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6892 return retval; 6893 } 6894 EXPORT_SYMBOL(mpt_set_taskmgmt_in_progress_flag); 6895 6896 /** 6897 * mpt_clear_taskmgmt_in_progress_flag - clear flags associated with task management 6898 * @ioc: Pointer to MPT_ADAPTER structure 6899 * 6900 **/ 6901 void 6902 mpt_clear_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc) 6903 { 6904 unsigned long flags; 6905 6906 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6907 ioc->taskmgmt_in_progress = 0; 6908 ioc->taskmgmt_quiesce_io = 0; 6909 if (ioc->alt_ioc) { 6910 ioc->alt_ioc->taskmgmt_in_progress = 0; 6911 ioc->alt_ioc->taskmgmt_quiesce_io = 0; 6912 } 6913 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6914 } 6915 EXPORT_SYMBOL(mpt_clear_taskmgmt_in_progress_flag); 6916 6917 6918 /** 6919 * mpt_halt_firmware - Halts the firmware if it is operational and panic 6920 * the kernel 6921 * @ioc: Pointer to MPT_ADAPTER structure 6922 * 6923 **/ 6924 void 6925 mpt_halt_firmware(MPT_ADAPTER *ioc) 6926 { 6927 u32 ioc_raw_state; 6928 6929 ioc_raw_state = mpt_GetIocState(ioc, 0); 6930 6931 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) { 6932 printk(MYIOC_s_ERR_FMT "IOC is in FAULT state (%04xh)!!!\n", 6933 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK); 6934 panic("%s: IOC Fault (%04xh)!!!\n", ioc->name, 6935 ioc_raw_state & MPI_DOORBELL_DATA_MASK); 6936 } else { 6937 CHIPREG_WRITE32(&ioc->chip->Doorbell, 0xC0FFEE00); 6938 panic("%s: Firmware is halted due to command timeout\n", 6939 ioc->name); 6940 } 6941 } 6942 EXPORT_SYMBOL(mpt_halt_firmware); 6943 6944 /** 6945 * mpt_SoftResetHandler - Issues a less expensive reset 6946 * @ioc: Pointer to MPT_ADAPTER structure 6947 * @sleepFlag: Indicates if sleep or schedule must be called. 6948 * 6949 * Returns 0 for SUCCESS or -1 if FAILED. 6950 * 6951 * Message Unit Reset - instructs the IOC to reset the Reply Post and 6952 * Free FIFO's. All the Message Frames on Reply Free FIFO are discarded. 6953 * All posted buffers are freed, and event notification is turned off. 6954 * IOC doesn't reply to any outstanding request. This will transfer IOC 6955 * to READY state. 6956 **/ 6957 static int 6958 mpt_SoftResetHandler(MPT_ADAPTER *ioc, int sleepFlag) 6959 { 6960 int rc; 6961 int ii; 6962 u8 cb_idx; 6963 unsigned long flags; 6964 u32 ioc_state; 6965 unsigned long time_count; 6966 6967 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SoftResetHandler Entered!\n", 6968 ioc->name)); 6969 6970 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK; 6971 6972 if (mpt_fwfault_debug) 6973 mpt_halt_firmware(ioc); 6974 6975 if (ioc_state == MPI_IOC_STATE_FAULT || 6976 ioc_state == MPI_IOC_STATE_RESET) { 6977 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6978 "skipping, either in FAULT or RESET state!\n", ioc->name)); 6979 return -1; 6980 } 6981 6982 if (ioc->bus_type == FC) { 6983 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6984 "skipping, because the bus type is FC!\n", ioc->name)); 6985 return -1; 6986 } 6987 6988 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6989 if (ioc->ioc_reset_in_progress) { 6990 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6991 return -1; 6992 } 6993 ioc->ioc_reset_in_progress = 1; 6994 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6995 6996 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 6997 if (MptResetHandlers[cb_idx]) 6998 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET); 6999 } 7000 7001 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 7002 if (ioc->taskmgmt_in_progress) { 7003 ioc->ioc_reset_in_progress = 0; 7004 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7005 return -1; 7006 } 7007 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7008 /* Disable reply interrupts (also blocks FreeQ) */ 7009 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 7010 ioc->active = 0; 7011 time_count = jiffies; 7012 7013 rc = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag); 7014 7015 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7016 if (MptResetHandlers[cb_idx]) 7017 mpt_signal_reset(cb_idx, ioc, MPT_IOC_PRE_RESET); 7018 } 7019 7020 if (rc) 7021 goto out; 7022 7023 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK; 7024 if (ioc_state != MPI_IOC_STATE_READY) 7025 goto out; 7026 7027 for (ii = 0; ii < 5; ii++) { 7028 /* Get IOC facts! Allow 5 retries */ 7029 rc = GetIocFacts(ioc, sleepFlag, 7030 MPT_HOSTEVENT_IOC_RECOVER); 7031 if (rc == 0) 7032 break; 7033 if (sleepFlag == CAN_SLEEP) 7034 msleep(100); 7035 else 7036 mdelay(100); 7037 } 7038 if (ii == 5) 7039 goto out; 7040 7041 rc = PrimeIocFifos(ioc); 7042 if (rc != 0) 7043 goto out; 7044 7045 rc = SendIocInit(ioc, sleepFlag); 7046 if (rc != 0) 7047 goto out; 7048 7049 rc = SendEventNotification(ioc, 1, sleepFlag); 7050 if (rc != 0) 7051 goto out; 7052 7053 if (ioc->hard_resets < -1) 7054 ioc->hard_resets++; 7055 7056 /* 7057 * At this point, we know soft reset succeeded. 7058 */ 7059 7060 ioc->active = 1; 7061 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM); 7062 7063 out: 7064 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 7065 ioc->ioc_reset_in_progress = 0; 7066 ioc->taskmgmt_quiesce_io = 0; 7067 ioc->taskmgmt_in_progress = 0; 7068 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7069 7070 if (ioc->active) { /* otherwise, hard reset coming */ 7071 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7072 if (MptResetHandlers[cb_idx]) 7073 mpt_signal_reset(cb_idx, ioc, 7074 MPT_IOC_POST_RESET); 7075 } 7076 } 7077 7078 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 7079 "SoftResetHandler: completed (%d seconds): %s\n", 7080 ioc->name, jiffies_to_msecs(jiffies - time_count)/1000, 7081 ((rc == 0) ? "SUCCESS" : "FAILED"))); 7082 7083 return rc; 7084 } 7085 7086 /** 7087 * mpt_Soft_Hard_ResetHandler - Try less expensive reset 7088 * @ioc: Pointer to MPT_ADAPTER structure 7089 * @sleepFlag: Indicates if sleep or schedule must be called. 7090 * 7091 * Returns 0 for SUCCESS or -1 if FAILED. 7092 * Try for softreset first, only if it fails go for expensive 7093 * HardReset. 7094 **/ 7095 int 7096 mpt_Soft_Hard_ResetHandler(MPT_ADAPTER *ioc, int sleepFlag) { 7097 int ret = -1; 7098 7099 ret = mpt_SoftResetHandler(ioc, sleepFlag); 7100 if (ret == 0) 7101 return ret; 7102 ret = mpt_HardResetHandler(ioc, sleepFlag); 7103 return ret; 7104 } 7105 EXPORT_SYMBOL(mpt_Soft_Hard_ResetHandler); 7106 7107 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7108 /* 7109 * Reset Handling 7110 */ 7111 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7112 /** 7113 * mpt_HardResetHandler - Generic reset handler 7114 * @ioc: Pointer to MPT_ADAPTER structure 7115 * @sleepFlag: Indicates if sleep or schedule must be called. 7116 * 7117 * Issues SCSI Task Management call based on input arg values. 7118 * If TaskMgmt fails, returns associated SCSI request. 7119 * 7120 * Remark: _HardResetHandler can be invoked from an interrupt thread (timer) 7121 * or a non-interrupt thread. In the former, must not call schedule(). 7122 * 7123 * Note: A return of -1 is a FATAL error case, as it means a 7124 * FW reload/initialization failed. 7125 * 7126 * Returns 0 for SUCCESS or -1 if FAILED. 7127 */ 7128 int 7129 mpt_HardResetHandler(MPT_ADAPTER *ioc, int sleepFlag) 7130 { 7131 int rc; 7132 u8 cb_idx; 7133 unsigned long flags; 7134 unsigned long time_count; 7135 7136 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HardResetHandler Entered!\n", ioc->name)); 7137 #ifdef MFCNT 7138 printk(MYIOC_s_INFO_FMT "HardResetHandler Entered!\n", ioc->name); 7139 printk("MF count 0x%x !\n", ioc->mfcnt); 7140 #endif 7141 if (mpt_fwfault_debug) 7142 mpt_halt_firmware(ioc); 7143 7144 /* Reset the adapter. Prevent more than 1 call to 7145 * mpt_do_ioc_recovery at any instant in time. 7146 */ 7147 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 7148 if (ioc->ioc_reset_in_progress) { 7149 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7150 ioc->wait_on_reset_completion = 1; 7151 do { 7152 ssleep(1); 7153 } while (ioc->ioc_reset_in_progress == 1); 7154 ioc->wait_on_reset_completion = 0; 7155 return ioc->reset_status; 7156 } 7157 if (ioc->wait_on_reset_completion) { 7158 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7159 rc = 0; 7160 time_count = jiffies; 7161 goto exit; 7162 } 7163 ioc->ioc_reset_in_progress = 1; 7164 if (ioc->alt_ioc) 7165 ioc->alt_ioc->ioc_reset_in_progress = 1; 7166 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7167 7168 7169 /* The SCSI driver needs to adjust timeouts on all current 7170 * commands prior to the diagnostic reset being issued. 7171 * Prevents timeouts occurring during a diagnostic reset...very bad. 7172 * For all other protocol drivers, this is a no-op. 7173 */ 7174 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7175 if (MptResetHandlers[cb_idx]) { 7176 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET); 7177 if (ioc->alt_ioc) 7178 mpt_signal_reset(cb_idx, ioc->alt_ioc, 7179 MPT_IOC_SETUP_RESET); 7180 } 7181 } 7182 7183 time_count = jiffies; 7184 rc = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_RECOVER, sleepFlag); 7185 if (rc != 0) { 7186 printk(KERN_WARNING MYNAM 7187 ": WARNING - (%d) Cannot recover %s, doorbell=0x%08x\n", 7188 rc, ioc->name, mpt_GetIocState(ioc, 0)); 7189 } else { 7190 if (ioc->hard_resets < -1) 7191 ioc->hard_resets++; 7192 } 7193 7194 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 7195 ioc->ioc_reset_in_progress = 0; 7196 ioc->taskmgmt_quiesce_io = 0; 7197 ioc->taskmgmt_in_progress = 0; 7198 ioc->reset_status = rc; 7199 if (ioc->alt_ioc) { 7200 ioc->alt_ioc->ioc_reset_in_progress = 0; 7201 ioc->alt_ioc->taskmgmt_quiesce_io = 0; 7202 ioc->alt_ioc->taskmgmt_in_progress = 0; 7203 } 7204 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7205 7206 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7207 if (MptResetHandlers[cb_idx]) { 7208 mpt_signal_reset(cb_idx, ioc, MPT_IOC_POST_RESET); 7209 if (ioc->alt_ioc) 7210 mpt_signal_reset(cb_idx, 7211 ioc->alt_ioc, MPT_IOC_POST_RESET); 7212 } 7213 } 7214 exit: 7215 dtmprintk(ioc, 7216 printk(MYIOC_s_DEBUG_FMT 7217 "HardResetHandler: completed (%d seconds): %s\n", ioc->name, 7218 jiffies_to_msecs(jiffies - time_count)/1000, ((rc == 0) ? 7219 "SUCCESS" : "FAILED"))); 7220 7221 return rc; 7222 } 7223 7224 #ifdef CONFIG_FUSION_LOGGING 7225 static void 7226 mpt_display_event_info(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply) 7227 { 7228 char *ds = NULL; 7229 u32 evData0; 7230 int ii; 7231 u8 event; 7232 char *evStr = ioc->evStr; 7233 7234 event = le32_to_cpu(pEventReply->Event) & 0xFF; 7235 evData0 = le32_to_cpu(pEventReply->Data[0]); 7236 7237 switch(event) { 7238 case MPI_EVENT_NONE: 7239 ds = "None"; 7240 break; 7241 case MPI_EVENT_LOG_DATA: 7242 ds = "Log Data"; 7243 break; 7244 case MPI_EVENT_STATE_CHANGE: 7245 ds = "State Change"; 7246 break; 7247 case MPI_EVENT_UNIT_ATTENTION: 7248 ds = "Unit Attention"; 7249 break; 7250 case MPI_EVENT_IOC_BUS_RESET: 7251 ds = "IOC Bus Reset"; 7252 break; 7253 case MPI_EVENT_EXT_BUS_RESET: 7254 ds = "External Bus Reset"; 7255 break; 7256 case MPI_EVENT_RESCAN: 7257 ds = "Bus Rescan Event"; 7258 break; 7259 case MPI_EVENT_LINK_STATUS_CHANGE: 7260 if (evData0 == MPI_EVENT_LINK_STATUS_FAILURE) 7261 ds = "Link Status(FAILURE) Change"; 7262 else 7263 ds = "Link Status(ACTIVE) Change"; 7264 break; 7265 case MPI_EVENT_LOOP_STATE_CHANGE: 7266 if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LIP) 7267 ds = "Loop State(LIP) Change"; 7268 else if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LPE) 7269 ds = "Loop State(LPE) Change"; 7270 else 7271 ds = "Loop State(LPB) Change"; 7272 break; 7273 case MPI_EVENT_LOGOUT: 7274 ds = "Logout"; 7275 break; 7276 case MPI_EVENT_EVENT_CHANGE: 7277 if (evData0) 7278 ds = "Events ON"; 7279 else 7280 ds = "Events OFF"; 7281 break; 7282 case MPI_EVENT_INTEGRATED_RAID: 7283 { 7284 u8 ReasonCode = (u8)(evData0 >> 16); 7285 switch (ReasonCode) { 7286 case MPI_EVENT_RAID_RC_VOLUME_CREATED : 7287 ds = "Integrated Raid: Volume Created"; 7288 break; 7289 case MPI_EVENT_RAID_RC_VOLUME_DELETED : 7290 ds = "Integrated Raid: Volume Deleted"; 7291 break; 7292 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED : 7293 ds = "Integrated Raid: Volume Settings Changed"; 7294 break; 7295 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED : 7296 ds = "Integrated Raid: Volume Status Changed"; 7297 break; 7298 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED : 7299 ds = "Integrated Raid: Volume Physdisk Changed"; 7300 break; 7301 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED : 7302 ds = "Integrated Raid: Physdisk Created"; 7303 break; 7304 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED : 7305 ds = "Integrated Raid: Physdisk Deleted"; 7306 break; 7307 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED : 7308 ds = "Integrated Raid: Physdisk Settings Changed"; 7309 break; 7310 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED : 7311 ds = "Integrated Raid: Physdisk Status Changed"; 7312 break; 7313 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED : 7314 ds = "Integrated Raid: Domain Validation Needed"; 7315 break; 7316 case MPI_EVENT_RAID_RC_SMART_DATA : 7317 ds = "Integrated Raid; Smart Data"; 7318 break; 7319 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED : 7320 ds = "Integrated Raid: Replace Action Started"; 7321 break; 7322 default: 7323 ds = "Integrated Raid"; 7324 break; 7325 } 7326 break; 7327 } 7328 case MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE: 7329 ds = "SCSI Device Status Change"; 7330 break; 7331 case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE: 7332 { 7333 u8 id = (u8)(evData0); 7334 u8 channel = (u8)(evData0 >> 8); 7335 u8 ReasonCode = (u8)(evData0 >> 16); 7336 switch (ReasonCode) { 7337 case MPI_EVENT_SAS_DEV_STAT_RC_ADDED: 7338 snprintf(evStr, EVENT_DESCR_STR_SZ, 7339 "SAS Device Status Change: Added: " 7340 "id=%d channel=%d", id, channel); 7341 break; 7342 case MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING: 7343 snprintf(evStr, EVENT_DESCR_STR_SZ, 7344 "SAS Device Status Change: Deleted: " 7345 "id=%d channel=%d", id, channel); 7346 break; 7347 case MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA: 7348 snprintf(evStr, EVENT_DESCR_STR_SZ, 7349 "SAS Device Status Change: SMART Data: " 7350 "id=%d channel=%d", id, channel); 7351 break; 7352 case MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED: 7353 snprintf(evStr, EVENT_DESCR_STR_SZ, 7354 "SAS Device Status Change: No Persistency: " 7355 "id=%d channel=%d", id, channel); 7356 break; 7357 case MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED: 7358 snprintf(evStr, EVENT_DESCR_STR_SZ, 7359 "SAS Device Status Change: Unsupported Device " 7360 "Discovered : id=%d channel=%d", id, channel); 7361 break; 7362 case MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET: 7363 snprintf(evStr, EVENT_DESCR_STR_SZ, 7364 "SAS Device Status Change: Internal Device " 7365 "Reset : id=%d channel=%d", id, channel); 7366 break; 7367 case MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL: 7368 snprintf(evStr, EVENT_DESCR_STR_SZ, 7369 "SAS Device Status Change: Internal Task " 7370 "Abort : id=%d channel=%d", id, channel); 7371 break; 7372 case MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL: 7373 snprintf(evStr, EVENT_DESCR_STR_SZ, 7374 "SAS Device Status Change: Internal Abort " 7375 "Task Set : id=%d channel=%d", id, channel); 7376 break; 7377 case MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL: 7378 snprintf(evStr, EVENT_DESCR_STR_SZ, 7379 "SAS Device Status Change: Internal Clear " 7380 "Task Set : id=%d channel=%d", id, channel); 7381 break; 7382 case MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL: 7383 snprintf(evStr, EVENT_DESCR_STR_SZ, 7384 "SAS Device Status Change: Internal Query " 7385 "Task : id=%d channel=%d", id, channel); 7386 break; 7387 default: 7388 snprintf(evStr, EVENT_DESCR_STR_SZ, 7389 "SAS Device Status Change: Unknown: " 7390 "id=%d channel=%d", id, channel); 7391 break; 7392 } 7393 break; 7394 } 7395 case MPI_EVENT_ON_BUS_TIMER_EXPIRED: 7396 ds = "Bus Timer Expired"; 7397 break; 7398 case MPI_EVENT_QUEUE_FULL: 7399 { 7400 u16 curr_depth = (u16)(evData0 >> 16); 7401 u8 channel = (u8)(evData0 >> 8); 7402 u8 id = (u8)(evData0); 7403 7404 snprintf(evStr, EVENT_DESCR_STR_SZ, 7405 "Queue Full: channel=%d id=%d depth=%d", 7406 channel, id, curr_depth); 7407 break; 7408 } 7409 case MPI_EVENT_SAS_SES: 7410 ds = "SAS SES Event"; 7411 break; 7412 case MPI_EVENT_PERSISTENT_TABLE_FULL: 7413 ds = "Persistent Table Full"; 7414 break; 7415 case MPI_EVENT_SAS_PHY_LINK_STATUS: 7416 { 7417 u8 LinkRates = (u8)(evData0 >> 8); 7418 u8 PhyNumber = (u8)(evData0); 7419 LinkRates = (LinkRates & MPI_EVENT_SAS_PLS_LR_CURRENT_MASK) >> 7420 MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT; 7421 switch (LinkRates) { 7422 case MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN: 7423 snprintf(evStr, EVENT_DESCR_STR_SZ, 7424 "SAS PHY Link Status: Phy=%d:" 7425 " Rate Unknown",PhyNumber); 7426 break; 7427 case MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED: 7428 snprintf(evStr, EVENT_DESCR_STR_SZ, 7429 "SAS PHY Link Status: Phy=%d:" 7430 " Phy Disabled",PhyNumber); 7431 break; 7432 case MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION: 7433 snprintf(evStr, EVENT_DESCR_STR_SZ, 7434 "SAS PHY Link Status: Phy=%d:" 7435 " Failed Speed Nego",PhyNumber); 7436 break; 7437 case MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE: 7438 snprintf(evStr, EVENT_DESCR_STR_SZ, 7439 "SAS PHY Link Status: Phy=%d:" 7440 " Sata OOB Completed",PhyNumber); 7441 break; 7442 case MPI_EVENT_SAS_PLS_LR_RATE_1_5: 7443 snprintf(evStr, EVENT_DESCR_STR_SZ, 7444 "SAS PHY Link Status: Phy=%d:" 7445 " Rate 1.5 Gbps",PhyNumber); 7446 break; 7447 case MPI_EVENT_SAS_PLS_LR_RATE_3_0: 7448 snprintf(evStr, EVENT_DESCR_STR_SZ, 7449 "SAS PHY Link Status: Phy=%d:" 7450 " Rate 3.0 Gbps", PhyNumber); 7451 break; 7452 case MPI_EVENT_SAS_PLS_LR_RATE_6_0: 7453 snprintf(evStr, EVENT_DESCR_STR_SZ, 7454 "SAS PHY Link Status: Phy=%d:" 7455 " Rate 6.0 Gbps", PhyNumber); 7456 break; 7457 default: 7458 snprintf(evStr, EVENT_DESCR_STR_SZ, 7459 "SAS PHY Link Status: Phy=%d", PhyNumber); 7460 break; 7461 } 7462 break; 7463 } 7464 case MPI_EVENT_SAS_DISCOVERY_ERROR: 7465 ds = "SAS Discovery Error"; 7466 break; 7467 case MPI_EVENT_IR_RESYNC_UPDATE: 7468 { 7469 u8 resync_complete = (u8)(evData0 >> 16); 7470 snprintf(evStr, EVENT_DESCR_STR_SZ, 7471 "IR Resync Update: Complete = %d:",resync_complete); 7472 break; 7473 } 7474 case MPI_EVENT_IR2: 7475 { 7476 u8 id = (u8)(evData0); 7477 u8 channel = (u8)(evData0 >> 8); 7478 u8 phys_num = (u8)(evData0 >> 24); 7479 u8 ReasonCode = (u8)(evData0 >> 16); 7480 7481 switch (ReasonCode) { 7482 case MPI_EVENT_IR2_RC_LD_STATE_CHANGED: 7483 snprintf(evStr, EVENT_DESCR_STR_SZ, 7484 "IR2: LD State Changed: " 7485 "id=%d channel=%d phys_num=%d", 7486 id, channel, phys_num); 7487 break; 7488 case MPI_EVENT_IR2_RC_PD_STATE_CHANGED: 7489 snprintf(evStr, EVENT_DESCR_STR_SZ, 7490 "IR2: PD State Changed " 7491 "id=%d channel=%d phys_num=%d", 7492 id, channel, phys_num); 7493 break; 7494 case MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL: 7495 snprintf(evStr, EVENT_DESCR_STR_SZ, 7496 "IR2: Bad Block Table Full: " 7497 "id=%d channel=%d phys_num=%d", 7498 id, channel, phys_num); 7499 break; 7500 case MPI_EVENT_IR2_RC_PD_INSERTED: 7501 snprintf(evStr, EVENT_DESCR_STR_SZ, 7502 "IR2: PD Inserted: " 7503 "id=%d channel=%d phys_num=%d", 7504 id, channel, phys_num); 7505 break; 7506 case MPI_EVENT_IR2_RC_PD_REMOVED: 7507 snprintf(evStr, EVENT_DESCR_STR_SZ, 7508 "IR2: PD Removed: " 7509 "id=%d channel=%d phys_num=%d", 7510 id, channel, phys_num); 7511 break; 7512 case MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED: 7513 snprintf(evStr, EVENT_DESCR_STR_SZ, 7514 "IR2: Foreign CFG Detected: " 7515 "id=%d channel=%d phys_num=%d", 7516 id, channel, phys_num); 7517 break; 7518 case MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR: 7519 snprintf(evStr, EVENT_DESCR_STR_SZ, 7520 "IR2: Rebuild Medium Error: " 7521 "id=%d channel=%d phys_num=%d", 7522 id, channel, phys_num); 7523 break; 7524 case MPI_EVENT_IR2_RC_DUAL_PORT_ADDED: 7525 snprintf(evStr, EVENT_DESCR_STR_SZ, 7526 "IR2: Dual Port Added: " 7527 "id=%d channel=%d phys_num=%d", 7528 id, channel, phys_num); 7529 break; 7530 case MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED: 7531 snprintf(evStr, EVENT_DESCR_STR_SZ, 7532 "IR2: Dual Port Removed: " 7533 "id=%d channel=%d phys_num=%d", 7534 id, channel, phys_num); 7535 break; 7536 default: 7537 ds = "IR2"; 7538 break; 7539 } 7540 break; 7541 } 7542 case MPI_EVENT_SAS_DISCOVERY: 7543 { 7544 if (evData0) 7545 ds = "SAS Discovery: Start"; 7546 else 7547 ds = "SAS Discovery: Stop"; 7548 break; 7549 } 7550 case MPI_EVENT_LOG_ENTRY_ADDED: 7551 ds = "SAS Log Entry Added"; 7552 break; 7553 7554 case MPI_EVENT_SAS_BROADCAST_PRIMITIVE: 7555 { 7556 u8 phy_num = (u8)(evData0); 7557 u8 port_num = (u8)(evData0 >> 8); 7558 u8 port_width = (u8)(evData0 >> 16); 7559 u8 primitive = (u8)(evData0 >> 24); 7560 snprintf(evStr, EVENT_DESCR_STR_SZ, 7561 "SAS Broadcast Primitive: phy=%d port=%d " 7562 "width=%d primitive=0x%02x", 7563 phy_num, port_num, port_width, primitive); 7564 break; 7565 } 7566 7567 case MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 7568 { 7569 u8 reason = (u8)(evData0); 7570 7571 switch (reason) { 7572 case MPI_EVENT_SAS_INIT_RC_ADDED: 7573 ds = "SAS Initiator Status Change: Added"; 7574 break; 7575 case MPI_EVENT_SAS_INIT_RC_REMOVED: 7576 ds = "SAS Initiator Status Change: Deleted"; 7577 break; 7578 default: 7579 ds = "SAS Initiator Status Change"; 7580 break; 7581 } 7582 break; 7583 } 7584 7585 case MPI_EVENT_SAS_INIT_TABLE_OVERFLOW: 7586 { 7587 u8 max_init = (u8)(evData0); 7588 u8 current_init = (u8)(evData0 >> 8); 7589 7590 snprintf(evStr, EVENT_DESCR_STR_SZ, 7591 "SAS Initiator Device Table Overflow: max initiators=%02d " 7592 "current initiators=%02d", 7593 max_init, current_init); 7594 break; 7595 } 7596 case MPI_EVENT_SAS_SMP_ERROR: 7597 { 7598 u8 status = (u8)(evData0); 7599 u8 port_num = (u8)(evData0 >> 8); 7600 u8 result = (u8)(evData0 >> 16); 7601 7602 if (status == MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID) 7603 snprintf(evStr, EVENT_DESCR_STR_SZ, 7604 "SAS SMP Error: port=%d result=0x%02x", 7605 port_num, result); 7606 else if (status == MPI_EVENT_SAS_SMP_CRC_ERROR) 7607 snprintf(evStr, EVENT_DESCR_STR_SZ, 7608 "SAS SMP Error: port=%d : CRC Error", 7609 port_num); 7610 else if (status == MPI_EVENT_SAS_SMP_TIMEOUT) 7611 snprintf(evStr, EVENT_DESCR_STR_SZ, 7612 "SAS SMP Error: port=%d : Timeout", 7613 port_num); 7614 else if (status == MPI_EVENT_SAS_SMP_NO_DESTINATION) 7615 snprintf(evStr, EVENT_DESCR_STR_SZ, 7616 "SAS SMP Error: port=%d : No Destination", 7617 port_num); 7618 else if (status == MPI_EVENT_SAS_SMP_BAD_DESTINATION) 7619 snprintf(evStr, EVENT_DESCR_STR_SZ, 7620 "SAS SMP Error: port=%d : Bad Destination", 7621 port_num); 7622 else 7623 snprintf(evStr, EVENT_DESCR_STR_SZ, 7624 "SAS SMP Error: port=%d : status=0x%02x", 7625 port_num, status); 7626 break; 7627 } 7628 7629 case MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE: 7630 { 7631 u8 reason = (u8)(evData0); 7632 7633 switch (reason) { 7634 case MPI_EVENT_SAS_EXP_RC_ADDED: 7635 ds = "Expander Status Change: Added"; 7636 break; 7637 case MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING: 7638 ds = "Expander Status Change: Deleted"; 7639 break; 7640 default: 7641 ds = "Expander Status Change"; 7642 break; 7643 } 7644 break; 7645 } 7646 7647 /* 7648 * MPT base "custom" events may be added here... 7649 */ 7650 default: 7651 ds = "Unknown"; 7652 break; 7653 } 7654 if (ds) 7655 strlcpy(evStr, ds, EVENT_DESCR_STR_SZ); 7656 7657 7658 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT 7659 "MPT event:(%02Xh) : %s\n", 7660 ioc->name, event, evStr)); 7661 7662 devtverboseprintk(ioc, printk(KERN_DEBUG MYNAM 7663 ": Event data:\n")); 7664 for (ii = 0; ii < le16_to_cpu(pEventReply->EventDataLength); ii++) 7665 devtverboseprintk(ioc, printk(" %08x", 7666 le32_to_cpu(pEventReply->Data[ii]))); 7667 devtverboseprintk(ioc, printk(KERN_DEBUG "\n")); 7668 } 7669 #endif 7670 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7671 /** 7672 * ProcessEventNotification - Route EventNotificationReply to all event handlers 7673 * @ioc: Pointer to MPT_ADAPTER structure 7674 * @pEventReply: Pointer to EventNotification reply frame 7675 * @evHandlers: Pointer to integer, number of event handlers 7676 * 7677 * Routes a received EventNotificationReply to all currently registered 7678 * event handlers. 7679 * Returns sum of event handlers return values. 7680 */ 7681 static int 7682 ProcessEventNotification(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply, int *evHandlers) 7683 { 7684 u16 evDataLen; 7685 u32 evData0 = 0; 7686 int ii; 7687 u8 cb_idx; 7688 int r = 0; 7689 int handlers = 0; 7690 u8 event; 7691 7692 /* 7693 * Do platform normalization of values 7694 */ 7695 event = le32_to_cpu(pEventReply->Event) & 0xFF; 7696 evDataLen = le16_to_cpu(pEventReply->EventDataLength); 7697 if (evDataLen) { 7698 evData0 = le32_to_cpu(pEventReply->Data[0]); 7699 } 7700 7701 #ifdef CONFIG_FUSION_LOGGING 7702 if (evDataLen) 7703 mpt_display_event_info(ioc, pEventReply); 7704 #endif 7705 7706 /* 7707 * Do general / base driver event processing 7708 */ 7709 switch(event) { 7710 case MPI_EVENT_EVENT_CHANGE: /* 0A */ 7711 if (evDataLen) { 7712 u8 evState = evData0 & 0xFF; 7713 7714 /* CHECKME! What if evState unexpectedly says OFF (0)? */ 7715 7716 /* Update EventState field in cached IocFacts */ 7717 if (ioc->facts.Function) { 7718 ioc->facts.EventState = evState; 7719 } 7720 } 7721 break; 7722 case MPI_EVENT_INTEGRATED_RAID: 7723 mptbase_raid_process_event_data(ioc, 7724 (MpiEventDataRaid_t *)pEventReply->Data); 7725 break; 7726 default: 7727 break; 7728 } 7729 7730 /* 7731 * Should this event be logged? Events are written sequentially. 7732 * When buffer is full, start again at the top. 7733 */ 7734 if (ioc->events && (ioc->eventTypes & ( 1 << event))) { 7735 int idx; 7736 7737 idx = ioc->eventContext % MPTCTL_EVENT_LOG_SIZE; 7738 7739 ioc->events[idx].event = event; 7740 ioc->events[idx].eventContext = ioc->eventContext; 7741 7742 for (ii = 0; ii < 2; ii++) { 7743 if (ii < evDataLen) 7744 ioc->events[idx].data[ii] = le32_to_cpu(pEventReply->Data[ii]); 7745 else 7746 ioc->events[idx].data[ii] = 0; 7747 } 7748 7749 ioc->eventContext++; 7750 } 7751 7752 7753 /* 7754 * Call each currently registered protocol event handler. 7755 */ 7756 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7757 if (MptEvHandlers[cb_idx]) { 7758 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT 7759 "Routing Event to event handler #%d\n", 7760 ioc->name, cb_idx)); 7761 r += (*(MptEvHandlers[cb_idx]))(ioc, pEventReply); 7762 handlers++; 7763 } 7764 } 7765 /* FIXME? Examine results here? */ 7766 7767 /* 7768 * If needed, send (a single) EventAck. 7769 */ 7770 if (pEventReply->AckRequired == MPI_EVENT_NOTIFICATION_ACK_REQUIRED) { 7771 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT 7772 "EventAck required\n",ioc->name)); 7773 if ((ii = SendEventAck(ioc, pEventReply)) != 0) { 7774 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SendEventAck returned %d\n", 7775 ioc->name, ii)); 7776 } 7777 } 7778 7779 *evHandlers = handlers; 7780 return r; 7781 } 7782 7783 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7784 /** 7785 * mpt_fc_log_info - Log information returned from Fibre Channel IOC. 7786 * @ioc: Pointer to MPT_ADAPTER structure 7787 * @log_info: U32 LogInfo reply word from the IOC 7788 * 7789 * Refer to lsi/mpi_log_fc.h. 7790 */ 7791 static void 7792 mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info) 7793 { 7794 char *desc = "unknown"; 7795 7796 switch (log_info & 0xFF000000) { 7797 case MPI_IOCLOGINFO_FC_INIT_BASE: 7798 desc = "FCP Initiator"; 7799 break; 7800 case MPI_IOCLOGINFO_FC_TARGET_BASE: 7801 desc = "FCP Target"; 7802 break; 7803 case MPI_IOCLOGINFO_FC_LAN_BASE: 7804 desc = "LAN"; 7805 break; 7806 case MPI_IOCLOGINFO_FC_MSG_BASE: 7807 desc = "MPI Message Layer"; 7808 break; 7809 case MPI_IOCLOGINFO_FC_LINK_BASE: 7810 desc = "FC Link"; 7811 break; 7812 case MPI_IOCLOGINFO_FC_CTX_BASE: 7813 desc = "Context Manager"; 7814 break; 7815 case MPI_IOCLOGINFO_FC_INVALID_FIELD_BYTE_OFFSET: 7816 desc = "Invalid Field Offset"; 7817 break; 7818 case MPI_IOCLOGINFO_FC_STATE_CHANGE: 7819 desc = "State Change Info"; 7820 break; 7821 } 7822 7823 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): SubClass={%s}, Value=(0x%06x)\n", 7824 ioc->name, log_info, desc, (log_info & 0xFFFFFF)); 7825 } 7826 7827 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7828 /** 7829 * mpt_spi_log_info - Log information returned from SCSI Parallel IOC. 7830 * @ioc: Pointer to MPT_ADAPTER structure 7831 * @log_info: U32 LogInfo word from the IOC 7832 * 7833 * Refer to lsi/sp_log.h. 7834 */ 7835 static void 7836 mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info) 7837 { 7838 u32 info = log_info & 0x00FF0000; 7839 char *desc = "unknown"; 7840 7841 switch (info) { 7842 case 0x00010000: 7843 desc = "bug! MID not found"; 7844 break; 7845 7846 case 0x00020000: 7847 desc = "Parity Error"; 7848 break; 7849 7850 case 0x00030000: 7851 desc = "ASYNC Outbound Overrun"; 7852 break; 7853 7854 case 0x00040000: 7855 desc = "SYNC Offset Error"; 7856 break; 7857 7858 case 0x00050000: 7859 desc = "BM Change"; 7860 break; 7861 7862 case 0x00060000: 7863 desc = "Msg In Overflow"; 7864 break; 7865 7866 case 0x00070000: 7867 desc = "DMA Error"; 7868 break; 7869 7870 case 0x00080000: 7871 desc = "Outbound DMA Overrun"; 7872 break; 7873 7874 case 0x00090000: 7875 desc = "Task Management"; 7876 break; 7877 7878 case 0x000A0000: 7879 desc = "Device Problem"; 7880 break; 7881 7882 case 0x000B0000: 7883 desc = "Invalid Phase Change"; 7884 break; 7885 7886 case 0x000C0000: 7887 desc = "Untagged Table Size"; 7888 break; 7889 7890 } 7891 7892 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): F/W: %s\n", ioc->name, log_info, desc); 7893 } 7894 7895 /* strings for sas loginfo */ 7896 static char *originator_str[] = { 7897 "IOP", /* 00h */ 7898 "PL", /* 01h */ 7899 "IR" /* 02h */ 7900 }; 7901 static char *iop_code_str[] = { 7902 NULL, /* 00h */ 7903 "Invalid SAS Address", /* 01h */ 7904 NULL, /* 02h */ 7905 "Invalid Page", /* 03h */ 7906 "Diag Message Error", /* 04h */ 7907 "Task Terminated", /* 05h */ 7908 "Enclosure Management", /* 06h */ 7909 "Target Mode" /* 07h */ 7910 }; 7911 static char *pl_code_str[] = { 7912 NULL, /* 00h */ 7913 "Open Failure", /* 01h */ 7914 "Invalid Scatter Gather List", /* 02h */ 7915 "Wrong Relative Offset or Frame Length", /* 03h */ 7916 "Frame Transfer Error", /* 04h */ 7917 "Transmit Frame Connected Low", /* 05h */ 7918 "SATA Non-NCQ RW Error Bit Set", /* 06h */ 7919 "SATA Read Log Receive Data Error", /* 07h */ 7920 "SATA NCQ Fail All Commands After Error", /* 08h */ 7921 "SATA Error in Receive Set Device Bit FIS", /* 09h */ 7922 "Receive Frame Invalid Message", /* 0Ah */ 7923 "Receive Context Message Valid Error", /* 0Bh */ 7924 "Receive Frame Current Frame Error", /* 0Ch */ 7925 "SATA Link Down", /* 0Dh */ 7926 "Discovery SATA Init W IOS", /* 0Eh */ 7927 "Config Invalid Page", /* 0Fh */ 7928 "Discovery SATA Init Timeout", /* 10h */ 7929 "Reset", /* 11h */ 7930 "Abort", /* 12h */ 7931 "IO Not Yet Executed", /* 13h */ 7932 "IO Executed", /* 14h */ 7933 "Persistent Reservation Out Not Affiliation " 7934 "Owner", /* 15h */ 7935 "Open Transmit DMA Abort", /* 16h */ 7936 "IO Device Missing Delay Retry", /* 17h */ 7937 "IO Cancelled Due to Receive Error", /* 18h */ 7938 NULL, /* 19h */ 7939 NULL, /* 1Ah */ 7940 NULL, /* 1Bh */ 7941 NULL, /* 1Ch */ 7942 NULL, /* 1Dh */ 7943 NULL, /* 1Eh */ 7944 NULL, /* 1Fh */ 7945 "Enclosure Management" /* 20h */ 7946 }; 7947 static char *ir_code_str[] = { 7948 "Raid Action Error", /* 00h */ 7949 NULL, /* 00h */ 7950 NULL, /* 01h */ 7951 NULL, /* 02h */ 7952 NULL, /* 03h */ 7953 NULL, /* 04h */ 7954 NULL, /* 05h */ 7955 NULL, /* 06h */ 7956 NULL /* 07h */ 7957 }; 7958 static char *raid_sub_code_str[] = { 7959 NULL, /* 00h */ 7960 "Volume Creation Failed: Data Passed too " 7961 "Large", /* 01h */ 7962 "Volume Creation Failed: Duplicate Volumes " 7963 "Attempted", /* 02h */ 7964 "Volume Creation Failed: Max Number " 7965 "Supported Volumes Exceeded", /* 03h */ 7966 "Volume Creation Failed: DMA Error", /* 04h */ 7967 "Volume Creation Failed: Invalid Volume Type", /* 05h */ 7968 "Volume Creation Failed: Error Reading " 7969 "MFG Page 4", /* 06h */ 7970 "Volume Creation Failed: Creating Internal " 7971 "Structures", /* 07h */ 7972 NULL, /* 08h */ 7973 NULL, /* 09h */ 7974 NULL, /* 0Ah */ 7975 NULL, /* 0Bh */ 7976 NULL, /* 0Ch */ 7977 NULL, /* 0Dh */ 7978 NULL, /* 0Eh */ 7979 NULL, /* 0Fh */ 7980 "Activation failed: Already Active Volume", /* 10h */ 7981 "Activation failed: Unsupported Volume Type", /* 11h */ 7982 "Activation failed: Too Many Active Volumes", /* 12h */ 7983 "Activation failed: Volume ID in Use", /* 13h */ 7984 "Activation failed: Reported Failure", /* 14h */ 7985 "Activation failed: Importing a Volume", /* 15h */ 7986 NULL, /* 16h */ 7987 NULL, /* 17h */ 7988 NULL, /* 18h */ 7989 NULL, /* 19h */ 7990 NULL, /* 1Ah */ 7991 NULL, /* 1Bh */ 7992 NULL, /* 1Ch */ 7993 NULL, /* 1Dh */ 7994 NULL, /* 1Eh */ 7995 NULL, /* 1Fh */ 7996 "Phys Disk failed: Too Many Phys Disks", /* 20h */ 7997 "Phys Disk failed: Data Passed too Large", /* 21h */ 7998 "Phys Disk failed: DMA Error", /* 22h */ 7999 "Phys Disk failed: Invalid <channel:id>", /* 23h */ 8000 "Phys Disk failed: Creating Phys Disk Config " 8001 "Page", /* 24h */ 8002 NULL, /* 25h */ 8003 NULL, /* 26h */ 8004 NULL, /* 27h */ 8005 NULL, /* 28h */ 8006 NULL, /* 29h */ 8007 NULL, /* 2Ah */ 8008 NULL, /* 2Bh */ 8009 NULL, /* 2Ch */ 8010 NULL, /* 2Dh */ 8011 NULL, /* 2Eh */ 8012 NULL, /* 2Fh */ 8013 "Compatibility Error: IR Disabled", /* 30h */ 8014 "Compatibility Error: Inquiry Command Failed", /* 31h */ 8015 "Compatibility Error: Device not Direct Access " 8016 "Device ", /* 32h */ 8017 "Compatibility Error: Removable Device Found", /* 33h */ 8018 "Compatibility Error: Device SCSI Version not " 8019 "2 or Higher", /* 34h */ 8020 "Compatibility Error: SATA Device, 48 BIT LBA " 8021 "not Supported", /* 35h */ 8022 "Compatibility Error: Device doesn't have " 8023 "512 Byte Block Sizes", /* 36h */ 8024 "Compatibility Error: Volume Type Check Failed", /* 37h */ 8025 "Compatibility Error: Volume Type is " 8026 "Unsupported by FW", /* 38h */ 8027 "Compatibility Error: Disk Drive too Small for " 8028 "use in Volume", /* 39h */ 8029 "Compatibility Error: Phys Disk for Create " 8030 "Volume not Found", /* 3Ah */ 8031 "Compatibility Error: Too Many or too Few " 8032 "Disks for Volume Type", /* 3Bh */ 8033 "Compatibility Error: Disk stripe Sizes " 8034 "Must be 64KB", /* 3Ch */ 8035 "Compatibility Error: IME Size Limited to < 2TB", /* 3Dh */ 8036 }; 8037 8038 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8039 /** 8040 * mpt_sas_log_info - Log information returned from SAS IOC. 8041 * @ioc: Pointer to MPT_ADAPTER structure 8042 * @log_info: U32 LogInfo reply word from the IOC 8043 * @cb_idx: callback function's handle 8044 * 8045 * Refer to lsi/mpi_log_sas.h. 8046 **/ 8047 static void 8048 mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info, u8 cb_idx) 8049 { 8050 union loginfo_type { 8051 u32 loginfo; 8052 struct { 8053 u32 subcode:16; 8054 u32 code:8; 8055 u32 originator:4; 8056 u32 bus_type:4; 8057 } dw; 8058 }; 8059 union loginfo_type sas_loginfo; 8060 char *originator_desc = NULL; 8061 char *code_desc = NULL; 8062 char *sub_code_desc = NULL; 8063 8064 sas_loginfo.loginfo = log_info; 8065 if ((sas_loginfo.dw.bus_type != 3 /*SAS*/) && 8066 (sas_loginfo.dw.originator < ARRAY_SIZE(originator_str))) 8067 return; 8068 8069 originator_desc = originator_str[sas_loginfo.dw.originator]; 8070 8071 switch (sas_loginfo.dw.originator) { 8072 8073 case 0: /* IOP */ 8074 if (sas_loginfo.dw.code < 8075 ARRAY_SIZE(iop_code_str)) 8076 code_desc = iop_code_str[sas_loginfo.dw.code]; 8077 break; 8078 case 1: /* PL */ 8079 if (sas_loginfo.dw.code < 8080 ARRAY_SIZE(pl_code_str)) 8081 code_desc = pl_code_str[sas_loginfo.dw.code]; 8082 break; 8083 case 2: /* IR */ 8084 if (sas_loginfo.dw.code >= 8085 ARRAY_SIZE(ir_code_str)) 8086 break; 8087 code_desc = ir_code_str[sas_loginfo.dw.code]; 8088 if (sas_loginfo.dw.subcode >= 8089 ARRAY_SIZE(raid_sub_code_str)) 8090 break; 8091 if (sas_loginfo.dw.code == 0) 8092 sub_code_desc = 8093 raid_sub_code_str[sas_loginfo.dw.subcode]; 8094 break; 8095 default: 8096 return; 8097 } 8098 8099 if (sub_code_desc != NULL) 8100 printk(MYIOC_s_INFO_FMT 8101 "LogInfo(0x%08x): Originator={%s}, Code={%s}," 8102 " SubCode={%s} cb_idx %s\n", 8103 ioc->name, log_info, originator_desc, code_desc, 8104 sub_code_desc, MptCallbacksName[cb_idx]); 8105 else if (code_desc != NULL) 8106 printk(MYIOC_s_INFO_FMT 8107 "LogInfo(0x%08x): Originator={%s}, Code={%s}," 8108 " SubCode(0x%04x) cb_idx %s\n", 8109 ioc->name, log_info, originator_desc, code_desc, 8110 sas_loginfo.dw.subcode, MptCallbacksName[cb_idx]); 8111 else 8112 printk(MYIOC_s_INFO_FMT 8113 "LogInfo(0x%08x): Originator={%s}, Code=(0x%02x)," 8114 " SubCode(0x%04x) cb_idx %s\n", 8115 ioc->name, log_info, originator_desc, 8116 sas_loginfo.dw.code, sas_loginfo.dw.subcode, 8117 MptCallbacksName[cb_idx]); 8118 } 8119 8120 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8121 /** 8122 * mpt_iocstatus_info_config - IOCSTATUS information for config pages 8123 * @ioc: Pointer to MPT_ADAPTER structure 8124 * @ioc_status: U32 IOCStatus word from IOC 8125 * @mf: Pointer to MPT request frame 8126 * 8127 * Refer to lsi/mpi.h. 8128 **/ 8129 static void 8130 mpt_iocstatus_info_config(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf) 8131 { 8132 Config_t *pReq = (Config_t *)mf; 8133 char extend_desc[EVENT_DESCR_STR_SZ]; 8134 char *desc = NULL; 8135 u32 form; 8136 u8 page_type; 8137 8138 if (pReq->Header.PageType == MPI_CONFIG_PAGETYPE_EXTENDED) 8139 page_type = pReq->ExtPageType; 8140 else 8141 page_type = pReq->Header.PageType; 8142 8143 /* 8144 * ignore invalid page messages for GET_NEXT_HANDLE 8145 */ 8146 form = le32_to_cpu(pReq->PageAddress); 8147 if (ioc_status == MPI_IOCSTATUS_CONFIG_INVALID_PAGE) { 8148 if (page_type == MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE || 8149 page_type == MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER || 8150 page_type == MPI_CONFIG_EXTPAGETYPE_ENCLOSURE) { 8151 if ((form >> MPI_SAS_DEVICE_PGAD_FORM_SHIFT) == 8152 MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE) 8153 return; 8154 } 8155 if (page_type == MPI_CONFIG_PAGETYPE_FC_DEVICE) 8156 if ((form & MPI_FC_DEVICE_PGAD_FORM_MASK) == 8157 MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 8158 return; 8159 } 8160 8161 snprintf(extend_desc, EVENT_DESCR_STR_SZ, 8162 "type=%02Xh, page=%02Xh, action=%02Xh, form=%08Xh", 8163 page_type, pReq->Header.PageNumber, pReq->Action, form); 8164 8165 switch (ioc_status) { 8166 8167 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */ 8168 desc = "Config Page Invalid Action"; 8169 break; 8170 8171 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */ 8172 desc = "Config Page Invalid Type"; 8173 break; 8174 8175 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */ 8176 desc = "Config Page Invalid Page"; 8177 break; 8178 8179 case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */ 8180 desc = "Config Page Invalid Data"; 8181 break; 8182 8183 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */ 8184 desc = "Config Page No Defaults"; 8185 break; 8186 8187 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */ 8188 desc = "Config Page Can't Commit"; 8189 break; 8190 } 8191 8192 if (!desc) 8193 return; 8194 8195 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s: %s\n", 8196 ioc->name, ioc_status, desc, extend_desc)); 8197 } 8198 8199 /** 8200 * mpt_iocstatus_info - IOCSTATUS information returned from IOC. 8201 * @ioc: Pointer to MPT_ADAPTER structure 8202 * @ioc_status: U32 IOCStatus word from IOC 8203 * @mf: Pointer to MPT request frame 8204 * 8205 * Refer to lsi/mpi.h. 8206 **/ 8207 static void 8208 mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf) 8209 { 8210 u32 status = ioc_status & MPI_IOCSTATUS_MASK; 8211 char *desc = NULL; 8212 8213 switch (status) { 8214 8215 /****************************************************************************/ 8216 /* Common IOCStatus values for all replies */ 8217 /****************************************************************************/ 8218 8219 case MPI_IOCSTATUS_INVALID_FUNCTION: /* 0x0001 */ 8220 desc = "Invalid Function"; 8221 break; 8222 8223 case MPI_IOCSTATUS_BUSY: /* 0x0002 */ 8224 desc = "Busy"; 8225 break; 8226 8227 case MPI_IOCSTATUS_INVALID_SGL: /* 0x0003 */ 8228 desc = "Invalid SGL"; 8229 break; 8230 8231 case MPI_IOCSTATUS_INTERNAL_ERROR: /* 0x0004 */ 8232 desc = "Internal Error"; 8233 break; 8234 8235 case MPI_IOCSTATUS_RESERVED: /* 0x0005 */ 8236 desc = "Reserved"; 8237 break; 8238 8239 case MPI_IOCSTATUS_INSUFFICIENT_RESOURCES: /* 0x0006 */ 8240 desc = "Insufficient Resources"; 8241 break; 8242 8243 case MPI_IOCSTATUS_INVALID_FIELD: /* 0x0007 */ 8244 desc = "Invalid Field"; 8245 break; 8246 8247 case MPI_IOCSTATUS_INVALID_STATE: /* 0x0008 */ 8248 desc = "Invalid State"; 8249 break; 8250 8251 /****************************************************************************/ 8252 /* Config IOCStatus values */ 8253 /****************************************************************************/ 8254 8255 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */ 8256 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */ 8257 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */ 8258 case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */ 8259 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */ 8260 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */ 8261 mpt_iocstatus_info_config(ioc, status, mf); 8262 break; 8263 8264 /****************************************************************************/ 8265 /* SCSIIO Reply (SPI, FCP, SAS) initiator values */ 8266 /* */ 8267 /* Look at mptscsih_iocstatus_info_scsiio in mptscsih.c */ 8268 /* */ 8269 /****************************************************************************/ 8270 8271 case MPI_IOCSTATUS_SCSI_RECOVERED_ERROR: /* 0x0040 */ 8272 case MPI_IOCSTATUS_SCSI_DATA_UNDERRUN: /* 0x0045 */ 8273 case MPI_IOCSTATUS_SCSI_INVALID_BUS: /* 0x0041 */ 8274 case MPI_IOCSTATUS_SCSI_INVALID_TARGETID: /* 0x0042 */ 8275 case MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE: /* 0x0043 */ 8276 case MPI_IOCSTATUS_SCSI_DATA_OVERRUN: /* 0x0044 */ 8277 case MPI_IOCSTATUS_SCSI_IO_DATA_ERROR: /* 0x0046 */ 8278 case MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR: /* 0x0047 */ 8279 case MPI_IOCSTATUS_SCSI_TASK_TERMINATED: /* 0x0048 */ 8280 case MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: /* 0x0049 */ 8281 case MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED: /* 0x004A */ 8282 case MPI_IOCSTATUS_SCSI_IOC_TERMINATED: /* 0x004B */ 8283 case MPI_IOCSTATUS_SCSI_EXT_TERMINATED: /* 0x004C */ 8284 break; 8285 8286 /****************************************************************************/ 8287 /* SCSI Target values */ 8288 /****************************************************************************/ 8289 8290 case MPI_IOCSTATUS_TARGET_PRIORITY_IO: /* 0x0060 */ 8291 desc = "Target: Priority IO"; 8292 break; 8293 8294 case MPI_IOCSTATUS_TARGET_INVALID_PORT: /* 0x0061 */ 8295 desc = "Target: Invalid Port"; 8296 break; 8297 8298 case MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX: /* 0x0062 */ 8299 desc = "Target Invalid IO Index:"; 8300 break; 8301 8302 case MPI_IOCSTATUS_TARGET_ABORTED: /* 0x0063 */ 8303 desc = "Target: Aborted"; 8304 break; 8305 8306 case MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: /* 0x0064 */ 8307 desc = "Target: No Conn Retryable"; 8308 break; 8309 8310 case MPI_IOCSTATUS_TARGET_NO_CONNECTION: /* 0x0065 */ 8311 desc = "Target: No Connection"; 8312 break; 8313 8314 case MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: /* 0x006A */ 8315 desc = "Target: Transfer Count Mismatch"; 8316 break; 8317 8318 case MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT: /* 0x006B */ 8319 desc = "Target: STS Data not Sent"; 8320 break; 8321 8322 case MPI_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: /* 0x006D */ 8323 desc = "Target: Data Offset Error"; 8324 break; 8325 8326 case MPI_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: /* 0x006E */ 8327 desc = "Target: Too Much Write Data"; 8328 break; 8329 8330 case MPI_IOCSTATUS_TARGET_IU_TOO_SHORT: /* 0x006F */ 8331 desc = "Target: IU Too Short"; 8332 break; 8333 8334 case MPI_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: /* 0x0070 */ 8335 desc = "Target: ACK NAK Timeout"; 8336 break; 8337 8338 case MPI_IOCSTATUS_TARGET_NAK_RECEIVED: /* 0x0071 */ 8339 desc = "Target: Nak Received"; 8340 break; 8341 8342 /****************************************************************************/ 8343 /* Fibre Channel Direct Access values */ 8344 /****************************************************************************/ 8345 8346 case MPI_IOCSTATUS_FC_ABORTED: /* 0x0066 */ 8347 desc = "FC: Aborted"; 8348 break; 8349 8350 case MPI_IOCSTATUS_FC_RX_ID_INVALID: /* 0x0067 */ 8351 desc = "FC: RX ID Invalid"; 8352 break; 8353 8354 case MPI_IOCSTATUS_FC_DID_INVALID: /* 0x0068 */ 8355 desc = "FC: DID Invalid"; 8356 break; 8357 8358 case MPI_IOCSTATUS_FC_NODE_LOGGED_OUT: /* 0x0069 */ 8359 desc = "FC: Node Logged Out"; 8360 break; 8361 8362 case MPI_IOCSTATUS_FC_EXCHANGE_CANCELED: /* 0x006C */ 8363 desc = "FC: Exchange Canceled"; 8364 break; 8365 8366 /****************************************************************************/ 8367 /* LAN values */ 8368 /****************************************************************************/ 8369 8370 case MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND: /* 0x0080 */ 8371 desc = "LAN: Device not Found"; 8372 break; 8373 8374 case MPI_IOCSTATUS_LAN_DEVICE_FAILURE: /* 0x0081 */ 8375 desc = "LAN: Device Failure"; 8376 break; 8377 8378 case MPI_IOCSTATUS_LAN_TRANSMIT_ERROR: /* 0x0082 */ 8379 desc = "LAN: Transmit Error"; 8380 break; 8381 8382 case MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED: /* 0x0083 */ 8383 desc = "LAN: Transmit Aborted"; 8384 break; 8385 8386 case MPI_IOCSTATUS_LAN_RECEIVE_ERROR: /* 0x0084 */ 8387 desc = "LAN: Receive Error"; 8388 break; 8389 8390 case MPI_IOCSTATUS_LAN_RECEIVE_ABORTED: /* 0x0085 */ 8391 desc = "LAN: Receive Aborted"; 8392 break; 8393 8394 case MPI_IOCSTATUS_LAN_PARTIAL_PACKET: /* 0x0086 */ 8395 desc = "LAN: Partial Packet"; 8396 break; 8397 8398 case MPI_IOCSTATUS_LAN_CANCELED: /* 0x0087 */ 8399 desc = "LAN: Canceled"; 8400 break; 8401 8402 /****************************************************************************/ 8403 /* Serial Attached SCSI values */ 8404 /****************************************************************************/ 8405 8406 case MPI_IOCSTATUS_SAS_SMP_REQUEST_FAILED: /* 0x0090 */ 8407 desc = "SAS: SMP Request Failed"; 8408 break; 8409 8410 case MPI_IOCSTATUS_SAS_SMP_DATA_OVERRUN: /* 0x0090 */ 8411 desc = "SAS: SMP Data Overrun"; 8412 break; 8413 8414 default: 8415 desc = "Others"; 8416 break; 8417 } 8418 8419 if (!desc) 8420 return; 8421 8422 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s\n", 8423 ioc->name, status, desc)); 8424 } 8425 8426 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8427 EXPORT_SYMBOL(mpt_attach); 8428 EXPORT_SYMBOL(mpt_detach); 8429 #ifdef CONFIG_PM 8430 EXPORT_SYMBOL(mpt_resume); 8431 EXPORT_SYMBOL(mpt_suspend); 8432 #endif 8433 EXPORT_SYMBOL(ioc_list); 8434 EXPORT_SYMBOL(mpt_register); 8435 EXPORT_SYMBOL(mpt_deregister); 8436 EXPORT_SYMBOL(mpt_event_register); 8437 EXPORT_SYMBOL(mpt_event_deregister); 8438 EXPORT_SYMBOL(mpt_reset_register); 8439 EXPORT_SYMBOL(mpt_reset_deregister); 8440 EXPORT_SYMBOL(mpt_device_driver_register); 8441 EXPORT_SYMBOL(mpt_device_driver_deregister); 8442 EXPORT_SYMBOL(mpt_get_msg_frame); 8443 EXPORT_SYMBOL(mpt_put_msg_frame); 8444 EXPORT_SYMBOL(mpt_put_msg_frame_hi_pri); 8445 EXPORT_SYMBOL(mpt_free_msg_frame); 8446 EXPORT_SYMBOL(mpt_send_handshake_request); 8447 EXPORT_SYMBOL(mpt_verify_adapter); 8448 EXPORT_SYMBOL(mpt_GetIocState); 8449 EXPORT_SYMBOL(mpt_print_ioc_summary); 8450 EXPORT_SYMBOL(mpt_HardResetHandler); 8451 EXPORT_SYMBOL(mpt_config); 8452 EXPORT_SYMBOL(mpt_findImVolumes); 8453 EXPORT_SYMBOL(mpt_alloc_fw_memory); 8454 EXPORT_SYMBOL(mpt_free_fw_memory); 8455 EXPORT_SYMBOL(mptbase_sas_persist_operation); 8456 EXPORT_SYMBOL(mpt_raid_phys_disk_pg0); 8457 8458 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8459 /** 8460 * fusion_init - Fusion MPT base driver initialization routine. 8461 * 8462 * Returns 0 for success, non-zero for failure. 8463 */ 8464 static int __init 8465 fusion_init(void) 8466 { 8467 u8 cb_idx; 8468 8469 show_mptmod_ver(my_NAME, my_VERSION); 8470 printk(KERN_INFO COPYRIGHT "\n"); 8471 8472 for (cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) { 8473 MptCallbacks[cb_idx] = NULL; 8474 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER; 8475 MptEvHandlers[cb_idx] = NULL; 8476 MptResetHandlers[cb_idx] = NULL; 8477 } 8478 8479 /* Register ourselves (mptbase) in order to facilitate 8480 * EventNotification handling. 8481 */ 8482 mpt_base_index = mpt_register(mptbase_reply, MPTBASE_DRIVER, 8483 "mptbase_reply"); 8484 8485 /* Register for hard reset handling callbacks. 8486 */ 8487 mpt_reset_register(mpt_base_index, mpt_ioc_reset); 8488 8489 #ifdef CONFIG_PROC_FS 8490 (void) procmpt_create(); 8491 #endif 8492 return 0; 8493 } 8494 8495 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8496 /** 8497 * fusion_exit - Perform driver unload cleanup. 8498 * 8499 * This routine frees all resources associated with each MPT adapter 8500 * and removes all %MPT_PROCFS_MPTBASEDIR entries. 8501 */ 8502 static void __exit 8503 fusion_exit(void) 8504 { 8505 8506 mpt_reset_deregister(mpt_base_index); 8507 8508 #ifdef CONFIG_PROC_FS 8509 procmpt_destroy(); 8510 #endif 8511 } 8512 8513 module_init(fusion_init); 8514 module_exit(fusion_exit); 8515