1 /* 2 * linux/drivers/message/fusion/mptbase.c 3 * This is the Fusion MPT base driver which supports multiple 4 * (SCSI + LAN) specialized protocol drivers. 5 * For use with LSI PCI chip/adapter(s) 6 * running LSI Fusion MPT (Message Passing Technology) firmware. 7 * 8 * Copyright (c) 1999-2008 LSI Corporation 9 * (mailto:DL-MPTFusionLinux@lsi.com) 10 * 11 */ 12 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 13 /* 14 This program is free software; you can redistribute it and/or modify 15 it under the terms of the GNU General Public License as published by 16 the Free Software Foundation; version 2 of the License. 17 18 This program is distributed in the hope that it will be useful, 19 but WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 GNU General Public License for more details. 22 23 NO WARRANTY 24 THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR 25 CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT 26 LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, 27 MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is 28 solely responsible for determining the appropriateness of using and 29 distributing the Program and assumes all risks associated with its 30 exercise of rights under this Agreement, including but not limited to 31 the risks and costs of program errors, damage to or loss of data, 32 programs or equipment, and unavailability or interruption of operations. 33 34 DISCLAIMER OF LIABILITY 35 NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY 36 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND 38 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 39 TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 40 USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED 41 HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES 42 43 You should have received a copy of the GNU General Public License 44 along with this program; if not, write to the Free Software 45 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 46 */ 47 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 48 49 #include <linux/kernel.h> 50 #include <linux/module.h> 51 #include <linux/errno.h> 52 #include <linux/init.h> 53 #include <linux/seq_file.h> 54 #include <linux/slab.h> 55 #include <linux/types.h> 56 #include <linux/pci.h> 57 #include <linux/kdev_t.h> 58 #include <linux/blkdev.h> 59 #include <linux/delay.h> 60 #include <linux/interrupt.h> 61 #include <linux/dma-mapping.h> 62 #include <linux/kthread.h> 63 #include <scsi/scsi_host.h> 64 65 #include "mptbase.h" 66 #include "lsi/mpi_log_fc.h" 67 68 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 69 #define my_NAME "Fusion MPT base driver" 70 #define my_VERSION MPT_LINUX_VERSION_COMMON 71 #define MYNAM "mptbase" 72 73 MODULE_AUTHOR(MODULEAUTHOR); 74 MODULE_DESCRIPTION(my_NAME); 75 MODULE_LICENSE("GPL"); 76 MODULE_VERSION(my_VERSION); 77 78 /* 79 * cmd line parameters 80 */ 81 82 static int mpt_msi_enable_spi; 83 module_param(mpt_msi_enable_spi, int, 0); 84 MODULE_PARM_DESC(mpt_msi_enable_spi, 85 " Enable MSI Support for SPI controllers (default=0)"); 86 87 static int mpt_msi_enable_fc; 88 module_param(mpt_msi_enable_fc, int, 0); 89 MODULE_PARM_DESC(mpt_msi_enable_fc, 90 " Enable MSI Support for FC controllers (default=0)"); 91 92 static int mpt_msi_enable_sas; 93 module_param(mpt_msi_enable_sas, int, 0); 94 MODULE_PARM_DESC(mpt_msi_enable_sas, 95 " Enable MSI Support for SAS controllers (default=0)"); 96 97 static int mpt_channel_mapping; 98 module_param(mpt_channel_mapping, int, 0); 99 MODULE_PARM_DESC(mpt_channel_mapping, " Mapping id's to channels (default=0)"); 100 101 static int mpt_debug_level; 102 static int mpt_set_debug_level(const char *val, const struct kernel_param *kp); 103 module_param_call(mpt_debug_level, mpt_set_debug_level, param_get_int, 104 &mpt_debug_level, 0600); 105 MODULE_PARM_DESC(mpt_debug_level, 106 " debug level - refer to mptdebug.h - (default=0)"); 107 108 int mpt_fwfault_debug; 109 EXPORT_SYMBOL(mpt_fwfault_debug); 110 module_param(mpt_fwfault_debug, int, 0600); 111 MODULE_PARM_DESC(mpt_fwfault_debug, 112 "Enable detection of Firmware fault and halt Firmware on fault - (default=0)"); 113 114 static char MptCallbacksName[MPT_MAX_PROTOCOL_DRIVERS] 115 [MPT_MAX_CALLBACKNAME_LEN+1]; 116 117 #ifdef MFCNT 118 static int mfcounter = 0; 119 #define PRINT_MF_COUNT 20000 120 #endif 121 122 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 123 /* 124 * Public data... 125 */ 126 127 #define WHOINIT_UNKNOWN 0xAA 128 129 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 130 /* 131 * Private data... 132 */ 133 /* Adapter link list */ 134 LIST_HEAD(ioc_list); 135 /* Callback lookup table */ 136 static MPT_CALLBACK MptCallbacks[MPT_MAX_PROTOCOL_DRIVERS]; 137 /* Protocol driver class lookup table */ 138 static int MptDriverClass[MPT_MAX_PROTOCOL_DRIVERS]; 139 /* Event handler lookup table */ 140 static MPT_EVHANDLER MptEvHandlers[MPT_MAX_PROTOCOL_DRIVERS]; 141 /* Reset handler lookup table */ 142 static MPT_RESETHANDLER MptResetHandlers[MPT_MAX_PROTOCOL_DRIVERS]; 143 static struct mpt_pci_driver *MptDeviceDriverHandlers[MPT_MAX_PROTOCOL_DRIVERS]; 144 145 #ifdef CONFIG_PROC_FS 146 static struct proc_dir_entry *mpt_proc_root_dir; 147 #endif 148 149 /* 150 * Driver Callback Index's 151 */ 152 static u8 mpt_base_index = MPT_MAX_PROTOCOL_DRIVERS; 153 static u8 last_drv_idx; 154 155 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 156 /* 157 * Forward protos... 158 */ 159 static irqreturn_t mpt_interrupt(int irq, void *bus_id); 160 static int mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, 161 MPT_FRAME_HDR *reply); 162 static int mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, 163 u32 *req, int replyBytes, u16 *u16reply, int maxwait, 164 int sleepFlag); 165 static int mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag); 166 static void mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev); 167 static void mpt_adapter_disable(MPT_ADAPTER *ioc); 168 static void mpt_adapter_dispose(MPT_ADAPTER *ioc); 169 170 static void MptDisplayIocCapabilities(MPT_ADAPTER *ioc); 171 static int MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag); 172 static int GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason); 173 static int GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag); 174 static int SendIocInit(MPT_ADAPTER *ioc, int sleepFlag); 175 static int SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag); 176 static int mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag); 177 static int mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag); 178 static int mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag); 179 static int KickStart(MPT_ADAPTER *ioc, int ignore, int sleepFlag); 180 static int SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag); 181 static int PrimeIocFifos(MPT_ADAPTER *ioc); 182 static int WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag); 183 static int WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag); 184 static int WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag); 185 static int GetLanConfigPages(MPT_ADAPTER *ioc); 186 static int GetIoUnitPage2(MPT_ADAPTER *ioc); 187 int mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode); 188 static int mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum); 189 static int mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum); 190 static void mpt_read_ioc_pg_1(MPT_ADAPTER *ioc); 191 static void mpt_read_ioc_pg_4(MPT_ADAPTER *ioc); 192 static void mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc); 193 static int SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch, 194 int sleepFlag); 195 static int SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp); 196 static int mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag); 197 static int mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init); 198 199 #ifdef CONFIG_PROC_FS 200 static int mpt_summary_proc_show(struct seq_file *m, void *v); 201 static int mpt_version_proc_show(struct seq_file *m, void *v); 202 static int mpt_iocinfo_proc_show(struct seq_file *m, void *v); 203 #endif 204 static void mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc); 205 206 static int ProcessEventNotification(MPT_ADAPTER *ioc, 207 EventNotificationReply_t *evReply, int *evHandlers); 208 static void mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf); 209 static void mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info); 210 static void mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info); 211 static void mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info , u8 cb_idx); 212 static int mpt_read_ioc_pg_3(MPT_ADAPTER *ioc); 213 static void mpt_inactive_raid_list_free(MPT_ADAPTER *ioc); 214 215 /* module entry point */ 216 static int __init fusion_init (void); 217 static void __exit fusion_exit (void); 218 219 #define CHIPREG_READ32(addr) readl_relaxed(addr) 220 #define CHIPREG_READ32_dmasync(addr) readl(addr) 221 #define CHIPREG_WRITE32(addr,val) writel(val, addr) 222 #define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr) 223 #define CHIPREG_PIO_READ32(addr) inl((unsigned long)addr) 224 225 static void 226 pci_disable_io_access(struct pci_dev *pdev) 227 { 228 u16 command_reg; 229 230 pci_read_config_word(pdev, PCI_COMMAND, &command_reg); 231 command_reg &= ~1; 232 pci_write_config_word(pdev, PCI_COMMAND, command_reg); 233 } 234 235 static void 236 pci_enable_io_access(struct pci_dev *pdev) 237 { 238 u16 command_reg; 239 240 pci_read_config_word(pdev, PCI_COMMAND, &command_reg); 241 command_reg |= 1; 242 pci_write_config_word(pdev, PCI_COMMAND, command_reg); 243 } 244 245 static int mpt_set_debug_level(const char *val, const struct kernel_param *kp) 246 { 247 int ret = param_set_int(val, kp); 248 MPT_ADAPTER *ioc; 249 250 if (ret) 251 return ret; 252 253 list_for_each_entry(ioc, &ioc_list, list) 254 ioc->debug_level = mpt_debug_level; 255 return 0; 256 } 257 258 /** 259 * mpt_get_cb_idx - obtain cb_idx for registered driver 260 * @dclass: class driver enum 261 * 262 * Returns cb_idx, or zero means it wasn't found 263 **/ 264 static u8 265 mpt_get_cb_idx(MPT_DRIVER_CLASS dclass) 266 { 267 u8 cb_idx; 268 269 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) 270 if (MptDriverClass[cb_idx] == dclass) 271 return cb_idx; 272 return 0; 273 } 274 275 /** 276 * mpt_is_discovery_complete - determine if discovery has completed 277 * @ioc: per adatper instance 278 * 279 * Returns 1 when discovery completed, else zero. 280 */ 281 static int 282 mpt_is_discovery_complete(MPT_ADAPTER *ioc) 283 { 284 ConfigExtendedPageHeader_t hdr; 285 CONFIGPARMS cfg; 286 SasIOUnitPage0_t *buffer; 287 dma_addr_t dma_handle; 288 int rc = 0; 289 290 memset(&hdr, 0, sizeof(ConfigExtendedPageHeader_t)); 291 memset(&cfg, 0, sizeof(CONFIGPARMS)); 292 hdr.PageVersion = MPI_SASIOUNITPAGE0_PAGEVERSION; 293 hdr.PageType = MPI_CONFIG_PAGETYPE_EXTENDED; 294 hdr.ExtPageType = MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT; 295 cfg.cfghdr.ehdr = &hdr; 296 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 297 298 if ((mpt_config(ioc, &cfg))) 299 goto out; 300 if (!hdr.ExtPageLength) 301 goto out; 302 303 buffer = pci_alloc_consistent(ioc->pcidev, hdr.ExtPageLength * 4, 304 &dma_handle); 305 if (!buffer) 306 goto out; 307 308 cfg.physAddr = dma_handle; 309 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 310 311 if ((mpt_config(ioc, &cfg))) 312 goto out_free_consistent; 313 314 if (!(buffer->PhyData[0].PortFlags & 315 MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS)) 316 rc = 1; 317 318 out_free_consistent: 319 pci_free_consistent(ioc->pcidev, hdr.ExtPageLength * 4, 320 buffer, dma_handle); 321 out: 322 return rc; 323 } 324 325 326 /** 327 * mpt_remove_dead_ioc_func - kthread context to remove dead ioc 328 * @arg: input argument, used to derive ioc 329 * 330 * Return 0 if controller is removed from pci subsystem. 331 * Return -1 for other case. 332 */ 333 static int mpt_remove_dead_ioc_func(void *arg) 334 { 335 MPT_ADAPTER *ioc = (MPT_ADAPTER *)arg; 336 struct pci_dev *pdev; 337 338 if (!ioc) 339 return -1; 340 341 pdev = ioc->pcidev; 342 if (!pdev) 343 return -1; 344 345 pci_stop_and_remove_bus_device_locked(pdev); 346 return 0; 347 } 348 349 350 351 /** 352 * mpt_fault_reset_work - work performed on workq after ioc fault 353 * @work: input argument, used to derive ioc 354 * 355 **/ 356 static void 357 mpt_fault_reset_work(struct work_struct *work) 358 { 359 MPT_ADAPTER *ioc = 360 container_of(work, MPT_ADAPTER, fault_reset_work.work); 361 u32 ioc_raw_state; 362 int rc; 363 unsigned long flags; 364 MPT_SCSI_HOST *hd; 365 struct task_struct *p; 366 367 if (ioc->ioc_reset_in_progress || !ioc->active) 368 goto out; 369 370 371 ioc_raw_state = mpt_GetIocState(ioc, 0); 372 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_MASK) { 373 printk(MYIOC_s_INFO_FMT "%s: IOC is non-operational !!!!\n", 374 ioc->name, __func__); 375 376 /* 377 * Call mptscsih_flush_pending_cmds callback so that we 378 * flush all pending commands back to OS. 379 * This call is required to aovid deadlock at block layer. 380 * Dead IOC will fail to do diag reset,and this call is safe 381 * since dead ioc will never return any command back from HW. 382 */ 383 hd = shost_priv(ioc->sh); 384 ioc->schedule_dead_ioc_flush_running_cmds(hd); 385 386 /*Remove the Dead Host */ 387 p = kthread_run(mpt_remove_dead_ioc_func, ioc, 388 "mpt_dead_ioc_%d", ioc->id); 389 if (IS_ERR(p)) { 390 printk(MYIOC_s_ERR_FMT 391 "%s: Running mpt_dead_ioc thread failed !\n", 392 ioc->name, __func__); 393 } else { 394 printk(MYIOC_s_WARN_FMT 395 "%s: Running mpt_dead_ioc thread success !\n", 396 ioc->name, __func__); 397 } 398 return; /* don't rearm timer */ 399 } 400 401 if ((ioc_raw_state & MPI_IOC_STATE_MASK) 402 == MPI_IOC_STATE_FAULT) { 403 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state (%04xh)!!!\n", 404 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK); 405 printk(MYIOC_s_WARN_FMT "Issuing HardReset from %s!!\n", 406 ioc->name, __func__); 407 rc = mpt_HardResetHandler(ioc, CAN_SLEEP); 408 printk(MYIOC_s_WARN_FMT "%s: HardReset: %s\n", ioc->name, 409 __func__, (rc == 0) ? "success" : "failed"); 410 ioc_raw_state = mpt_GetIocState(ioc, 0); 411 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) 412 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state after " 413 "reset (%04xh)\n", ioc->name, ioc_raw_state & 414 MPI_DOORBELL_DATA_MASK); 415 } else if (ioc->bus_type == SAS && ioc->sas_discovery_quiesce_io) { 416 if ((mpt_is_discovery_complete(ioc))) { 417 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "clearing " 418 "discovery_quiesce_io flag\n", ioc->name)); 419 ioc->sas_discovery_quiesce_io = 0; 420 } 421 } 422 423 out: 424 /* 425 * Take turns polling alternate controller 426 */ 427 if (ioc->alt_ioc) 428 ioc = ioc->alt_ioc; 429 430 /* rearm the timer */ 431 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 432 if (ioc->reset_work_q) 433 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work, 434 msecs_to_jiffies(MPT_POLLING_INTERVAL)); 435 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 436 } 437 438 439 /* 440 * Process turbo (context) reply... 441 */ 442 static void 443 mpt_turbo_reply(MPT_ADAPTER *ioc, u32 pa) 444 { 445 MPT_FRAME_HDR *mf = NULL; 446 MPT_FRAME_HDR *mr = NULL; 447 u16 req_idx = 0; 448 u8 cb_idx; 449 450 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got TURBO reply req_idx=%08x\n", 451 ioc->name, pa)); 452 453 switch (pa >> MPI_CONTEXT_REPLY_TYPE_SHIFT) { 454 case MPI_CONTEXT_REPLY_TYPE_SCSI_INIT: 455 req_idx = pa & 0x0000FFFF; 456 cb_idx = (pa & 0x00FF0000) >> 16; 457 mf = MPT_INDEX_2_MFPTR(ioc, req_idx); 458 break; 459 case MPI_CONTEXT_REPLY_TYPE_LAN: 460 cb_idx = mpt_get_cb_idx(MPTLAN_DRIVER); 461 /* 462 * Blind set of mf to NULL here was fatal 463 * after lan_reply says "freeme" 464 * Fix sort of combined with an optimization here; 465 * added explicit check for case where lan_reply 466 * was just returning 1 and doing nothing else. 467 * For this case skip the callback, but set up 468 * proper mf value first here:-) 469 */ 470 if ((pa & 0x58000000) == 0x58000000) { 471 req_idx = pa & 0x0000FFFF; 472 mf = MPT_INDEX_2_MFPTR(ioc, req_idx); 473 mpt_free_msg_frame(ioc, mf); 474 mb(); 475 return; 476 } 477 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa); 478 break; 479 case MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET: 480 cb_idx = mpt_get_cb_idx(MPTSTM_DRIVER); 481 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa); 482 break; 483 default: 484 cb_idx = 0; 485 BUG(); 486 } 487 488 /* Check for (valid) IO callback! */ 489 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS || 490 MptCallbacks[cb_idx] == NULL) { 491 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n", 492 __func__, ioc->name, cb_idx); 493 goto out; 494 } 495 496 if (MptCallbacks[cb_idx](ioc, mf, mr)) 497 mpt_free_msg_frame(ioc, mf); 498 out: 499 mb(); 500 } 501 502 static void 503 mpt_reply(MPT_ADAPTER *ioc, u32 pa) 504 { 505 MPT_FRAME_HDR *mf; 506 MPT_FRAME_HDR *mr; 507 u16 req_idx; 508 u8 cb_idx; 509 int freeme; 510 511 u32 reply_dma_low; 512 u16 ioc_stat; 513 514 /* non-TURBO reply! Hmmm, something may be up... 515 * Newest turbo reply mechanism; get address 516 * via left shift 1 (get rid of MPI_ADDRESS_REPLY_A_BIT)! 517 */ 518 519 /* Map DMA address of reply header to cpu address. 520 * pa is 32 bits - but the dma address may be 32 or 64 bits 521 * get offset based only only the low addresses 522 */ 523 524 reply_dma_low = (pa <<= 1); 525 mr = (MPT_FRAME_HDR *)((u8 *)ioc->reply_frames + 526 (reply_dma_low - ioc->reply_frames_low_dma)); 527 528 req_idx = le16_to_cpu(mr->u.frame.hwhdr.msgctxu.fld.req_idx); 529 cb_idx = mr->u.frame.hwhdr.msgctxu.fld.cb_idx; 530 mf = MPT_INDEX_2_MFPTR(ioc, req_idx); 531 532 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got non-TURBO reply=%p req_idx=%x cb_idx=%x Function=%x\n", 533 ioc->name, mr, req_idx, cb_idx, mr->u.hdr.Function)); 534 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mr); 535 536 /* Check/log IOC log info 537 */ 538 ioc_stat = le16_to_cpu(mr->u.reply.IOCStatus); 539 if (ioc_stat & MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 540 u32 log_info = le32_to_cpu(mr->u.reply.IOCLogInfo); 541 if (ioc->bus_type == FC) 542 mpt_fc_log_info(ioc, log_info); 543 else if (ioc->bus_type == SPI) 544 mpt_spi_log_info(ioc, log_info); 545 else if (ioc->bus_type == SAS) 546 mpt_sas_log_info(ioc, log_info, cb_idx); 547 } 548 549 if (ioc_stat & MPI_IOCSTATUS_MASK) 550 mpt_iocstatus_info(ioc, (u32)ioc_stat, mf); 551 552 /* Check for (valid) IO callback! */ 553 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS || 554 MptCallbacks[cb_idx] == NULL) { 555 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n", 556 __func__, ioc->name, cb_idx); 557 freeme = 0; 558 goto out; 559 } 560 561 freeme = MptCallbacks[cb_idx](ioc, mf, mr); 562 563 out: 564 /* Flush (non-TURBO) reply with a WRITE! */ 565 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, pa); 566 567 if (freeme) 568 mpt_free_msg_frame(ioc, mf); 569 mb(); 570 } 571 572 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 573 /** 574 * mpt_interrupt - MPT adapter (IOC) specific interrupt handler. 575 * @irq: irq number (not used) 576 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure 577 * 578 * This routine is registered via the request_irq() kernel API call, 579 * and handles all interrupts generated from a specific MPT adapter 580 * (also referred to as a IO Controller or IOC). 581 * This routine must clear the interrupt from the adapter and does 582 * so by reading the reply FIFO. Multiple replies may be processed 583 * per single call to this routine. 584 * 585 * This routine handles register-level access of the adapter but 586 * dispatches (calls) a protocol-specific callback routine to handle 587 * the protocol-specific details of the MPT request completion. 588 */ 589 static irqreturn_t 590 mpt_interrupt(int irq, void *bus_id) 591 { 592 MPT_ADAPTER *ioc = bus_id; 593 u32 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo); 594 595 if (pa == 0xFFFFFFFF) 596 return IRQ_NONE; 597 598 /* 599 * Drain the reply FIFO! 600 */ 601 do { 602 if (pa & MPI_ADDRESS_REPLY_A_BIT) 603 mpt_reply(ioc, pa); 604 else 605 mpt_turbo_reply(ioc, pa); 606 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo); 607 } while (pa != 0xFFFFFFFF); 608 609 return IRQ_HANDLED; 610 } 611 612 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 613 /** 614 * mptbase_reply - MPT base driver's callback routine 615 * @ioc: Pointer to MPT_ADAPTER structure 616 * @req: Pointer to original MPT request frame 617 * @reply: Pointer to MPT reply frame (NULL if TurboReply) 618 * 619 * MPT base driver's callback routine; all base driver 620 * "internal" request/reply processing is routed here. 621 * Currently used for EventNotification and EventAck handling. 622 * 623 * Returns 1 indicating original alloc'd request frame ptr 624 * should be freed, or 0 if it shouldn't. 625 */ 626 static int 627 mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, MPT_FRAME_HDR *reply) 628 { 629 EventNotificationReply_t *pEventReply; 630 u8 event; 631 int evHandlers; 632 int freereq = 1; 633 634 switch (reply->u.hdr.Function) { 635 case MPI_FUNCTION_EVENT_NOTIFICATION: 636 pEventReply = (EventNotificationReply_t *)reply; 637 evHandlers = 0; 638 ProcessEventNotification(ioc, pEventReply, &evHandlers); 639 event = le32_to_cpu(pEventReply->Event) & 0xFF; 640 if (pEventReply->MsgFlags & MPI_MSGFLAGS_CONTINUATION_REPLY) 641 freereq = 0; 642 if (event != MPI_EVENT_EVENT_CHANGE) 643 break; 644 fallthrough; 645 case MPI_FUNCTION_CONFIG: 646 case MPI_FUNCTION_SAS_IO_UNIT_CONTROL: 647 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_COMMAND_GOOD; 648 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_RF_VALID; 649 memcpy(ioc->mptbase_cmds.reply, reply, 650 min(MPT_DEFAULT_FRAME_SIZE, 651 4 * reply->u.reply.MsgLength)); 652 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) { 653 ioc->mptbase_cmds.status &= ~MPT_MGMT_STATUS_PENDING; 654 complete(&ioc->mptbase_cmds.done); 655 } else 656 freereq = 0; 657 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_FREE_MF) 658 freereq = 1; 659 break; 660 case MPI_FUNCTION_EVENT_ACK: 661 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT 662 "EventAck reply received\n", ioc->name)); 663 break; 664 default: 665 printk(MYIOC_s_ERR_FMT 666 "Unexpected msg function (=%02Xh) reply received!\n", 667 ioc->name, reply->u.hdr.Function); 668 break; 669 } 670 671 /* 672 * Conditionally tell caller to free the original 673 * EventNotification/EventAck/unexpected request frame! 674 */ 675 return freereq; 676 } 677 678 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 679 /** 680 * mpt_register - Register protocol-specific main callback handler. 681 * @cbfunc: callback function pointer 682 * @dclass: Protocol driver's class (%MPT_DRIVER_CLASS enum value) 683 * @func_name: call function's name 684 * 685 * This routine is called by a protocol-specific driver (SCSI host, 686 * LAN, SCSI target) to register its reply callback routine. Each 687 * protocol-specific driver must do this before it will be able to 688 * use any IOC resources, such as obtaining request frames. 689 * 690 * NOTES: The SCSI protocol driver currently calls this routine thrice 691 * in order to register separate callbacks; one for "normal" SCSI IO; 692 * one for MptScsiTaskMgmt requests; one for Scan/DV requests. 693 * 694 * Returns u8 valued "handle" in the range (and S.O.D. order) 695 * {N,...,7,6,5,...,1} if successful. 696 * A return value of MPT_MAX_PROTOCOL_DRIVERS (including zero!) should be 697 * considered an error by the caller. 698 */ 699 u8 700 mpt_register(MPT_CALLBACK cbfunc, MPT_DRIVER_CLASS dclass, char *func_name) 701 { 702 u8 cb_idx; 703 last_drv_idx = MPT_MAX_PROTOCOL_DRIVERS; 704 705 /* 706 * Search for empty callback slot in this order: {N,...,7,6,5,...,1} 707 * (slot/handle 0 is reserved!) 708 */ 709 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 710 if (MptCallbacks[cb_idx] == NULL) { 711 MptCallbacks[cb_idx] = cbfunc; 712 MptDriverClass[cb_idx] = dclass; 713 MptEvHandlers[cb_idx] = NULL; 714 last_drv_idx = cb_idx; 715 strlcpy(MptCallbacksName[cb_idx], func_name, 716 MPT_MAX_CALLBACKNAME_LEN+1); 717 break; 718 } 719 } 720 721 return last_drv_idx; 722 } 723 724 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 725 /** 726 * mpt_deregister - Deregister a protocol drivers resources. 727 * @cb_idx: previously registered callback handle 728 * 729 * Each protocol-specific driver should call this routine when its 730 * module is unloaded. 731 */ 732 void 733 mpt_deregister(u8 cb_idx) 734 { 735 if (cb_idx && (cb_idx < MPT_MAX_PROTOCOL_DRIVERS)) { 736 MptCallbacks[cb_idx] = NULL; 737 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER; 738 MptEvHandlers[cb_idx] = NULL; 739 740 last_drv_idx++; 741 } 742 } 743 744 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 745 /** 746 * mpt_event_register - Register protocol-specific event callback handler. 747 * @cb_idx: previously registered (via mpt_register) callback handle 748 * @ev_cbfunc: callback function 749 * 750 * This routine can be called by one or more protocol-specific drivers 751 * if/when they choose to be notified of MPT events. 752 * 753 * Returns 0 for success. 754 */ 755 int 756 mpt_event_register(u8 cb_idx, MPT_EVHANDLER ev_cbfunc) 757 { 758 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 759 return -1; 760 761 MptEvHandlers[cb_idx] = ev_cbfunc; 762 return 0; 763 } 764 765 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 766 /** 767 * mpt_event_deregister - Deregister protocol-specific event callback handler 768 * @cb_idx: previously registered callback handle 769 * 770 * Each protocol-specific driver should call this routine 771 * when it does not (or can no longer) handle events, 772 * or when its module is unloaded. 773 */ 774 void 775 mpt_event_deregister(u8 cb_idx) 776 { 777 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 778 return; 779 780 MptEvHandlers[cb_idx] = NULL; 781 } 782 783 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 784 /** 785 * mpt_reset_register - Register protocol-specific IOC reset handler. 786 * @cb_idx: previously registered (via mpt_register) callback handle 787 * @reset_func: reset function 788 * 789 * This routine can be called by one or more protocol-specific drivers 790 * if/when they choose to be notified of IOC resets. 791 * 792 * Returns 0 for success. 793 */ 794 int 795 mpt_reset_register(u8 cb_idx, MPT_RESETHANDLER reset_func) 796 { 797 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 798 return -1; 799 800 MptResetHandlers[cb_idx] = reset_func; 801 return 0; 802 } 803 804 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 805 /** 806 * mpt_reset_deregister - Deregister protocol-specific IOC reset handler. 807 * @cb_idx: previously registered callback handle 808 * 809 * Each protocol-specific driver should call this routine 810 * when it does not (or can no longer) handle IOC reset handling, 811 * or when its module is unloaded. 812 */ 813 void 814 mpt_reset_deregister(u8 cb_idx) 815 { 816 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 817 return; 818 819 MptResetHandlers[cb_idx] = NULL; 820 } 821 822 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 823 /** 824 * mpt_device_driver_register - Register device driver hooks 825 * @dd_cbfunc: driver callbacks struct 826 * @cb_idx: MPT protocol driver index 827 */ 828 int 829 mpt_device_driver_register(struct mpt_pci_driver * dd_cbfunc, u8 cb_idx) 830 { 831 MPT_ADAPTER *ioc; 832 833 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 834 return -EINVAL; 835 836 MptDeviceDriverHandlers[cb_idx] = dd_cbfunc; 837 838 /* call per pci device probe entry point */ 839 list_for_each_entry(ioc, &ioc_list, list) { 840 if (dd_cbfunc->probe) 841 dd_cbfunc->probe(ioc->pcidev); 842 } 843 844 return 0; 845 } 846 847 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 848 /** 849 * mpt_device_driver_deregister - DeRegister device driver hooks 850 * @cb_idx: MPT protocol driver index 851 */ 852 void 853 mpt_device_driver_deregister(u8 cb_idx) 854 { 855 struct mpt_pci_driver *dd_cbfunc; 856 MPT_ADAPTER *ioc; 857 858 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS) 859 return; 860 861 dd_cbfunc = MptDeviceDriverHandlers[cb_idx]; 862 863 list_for_each_entry(ioc, &ioc_list, list) { 864 if (dd_cbfunc->remove) 865 dd_cbfunc->remove(ioc->pcidev); 866 } 867 868 MptDeviceDriverHandlers[cb_idx] = NULL; 869 } 870 871 872 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 873 /** 874 * mpt_get_msg_frame - Obtain an MPT request frame from the pool 875 * @cb_idx: Handle of registered MPT protocol driver 876 * @ioc: Pointer to MPT adapter structure 877 * 878 * Obtain an MPT request frame from the pool (of 1024) that are 879 * allocated per MPT adapter. 880 * 881 * Returns pointer to a MPT request frame or %NULL if none are available 882 * or IOC is not active. 883 */ 884 MPT_FRAME_HDR* 885 mpt_get_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc) 886 { 887 MPT_FRAME_HDR *mf; 888 unsigned long flags; 889 u16 req_idx; /* Request index */ 890 891 /* validate handle and ioc identifier */ 892 893 #ifdef MFCNT 894 if (!ioc->active) 895 printk(MYIOC_s_WARN_FMT "IOC Not Active! mpt_get_msg_frame " 896 "returning NULL!\n", ioc->name); 897 #endif 898 899 /* If interrupts are not attached, do not return a request frame */ 900 if (!ioc->active) 901 return NULL; 902 903 spin_lock_irqsave(&ioc->FreeQlock, flags); 904 if (!list_empty(&ioc->FreeQ)) { 905 int req_offset; 906 907 mf = list_entry(ioc->FreeQ.next, MPT_FRAME_HDR, 908 u.frame.linkage.list); 909 list_del(&mf->u.frame.linkage.list); 910 mf->u.frame.linkage.arg1 = 0; 911 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */ 912 req_offset = (u8 *)mf - (u8 *)ioc->req_frames; 913 /* u16! */ 914 req_idx = req_offset / ioc->req_sz; 915 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx); 916 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0; 917 /* Default, will be changed if necessary in SG generation */ 918 ioc->RequestNB[req_idx] = ioc->NB_for_64_byte_frame; 919 #ifdef MFCNT 920 ioc->mfcnt++; 921 #endif 922 } 923 else 924 mf = NULL; 925 spin_unlock_irqrestore(&ioc->FreeQlock, flags); 926 927 #ifdef MFCNT 928 if (mf == NULL) 929 printk(MYIOC_s_WARN_FMT "IOC Active. No free Msg Frames! " 930 "Count 0x%x Max 0x%x\n", ioc->name, ioc->mfcnt, 931 ioc->req_depth); 932 mfcounter++; 933 if (mfcounter == PRINT_MF_COUNT) 934 printk(MYIOC_s_INFO_FMT "MF Count 0x%x Max 0x%x \n", ioc->name, 935 ioc->mfcnt, ioc->req_depth); 936 #endif 937 938 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_get_msg_frame(%d,%d), got mf=%p\n", 939 ioc->name, cb_idx, ioc->id, mf)); 940 return mf; 941 } 942 943 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 944 /** 945 * mpt_put_msg_frame - Send a protocol-specific MPT request frame to an IOC 946 * @cb_idx: Handle of registered MPT protocol driver 947 * @ioc: Pointer to MPT adapter structure 948 * @mf: Pointer to MPT request frame 949 * 950 * This routine posts an MPT request frame to the request post FIFO of a 951 * specific MPT adapter. 952 */ 953 void 954 mpt_put_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf) 955 { 956 u32 mf_dma_addr; 957 int req_offset; 958 u16 req_idx; /* Request index */ 959 960 /* ensure values are reset properly! */ 961 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */ 962 req_offset = (u8 *)mf - (u8 *)ioc->req_frames; 963 /* u16! */ 964 req_idx = req_offset / ioc->req_sz; 965 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx); 966 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0; 967 968 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf); 969 970 mf_dma_addr = (ioc->req_frames_low_dma + req_offset) | ioc->RequestNB[req_idx]; 971 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d " 972 "RequestNB=%x\n", ioc->name, mf_dma_addr, req_idx, 973 ioc->RequestNB[req_idx])); 974 CHIPREG_WRITE32(&ioc->chip->RequestFifo, mf_dma_addr); 975 } 976 977 /** 978 * mpt_put_msg_frame_hi_pri - Send a hi-pri protocol-specific MPT request frame 979 * @cb_idx: Handle of registered MPT protocol driver 980 * @ioc: Pointer to MPT adapter structure 981 * @mf: Pointer to MPT request frame 982 * 983 * Send a protocol-specific MPT request frame to an IOC using 984 * hi-priority request queue. 985 * 986 * This routine posts an MPT request frame to the request post FIFO of a 987 * specific MPT adapter. 988 **/ 989 void 990 mpt_put_msg_frame_hi_pri(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf) 991 { 992 u32 mf_dma_addr; 993 int req_offset; 994 u16 req_idx; /* Request index */ 995 996 /* ensure values are reset properly! */ 997 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; 998 req_offset = (u8 *)mf - (u8 *)ioc->req_frames; 999 req_idx = req_offset / ioc->req_sz; 1000 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx); 1001 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0; 1002 1003 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf); 1004 1005 mf_dma_addr = (ioc->req_frames_low_dma + req_offset); 1006 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d\n", 1007 ioc->name, mf_dma_addr, req_idx)); 1008 CHIPREG_WRITE32(&ioc->chip->RequestHiPriFifo, mf_dma_addr); 1009 } 1010 1011 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1012 /** 1013 * mpt_free_msg_frame - Place MPT request frame back on FreeQ. 1014 * @ioc: Pointer to MPT adapter structure 1015 * @mf: Pointer to MPT request frame 1016 * 1017 * This routine places a MPT request frame back on the MPT adapter's 1018 * FreeQ. 1019 */ 1020 void 1021 mpt_free_msg_frame(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf) 1022 { 1023 unsigned long flags; 1024 1025 /* Put Request back on FreeQ! */ 1026 spin_lock_irqsave(&ioc->FreeQlock, flags); 1027 if (cpu_to_le32(mf->u.frame.linkage.arg1) == 0xdeadbeaf) 1028 goto out; 1029 /* signature to know if this mf is freed */ 1030 mf->u.frame.linkage.arg1 = cpu_to_le32(0xdeadbeaf); 1031 list_add(&mf->u.frame.linkage.list, &ioc->FreeQ); 1032 #ifdef MFCNT 1033 ioc->mfcnt--; 1034 #endif 1035 out: 1036 spin_unlock_irqrestore(&ioc->FreeQlock, flags); 1037 } 1038 1039 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1040 /** 1041 * mpt_add_sge - Place a simple 32 bit SGE at address pAddr. 1042 * @pAddr: virtual address for SGE 1043 * @flagslength: SGE flags and data transfer length 1044 * @dma_addr: Physical address 1045 * 1046 * This routine places a MPT request frame back on the MPT adapter's 1047 * FreeQ. 1048 */ 1049 static void 1050 mpt_add_sge(void *pAddr, u32 flagslength, dma_addr_t dma_addr) 1051 { 1052 SGESimple32_t *pSge = (SGESimple32_t *) pAddr; 1053 pSge->FlagsLength = cpu_to_le32(flagslength); 1054 pSge->Address = cpu_to_le32(dma_addr); 1055 } 1056 1057 /** 1058 * mpt_add_sge_64bit - Place a simple 64 bit SGE at address pAddr. 1059 * @pAddr: virtual address for SGE 1060 * @flagslength: SGE flags and data transfer length 1061 * @dma_addr: Physical address 1062 * 1063 * This routine places a MPT request frame back on the MPT adapter's 1064 * FreeQ. 1065 **/ 1066 static void 1067 mpt_add_sge_64bit(void *pAddr, u32 flagslength, dma_addr_t dma_addr) 1068 { 1069 SGESimple64_t *pSge = (SGESimple64_t *) pAddr; 1070 pSge->Address.Low = cpu_to_le32 1071 (lower_32_bits(dma_addr)); 1072 pSge->Address.High = cpu_to_le32 1073 (upper_32_bits(dma_addr)); 1074 pSge->FlagsLength = cpu_to_le32 1075 ((flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING)); 1076 } 1077 1078 /** 1079 * mpt_add_sge_64bit_1078 - Place a simple 64 bit SGE at address pAddr (1078 workaround). 1080 * @pAddr: virtual address for SGE 1081 * @flagslength: SGE flags and data transfer length 1082 * @dma_addr: Physical address 1083 * 1084 * This routine places a MPT request frame back on the MPT adapter's 1085 * FreeQ. 1086 **/ 1087 static void 1088 mpt_add_sge_64bit_1078(void *pAddr, u32 flagslength, dma_addr_t dma_addr) 1089 { 1090 SGESimple64_t *pSge = (SGESimple64_t *) pAddr; 1091 u32 tmp; 1092 1093 pSge->Address.Low = cpu_to_le32 1094 (lower_32_bits(dma_addr)); 1095 tmp = (u32)(upper_32_bits(dma_addr)); 1096 1097 /* 1098 * 1078 errata workaround for the 36GB limitation 1099 */ 1100 if ((((u64)dma_addr + MPI_SGE_LENGTH(flagslength)) >> 32) == 9) { 1101 flagslength |= 1102 MPI_SGE_SET_FLAGS(MPI_SGE_FLAGS_LOCAL_ADDRESS); 1103 tmp |= (1<<31); 1104 if (mpt_debug_level & MPT_DEBUG_36GB_MEM) 1105 printk(KERN_DEBUG "1078 P0M2 addressing for " 1106 "addr = 0x%llx len = %d\n", 1107 (unsigned long long)dma_addr, 1108 MPI_SGE_LENGTH(flagslength)); 1109 } 1110 1111 pSge->Address.High = cpu_to_le32(tmp); 1112 pSge->FlagsLength = cpu_to_le32( 1113 (flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING)); 1114 } 1115 1116 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1117 /** 1118 * mpt_add_chain - Place a 32 bit chain SGE at address pAddr. 1119 * @pAddr: virtual address for SGE 1120 * @next: nextChainOffset value (u32's) 1121 * @length: length of next SGL segment 1122 * @dma_addr: Physical address 1123 * 1124 */ 1125 static void 1126 mpt_add_chain(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr) 1127 { 1128 SGEChain32_t *pChain = (SGEChain32_t *) pAddr; 1129 1130 pChain->Length = cpu_to_le16(length); 1131 pChain->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT; 1132 pChain->NextChainOffset = next; 1133 pChain->Address = cpu_to_le32(dma_addr); 1134 } 1135 1136 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1137 /** 1138 * mpt_add_chain_64bit - Place a 64 bit chain SGE at address pAddr. 1139 * @pAddr: virtual address for SGE 1140 * @next: nextChainOffset value (u32's) 1141 * @length: length of next SGL segment 1142 * @dma_addr: Physical address 1143 * 1144 */ 1145 static void 1146 mpt_add_chain_64bit(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr) 1147 { 1148 SGEChain64_t *pChain = (SGEChain64_t *) pAddr; 1149 u32 tmp = dma_addr & 0xFFFFFFFF; 1150 1151 pChain->Length = cpu_to_le16(length); 1152 pChain->Flags = (MPI_SGE_FLAGS_CHAIN_ELEMENT | 1153 MPI_SGE_FLAGS_64_BIT_ADDRESSING); 1154 1155 pChain->NextChainOffset = next; 1156 1157 pChain->Address.Low = cpu_to_le32(tmp); 1158 tmp = (u32)(upper_32_bits(dma_addr)); 1159 pChain->Address.High = cpu_to_le32(tmp); 1160 } 1161 1162 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1163 /** 1164 * mpt_send_handshake_request - Send MPT request via doorbell handshake method. 1165 * @cb_idx: Handle of registered MPT protocol driver 1166 * @ioc: Pointer to MPT adapter structure 1167 * @reqBytes: Size of the request in bytes 1168 * @req: Pointer to MPT request frame 1169 * @sleepFlag: Use schedule if CAN_SLEEP else use udelay. 1170 * 1171 * This routine is used exclusively to send MptScsiTaskMgmt 1172 * requests since they are required to be sent via doorbell handshake. 1173 * 1174 * NOTE: It is the callers responsibility to byte-swap fields in the 1175 * request which are greater than 1 byte in size. 1176 * 1177 * Returns 0 for success, non-zero for failure. 1178 */ 1179 int 1180 mpt_send_handshake_request(u8 cb_idx, MPT_ADAPTER *ioc, int reqBytes, u32 *req, int sleepFlag) 1181 { 1182 int r = 0; 1183 u8 *req_as_bytes; 1184 int ii; 1185 1186 /* State is known to be good upon entering 1187 * this function so issue the bus reset 1188 * request. 1189 */ 1190 1191 /* 1192 * Emulate what mpt_put_msg_frame() does /wrt to sanity 1193 * setting cb_idx/req_idx. But ONLY if this request 1194 * is in proper (pre-alloc'd) request buffer range... 1195 */ 1196 ii = MFPTR_2_MPT_INDEX(ioc,(MPT_FRAME_HDR*)req); 1197 if (reqBytes >= 12 && ii >= 0 && ii < ioc->req_depth) { 1198 MPT_FRAME_HDR *mf = (MPT_FRAME_HDR*)req; 1199 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(ii); 1200 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; 1201 } 1202 1203 /* Make sure there are no doorbells */ 1204 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1205 1206 CHIPREG_WRITE32(&ioc->chip->Doorbell, 1207 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) | 1208 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT))); 1209 1210 /* Wait for IOC doorbell int */ 1211 if ((ii = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) { 1212 return ii; 1213 } 1214 1215 /* Read doorbell and check for active bit */ 1216 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE)) 1217 return -5; 1218 1219 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_send_handshake_request start, WaitCnt=%d\n", 1220 ioc->name, ii)); 1221 1222 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1223 1224 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) { 1225 return -2; 1226 } 1227 1228 /* Send request via doorbell handshake */ 1229 req_as_bytes = (u8 *) req; 1230 for (ii = 0; ii < reqBytes/4; ii++) { 1231 u32 word; 1232 1233 word = ((req_as_bytes[(ii*4) + 0] << 0) | 1234 (req_as_bytes[(ii*4) + 1] << 8) | 1235 (req_as_bytes[(ii*4) + 2] << 16) | 1236 (req_as_bytes[(ii*4) + 3] << 24)); 1237 CHIPREG_WRITE32(&ioc->chip->Doorbell, word); 1238 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) { 1239 r = -3; 1240 break; 1241 } 1242 } 1243 1244 if (r >= 0 && WaitForDoorbellInt(ioc, 10, sleepFlag) >= 0) 1245 r = 0; 1246 else 1247 r = -4; 1248 1249 /* Make sure there are no doorbells */ 1250 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1251 1252 return r; 1253 } 1254 1255 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1256 /** 1257 * mpt_host_page_access_control - control the IOC's Host Page Buffer access 1258 * @ioc: Pointer to MPT adapter structure 1259 * @access_control_value: define bits below 1260 * @sleepFlag: Specifies whether the process can sleep 1261 * 1262 * Provides mechanism for the host driver to control the IOC's 1263 * Host Page Buffer access. 1264 * 1265 * Access Control Value - bits[15:12] 1266 * 0h Reserved 1267 * 1h Enable Access { MPI_DB_HPBAC_ENABLE_ACCESS } 1268 * 2h Disable Access { MPI_DB_HPBAC_DISABLE_ACCESS } 1269 * 3h Free Buffer { MPI_DB_HPBAC_FREE_BUFFER } 1270 * 1271 * Returns 0 for success, non-zero for failure. 1272 */ 1273 1274 static int 1275 mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag) 1276 { 1277 /* return if in use */ 1278 if (CHIPREG_READ32(&ioc->chip->Doorbell) 1279 & MPI_DOORBELL_ACTIVE) 1280 return -1; 1281 1282 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1283 1284 CHIPREG_WRITE32(&ioc->chip->Doorbell, 1285 ((MPI_FUNCTION_HOST_PAGEBUF_ACCESS_CONTROL 1286 <<MPI_DOORBELL_FUNCTION_SHIFT) | 1287 (access_control_value<<12))); 1288 1289 /* Wait for IOC to clear Doorbell Status bit */ 1290 if (WaitForDoorbellAck(ioc, 5, sleepFlag) < 0) 1291 return -2; 1292 else 1293 return 0; 1294 } 1295 1296 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1297 /** 1298 * mpt_host_page_alloc - allocate system memory for the fw 1299 * @ioc: Pointer to pointer to IOC adapter 1300 * @ioc_init: Pointer to ioc init config page 1301 * 1302 * If we already allocated memory in past, then resend the same pointer. 1303 * Returns 0 for success, non-zero for failure. 1304 */ 1305 static int 1306 mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init) 1307 { 1308 char *psge; 1309 int flags_length; 1310 u32 host_page_buffer_sz=0; 1311 1312 if(!ioc->HostPageBuffer) { 1313 1314 host_page_buffer_sz = 1315 le32_to_cpu(ioc->facts.HostPageBufferSGE.FlagsLength) & 0xFFFFFF; 1316 1317 if(!host_page_buffer_sz) 1318 return 0; /* fw doesn't need any host buffers */ 1319 1320 /* spin till we get enough memory */ 1321 while (host_page_buffer_sz > 0) { 1322 ioc->HostPageBuffer = 1323 dma_alloc_coherent(&ioc->pcidev->dev, 1324 host_page_buffer_sz, 1325 &ioc->HostPageBuffer_dma, 1326 GFP_KERNEL); 1327 if (ioc->HostPageBuffer) { 1328 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 1329 "host_page_buffer @ %p, dma @ %x, sz=%d bytes\n", 1330 ioc->name, ioc->HostPageBuffer, 1331 (u32)ioc->HostPageBuffer_dma, 1332 host_page_buffer_sz)); 1333 ioc->alloc_total += host_page_buffer_sz; 1334 ioc->HostPageBuffer_sz = host_page_buffer_sz; 1335 break; 1336 } 1337 1338 host_page_buffer_sz -= (4*1024); 1339 } 1340 } 1341 1342 if(!ioc->HostPageBuffer) { 1343 printk(MYIOC_s_ERR_FMT 1344 "Failed to alloc memory for host_page_buffer!\n", 1345 ioc->name); 1346 return -999; 1347 } 1348 1349 psge = (char *)&ioc_init->HostPageBufferSGE; 1350 flags_length = MPI_SGE_FLAGS_SIMPLE_ELEMENT | 1351 MPI_SGE_FLAGS_SYSTEM_ADDRESS | 1352 MPI_SGE_FLAGS_HOST_TO_IOC | 1353 MPI_SGE_FLAGS_END_OF_BUFFER; 1354 flags_length = flags_length << MPI_SGE_FLAGS_SHIFT; 1355 flags_length |= ioc->HostPageBuffer_sz; 1356 ioc->add_sge(psge, flags_length, ioc->HostPageBuffer_dma); 1357 ioc->facts.HostPageBufferSGE = ioc_init->HostPageBufferSGE; 1358 1359 return 0; 1360 } 1361 1362 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1363 /** 1364 * mpt_verify_adapter - Given IOC identifier, set pointer to its adapter structure. 1365 * @iocid: IOC unique identifier (integer) 1366 * @iocpp: Pointer to pointer to IOC adapter 1367 * 1368 * Given a unique IOC identifier, set pointer to the associated MPT 1369 * adapter structure. 1370 * 1371 * Returns iocid and sets iocpp if iocid is found. 1372 * Returns -1 if iocid is not found. 1373 */ 1374 int 1375 mpt_verify_adapter(int iocid, MPT_ADAPTER **iocpp) 1376 { 1377 MPT_ADAPTER *ioc; 1378 1379 list_for_each_entry(ioc,&ioc_list,list) { 1380 if (ioc->id == iocid) { 1381 *iocpp =ioc; 1382 return iocid; 1383 } 1384 } 1385 1386 *iocpp = NULL; 1387 return -1; 1388 } 1389 1390 /** 1391 * mpt_get_product_name - returns product string 1392 * @vendor: pci vendor id 1393 * @device: pci device id 1394 * @revision: pci revision id 1395 * 1396 * Returns product string displayed when driver loads, 1397 * in /proc/mpt/summary and /sysfs/class/scsi_host/host<X>/version_product 1398 * 1399 **/ 1400 static const char* 1401 mpt_get_product_name(u16 vendor, u16 device, u8 revision) 1402 { 1403 char *product_str = NULL; 1404 1405 if (vendor == PCI_VENDOR_ID_BROCADE) { 1406 switch (device) 1407 { 1408 case MPI_MANUFACTPAGE_DEVICEID_FC949E: 1409 switch (revision) 1410 { 1411 case 0x00: 1412 product_str = "BRE040 A0"; 1413 break; 1414 case 0x01: 1415 product_str = "BRE040 A1"; 1416 break; 1417 default: 1418 product_str = "BRE040"; 1419 break; 1420 } 1421 break; 1422 } 1423 goto out; 1424 } 1425 1426 switch (device) 1427 { 1428 case MPI_MANUFACTPAGE_DEVICEID_FC909: 1429 product_str = "LSIFC909 B1"; 1430 break; 1431 case MPI_MANUFACTPAGE_DEVICEID_FC919: 1432 product_str = "LSIFC919 B0"; 1433 break; 1434 case MPI_MANUFACTPAGE_DEVICEID_FC929: 1435 product_str = "LSIFC929 B0"; 1436 break; 1437 case MPI_MANUFACTPAGE_DEVICEID_FC919X: 1438 if (revision < 0x80) 1439 product_str = "LSIFC919X A0"; 1440 else 1441 product_str = "LSIFC919XL A1"; 1442 break; 1443 case MPI_MANUFACTPAGE_DEVICEID_FC929X: 1444 if (revision < 0x80) 1445 product_str = "LSIFC929X A0"; 1446 else 1447 product_str = "LSIFC929XL A1"; 1448 break; 1449 case MPI_MANUFACTPAGE_DEVICEID_FC939X: 1450 product_str = "LSIFC939X A1"; 1451 break; 1452 case MPI_MANUFACTPAGE_DEVICEID_FC949X: 1453 product_str = "LSIFC949X A1"; 1454 break; 1455 case MPI_MANUFACTPAGE_DEVICEID_FC949E: 1456 switch (revision) 1457 { 1458 case 0x00: 1459 product_str = "LSIFC949E A0"; 1460 break; 1461 case 0x01: 1462 product_str = "LSIFC949E A1"; 1463 break; 1464 default: 1465 product_str = "LSIFC949E"; 1466 break; 1467 } 1468 break; 1469 case MPI_MANUFACTPAGE_DEVID_53C1030: 1470 switch (revision) 1471 { 1472 case 0x00: 1473 product_str = "LSI53C1030 A0"; 1474 break; 1475 case 0x01: 1476 product_str = "LSI53C1030 B0"; 1477 break; 1478 case 0x03: 1479 product_str = "LSI53C1030 B1"; 1480 break; 1481 case 0x07: 1482 product_str = "LSI53C1030 B2"; 1483 break; 1484 case 0x08: 1485 product_str = "LSI53C1030 C0"; 1486 break; 1487 case 0x80: 1488 product_str = "LSI53C1030T A0"; 1489 break; 1490 case 0x83: 1491 product_str = "LSI53C1030T A2"; 1492 break; 1493 case 0x87: 1494 product_str = "LSI53C1030T A3"; 1495 break; 1496 case 0xc1: 1497 product_str = "LSI53C1020A A1"; 1498 break; 1499 default: 1500 product_str = "LSI53C1030"; 1501 break; 1502 } 1503 break; 1504 case MPI_MANUFACTPAGE_DEVID_1030_53C1035: 1505 switch (revision) 1506 { 1507 case 0x03: 1508 product_str = "LSI53C1035 A2"; 1509 break; 1510 case 0x04: 1511 product_str = "LSI53C1035 B0"; 1512 break; 1513 default: 1514 product_str = "LSI53C1035"; 1515 break; 1516 } 1517 break; 1518 case MPI_MANUFACTPAGE_DEVID_SAS1064: 1519 switch (revision) 1520 { 1521 case 0x00: 1522 product_str = "LSISAS1064 A1"; 1523 break; 1524 case 0x01: 1525 product_str = "LSISAS1064 A2"; 1526 break; 1527 case 0x02: 1528 product_str = "LSISAS1064 A3"; 1529 break; 1530 case 0x03: 1531 product_str = "LSISAS1064 A4"; 1532 break; 1533 default: 1534 product_str = "LSISAS1064"; 1535 break; 1536 } 1537 break; 1538 case MPI_MANUFACTPAGE_DEVID_SAS1064E: 1539 switch (revision) 1540 { 1541 case 0x00: 1542 product_str = "LSISAS1064E A0"; 1543 break; 1544 case 0x01: 1545 product_str = "LSISAS1064E B0"; 1546 break; 1547 case 0x02: 1548 product_str = "LSISAS1064E B1"; 1549 break; 1550 case 0x04: 1551 product_str = "LSISAS1064E B2"; 1552 break; 1553 case 0x08: 1554 product_str = "LSISAS1064E B3"; 1555 break; 1556 default: 1557 product_str = "LSISAS1064E"; 1558 break; 1559 } 1560 break; 1561 case MPI_MANUFACTPAGE_DEVID_SAS1068: 1562 switch (revision) 1563 { 1564 case 0x00: 1565 product_str = "LSISAS1068 A0"; 1566 break; 1567 case 0x01: 1568 product_str = "LSISAS1068 B0"; 1569 break; 1570 case 0x02: 1571 product_str = "LSISAS1068 B1"; 1572 break; 1573 default: 1574 product_str = "LSISAS1068"; 1575 break; 1576 } 1577 break; 1578 case MPI_MANUFACTPAGE_DEVID_SAS1068E: 1579 switch (revision) 1580 { 1581 case 0x00: 1582 product_str = "LSISAS1068E A0"; 1583 break; 1584 case 0x01: 1585 product_str = "LSISAS1068E B0"; 1586 break; 1587 case 0x02: 1588 product_str = "LSISAS1068E B1"; 1589 break; 1590 case 0x04: 1591 product_str = "LSISAS1068E B2"; 1592 break; 1593 case 0x08: 1594 product_str = "LSISAS1068E B3"; 1595 break; 1596 default: 1597 product_str = "LSISAS1068E"; 1598 break; 1599 } 1600 break; 1601 case MPI_MANUFACTPAGE_DEVID_SAS1078: 1602 switch (revision) 1603 { 1604 case 0x00: 1605 product_str = "LSISAS1078 A0"; 1606 break; 1607 case 0x01: 1608 product_str = "LSISAS1078 B0"; 1609 break; 1610 case 0x02: 1611 product_str = "LSISAS1078 C0"; 1612 break; 1613 case 0x03: 1614 product_str = "LSISAS1078 C1"; 1615 break; 1616 case 0x04: 1617 product_str = "LSISAS1078 C2"; 1618 break; 1619 default: 1620 product_str = "LSISAS1078"; 1621 break; 1622 } 1623 break; 1624 } 1625 1626 out: 1627 return product_str; 1628 } 1629 1630 /** 1631 * mpt_mapresources - map in memory mapped io 1632 * @ioc: Pointer to pointer to IOC adapter 1633 * 1634 **/ 1635 static int 1636 mpt_mapresources(MPT_ADAPTER *ioc) 1637 { 1638 u8 __iomem *mem; 1639 int ii; 1640 resource_size_t mem_phys; 1641 unsigned long port; 1642 u32 msize; 1643 u32 psize; 1644 int r = -ENODEV; 1645 struct pci_dev *pdev; 1646 1647 pdev = ioc->pcidev; 1648 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM); 1649 if (pci_enable_device_mem(pdev)) { 1650 printk(MYIOC_s_ERR_FMT "pci_enable_device_mem() " 1651 "failed\n", ioc->name); 1652 return r; 1653 } 1654 if (pci_request_selected_regions(pdev, ioc->bars, "mpt")) { 1655 printk(MYIOC_s_ERR_FMT "pci_request_selected_regions() with " 1656 "MEM failed\n", ioc->name); 1657 goto out_pci_disable_device; 1658 } 1659 1660 if (sizeof(dma_addr_t) > 4) { 1661 const uint64_t required_mask = dma_get_required_mask 1662 (&pdev->dev); 1663 if (required_mask > DMA_BIT_MASK(32) 1664 && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) 1665 && !pci_set_consistent_dma_mask(pdev, 1666 DMA_BIT_MASK(64))) { 1667 ioc->dma_mask = DMA_BIT_MASK(64); 1668 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 1669 ": 64 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", 1670 ioc->name)); 1671 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) 1672 && !pci_set_consistent_dma_mask(pdev, 1673 DMA_BIT_MASK(32))) { 1674 ioc->dma_mask = DMA_BIT_MASK(32); 1675 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 1676 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", 1677 ioc->name)); 1678 } else { 1679 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n", 1680 ioc->name, pci_name(pdev)); 1681 goto out_pci_release_region; 1682 } 1683 } else { 1684 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) 1685 && !pci_set_consistent_dma_mask(pdev, 1686 DMA_BIT_MASK(32))) { 1687 ioc->dma_mask = DMA_BIT_MASK(32); 1688 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 1689 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n", 1690 ioc->name)); 1691 } else { 1692 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n", 1693 ioc->name, pci_name(pdev)); 1694 goto out_pci_release_region; 1695 } 1696 } 1697 1698 mem_phys = msize = 0; 1699 port = psize = 0; 1700 for (ii = 0; ii < DEVICE_COUNT_RESOURCE; ii++) { 1701 if (pci_resource_flags(pdev, ii) & PCI_BASE_ADDRESS_SPACE_IO) { 1702 if (psize) 1703 continue; 1704 /* Get I/O space! */ 1705 port = pci_resource_start(pdev, ii); 1706 psize = pci_resource_len(pdev, ii); 1707 } else { 1708 if (msize) 1709 continue; 1710 /* Get memmap */ 1711 mem_phys = pci_resource_start(pdev, ii); 1712 msize = pci_resource_len(pdev, ii); 1713 } 1714 } 1715 ioc->mem_size = msize; 1716 1717 mem = NULL; 1718 /* Get logical ptr for PciMem0 space */ 1719 /*mem = ioremap(mem_phys, msize);*/ 1720 mem = ioremap(mem_phys, msize); 1721 if (mem == NULL) { 1722 printk(MYIOC_s_ERR_FMT ": ERROR - Unable to map adapter" 1723 " memory!\n", ioc->name); 1724 r = -EINVAL; 1725 goto out_pci_release_region; 1726 } 1727 ioc->memmap = mem; 1728 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "mem = %p, mem_phys = %llx\n", 1729 ioc->name, mem, (unsigned long long)mem_phys)); 1730 1731 ioc->mem_phys = mem_phys; 1732 ioc->chip = (SYSIF_REGS __iomem *)mem; 1733 1734 /* Save Port IO values in case we need to do downloadboot */ 1735 ioc->pio_mem_phys = port; 1736 ioc->pio_chip = (SYSIF_REGS __iomem *)port; 1737 1738 return 0; 1739 1740 out_pci_release_region: 1741 pci_release_selected_regions(pdev, ioc->bars); 1742 out_pci_disable_device: 1743 pci_disable_device(pdev); 1744 return r; 1745 } 1746 1747 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 1748 /** 1749 * mpt_attach - Install a PCI intelligent MPT adapter. 1750 * @pdev: Pointer to pci_dev structure 1751 * @id: PCI device ID information 1752 * 1753 * This routine performs all the steps necessary to bring the IOC of 1754 * a MPT adapter to a OPERATIONAL state. This includes registering 1755 * memory regions, registering the interrupt, and allocating request 1756 * and reply memory pools. 1757 * 1758 * This routine also pre-fetches the LAN MAC address of a Fibre Channel 1759 * MPT adapter. 1760 * 1761 * Returns 0 for success, non-zero for failure. 1762 * 1763 * TODO: Add support for polled controllers 1764 */ 1765 int 1766 mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id) 1767 { 1768 MPT_ADAPTER *ioc; 1769 u8 cb_idx; 1770 int r = -ENODEV; 1771 u8 pcixcmd; 1772 static int mpt_ids = 0; 1773 #ifdef CONFIG_PROC_FS 1774 struct proc_dir_entry *dent; 1775 #endif 1776 1777 ioc = kzalloc(sizeof(MPT_ADAPTER), GFP_KERNEL); 1778 if (ioc == NULL) { 1779 printk(KERN_ERR MYNAM ": ERROR - Insufficient memory to add adapter!\n"); 1780 return -ENOMEM; 1781 } 1782 1783 ioc->id = mpt_ids++; 1784 sprintf(ioc->name, "ioc%d", ioc->id); 1785 dinitprintk(ioc, printk(KERN_WARNING MYNAM ": mpt_adapter_install\n")); 1786 1787 /* 1788 * set initial debug level 1789 * (refer to mptdebug.h) 1790 * 1791 */ 1792 ioc->debug_level = mpt_debug_level; 1793 if (mpt_debug_level) 1794 printk(KERN_INFO "mpt_debug_level=%xh\n", mpt_debug_level); 1795 1796 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": mpt_adapter_install\n", ioc->name)); 1797 1798 ioc->pcidev = pdev; 1799 if (mpt_mapresources(ioc)) { 1800 goto out_free_ioc; 1801 } 1802 1803 /* 1804 * Setting up proper handlers for scatter gather handling 1805 */ 1806 if (ioc->dma_mask == DMA_BIT_MASK(64)) { 1807 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) 1808 ioc->add_sge = &mpt_add_sge_64bit_1078; 1809 else 1810 ioc->add_sge = &mpt_add_sge_64bit; 1811 ioc->add_chain = &mpt_add_chain_64bit; 1812 ioc->sg_addr_size = 8; 1813 } else { 1814 ioc->add_sge = &mpt_add_sge; 1815 ioc->add_chain = &mpt_add_chain; 1816 ioc->sg_addr_size = 4; 1817 } 1818 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size; 1819 1820 ioc->alloc_total = sizeof(MPT_ADAPTER); 1821 ioc->req_sz = MPT_DEFAULT_FRAME_SIZE; /* avoid div by zero! */ 1822 ioc->reply_sz = MPT_REPLY_FRAME_SIZE; 1823 1824 1825 spin_lock_init(&ioc->taskmgmt_lock); 1826 mutex_init(&ioc->internal_cmds.mutex); 1827 init_completion(&ioc->internal_cmds.done); 1828 mutex_init(&ioc->mptbase_cmds.mutex); 1829 init_completion(&ioc->mptbase_cmds.done); 1830 mutex_init(&ioc->taskmgmt_cmds.mutex); 1831 init_completion(&ioc->taskmgmt_cmds.done); 1832 1833 /* Initialize the event logging. 1834 */ 1835 ioc->eventTypes = 0; /* None */ 1836 ioc->eventContext = 0; 1837 ioc->eventLogSize = 0; 1838 ioc->events = NULL; 1839 1840 #ifdef MFCNT 1841 ioc->mfcnt = 0; 1842 #endif 1843 1844 ioc->sh = NULL; 1845 ioc->cached_fw = NULL; 1846 1847 /* Initialize SCSI Config Data structure 1848 */ 1849 memset(&ioc->spi_data, 0, sizeof(SpiCfgData)); 1850 1851 /* Initialize the fc rport list head. 1852 */ 1853 INIT_LIST_HEAD(&ioc->fc_rports); 1854 1855 /* Find lookup slot. */ 1856 INIT_LIST_HEAD(&ioc->list); 1857 1858 1859 /* Initialize workqueue */ 1860 INIT_DELAYED_WORK(&ioc->fault_reset_work, mpt_fault_reset_work); 1861 1862 snprintf(ioc->reset_work_q_name, MPT_KOBJ_NAME_LEN, 1863 "mpt_poll_%d", ioc->id); 1864 ioc->reset_work_q = alloc_workqueue(ioc->reset_work_q_name, 1865 WQ_MEM_RECLAIM, 0); 1866 if (!ioc->reset_work_q) { 1867 printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n", 1868 ioc->name); 1869 r = -ENOMEM; 1870 goto out_unmap_resources; 1871 } 1872 1873 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "facts @ %p, pfacts[0] @ %p\n", 1874 ioc->name, &ioc->facts, &ioc->pfacts[0])); 1875 1876 ioc->prod_name = mpt_get_product_name(pdev->vendor, pdev->device, 1877 pdev->revision); 1878 1879 switch (pdev->device) 1880 { 1881 case MPI_MANUFACTPAGE_DEVICEID_FC939X: 1882 case MPI_MANUFACTPAGE_DEVICEID_FC949X: 1883 ioc->errata_flag_1064 = 1; 1884 fallthrough; 1885 case MPI_MANUFACTPAGE_DEVICEID_FC909: 1886 case MPI_MANUFACTPAGE_DEVICEID_FC929: 1887 case MPI_MANUFACTPAGE_DEVICEID_FC919: 1888 case MPI_MANUFACTPAGE_DEVICEID_FC949E: 1889 ioc->bus_type = FC; 1890 break; 1891 1892 case MPI_MANUFACTPAGE_DEVICEID_FC929X: 1893 if (pdev->revision < XL_929) { 1894 /* 929X Chip Fix. Set Split transactions level 1895 * for PCIX. Set MOST bits to zero. 1896 */ 1897 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1898 pcixcmd &= 0x8F; 1899 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1900 } else { 1901 /* 929XL Chip Fix. Set MMRBC to 0x08. 1902 */ 1903 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1904 pcixcmd |= 0x08; 1905 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1906 } 1907 ioc->bus_type = FC; 1908 break; 1909 1910 case MPI_MANUFACTPAGE_DEVICEID_FC919X: 1911 /* 919X Chip Fix. Set Split transactions level 1912 * for PCIX. Set MOST bits to zero. 1913 */ 1914 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1915 pcixcmd &= 0x8F; 1916 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1917 ioc->bus_type = FC; 1918 break; 1919 1920 case MPI_MANUFACTPAGE_DEVID_53C1030: 1921 /* 1030 Chip Fix. Disable Split transactions 1922 * for PCIX. Set MOST bits to zero if Rev < C0( = 8). 1923 */ 1924 if (pdev->revision < C0_1030) { 1925 pci_read_config_byte(pdev, 0x6a, &pcixcmd); 1926 pcixcmd &= 0x8F; 1927 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1928 } 1929 fallthrough; 1930 1931 case MPI_MANUFACTPAGE_DEVID_1030_53C1035: 1932 ioc->bus_type = SPI; 1933 break; 1934 1935 case MPI_MANUFACTPAGE_DEVID_SAS1064: 1936 case MPI_MANUFACTPAGE_DEVID_SAS1068: 1937 ioc->errata_flag_1064 = 1; 1938 ioc->bus_type = SAS; 1939 break; 1940 1941 case MPI_MANUFACTPAGE_DEVID_SAS1064E: 1942 case MPI_MANUFACTPAGE_DEVID_SAS1068E: 1943 case MPI_MANUFACTPAGE_DEVID_SAS1078: 1944 ioc->bus_type = SAS; 1945 break; 1946 } 1947 1948 1949 switch (ioc->bus_type) { 1950 1951 case SAS: 1952 ioc->msi_enable = mpt_msi_enable_sas; 1953 break; 1954 1955 case SPI: 1956 ioc->msi_enable = mpt_msi_enable_spi; 1957 break; 1958 1959 case FC: 1960 ioc->msi_enable = mpt_msi_enable_fc; 1961 break; 1962 1963 default: 1964 ioc->msi_enable = 0; 1965 break; 1966 } 1967 1968 ioc->fw_events_off = 1; 1969 1970 if (ioc->errata_flag_1064) 1971 pci_disable_io_access(pdev); 1972 1973 spin_lock_init(&ioc->FreeQlock); 1974 1975 /* Disable all! */ 1976 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 1977 ioc->active = 0; 1978 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 1979 1980 /* Set IOC ptr in the pcidev's driver data. */ 1981 pci_set_drvdata(ioc->pcidev, ioc); 1982 1983 /* Set lookup ptr. */ 1984 list_add_tail(&ioc->list, &ioc_list); 1985 1986 /* Check for "bound ports" (929, 929X, 1030, 1035) to reduce redundant resets. 1987 */ 1988 mpt_detect_bound_ports(ioc, pdev); 1989 1990 INIT_LIST_HEAD(&ioc->fw_event_list); 1991 spin_lock_init(&ioc->fw_event_lock); 1992 snprintf(ioc->fw_event_q_name, MPT_KOBJ_NAME_LEN, "mpt/%d", ioc->id); 1993 ioc->fw_event_q = alloc_workqueue(ioc->fw_event_q_name, 1994 WQ_MEM_RECLAIM, 0); 1995 if (!ioc->fw_event_q) { 1996 printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n", 1997 ioc->name); 1998 r = -ENOMEM; 1999 goto out_remove_ioc; 2000 } 2001 2002 if ((r = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP, 2003 CAN_SLEEP)) != 0){ 2004 printk(MYIOC_s_ERR_FMT "didn't initialize properly! (%d)\n", 2005 ioc->name, r); 2006 2007 destroy_workqueue(ioc->fw_event_q); 2008 ioc->fw_event_q = NULL; 2009 2010 list_del(&ioc->list); 2011 if (ioc->alt_ioc) 2012 ioc->alt_ioc->alt_ioc = NULL; 2013 iounmap(ioc->memmap); 2014 if (pci_is_enabled(pdev)) 2015 pci_disable_device(pdev); 2016 if (r != -5) 2017 pci_release_selected_regions(pdev, ioc->bars); 2018 2019 destroy_workqueue(ioc->reset_work_q); 2020 ioc->reset_work_q = NULL; 2021 2022 kfree(ioc); 2023 return r; 2024 } 2025 2026 /* call per device driver probe entry point */ 2027 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) { 2028 if(MptDeviceDriverHandlers[cb_idx] && 2029 MptDeviceDriverHandlers[cb_idx]->probe) { 2030 MptDeviceDriverHandlers[cb_idx]->probe(pdev); 2031 } 2032 } 2033 2034 #ifdef CONFIG_PROC_FS 2035 /* 2036 * Create "/proc/mpt/iocN" subdirectory entry for each MPT adapter. 2037 */ 2038 dent = proc_mkdir(ioc->name, mpt_proc_root_dir); 2039 if (dent) { 2040 proc_create_single_data("info", S_IRUGO, dent, 2041 mpt_iocinfo_proc_show, ioc); 2042 proc_create_single_data("summary", S_IRUGO, dent, 2043 mpt_summary_proc_show, ioc); 2044 } 2045 #endif 2046 2047 if (!ioc->alt_ioc) 2048 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work, 2049 msecs_to_jiffies(MPT_POLLING_INTERVAL)); 2050 2051 return 0; 2052 2053 out_remove_ioc: 2054 list_del(&ioc->list); 2055 if (ioc->alt_ioc) 2056 ioc->alt_ioc->alt_ioc = NULL; 2057 2058 destroy_workqueue(ioc->reset_work_q); 2059 ioc->reset_work_q = NULL; 2060 2061 out_unmap_resources: 2062 iounmap(ioc->memmap); 2063 pci_disable_device(pdev); 2064 pci_release_selected_regions(pdev, ioc->bars); 2065 2066 out_free_ioc: 2067 kfree(ioc); 2068 2069 return r; 2070 } 2071 2072 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2073 /** 2074 * mpt_detach - Remove a PCI intelligent MPT adapter. 2075 * @pdev: Pointer to pci_dev structure 2076 */ 2077 2078 void 2079 mpt_detach(struct pci_dev *pdev) 2080 { 2081 MPT_ADAPTER *ioc = pci_get_drvdata(pdev); 2082 char pname[64]; 2083 u8 cb_idx; 2084 unsigned long flags; 2085 struct workqueue_struct *wq; 2086 2087 /* 2088 * Stop polling ioc for fault condition 2089 */ 2090 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 2091 wq = ioc->reset_work_q; 2092 ioc->reset_work_q = NULL; 2093 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 2094 cancel_delayed_work(&ioc->fault_reset_work); 2095 destroy_workqueue(wq); 2096 2097 spin_lock_irqsave(&ioc->fw_event_lock, flags); 2098 wq = ioc->fw_event_q; 2099 ioc->fw_event_q = NULL; 2100 spin_unlock_irqrestore(&ioc->fw_event_lock, flags); 2101 destroy_workqueue(wq); 2102 2103 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/summary", ioc->name); 2104 remove_proc_entry(pname, NULL); 2105 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/info", ioc->name); 2106 remove_proc_entry(pname, NULL); 2107 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s", ioc->name); 2108 remove_proc_entry(pname, NULL); 2109 2110 /* call per device driver remove entry point */ 2111 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) { 2112 if(MptDeviceDriverHandlers[cb_idx] && 2113 MptDeviceDriverHandlers[cb_idx]->remove) { 2114 MptDeviceDriverHandlers[cb_idx]->remove(pdev); 2115 } 2116 } 2117 2118 /* Disable interrupts! */ 2119 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 2120 2121 ioc->active = 0; 2122 synchronize_irq(pdev->irq); 2123 2124 /* Clear any lingering interrupt */ 2125 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 2126 2127 CHIPREG_READ32(&ioc->chip->IntStatus); 2128 2129 mpt_adapter_dispose(ioc); 2130 2131 } 2132 2133 /************************************************************************** 2134 * Power Management 2135 */ 2136 #ifdef CONFIG_PM 2137 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2138 /** 2139 * mpt_suspend - Fusion MPT base driver suspend routine. 2140 * @pdev: Pointer to pci_dev structure 2141 * @state: new state to enter 2142 */ 2143 int 2144 mpt_suspend(struct pci_dev *pdev, pm_message_t state) 2145 { 2146 u32 device_state; 2147 MPT_ADAPTER *ioc = pci_get_drvdata(pdev); 2148 2149 device_state = pci_choose_state(pdev, state); 2150 printk(MYIOC_s_INFO_FMT "pci-suspend: pdev=0x%p, slot=%s, Entering " 2151 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev), 2152 device_state); 2153 2154 /* put ioc into READY_STATE */ 2155 if (SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, CAN_SLEEP)) { 2156 printk(MYIOC_s_ERR_FMT 2157 "pci-suspend: IOC msg unit reset failed!\n", ioc->name); 2158 } 2159 2160 /* disable interrupts */ 2161 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 2162 ioc->active = 0; 2163 2164 /* Clear any lingering interrupt */ 2165 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 2166 2167 free_irq(ioc->pci_irq, ioc); 2168 if (ioc->msi_enable) 2169 pci_disable_msi(ioc->pcidev); 2170 ioc->pci_irq = -1; 2171 pci_save_state(pdev); 2172 pci_disable_device(pdev); 2173 pci_release_selected_regions(pdev, ioc->bars); 2174 pci_set_power_state(pdev, device_state); 2175 return 0; 2176 } 2177 2178 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2179 /** 2180 * mpt_resume - Fusion MPT base driver resume routine. 2181 * @pdev: Pointer to pci_dev structure 2182 */ 2183 int 2184 mpt_resume(struct pci_dev *pdev) 2185 { 2186 MPT_ADAPTER *ioc = pci_get_drvdata(pdev); 2187 u32 device_state = pdev->current_state; 2188 int recovery_state; 2189 int err; 2190 2191 printk(MYIOC_s_INFO_FMT "pci-resume: pdev=0x%p, slot=%s, Previous " 2192 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev), 2193 device_state); 2194 2195 pci_set_power_state(pdev, PCI_D0); 2196 pci_enable_wake(pdev, PCI_D0, 0); 2197 pci_restore_state(pdev); 2198 ioc->pcidev = pdev; 2199 err = mpt_mapresources(ioc); 2200 if (err) 2201 return err; 2202 2203 if (ioc->dma_mask == DMA_BIT_MASK(64)) { 2204 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) 2205 ioc->add_sge = &mpt_add_sge_64bit_1078; 2206 else 2207 ioc->add_sge = &mpt_add_sge_64bit; 2208 ioc->add_chain = &mpt_add_chain_64bit; 2209 ioc->sg_addr_size = 8; 2210 } else { 2211 2212 ioc->add_sge = &mpt_add_sge; 2213 ioc->add_chain = &mpt_add_chain; 2214 ioc->sg_addr_size = 4; 2215 } 2216 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size; 2217 2218 printk(MYIOC_s_INFO_FMT "pci-resume: ioc-state=0x%x,doorbell=0x%x\n", 2219 ioc->name, (mpt_GetIocState(ioc, 1) >> MPI_IOC_STATE_SHIFT), 2220 CHIPREG_READ32(&ioc->chip->Doorbell)); 2221 2222 /* 2223 * Errata workaround for SAS pci express: 2224 * Upon returning to the D0 state, the contents of the doorbell will be 2225 * stale data, and this will incorrectly signal to the host driver that 2226 * the firmware is ready to process mpt commands. The workaround is 2227 * to issue a diagnostic reset. 2228 */ 2229 if (ioc->bus_type == SAS && (pdev->device == 2230 MPI_MANUFACTPAGE_DEVID_SAS1068E || pdev->device == 2231 MPI_MANUFACTPAGE_DEVID_SAS1064E)) { 2232 if (KickStart(ioc, 1, CAN_SLEEP) < 0) { 2233 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover\n", 2234 ioc->name); 2235 goto out; 2236 } 2237 } 2238 2239 /* bring ioc to operational state */ 2240 printk(MYIOC_s_INFO_FMT "Sending mpt_do_ioc_recovery\n", ioc->name); 2241 recovery_state = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP, 2242 CAN_SLEEP); 2243 if (recovery_state != 0) 2244 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover, " 2245 "error:[%x]\n", ioc->name, recovery_state); 2246 else 2247 printk(MYIOC_s_INFO_FMT 2248 "pci-resume: success\n", ioc->name); 2249 out: 2250 return 0; 2251 2252 } 2253 #endif 2254 2255 static int 2256 mpt_signal_reset(u8 index, MPT_ADAPTER *ioc, int reset_phase) 2257 { 2258 if ((MptDriverClass[index] == MPTSPI_DRIVER && 2259 ioc->bus_type != SPI) || 2260 (MptDriverClass[index] == MPTFC_DRIVER && 2261 ioc->bus_type != FC) || 2262 (MptDriverClass[index] == MPTSAS_DRIVER && 2263 ioc->bus_type != SAS)) 2264 /* make sure we only call the relevant reset handler 2265 * for the bus */ 2266 return 0; 2267 return (MptResetHandlers[index])(ioc, reset_phase); 2268 } 2269 2270 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2271 /** 2272 * mpt_do_ioc_recovery - Initialize or recover MPT adapter. 2273 * @ioc: Pointer to MPT adapter structure 2274 * @reason: Event word / reason 2275 * @sleepFlag: Use schedule if CAN_SLEEP else use udelay. 2276 * 2277 * This routine performs all the steps necessary to bring the IOC 2278 * to a OPERATIONAL state. 2279 * 2280 * This routine also pre-fetches the LAN MAC address of a Fibre Channel 2281 * MPT adapter. 2282 * 2283 * Returns: 2284 * 0 for success 2285 * -1 if failed to get board READY 2286 * -2 if READY but IOCFacts Failed 2287 * -3 if READY but PrimeIOCFifos Failed 2288 * -4 if READY but IOCInit Failed 2289 * -5 if failed to enable_device and/or request_selected_regions 2290 * -6 if failed to upload firmware 2291 */ 2292 static int 2293 mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag) 2294 { 2295 int hard_reset_done = 0; 2296 int alt_ioc_ready = 0; 2297 int hard; 2298 int rc=0; 2299 int ii; 2300 int ret = 0; 2301 int reset_alt_ioc_active = 0; 2302 int irq_allocated = 0; 2303 u8 *a; 2304 2305 printk(MYIOC_s_INFO_FMT "Initiating %s\n", ioc->name, 2306 reason == MPT_HOSTEVENT_IOC_BRINGUP ? "bringup" : "recovery"); 2307 2308 /* Disable reply interrupts (also blocks FreeQ) */ 2309 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 2310 ioc->active = 0; 2311 2312 if (ioc->alt_ioc) { 2313 if (ioc->alt_ioc->active || 2314 reason == MPT_HOSTEVENT_IOC_RECOVER) { 2315 reset_alt_ioc_active = 1; 2316 /* Disable alt-IOC's reply interrupts 2317 * (and FreeQ) for a bit 2318 **/ 2319 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, 2320 0xFFFFFFFF); 2321 ioc->alt_ioc->active = 0; 2322 } 2323 } 2324 2325 hard = 1; 2326 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) 2327 hard = 0; 2328 2329 if ((hard_reset_done = MakeIocReady(ioc, hard, sleepFlag)) < 0) { 2330 if (hard_reset_done == -4) { 2331 printk(MYIOC_s_WARN_FMT "Owned by PEER..skipping!\n", 2332 ioc->name); 2333 2334 if (reset_alt_ioc_active && ioc->alt_ioc) { 2335 /* (re)Enable alt-IOC! (reply interrupt, FreeQ) */ 2336 dprintk(ioc, printk(MYIOC_s_INFO_FMT 2337 "alt_ioc reply irq re-enabled\n", ioc->alt_ioc->name)); 2338 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, MPI_HIM_DIM); 2339 ioc->alt_ioc->active = 1; 2340 } 2341 2342 } else { 2343 printk(MYIOC_s_WARN_FMT 2344 "NOT READY WARNING!\n", ioc->name); 2345 } 2346 ret = -1; 2347 goto out; 2348 } 2349 2350 /* hard_reset_done = 0 if a soft reset was performed 2351 * and 1 if a hard reset was performed. 2352 */ 2353 if (hard_reset_done && reset_alt_ioc_active && ioc->alt_ioc) { 2354 if ((rc = MakeIocReady(ioc->alt_ioc, 0, sleepFlag)) == 0) 2355 alt_ioc_ready = 1; 2356 else 2357 printk(MYIOC_s_WARN_FMT 2358 ": alt-ioc Not ready WARNING!\n", 2359 ioc->alt_ioc->name); 2360 } 2361 2362 for (ii=0; ii<5; ii++) { 2363 /* Get IOC facts! Allow 5 retries */ 2364 if ((rc = GetIocFacts(ioc, sleepFlag, reason)) == 0) 2365 break; 2366 } 2367 2368 2369 if (ii == 5) { 2370 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2371 "Retry IocFacts failed rc=%x\n", ioc->name, rc)); 2372 ret = -2; 2373 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) { 2374 MptDisplayIocCapabilities(ioc); 2375 } 2376 2377 if (alt_ioc_ready) { 2378 if ((rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason)) != 0) { 2379 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2380 "Initial Alt IocFacts failed rc=%x\n", 2381 ioc->name, rc)); 2382 /* Retry - alt IOC was initialized once 2383 */ 2384 rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason); 2385 } 2386 if (rc) { 2387 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2388 "Retry Alt IocFacts failed rc=%x\n", ioc->name, rc)); 2389 alt_ioc_ready = 0; 2390 reset_alt_ioc_active = 0; 2391 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) { 2392 MptDisplayIocCapabilities(ioc->alt_ioc); 2393 } 2394 } 2395 2396 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP) && 2397 (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)) { 2398 pci_release_selected_regions(ioc->pcidev, ioc->bars); 2399 ioc->bars = pci_select_bars(ioc->pcidev, IORESOURCE_MEM | 2400 IORESOURCE_IO); 2401 if (pci_enable_device(ioc->pcidev)) 2402 return -5; 2403 if (pci_request_selected_regions(ioc->pcidev, ioc->bars, 2404 "mpt")) 2405 return -5; 2406 } 2407 2408 /* 2409 * Device is reset now. It must have de-asserted the interrupt line 2410 * (if it was asserted) and it should be safe to register for the 2411 * interrupt now. 2412 */ 2413 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) { 2414 ioc->pci_irq = -1; 2415 if (ioc->pcidev->irq) { 2416 if (ioc->msi_enable && !pci_enable_msi(ioc->pcidev)) 2417 printk(MYIOC_s_INFO_FMT "PCI-MSI enabled\n", 2418 ioc->name); 2419 else 2420 ioc->msi_enable = 0; 2421 rc = request_irq(ioc->pcidev->irq, mpt_interrupt, 2422 IRQF_SHARED, ioc->name, ioc); 2423 if (rc < 0) { 2424 printk(MYIOC_s_ERR_FMT "Unable to allocate " 2425 "interrupt %d!\n", 2426 ioc->name, ioc->pcidev->irq); 2427 if (ioc->msi_enable) 2428 pci_disable_msi(ioc->pcidev); 2429 ret = -EBUSY; 2430 goto out; 2431 } 2432 irq_allocated = 1; 2433 ioc->pci_irq = ioc->pcidev->irq; 2434 pci_set_master(ioc->pcidev); /* ?? */ 2435 pci_set_drvdata(ioc->pcidev, ioc); 2436 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 2437 "installed at interrupt %d\n", ioc->name, 2438 ioc->pcidev->irq)); 2439 } 2440 } 2441 2442 /* Prime reply & request queues! 2443 * (mucho alloc's) Must be done prior to 2444 * init as upper addresses are needed for init. 2445 * If fails, continue with alt-ioc processing 2446 */ 2447 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "PrimeIocFifos\n", 2448 ioc->name)); 2449 if ((ret == 0) && ((rc = PrimeIocFifos(ioc)) != 0)) 2450 ret = -3; 2451 2452 /* May need to check/upload firmware & data here! 2453 * If fails, continue with alt-ioc processing 2454 */ 2455 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "SendIocInit\n", 2456 ioc->name)); 2457 if ((ret == 0) && ((rc = SendIocInit(ioc, sleepFlag)) != 0)) 2458 ret = -4; 2459 // NEW! 2460 if (alt_ioc_ready && ((rc = PrimeIocFifos(ioc->alt_ioc)) != 0)) { 2461 printk(MYIOC_s_WARN_FMT 2462 ": alt-ioc (%d) FIFO mgmt alloc WARNING!\n", 2463 ioc->alt_ioc->name, rc); 2464 alt_ioc_ready = 0; 2465 reset_alt_ioc_active = 0; 2466 } 2467 2468 if (alt_ioc_ready) { 2469 if ((rc = SendIocInit(ioc->alt_ioc, sleepFlag)) != 0) { 2470 alt_ioc_ready = 0; 2471 reset_alt_ioc_active = 0; 2472 printk(MYIOC_s_WARN_FMT 2473 ": alt-ioc: (%d) init failure WARNING!\n", 2474 ioc->alt_ioc->name, rc); 2475 } 2476 } 2477 2478 if (reason == MPT_HOSTEVENT_IOC_BRINGUP){ 2479 if (ioc->upload_fw) { 2480 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2481 "firmware upload required!\n", ioc->name)); 2482 2483 /* Controller is not operational, cannot do upload 2484 */ 2485 if (ret == 0) { 2486 rc = mpt_do_upload(ioc, sleepFlag); 2487 if (rc == 0) { 2488 if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) { 2489 /* 2490 * Maintain only one pointer to FW memory 2491 * so there will not be two attempt to 2492 * downloadboot onboard dual function 2493 * chips (mpt_adapter_disable, 2494 * mpt_diag_reset) 2495 */ 2496 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2497 "mpt_upload: alt_%s has cached_fw=%p \n", 2498 ioc->name, ioc->alt_ioc->name, ioc->alt_ioc->cached_fw)); 2499 ioc->cached_fw = NULL; 2500 } 2501 } else { 2502 printk(MYIOC_s_WARN_FMT 2503 "firmware upload failure!\n", ioc->name); 2504 ret = -6; 2505 } 2506 } 2507 } 2508 } 2509 2510 /* Enable MPT base driver management of EventNotification 2511 * and EventAck handling. 2512 */ 2513 if ((ret == 0) && (!ioc->facts.EventState)) { 2514 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 2515 "SendEventNotification\n", 2516 ioc->name)); 2517 ret = SendEventNotification(ioc, 1, sleepFlag); /* 1=Enable */ 2518 } 2519 2520 if (ioc->alt_ioc && alt_ioc_ready && !ioc->alt_ioc->facts.EventState) 2521 rc = SendEventNotification(ioc->alt_ioc, 1, sleepFlag); 2522 2523 if (ret == 0) { 2524 /* Enable! (reply interrupt) */ 2525 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM); 2526 ioc->active = 1; 2527 } 2528 if (rc == 0) { /* alt ioc */ 2529 if (reset_alt_ioc_active && ioc->alt_ioc) { 2530 /* (re)Enable alt-IOC! (reply interrupt) */ 2531 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "alt-ioc" 2532 "reply irq re-enabled\n", 2533 ioc->alt_ioc->name)); 2534 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, 2535 MPI_HIM_DIM); 2536 ioc->alt_ioc->active = 1; 2537 } 2538 } 2539 2540 2541 /* Add additional "reason" check before call to GetLanConfigPages 2542 * (combined with GetIoUnitPage2 call). This prevents a somewhat 2543 * recursive scenario; GetLanConfigPages times out, timer expired 2544 * routine calls HardResetHandler, which calls into here again, 2545 * and we try GetLanConfigPages again... 2546 */ 2547 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) { 2548 2549 /* 2550 * Initialize link list for inactive raid volumes. 2551 */ 2552 mutex_init(&ioc->raid_data.inactive_list_mutex); 2553 INIT_LIST_HEAD(&ioc->raid_data.inactive_list); 2554 2555 switch (ioc->bus_type) { 2556 2557 case SAS: 2558 /* clear persistency table */ 2559 if(ioc->facts.IOCExceptions & 2560 MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL) { 2561 ret = mptbase_sas_persist_operation(ioc, 2562 MPI_SAS_OP_CLEAR_NOT_PRESENT); 2563 if(ret != 0) 2564 goto out; 2565 } 2566 2567 /* Find IM volumes 2568 */ 2569 mpt_findImVolumes(ioc); 2570 2571 /* Check, and possibly reset, the coalescing value 2572 */ 2573 mpt_read_ioc_pg_1(ioc); 2574 2575 break; 2576 2577 case FC: 2578 if ((ioc->pfacts[0].ProtocolFlags & 2579 MPI_PORTFACTS_PROTOCOL_LAN) && 2580 (ioc->lan_cnfg_page0.Header.PageLength == 0)) { 2581 /* 2582 * Pre-fetch the ports LAN MAC address! 2583 * (LANPage1_t stuff) 2584 */ 2585 (void) GetLanConfigPages(ioc); 2586 a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow; 2587 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2588 "LanAddr = %pMR\n", ioc->name, a)); 2589 } 2590 break; 2591 2592 case SPI: 2593 /* Get NVRAM and adapter maximums from SPP 0 and 2 2594 */ 2595 mpt_GetScsiPortSettings(ioc, 0); 2596 2597 /* Get version and length of SDP 1 2598 */ 2599 mpt_readScsiDevicePageHeaders(ioc, 0); 2600 2601 /* Find IM volumes 2602 */ 2603 if (ioc->facts.MsgVersion >= MPI_VERSION_01_02) 2604 mpt_findImVolumes(ioc); 2605 2606 /* Check, and possibly reset, the coalescing value 2607 */ 2608 mpt_read_ioc_pg_1(ioc); 2609 2610 mpt_read_ioc_pg_4(ioc); 2611 2612 break; 2613 } 2614 2615 GetIoUnitPage2(ioc); 2616 mpt_get_manufacturing_pg_0(ioc); 2617 } 2618 2619 out: 2620 if ((ret != 0) && irq_allocated) { 2621 free_irq(ioc->pci_irq, ioc); 2622 if (ioc->msi_enable) 2623 pci_disable_msi(ioc->pcidev); 2624 } 2625 return ret; 2626 } 2627 2628 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2629 /** 2630 * mpt_detect_bound_ports - Search for matching PCI bus/dev_function 2631 * @ioc: Pointer to MPT adapter structure 2632 * @pdev: Pointer to (struct pci_dev) structure 2633 * 2634 * Search for PCI bus/dev_function which matches 2635 * PCI bus/dev_function (+/-1) for newly discovered 929, 2636 * 929X, 1030 or 1035. 2637 * 2638 * If match on PCI dev_function +/-1 is found, bind the two MPT adapters 2639 * using alt_ioc pointer fields in their %MPT_ADAPTER structures. 2640 */ 2641 static void 2642 mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev) 2643 { 2644 struct pci_dev *peer=NULL; 2645 unsigned int slot = PCI_SLOT(pdev->devfn); 2646 unsigned int func = PCI_FUNC(pdev->devfn); 2647 MPT_ADAPTER *ioc_srch; 2648 2649 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "PCI device %s devfn=%x/%x," 2650 " searching for devfn match on %x or %x\n", 2651 ioc->name, pci_name(pdev), pdev->bus->number, 2652 pdev->devfn, func-1, func+1)); 2653 2654 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func-1)); 2655 if (!peer) { 2656 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func+1)); 2657 if (!peer) 2658 return; 2659 } 2660 2661 list_for_each_entry(ioc_srch, &ioc_list, list) { 2662 struct pci_dev *_pcidev = ioc_srch->pcidev; 2663 if (_pcidev == peer) { 2664 /* Paranoia checks */ 2665 if (ioc->alt_ioc != NULL) { 2666 printk(MYIOC_s_WARN_FMT 2667 "Oops, already bound (%s <==> %s)!\n", 2668 ioc->name, ioc->name, ioc->alt_ioc->name); 2669 break; 2670 } else if (ioc_srch->alt_ioc != NULL) { 2671 printk(MYIOC_s_WARN_FMT 2672 "Oops, already bound (%s <==> %s)!\n", 2673 ioc_srch->name, ioc_srch->name, 2674 ioc_srch->alt_ioc->name); 2675 break; 2676 } 2677 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2678 "FOUND! binding %s <==> %s\n", 2679 ioc->name, ioc->name, ioc_srch->name)); 2680 ioc_srch->alt_ioc = ioc; 2681 ioc->alt_ioc = ioc_srch; 2682 } 2683 } 2684 pci_dev_put(peer); 2685 } 2686 2687 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2688 /** 2689 * mpt_adapter_disable - Disable misbehaving MPT adapter. 2690 * @ioc: Pointer to MPT adapter structure 2691 */ 2692 static void 2693 mpt_adapter_disable(MPT_ADAPTER *ioc) 2694 { 2695 int sz; 2696 int ret; 2697 2698 if (ioc->cached_fw != NULL) { 2699 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2700 "%s: Pushing FW onto adapter\n", __func__, ioc->name)); 2701 if ((ret = mpt_downloadboot(ioc, (MpiFwHeader_t *) 2702 ioc->cached_fw, CAN_SLEEP)) < 0) { 2703 printk(MYIOC_s_WARN_FMT 2704 ": firmware downloadboot failure (%d)!\n", 2705 ioc->name, ret); 2706 } 2707 } 2708 2709 /* 2710 * Put the controller into ready state (if its not already) 2711 */ 2712 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) { 2713 if (!SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, 2714 CAN_SLEEP)) { 2715 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) 2716 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit " 2717 "reset failed to put ioc in ready state!\n", 2718 ioc->name, __func__); 2719 } else 2720 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit reset " 2721 "failed!\n", ioc->name, __func__); 2722 } 2723 2724 2725 /* Disable adapter interrupts! */ 2726 synchronize_irq(ioc->pcidev->irq); 2727 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 2728 ioc->active = 0; 2729 2730 /* Clear any lingering interrupt */ 2731 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 2732 CHIPREG_READ32(&ioc->chip->IntStatus); 2733 2734 if (ioc->alloc != NULL) { 2735 sz = ioc->alloc_sz; 2736 dexitprintk(ioc, printk(MYIOC_s_INFO_FMT "free @ %p, sz=%d bytes\n", 2737 ioc->name, ioc->alloc, ioc->alloc_sz)); 2738 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->alloc, 2739 ioc->alloc_dma); 2740 ioc->reply_frames = NULL; 2741 ioc->req_frames = NULL; 2742 ioc->alloc = NULL; 2743 ioc->alloc_total -= sz; 2744 } 2745 2746 if (ioc->sense_buf_pool != NULL) { 2747 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC); 2748 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->sense_buf_pool, 2749 ioc->sense_buf_pool_dma); 2750 ioc->sense_buf_pool = NULL; 2751 ioc->alloc_total -= sz; 2752 } 2753 2754 if (ioc->events != NULL){ 2755 sz = MPTCTL_EVENT_LOG_SIZE * sizeof(MPT_IOCTL_EVENTS); 2756 kfree(ioc->events); 2757 ioc->events = NULL; 2758 ioc->alloc_total -= sz; 2759 } 2760 2761 mpt_free_fw_memory(ioc); 2762 2763 kfree(ioc->spi_data.nvram); 2764 mpt_inactive_raid_list_free(ioc); 2765 kfree(ioc->raid_data.pIocPg2); 2766 kfree(ioc->raid_data.pIocPg3); 2767 ioc->spi_data.nvram = NULL; 2768 ioc->raid_data.pIocPg3 = NULL; 2769 2770 if (ioc->spi_data.pIocPg4 != NULL) { 2771 sz = ioc->spi_data.IocPg4Sz; 2772 pci_free_consistent(ioc->pcidev, sz, 2773 ioc->spi_data.pIocPg4, 2774 ioc->spi_data.IocPg4_dma); 2775 ioc->spi_data.pIocPg4 = NULL; 2776 ioc->alloc_total -= sz; 2777 } 2778 2779 if (ioc->ReqToChain != NULL) { 2780 kfree(ioc->ReqToChain); 2781 kfree(ioc->RequestNB); 2782 ioc->ReqToChain = NULL; 2783 } 2784 2785 kfree(ioc->ChainToChain); 2786 ioc->ChainToChain = NULL; 2787 2788 if (ioc->HostPageBuffer != NULL) { 2789 if((ret = mpt_host_page_access_control(ioc, 2790 MPI_DB_HPBAC_FREE_BUFFER, NO_SLEEP)) != 0) { 2791 printk(MYIOC_s_ERR_FMT 2792 ": %s: host page buffers free failed (%d)!\n", 2793 ioc->name, __func__, ret); 2794 } 2795 dexitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 2796 "HostPageBuffer free @ %p, sz=%d bytes\n", 2797 ioc->name, ioc->HostPageBuffer, 2798 ioc->HostPageBuffer_sz)); 2799 dma_free_coherent(&ioc->pcidev->dev, ioc->HostPageBuffer_sz, 2800 ioc->HostPageBuffer, ioc->HostPageBuffer_dma); 2801 ioc->HostPageBuffer = NULL; 2802 ioc->HostPageBuffer_sz = 0; 2803 ioc->alloc_total -= ioc->HostPageBuffer_sz; 2804 } 2805 2806 pci_set_drvdata(ioc->pcidev, NULL); 2807 } 2808 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2809 /** 2810 * mpt_adapter_dispose - Free all resources associated with an MPT adapter 2811 * @ioc: Pointer to MPT adapter structure 2812 * 2813 * This routine unregisters h/w resources and frees all alloc'd memory 2814 * associated with a MPT adapter structure. 2815 */ 2816 static void 2817 mpt_adapter_dispose(MPT_ADAPTER *ioc) 2818 { 2819 int sz_first, sz_last; 2820 2821 if (ioc == NULL) 2822 return; 2823 2824 sz_first = ioc->alloc_total; 2825 2826 mpt_adapter_disable(ioc); 2827 2828 if (ioc->pci_irq != -1) { 2829 free_irq(ioc->pci_irq, ioc); 2830 if (ioc->msi_enable) 2831 pci_disable_msi(ioc->pcidev); 2832 ioc->pci_irq = -1; 2833 } 2834 2835 if (ioc->memmap != NULL) { 2836 iounmap(ioc->memmap); 2837 ioc->memmap = NULL; 2838 } 2839 2840 pci_disable_device(ioc->pcidev); 2841 pci_release_selected_regions(ioc->pcidev, ioc->bars); 2842 2843 /* Zap the adapter lookup ptr! */ 2844 list_del(&ioc->list); 2845 2846 sz_last = ioc->alloc_total; 2847 dprintk(ioc, printk(MYIOC_s_INFO_FMT "free'd %d of %d bytes\n", 2848 ioc->name, sz_first-sz_last+(int)sizeof(*ioc), sz_first)); 2849 2850 if (ioc->alt_ioc) 2851 ioc->alt_ioc->alt_ioc = NULL; 2852 2853 kfree(ioc); 2854 } 2855 2856 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2857 /** 2858 * MptDisplayIocCapabilities - Disply IOC's capabilities. 2859 * @ioc: Pointer to MPT adapter structure 2860 */ 2861 static void 2862 MptDisplayIocCapabilities(MPT_ADAPTER *ioc) 2863 { 2864 int i = 0; 2865 2866 printk(KERN_INFO "%s: ", ioc->name); 2867 if (ioc->prod_name) 2868 pr_cont("%s: ", ioc->prod_name); 2869 pr_cont("Capabilities={"); 2870 2871 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR) { 2872 pr_cont("Initiator"); 2873 i++; 2874 } 2875 2876 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) { 2877 pr_cont("%sTarget", i ? "," : ""); 2878 i++; 2879 } 2880 2881 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) { 2882 pr_cont("%sLAN", i ? "," : ""); 2883 i++; 2884 } 2885 2886 #if 0 2887 /* 2888 * This would probably evoke more questions than it's worth 2889 */ 2890 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) { 2891 pr_cont("%sLogBusAddr", i ? "," : ""); 2892 i++; 2893 } 2894 #endif 2895 2896 pr_cont("}\n"); 2897 } 2898 2899 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 2900 /** 2901 * MakeIocReady - Get IOC to a READY state, using KickStart if needed. 2902 * @ioc: Pointer to MPT_ADAPTER structure 2903 * @force: Force hard KickStart of IOC 2904 * @sleepFlag: Specifies whether the process can sleep 2905 * 2906 * Returns: 2907 * 1 - DIAG reset and READY 2908 * 0 - READY initially OR soft reset and READY 2909 * -1 - Any failure on KickStart 2910 * -2 - Msg Unit Reset Failed 2911 * -3 - IO Unit Reset Failed 2912 * -4 - IOC owned by a PEER 2913 */ 2914 static int 2915 MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag) 2916 { 2917 u32 ioc_state; 2918 int statefault = 0; 2919 int cntdn; 2920 int hard_reset_done = 0; 2921 int r; 2922 int ii; 2923 int whoinit; 2924 2925 /* Get current [raw] IOC state */ 2926 ioc_state = mpt_GetIocState(ioc, 0); 2927 dhsprintk(ioc, printk(MYIOC_s_INFO_FMT "MakeIocReady [raw] state=%08x\n", ioc->name, ioc_state)); 2928 2929 /* 2930 * Check to see if IOC got left/stuck in doorbell handshake 2931 * grip of death. If so, hard reset the IOC. 2932 */ 2933 if (ioc_state & MPI_DOORBELL_ACTIVE) { 2934 statefault = 1; 2935 printk(MYIOC_s_WARN_FMT "Unexpected doorbell active!\n", 2936 ioc->name); 2937 } 2938 2939 /* Is it already READY? */ 2940 if (!statefault && 2941 ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_READY)) { 2942 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 2943 "IOC is in READY state\n", ioc->name)); 2944 return 0; 2945 } 2946 2947 /* 2948 * Check to see if IOC is in FAULT state. 2949 */ 2950 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) { 2951 statefault = 2; 2952 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state!!!\n", 2953 ioc->name); 2954 printk(MYIOC_s_WARN_FMT " FAULT code = %04xh\n", 2955 ioc->name, ioc_state & MPI_DOORBELL_DATA_MASK); 2956 } 2957 2958 /* 2959 * Hmmm... Did it get left operational? 2960 */ 2961 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_OPERATIONAL) { 2962 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOC operational unexpected\n", 2963 ioc->name)); 2964 2965 /* Check WhoInit. 2966 * If PCI Peer, exit. 2967 * Else, if no fault conditions are present, issue a MessageUnitReset 2968 * Else, fall through to KickStart case 2969 */ 2970 whoinit = (ioc_state & MPI_DOORBELL_WHO_INIT_MASK) >> MPI_DOORBELL_WHO_INIT_SHIFT; 2971 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT 2972 "whoinit 0x%x statefault %d force %d\n", 2973 ioc->name, whoinit, statefault, force)); 2974 if (whoinit == MPI_WHOINIT_PCI_PEER) 2975 return -4; 2976 else { 2977 if ((statefault == 0 ) && (force == 0)) { 2978 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) == 0) 2979 return 0; 2980 } 2981 statefault = 3; 2982 } 2983 } 2984 2985 hard_reset_done = KickStart(ioc, statefault||force, sleepFlag); 2986 if (hard_reset_done < 0) 2987 return -1; 2988 2989 /* 2990 * Loop here waiting for IOC to come READY. 2991 */ 2992 ii = 0; 2993 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 5; /* 5 seconds */ 2994 2995 while ((ioc_state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) { 2996 if (ioc_state == MPI_IOC_STATE_OPERATIONAL) { 2997 /* 2998 * BIOS or previous driver load left IOC in OP state. 2999 * Reset messaging FIFOs. 3000 */ 3001 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) != 0) { 3002 printk(MYIOC_s_ERR_FMT "IOC msg unit reset failed!\n", ioc->name); 3003 return -2; 3004 } 3005 } else if (ioc_state == MPI_IOC_STATE_RESET) { 3006 /* 3007 * Something is wrong. Try to get IOC back 3008 * to a known state. 3009 */ 3010 if ((r = SendIocReset(ioc, MPI_FUNCTION_IO_UNIT_RESET, sleepFlag)) != 0) { 3011 printk(MYIOC_s_ERR_FMT "IO unit reset failed!\n", ioc->name); 3012 return -3; 3013 } 3014 } 3015 3016 ii++; cntdn--; 3017 if (!cntdn) { 3018 printk(MYIOC_s_ERR_FMT 3019 "Wait IOC_READY state (0x%x) timeout(%d)!\n", 3020 ioc->name, ioc_state, (int)((ii+5)/HZ)); 3021 return -ETIME; 3022 } 3023 3024 if (sleepFlag == CAN_SLEEP) { 3025 msleep(1); 3026 } else { 3027 mdelay (1); /* 1 msec delay */ 3028 } 3029 3030 } 3031 3032 if (statefault < 3) { 3033 printk(MYIOC_s_INFO_FMT "Recovered from %s\n", ioc->name, 3034 statefault == 1 ? "stuck handshake" : "IOC FAULT"); 3035 } 3036 3037 return hard_reset_done; 3038 } 3039 3040 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3041 /** 3042 * mpt_GetIocState - Get the current state of a MPT adapter. 3043 * @ioc: Pointer to MPT_ADAPTER structure 3044 * @cooked: Request raw or cooked IOC state 3045 * 3046 * Returns all IOC Doorbell register bits if cooked==0, else just the 3047 * Doorbell bits in MPI_IOC_STATE_MASK. 3048 */ 3049 u32 3050 mpt_GetIocState(MPT_ADAPTER *ioc, int cooked) 3051 { 3052 u32 s, sc; 3053 3054 /* Get! */ 3055 s = CHIPREG_READ32(&ioc->chip->Doorbell); 3056 sc = s & MPI_IOC_STATE_MASK; 3057 3058 /* Save! */ 3059 ioc->last_state = sc; 3060 3061 return cooked ? sc : s; 3062 } 3063 3064 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3065 /** 3066 * GetIocFacts - Send IOCFacts request to MPT adapter. 3067 * @ioc: Pointer to MPT_ADAPTER structure 3068 * @sleepFlag: Specifies whether the process can sleep 3069 * @reason: If recovery, only update facts. 3070 * 3071 * Returns 0 for success, non-zero for failure. 3072 */ 3073 static int 3074 GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason) 3075 { 3076 IOCFacts_t get_facts; 3077 IOCFactsReply_t *facts; 3078 int r; 3079 int req_sz; 3080 int reply_sz; 3081 int sz; 3082 u32 vv; 3083 u8 shiftFactor=1; 3084 3085 /* IOC *must* NOT be in RESET state! */ 3086 if (ioc->last_state == MPI_IOC_STATE_RESET) { 3087 printk(KERN_ERR MYNAM 3088 ": ERROR - Can't get IOCFacts, %s NOT READY! (%08x)\n", 3089 ioc->name, ioc->last_state); 3090 return -44; 3091 } 3092 3093 facts = &ioc->facts; 3094 3095 /* Destination (reply area)... */ 3096 reply_sz = sizeof(*facts); 3097 memset(facts, 0, reply_sz); 3098 3099 /* Request area (get_facts on the stack right now!) */ 3100 req_sz = sizeof(get_facts); 3101 memset(&get_facts, 0, req_sz); 3102 3103 get_facts.Function = MPI_FUNCTION_IOC_FACTS; 3104 /* Assert: All other get_facts fields are zero! */ 3105 3106 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3107 "Sending get IocFacts request req_sz=%d reply_sz=%d\n", 3108 ioc->name, req_sz, reply_sz)); 3109 3110 /* No non-zero fields in the get_facts request are greater than 3111 * 1 byte in size, so we can just fire it off as is. 3112 */ 3113 r = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_facts, 3114 reply_sz, (u16*)facts, 5 /*seconds*/, sleepFlag); 3115 if (r != 0) 3116 return r; 3117 3118 /* 3119 * Now byte swap (GRRR) the necessary fields before any further 3120 * inspection of reply contents. 3121 * 3122 * But need to do some sanity checks on MsgLength (byte) field 3123 * to make sure we don't zero IOC's req_sz! 3124 */ 3125 /* Did we get a valid reply? */ 3126 if (facts->MsgLength > offsetof(IOCFactsReply_t, RequestFrameSize)/sizeof(u32)) { 3127 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) { 3128 /* 3129 * If not been here, done that, save off first WhoInit value 3130 */ 3131 if (ioc->FirstWhoInit == WHOINIT_UNKNOWN) 3132 ioc->FirstWhoInit = facts->WhoInit; 3133 } 3134 3135 facts->MsgVersion = le16_to_cpu(facts->MsgVersion); 3136 facts->MsgContext = le32_to_cpu(facts->MsgContext); 3137 facts->IOCExceptions = le16_to_cpu(facts->IOCExceptions); 3138 facts->IOCStatus = le16_to_cpu(facts->IOCStatus); 3139 facts->IOCLogInfo = le32_to_cpu(facts->IOCLogInfo); 3140 /* CHECKME! IOCStatus, IOCLogInfo */ 3141 3142 facts->ReplyQueueDepth = le16_to_cpu(facts->ReplyQueueDepth); 3143 facts->RequestFrameSize = le16_to_cpu(facts->RequestFrameSize); 3144 3145 /* 3146 * FC f/w version changed between 1.1 and 1.2 3147 * Old: u16{Major(4),Minor(4),SubMinor(8)} 3148 * New: u32{Major(8),Minor(8),Unit(8),Dev(8)} 3149 */ 3150 if (facts->MsgVersion < MPI_VERSION_01_02) { 3151 /* 3152 * Handle old FC f/w style, convert to new... 3153 */ 3154 u16 oldv = le16_to_cpu(facts->Reserved_0101_FWVersion); 3155 facts->FWVersion.Word = 3156 ((oldv<<12) & 0xFF000000) | 3157 ((oldv<<8) & 0x000FFF00); 3158 } else 3159 facts->FWVersion.Word = le32_to_cpu(facts->FWVersion.Word); 3160 3161 facts->ProductID = le16_to_cpu(facts->ProductID); 3162 3163 if ((ioc->facts.ProductID & MPI_FW_HEADER_PID_PROD_MASK) 3164 > MPI_FW_HEADER_PID_PROD_TARGET_SCSI) 3165 ioc->ir_firmware = 1; 3166 3167 facts->CurrentHostMfaHighAddr = 3168 le32_to_cpu(facts->CurrentHostMfaHighAddr); 3169 facts->GlobalCredits = le16_to_cpu(facts->GlobalCredits); 3170 facts->CurrentSenseBufferHighAddr = 3171 le32_to_cpu(facts->CurrentSenseBufferHighAddr); 3172 facts->CurReplyFrameSize = 3173 le16_to_cpu(facts->CurReplyFrameSize); 3174 facts->IOCCapabilities = le32_to_cpu(facts->IOCCapabilities); 3175 3176 /* 3177 * Handle NEW (!) IOCFactsReply fields in MPI-1.01.xx 3178 * Older MPI-1.00.xx struct had 13 dwords, and enlarged 3179 * to 14 in MPI-1.01.0x. 3180 */ 3181 if (facts->MsgLength >= (offsetof(IOCFactsReply_t,FWImageSize) + 7)/4 && 3182 facts->MsgVersion > MPI_VERSION_01_00) { 3183 facts->FWImageSize = le32_to_cpu(facts->FWImageSize); 3184 } 3185 3186 facts->FWImageSize = ALIGN(facts->FWImageSize, 4); 3187 3188 if (!facts->RequestFrameSize) { 3189 /* Something is wrong! */ 3190 printk(MYIOC_s_ERR_FMT "IOC reported invalid 0 request size!\n", 3191 ioc->name); 3192 return -55; 3193 } 3194 3195 r = sz = facts->BlockSize; 3196 vv = ((63 / (sz * 4)) + 1) & 0x03; 3197 ioc->NB_for_64_byte_frame = vv; 3198 while ( sz ) 3199 { 3200 shiftFactor++; 3201 sz = sz >> 1; 3202 } 3203 ioc->NBShiftFactor = shiftFactor; 3204 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3205 "NB_for_64_byte_frame=%x NBShiftFactor=%x BlockSize=%x\n", 3206 ioc->name, vv, shiftFactor, r)); 3207 3208 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) { 3209 /* 3210 * Set values for this IOC's request & reply frame sizes, 3211 * and request & reply queue depths... 3212 */ 3213 ioc->req_sz = min(MPT_DEFAULT_FRAME_SIZE, facts->RequestFrameSize * 4); 3214 ioc->req_depth = min_t(int, MPT_MAX_REQ_DEPTH, facts->GlobalCredits); 3215 ioc->reply_sz = MPT_REPLY_FRAME_SIZE; 3216 ioc->reply_depth = min_t(int, MPT_DEFAULT_REPLY_DEPTH, facts->ReplyQueueDepth); 3217 3218 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "reply_sz=%3d, reply_depth=%4d\n", 3219 ioc->name, ioc->reply_sz, ioc->reply_depth)); 3220 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "req_sz =%3d, req_depth =%4d\n", 3221 ioc->name, ioc->req_sz, ioc->req_depth)); 3222 3223 /* Get port facts! */ 3224 if ( (r = GetPortFacts(ioc, 0, sleepFlag)) != 0 ) 3225 return r; 3226 } 3227 } else { 3228 printk(MYIOC_s_ERR_FMT 3229 "Invalid IOC facts reply, msgLength=%d offsetof=%zd!\n", 3230 ioc->name, facts->MsgLength, (offsetof(IOCFactsReply_t, 3231 RequestFrameSize)/sizeof(u32))); 3232 return -66; 3233 } 3234 3235 return 0; 3236 } 3237 3238 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3239 /** 3240 * GetPortFacts - Send PortFacts request to MPT adapter. 3241 * @ioc: Pointer to MPT_ADAPTER structure 3242 * @portnum: Port number 3243 * @sleepFlag: Specifies whether the process can sleep 3244 * 3245 * Returns 0 for success, non-zero for failure. 3246 */ 3247 static int 3248 GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag) 3249 { 3250 PortFacts_t get_pfacts; 3251 PortFactsReply_t *pfacts; 3252 int ii; 3253 int req_sz; 3254 int reply_sz; 3255 int max_id; 3256 3257 /* IOC *must* NOT be in RESET state! */ 3258 if (ioc->last_state == MPI_IOC_STATE_RESET) { 3259 printk(MYIOC_s_ERR_FMT "Can't get PortFacts NOT READY! (%08x)\n", 3260 ioc->name, ioc->last_state ); 3261 return -4; 3262 } 3263 3264 pfacts = &ioc->pfacts[portnum]; 3265 3266 /* Destination (reply area)... */ 3267 reply_sz = sizeof(*pfacts); 3268 memset(pfacts, 0, reply_sz); 3269 3270 /* Request area (get_pfacts on the stack right now!) */ 3271 req_sz = sizeof(get_pfacts); 3272 memset(&get_pfacts, 0, req_sz); 3273 3274 get_pfacts.Function = MPI_FUNCTION_PORT_FACTS; 3275 get_pfacts.PortNumber = portnum; 3276 /* Assert: All other get_pfacts fields are zero! */ 3277 3278 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending get PortFacts(%d) request\n", 3279 ioc->name, portnum)); 3280 3281 /* No non-zero fields in the get_pfacts request are greater than 3282 * 1 byte in size, so we can just fire it off as is. 3283 */ 3284 ii = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_pfacts, 3285 reply_sz, (u16*)pfacts, 5 /*seconds*/, sleepFlag); 3286 if (ii != 0) 3287 return ii; 3288 3289 /* Did we get a valid reply? */ 3290 3291 /* Now byte swap the necessary fields in the response. */ 3292 pfacts->MsgContext = le32_to_cpu(pfacts->MsgContext); 3293 pfacts->IOCStatus = le16_to_cpu(pfacts->IOCStatus); 3294 pfacts->IOCLogInfo = le32_to_cpu(pfacts->IOCLogInfo); 3295 pfacts->MaxDevices = le16_to_cpu(pfacts->MaxDevices); 3296 pfacts->PortSCSIID = le16_to_cpu(pfacts->PortSCSIID); 3297 pfacts->ProtocolFlags = le16_to_cpu(pfacts->ProtocolFlags); 3298 pfacts->MaxPostedCmdBuffers = le16_to_cpu(pfacts->MaxPostedCmdBuffers); 3299 pfacts->MaxPersistentIDs = le16_to_cpu(pfacts->MaxPersistentIDs); 3300 pfacts->MaxLanBuckets = le16_to_cpu(pfacts->MaxLanBuckets); 3301 3302 max_id = (ioc->bus_type == SAS) ? pfacts->PortSCSIID : 3303 pfacts->MaxDevices; 3304 ioc->devices_per_bus = (max_id > 255) ? 256 : max_id; 3305 ioc->number_of_buses = (ioc->devices_per_bus < 256) ? 1 : max_id/256; 3306 3307 /* 3308 * Place all the devices on channels 3309 * 3310 * (for debuging) 3311 */ 3312 if (mpt_channel_mapping) { 3313 ioc->devices_per_bus = 1; 3314 ioc->number_of_buses = (max_id > 255) ? 255 : max_id; 3315 } 3316 3317 return 0; 3318 } 3319 3320 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3321 /** 3322 * SendIocInit - Send IOCInit request to MPT adapter. 3323 * @ioc: Pointer to MPT_ADAPTER structure 3324 * @sleepFlag: Specifies whether the process can sleep 3325 * 3326 * Send IOCInit followed by PortEnable to bring IOC to OPERATIONAL state. 3327 * 3328 * Returns 0 for success, non-zero for failure. 3329 */ 3330 static int 3331 SendIocInit(MPT_ADAPTER *ioc, int sleepFlag) 3332 { 3333 IOCInit_t ioc_init; 3334 MPIDefaultReply_t init_reply; 3335 u32 state; 3336 int r; 3337 int count; 3338 int cntdn; 3339 3340 memset(&ioc_init, 0, sizeof(ioc_init)); 3341 memset(&init_reply, 0, sizeof(init_reply)); 3342 3343 ioc_init.WhoInit = MPI_WHOINIT_HOST_DRIVER; 3344 ioc_init.Function = MPI_FUNCTION_IOC_INIT; 3345 3346 /* If we are in a recovery mode and we uploaded the FW image, 3347 * then this pointer is not NULL. Skip the upload a second time. 3348 * Set this flag if cached_fw set for either IOC. 3349 */ 3350 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT) 3351 ioc->upload_fw = 1; 3352 else 3353 ioc->upload_fw = 0; 3354 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "upload_fw %d facts.Flags=%x\n", 3355 ioc->name, ioc->upload_fw, ioc->facts.Flags)); 3356 3357 ioc_init.MaxDevices = (U8)ioc->devices_per_bus; 3358 ioc_init.MaxBuses = (U8)ioc->number_of_buses; 3359 3360 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "facts.MsgVersion=%x\n", 3361 ioc->name, ioc->facts.MsgVersion)); 3362 if (ioc->facts.MsgVersion >= MPI_VERSION_01_05) { 3363 // set MsgVersion and HeaderVersion host driver was built with 3364 ioc_init.MsgVersion = cpu_to_le16(MPI_VERSION); 3365 ioc_init.HeaderVersion = cpu_to_le16(MPI_HEADER_VERSION); 3366 3367 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT) { 3368 ioc_init.HostPageBufferSGE = ioc->facts.HostPageBufferSGE; 3369 } else if(mpt_host_page_alloc(ioc, &ioc_init)) 3370 return -99; 3371 } 3372 ioc_init.ReplyFrameSize = cpu_to_le16(ioc->reply_sz); /* in BYTES */ 3373 3374 if (ioc->sg_addr_size == sizeof(u64)) { 3375 /* Save the upper 32-bits of the request 3376 * (reply) and sense buffers. 3377 */ 3378 ioc_init.HostMfaHighAddr = cpu_to_le32((u32)((u64)ioc->alloc_dma >> 32)); 3379 ioc_init.SenseBufferHighAddr = cpu_to_le32((u32)((u64)ioc->sense_buf_pool_dma >> 32)); 3380 } else { 3381 /* Force 32-bit addressing */ 3382 ioc_init.HostMfaHighAddr = cpu_to_le32(0); 3383 ioc_init.SenseBufferHighAddr = cpu_to_le32(0); 3384 } 3385 3386 ioc->facts.CurrentHostMfaHighAddr = ioc_init.HostMfaHighAddr; 3387 ioc->facts.CurrentSenseBufferHighAddr = ioc_init.SenseBufferHighAddr; 3388 ioc->facts.MaxDevices = ioc_init.MaxDevices; 3389 ioc->facts.MaxBuses = ioc_init.MaxBuses; 3390 3391 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOCInit (req @ %p)\n", 3392 ioc->name, &ioc_init)); 3393 3394 r = mpt_handshake_req_reply_wait(ioc, sizeof(IOCInit_t), (u32*)&ioc_init, 3395 sizeof(MPIDefaultReply_t), (u16*)&init_reply, 10 /*seconds*/, sleepFlag); 3396 if (r != 0) { 3397 printk(MYIOC_s_ERR_FMT "Sending IOCInit failed(%d)!\n",ioc->name, r); 3398 return r; 3399 } 3400 3401 /* No need to byte swap the multibyte fields in the reply 3402 * since we don't even look at its contents. 3403 */ 3404 3405 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending PortEnable (req @ %p)\n", 3406 ioc->name, &ioc_init)); 3407 3408 if ((r = SendPortEnable(ioc, 0, sleepFlag)) != 0) { 3409 printk(MYIOC_s_ERR_FMT "Sending PortEnable failed(%d)!\n",ioc->name, r); 3410 return r; 3411 } 3412 3413 /* YIKES! SUPER IMPORTANT!!! 3414 * Poll IocState until _OPERATIONAL while IOC is doing 3415 * LoopInit and TargetDiscovery! 3416 */ 3417 count = 0; 3418 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 60; /* 60 seconds */ 3419 state = mpt_GetIocState(ioc, 1); 3420 while (state != MPI_IOC_STATE_OPERATIONAL && --cntdn) { 3421 if (sleepFlag == CAN_SLEEP) { 3422 msleep(1); 3423 } else { 3424 mdelay(1); 3425 } 3426 3427 if (!cntdn) { 3428 printk(MYIOC_s_ERR_FMT "Wait IOC_OP state timeout(%d)!\n", 3429 ioc->name, (int)((count+5)/HZ)); 3430 return -9; 3431 } 3432 3433 state = mpt_GetIocState(ioc, 1); 3434 count++; 3435 } 3436 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wait IOC_OPERATIONAL state (cnt=%d)\n", 3437 ioc->name, count)); 3438 3439 ioc->aen_event_read_flag=0; 3440 return r; 3441 } 3442 3443 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3444 /** 3445 * SendPortEnable - Send PortEnable request to MPT adapter port. 3446 * @ioc: Pointer to MPT_ADAPTER structure 3447 * @portnum: Port number to enable 3448 * @sleepFlag: Specifies whether the process can sleep 3449 * 3450 * Send PortEnable to bring IOC to OPERATIONAL state. 3451 * 3452 * Returns 0 for success, non-zero for failure. 3453 */ 3454 static int 3455 SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag) 3456 { 3457 PortEnable_t port_enable; 3458 MPIDefaultReply_t reply_buf; 3459 int rc; 3460 int req_sz; 3461 int reply_sz; 3462 3463 /* Destination... */ 3464 reply_sz = sizeof(MPIDefaultReply_t); 3465 memset(&reply_buf, 0, reply_sz); 3466 3467 req_sz = sizeof(PortEnable_t); 3468 memset(&port_enable, 0, req_sz); 3469 3470 port_enable.Function = MPI_FUNCTION_PORT_ENABLE; 3471 port_enable.PortNumber = portnum; 3472 /* port_enable.ChainOffset = 0; */ 3473 /* port_enable.MsgFlags = 0; */ 3474 /* port_enable.MsgContext = 0; */ 3475 3476 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending Port(%d)Enable (req @ %p)\n", 3477 ioc->name, portnum, &port_enable)); 3478 3479 /* RAID FW may take a long time to enable 3480 */ 3481 if (ioc->ir_firmware || ioc->bus_type == SAS) { 3482 rc = mpt_handshake_req_reply_wait(ioc, req_sz, 3483 (u32*)&port_enable, reply_sz, (u16*)&reply_buf, 3484 300 /*seconds*/, sleepFlag); 3485 } else { 3486 rc = mpt_handshake_req_reply_wait(ioc, req_sz, 3487 (u32*)&port_enable, reply_sz, (u16*)&reply_buf, 3488 30 /*seconds*/, sleepFlag); 3489 } 3490 return rc; 3491 } 3492 3493 /** 3494 * mpt_alloc_fw_memory - allocate firmware memory 3495 * @ioc: Pointer to MPT_ADAPTER structure 3496 * @size: total FW bytes 3497 * 3498 * If memory has already been allocated, the same (cached) value 3499 * is returned. 3500 * 3501 * Return 0 if successful, or non-zero for failure 3502 **/ 3503 int 3504 mpt_alloc_fw_memory(MPT_ADAPTER *ioc, int size) 3505 { 3506 int rc; 3507 3508 if (ioc->cached_fw) { 3509 rc = 0; /* use already allocated memory */ 3510 goto out; 3511 } 3512 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) { 3513 ioc->cached_fw = ioc->alt_ioc->cached_fw; /* use alt_ioc's memory */ 3514 ioc->cached_fw_dma = ioc->alt_ioc->cached_fw_dma; 3515 rc = 0; 3516 goto out; 3517 } 3518 ioc->cached_fw = pci_alloc_consistent(ioc->pcidev, size, &ioc->cached_fw_dma); 3519 if (!ioc->cached_fw) { 3520 printk(MYIOC_s_ERR_FMT "Unable to allocate memory for the cached firmware image!\n", 3521 ioc->name); 3522 rc = -1; 3523 } else { 3524 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Image @ %p[%p], sz=%d[%x] bytes\n", 3525 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, size, size)); 3526 ioc->alloc_total += size; 3527 rc = 0; 3528 } 3529 out: 3530 return rc; 3531 } 3532 3533 /** 3534 * mpt_free_fw_memory - free firmware memory 3535 * @ioc: Pointer to MPT_ADAPTER structure 3536 * 3537 * If alt_img is NULL, delete from ioc structure. 3538 * Else, delete a secondary image in same format. 3539 **/ 3540 void 3541 mpt_free_fw_memory(MPT_ADAPTER *ioc) 3542 { 3543 int sz; 3544 3545 if (!ioc->cached_fw) 3546 return; 3547 3548 sz = ioc->facts.FWImageSize; 3549 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "free_fw_memory: FW Image @ %p[%p], sz=%d[%x] bytes\n", 3550 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz)); 3551 pci_free_consistent(ioc->pcidev, sz, ioc->cached_fw, ioc->cached_fw_dma); 3552 ioc->alloc_total -= sz; 3553 ioc->cached_fw = NULL; 3554 } 3555 3556 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3557 /** 3558 * mpt_do_upload - Construct and Send FWUpload request to MPT adapter port. 3559 * @ioc: Pointer to MPT_ADAPTER structure 3560 * @sleepFlag: Specifies whether the process can sleep 3561 * 3562 * Returns 0 for success, >0 for handshake failure 3563 * <0 for fw upload failure. 3564 * 3565 * Remark: If bound IOC and a successful FWUpload was performed 3566 * on the bound IOC, the second image is discarded 3567 * and memory is free'd. Both channels must upload to prevent 3568 * IOC from running in degraded mode. 3569 */ 3570 static int 3571 mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag) 3572 { 3573 u8 reply[sizeof(FWUploadReply_t)]; 3574 FWUpload_t *prequest; 3575 FWUploadReply_t *preply; 3576 FWUploadTCSGE_t *ptcsge; 3577 u32 flagsLength; 3578 int ii, sz, reply_sz; 3579 int cmdStatus; 3580 int request_size; 3581 /* If the image size is 0, we are done. 3582 */ 3583 if ((sz = ioc->facts.FWImageSize) == 0) 3584 return 0; 3585 3586 if (mpt_alloc_fw_memory(ioc, ioc->facts.FWImageSize) != 0) 3587 return -ENOMEM; 3588 3589 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": FW Image @ %p[%p], sz=%d[%x] bytes\n", 3590 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz)); 3591 3592 prequest = (sleepFlag == NO_SLEEP) ? kzalloc(ioc->req_sz, GFP_ATOMIC) : 3593 kzalloc(ioc->req_sz, GFP_KERNEL); 3594 if (!prequest) { 3595 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed " 3596 "while allocating memory \n", ioc->name)); 3597 mpt_free_fw_memory(ioc); 3598 return -ENOMEM; 3599 } 3600 3601 preply = (FWUploadReply_t *)&reply; 3602 3603 reply_sz = sizeof(reply); 3604 memset(preply, 0, reply_sz); 3605 3606 prequest->ImageType = MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM; 3607 prequest->Function = MPI_FUNCTION_FW_UPLOAD; 3608 3609 ptcsge = (FWUploadTCSGE_t *) &prequest->SGL; 3610 ptcsge->DetailsLength = 12; 3611 ptcsge->Flags = MPI_SGE_FLAGS_TRANSACTION_ELEMENT; 3612 ptcsge->ImageSize = cpu_to_le32(sz); 3613 ptcsge++; 3614 3615 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ | sz; 3616 ioc->add_sge((char *)ptcsge, flagsLength, ioc->cached_fw_dma); 3617 request_size = offsetof(FWUpload_t, SGL) + sizeof(FWUploadTCSGE_t) + 3618 ioc->SGE_size; 3619 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending FW Upload " 3620 " (req @ %p) fw_size=%d mf_request_size=%d\n", ioc->name, prequest, 3621 ioc->facts.FWImageSize, request_size)); 3622 DBG_DUMP_FW_REQUEST_FRAME(ioc, (u32 *)prequest); 3623 3624 ii = mpt_handshake_req_reply_wait(ioc, request_size, (u32 *)prequest, 3625 reply_sz, (u16 *)preply, 65 /*seconds*/, sleepFlag); 3626 3627 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Upload completed " 3628 "rc=%x \n", ioc->name, ii)); 3629 3630 cmdStatus = -EFAULT; 3631 if (ii == 0) { 3632 /* Handshake transfer was complete and successful. 3633 * Check the Reply Frame. 3634 */ 3635 int status; 3636 status = le16_to_cpu(preply->IOCStatus) & 3637 MPI_IOCSTATUS_MASK; 3638 if (status == MPI_IOCSTATUS_SUCCESS && 3639 ioc->facts.FWImageSize == 3640 le32_to_cpu(preply->ActualImageSize)) 3641 cmdStatus = 0; 3642 } 3643 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": do_upload cmdStatus=%d \n", 3644 ioc->name, cmdStatus)); 3645 3646 3647 if (cmdStatus) { 3648 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed, " 3649 "freeing image \n", ioc->name)); 3650 mpt_free_fw_memory(ioc); 3651 } 3652 kfree(prequest); 3653 3654 return cmdStatus; 3655 } 3656 3657 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3658 /** 3659 * mpt_downloadboot - DownloadBoot code 3660 * @ioc: Pointer to MPT_ADAPTER structure 3661 * @pFwHeader: Pointer to firmware header info 3662 * @sleepFlag: Specifies whether the process can sleep 3663 * 3664 * FwDownloadBoot requires Programmed IO access. 3665 * 3666 * Returns 0 for success 3667 * -1 FW Image size is 0 3668 * -2 No valid cached_fw Pointer 3669 * <0 for fw upload failure. 3670 */ 3671 static int 3672 mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag) 3673 { 3674 MpiExtImageHeader_t *pExtImage; 3675 u32 fwSize; 3676 u32 diag0val; 3677 int count; 3678 u32 *ptrFw; 3679 u32 diagRwData; 3680 u32 nextImage; 3681 u32 load_addr; 3682 u32 ioc_state=0; 3683 3684 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot: fw size 0x%x (%d), FW Ptr %p\n", 3685 ioc->name, pFwHeader->ImageSize, pFwHeader->ImageSize, pFwHeader)); 3686 3687 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 3688 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); 3689 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE); 3690 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE); 3691 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE); 3692 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); 3693 3694 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM)); 3695 3696 /* wait 1 msec */ 3697 if (sleepFlag == CAN_SLEEP) { 3698 msleep(1); 3699 } else { 3700 mdelay (1); 3701 } 3702 3703 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 3704 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER); 3705 3706 for (count = 0; count < 30; count ++) { 3707 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 3708 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) { 3709 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RESET_ADAPTER cleared, count=%d\n", 3710 ioc->name, count)); 3711 break; 3712 } 3713 /* wait .1 sec */ 3714 if (sleepFlag == CAN_SLEEP) { 3715 msleep (100); 3716 } else { 3717 mdelay (100); 3718 } 3719 } 3720 3721 if ( count == 30 ) { 3722 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot failed! " 3723 "Unable to get MPI_DIAG_DRWE mode, diag0val=%x\n", 3724 ioc->name, diag0val)); 3725 return -3; 3726 } 3727 3728 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 3729 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); 3730 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE); 3731 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE); 3732 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE); 3733 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); 3734 3735 /* Set the DiagRwEn and Disable ARM bits */ 3736 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_RW_ENABLE | MPI_DIAG_DISABLE_ARM)); 3737 3738 fwSize = (pFwHeader->ImageSize + 3)/4; 3739 ptrFw = (u32 *) pFwHeader; 3740 3741 /* Write the LoadStartAddress to the DiagRw Address Register 3742 * using Programmed IO 3743 */ 3744 if (ioc->errata_flag_1064) 3745 pci_enable_io_access(ioc->pcidev); 3746 3747 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress); 3748 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "LoadStart addr written 0x%x \n", 3749 ioc->name, pFwHeader->LoadStartAddress)); 3750 3751 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write FW Image: 0x%x bytes @ %p\n", 3752 ioc->name, fwSize*4, ptrFw)); 3753 while (fwSize--) { 3754 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++); 3755 } 3756 3757 nextImage = pFwHeader->NextImageHeaderOffset; 3758 while (nextImage) { 3759 pExtImage = (MpiExtImageHeader_t *) ((char *)pFwHeader + nextImage); 3760 3761 load_addr = pExtImage->LoadStartAddress; 3762 3763 fwSize = (pExtImage->ImageSize + 3) >> 2; 3764 ptrFw = (u32 *)pExtImage; 3765 3766 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write Ext Image: 0x%x (%d) bytes @ %p load_addr=%x\n", 3767 ioc->name, fwSize*4, fwSize*4, ptrFw, load_addr)); 3768 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, load_addr); 3769 3770 while (fwSize--) { 3771 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++); 3772 } 3773 nextImage = pExtImage->NextImageHeaderOffset; 3774 } 3775 3776 /* Write the IopResetVectorRegAddr */ 3777 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Addr=%x! \n", ioc->name, pFwHeader->IopResetRegAddr)); 3778 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->IopResetRegAddr); 3779 3780 /* Write the IopResetVectorValue */ 3781 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Value=%x! \n", ioc->name, pFwHeader->IopResetVectorValue)); 3782 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, pFwHeader->IopResetVectorValue); 3783 3784 /* Clear the internal flash bad bit - autoincrementing register, 3785 * so must do two writes. 3786 */ 3787 if (ioc->bus_type == SPI) { 3788 /* 3789 * 1030 and 1035 H/W errata, workaround to access 3790 * the ClearFlashBadSignatureBit 3791 */ 3792 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000); 3793 diagRwData = CHIPREG_PIO_READ32(&ioc->pio_chip->DiagRwData); 3794 diagRwData |= 0x40000000; 3795 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000); 3796 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData); 3797 3798 } else /* if((ioc->bus_type == SAS) || (ioc->bus_type == FC)) */ { 3799 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 3800 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | 3801 MPI_DIAG_CLEAR_FLASH_BAD_SIG); 3802 3803 /* wait 1 msec */ 3804 if (sleepFlag == CAN_SLEEP) { 3805 msleep (1); 3806 } else { 3807 mdelay (1); 3808 } 3809 } 3810 3811 if (ioc->errata_flag_1064) 3812 pci_disable_io_access(ioc->pcidev); 3813 3814 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 3815 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot diag0val=%x, " 3816 "turning off PREVENT_IOC_BOOT, DISABLE_ARM, RW_ENABLE\n", 3817 ioc->name, diag0val)); 3818 diag0val &= ~(MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM | MPI_DIAG_RW_ENABLE); 3819 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot now diag0val=%x\n", 3820 ioc->name, diag0val)); 3821 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val); 3822 3823 /* Write 0xFF to reset the sequencer */ 3824 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 3825 3826 if (ioc->bus_type == SAS) { 3827 ioc_state = mpt_GetIocState(ioc, 0); 3828 if ( (GetIocFacts(ioc, sleepFlag, 3829 MPT_HOSTEVENT_IOC_BRINGUP)) != 0 ) { 3830 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "GetIocFacts failed: IocState=%x\n", 3831 ioc->name, ioc_state)); 3832 return -EFAULT; 3833 } 3834 } 3835 3836 for (count=0; count<HZ*20; count++) { 3837 if ((ioc_state = mpt_GetIocState(ioc, 0)) & MPI_IOC_STATE_READY) { 3838 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3839 "downloadboot successful! (count=%d) IocState=%x\n", 3840 ioc->name, count, ioc_state)); 3841 if (ioc->bus_type == SAS) { 3842 return 0; 3843 } 3844 if ((SendIocInit(ioc, sleepFlag)) != 0) { 3845 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3846 "downloadboot: SendIocInit failed\n", 3847 ioc->name)); 3848 return -EFAULT; 3849 } 3850 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3851 "downloadboot: SendIocInit successful\n", 3852 ioc->name)); 3853 return 0; 3854 } 3855 if (sleepFlag == CAN_SLEEP) { 3856 msleep (10); 3857 } else { 3858 mdelay (10); 3859 } 3860 } 3861 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT 3862 "downloadboot failed! IocState=%x\n",ioc->name, ioc_state)); 3863 return -EFAULT; 3864 } 3865 3866 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3867 /** 3868 * KickStart - Perform hard reset of MPT adapter. 3869 * @ioc: Pointer to MPT_ADAPTER structure 3870 * @force: Force hard reset 3871 * @sleepFlag: Specifies whether the process can sleep 3872 * 3873 * This routine places MPT adapter in diagnostic mode via the 3874 * WriteSequence register, and then performs a hard reset of adapter 3875 * via the Diagnostic register. 3876 * 3877 * Inputs: sleepflag - CAN_SLEEP (non-interrupt thread) 3878 * or NO_SLEEP (interrupt thread, use mdelay) 3879 * force - 1 if doorbell active, board fault state 3880 * board operational, IOC_RECOVERY or 3881 * IOC_BRINGUP and there is an alt_ioc. 3882 * 0 else 3883 * 3884 * Returns: 3885 * 1 - hard reset, READY 3886 * 0 - no reset due to History bit, READY 3887 * -1 - no reset due to History bit but not READY 3888 * OR reset but failed to come READY 3889 * -2 - no reset, could not enter DIAG mode 3890 * -3 - reset but bad FW bit 3891 */ 3892 static int 3893 KickStart(MPT_ADAPTER *ioc, int force, int sleepFlag) 3894 { 3895 int hard_reset_done = 0; 3896 u32 ioc_state=0; 3897 int cnt,cntdn; 3898 3899 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStarting!\n", ioc->name)); 3900 if (ioc->bus_type == SPI) { 3901 /* Always issue a Msg Unit Reset first. This will clear some 3902 * SCSI bus hang conditions. 3903 */ 3904 SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag); 3905 3906 if (sleepFlag == CAN_SLEEP) { 3907 msleep (1000); 3908 } else { 3909 mdelay (1000); 3910 } 3911 } 3912 3913 hard_reset_done = mpt_diag_reset(ioc, force, sleepFlag); 3914 if (hard_reset_done < 0) 3915 return hard_reset_done; 3916 3917 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset successful!\n", 3918 ioc->name)); 3919 3920 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 2; /* 2 seconds */ 3921 for (cnt=0; cnt<cntdn; cnt++) { 3922 ioc_state = mpt_GetIocState(ioc, 1); 3923 if ((ioc_state == MPI_IOC_STATE_READY) || (ioc_state == MPI_IOC_STATE_OPERATIONAL)) { 3924 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStart successful! (cnt=%d)\n", 3925 ioc->name, cnt)); 3926 return hard_reset_done; 3927 } 3928 if (sleepFlag == CAN_SLEEP) { 3929 msleep (10); 3930 } else { 3931 mdelay (10); 3932 } 3933 } 3934 3935 dinitprintk(ioc, printk(MYIOC_s_ERR_FMT "Failed to come READY after reset! IocState=%x\n", 3936 ioc->name, mpt_GetIocState(ioc, 0))); 3937 return -1; 3938 } 3939 3940 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 3941 /** 3942 * mpt_diag_reset - Perform hard reset of the adapter. 3943 * @ioc: Pointer to MPT_ADAPTER structure 3944 * @ignore: Set if to honor and clear to ignore 3945 * the reset history bit 3946 * @sleepFlag: CAN_SLEEP if called in a non-interrupt thread, 3947 * else set to NO_SLEEP (use mdelay instead) 3948 * 3949 * This routine places the adapter in diagnostic mode via the 3950 * WriteSequence register and then performs a hard reset of adapter 3951 * via the Diagnostic register. Adapter should be in ready state 3952 * upon successful completion. 3953 * 3954 * Returns: 1 hard reset successful 3955 * 0 no reset performed because reset history bit set 3956 * -2 enabling diagnostic mode failed 3957 * -3 diagnostic reset failed 3958 */ 3959 static int 3960 mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag) 3961 { 3962 u32 diag0val; 3963 u32 doorbell; 3964 int hard_reset_done = 0; 3965 int count = 0; 3966 u32 diag1val = 0; 3967 MpiFwHeader_t *cached_fw; /* Pointer to FW */ 3968 u8 cb_idx; 3969 3970 /* Clear any existing interrupts */ 3971 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 3972 3973 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) { 3974 3975 if (!ignore) 3976 return 0; 3977 3978 drsprintk(ioc, printk(MYIOC_s_WARN_FMT "%s: Doorbell=%p; 1078 reset " 3979 "address=%p\n", ioc->name, __func__, 3980 &ioc->chip->Doorbell, &ioc->chip->Reset_1078)); 3981 CHIPREG_WRITE32(&ioc->chip->Reset_1078, 0x07); 3982 if (sleepFlag == CAN_SLEEP) 3983 msleep(1); 3984 else 3985 mdelay(1); 3986 3987 /* 3988 * Call each currently registered protocol IOC reset handler 3989 * with pre-reset indication. 3990 * NOTE: If we're doing _IOC_BRINGUP, there can be no 3991 * MptResetHandlers[] registered yet. 3992 */ 3993 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 3994 if (MptResetHandlers[cb_idx]) 3995 (*(MptResetHandlers[cb_idx]))(ioc, 3996 MPT_IOC_PRE_RESET); 3997 } 3998 3999 for (count = 0; count < 60; count ++) { 4000 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell); 4001 doorbell &= MPI_IOC_STATE_MASK; 4002 4003 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4004 "looking for READY STATE: doorbell=%x" 4005 " count=%d\n", 4006 ioc->name, doorbell, count)); 4007 4008 if (doorbell == MPI_IOC_STATE_READY) { 4009 return 1; 4010 } 4011 4012 /* wait 1 sec */ 4013 if (sleepFlag == CAN_SLEEP) 4014 msleep(1000); 4015 else 4016 mdelay(1000); 4017 } 4018 return -1; 4019 } 4020 4021 /* Use "Diagnostic reset" method! (only thing available!) */ 4022 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4023 4024 if (ioc->debug_level & MPT_DEBUG) { 4025 if (ioc->alt_ioc) 4026 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); 4027 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG1: diag0=%08x, diag1=%08x\n", 4028 ioc->name, diag0val, diag1val)); 4029 } 4030 4031 /* Do the reset if we are told to ignore the reset history 4032 * or if the reset history is 0 4033 */ 4034 if (ignore || !(diag0val & MPI_DIAG_RESET_HISTORY)) { 4035 while ((diag0val & MPI_DIAG_DRWE) == 0) { 4036 /* Write magic sequence to WriteSequence register 4037 * Loop until in diagnostic mode 4038 */ 4039 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 4040 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); 4041 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE); 4042 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE); 4043 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE); 4044 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); 4045 4046 /* wait 100 msec */ 4047 if (sleepFlag == CAN_SLEEP) { 4048 msleep (100); 4049 } else { 4050 mdelay (100); 4051 } 4052 4053 count++; 4054 if (count > 20) { 4055 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n", 4056 ioc->name, diag0val); 4057 return -2; 4058 4059 } 4060 4061 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4062 4063 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wrote magic DiagWriteEn sequence (%x)\n", 4064 ioc->name, diag0val)); 4065 } 4066 4067 if (ioc->debug_level & MPT_DEBUG) { 4068 if (ioc->alt_ioc) 4069 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); 4070 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG2: diag0=%08x, diag1=%08x\n", 4071 ioc->name, diag0val, diag1val)); 4072 } 4073 /* 4074 * Disable the ARM (Bug fix) 4075 * 4076 */ 4077 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_DISABLE_ARM); 4078 mdelay(1); 4079 4080 /* 4081 * Now hit the reset bit in the Diagnostic register 4082 * (THE BIG HAMMER!) (Clears DRWE bit). 4083 */ 4084 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER); 4085 hard_reset_done = 1; 4086 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset performed\n", 4087 ioc->name)); 4088 4089 /* 4090 * Call each currently registered protocol IOC reset handler 4091 * with pre-reset indication. 4092 * NOTE: If we're doing _IOC_BRINGUP, there can be no 4093 * MptResetHandlers[] registered yet. 4094 */ 4095 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 4096 if (MptResetHandlers[cb_idx]) { 4097 mpt_signal_reset(cb_idx, 4098 ioc, MPT_IOC_PRE_RESET); 4099 if (ioc->alt_ioc) { 4100 mpt_signal_reset(cb_idx, 4101 ioc->alt_ioc, MPT_IOC_PRE_RESET); 4102 } 4103 } 4104 } 4105 4106 if (ioc->cached_fw) 4107 cached_fw = (MpiFwHeader_t *)ioc->cached_fw; 4108 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) 4109 cached_fw = (MpiFwHeader_t *)ioc->alt_ioc->cached_fw; 4110 else 4111 cached_fw = NULL; 4112 if (cached_fw) { 4113 /* If the DownloadBoot operation fails, the 4114 * IOC will be left unusable. This is a fatal error 4115 * case. _diag_reset will return < 0 4116 */ 4117 for (count = 0; count < 30; count ++) { 4118 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4119 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) { 4120 break; 4121 } 4122 4123 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "cached_fw: diag0val=%x count=%d\n", 4124 ioc->name, diag0val, count)); 4125 /* wait 1 sec */ 4126 if (sleepFlag == CAN_SLEEP) { 4127 msleep (1000); 4128 } else { 4129 mdelay (1000); 4130 } 4131 } 4132 if ((count = mpt_downloadboot(ioc, cached_fw, sleepFlag)) < 0) { 4133 printk(MYIOC_s_WARN_FMT 4134 "firmware downloadboot failure (%d)!\n", ioc->name, count); 4135 } 4136 4137 } else { 4138 /* Wait for FW to reload and for board 4139 * to go to the READY state. 4140 * Maximum wait is 60 seconds. 4141 * If fail, no error will check again 4142 * with calling program. 4143 */ 4144 for (count = 0; count < 60; count ++) { 4145 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell); 4146 doorbell &= MPI_IOC_STATE_MASK; 4147 4148 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4149 "looking for READY STATE: doorbell=%x" 4150 " count=%d\n", ioc->name, doorbell, count)); 4151 4152 if (doorbell == MPI_IOC_STATE_READY) { 4153 break; 4154 } 4155 4156 /* wait 1 sec */ 4157 if (sleepFlag == CAN_SLEEP) { 4158 msleep (1000); 4159 } else { 4160 mdelay (1000); 4161 } 4162 } 4163 4164 if (doorbell != MPI_IOC_STATE_READY) 4165 printk(MYIOC_s_ERR_FMT "Failed to come READY " 4166 "after reset! IocState=%x", ioc->name, 4167 doorbell); 4168 } 4169 } 4170 4171 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4172 if (ioc->debug_level & MPT_DEBUG) { 4173 if (ioc->alt_ioc) 4174 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); 4175 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG3: diag0=%08x, diag1=%08x\n", 4176 ioc->name, diag0val, diag1val)); 4177 } 4178 4179 /* Clear RESET_HISTORY bit! Place board in the 4180 * diagnostic mode to update the diag register. 4181 */ 4182 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4183 count = 0; 4184 while ((diag0val & MPI_DIAG_DRWE) == 0) { 4185 /* Write magic sequence to WriteSequence register 4186 * Loop until in diagnostic mode 4187 */ 4188 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 4189 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); 4190 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE); 4191 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE); 4192 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE); 4193 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE); 4194 4195 /* wait 100 msec */ 4196 if (sleepFlag == CAN_SLEEP) { 4197 msleep (100); 4198 } else { 4199 mdelay (100); 4200 } 4201 4202 count++; 4203 if (count > 20) { 4204 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n", 4205 ioc->name, diag0val); 4206 break; 4207 } 4208 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4209 } 4210 diag0val &= ~MPI_DIAG_RESET_HISTORY; 4211 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val); 4212 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4213 if (diag0val & MPI_DIAG_RESET_HISTORY) { 4214 printk(MYIOC_s_WARN_FMT "ResetHistory bit failed to clear!\n", 4215 ioc->name); 4216 } 4217 4218 /* Disable Diagnostic Mode 4219 */ 4220 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFFFFFFFF); 4221 4222 /* Check FW reload status flags. 4223 */ 4224 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 4225 if (diag0val & (MPI_DIAG_FLASH_BAD_SIG | MPI_DIAG_RESET_ADAPTER | MPI_DIAG_DISABLE_ARM)) { 4226 printk(MYIOC_s_ERR_FMT "Diagnostic reset FAILED! (%02xh)\n", 4227 ioc->name, diag0val); 4228 return -3; 4229 } 4230 4231 if (ioc->debug_level & MPT_DEBUG) { 4232 if (ioc->alt_ioc) 4233 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic); 4234 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG4: diag0=%08x, diag1=%08x\n", 4235 ioc->name, diag0val, diag1val)); 4236 } 4237 4238 /* 4239 * Reset flag that says we've enabled event notification 4240 */ 4241 ioc->facts.EventState = 0; 4242 4243 if (ioc->alt_ioc) 4244 ioc->alt_ioc->facts.EventState = 0; 4245 4246 return hard_reset_done; 4247 } 4248 4249 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4250 /** 4251 * SendIocReset - Send IOCReset request to MPT adapter. 4252 * @ioc: Pointer to MPT_ADAPTER structure 4253 * @reset_type: reset type, expected values are 4254 * %MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET or %MPI_FUNCTION_IO_UNIT_RESET 4255 * @sleepFlag: Specifies whether the process can sleep 4256 * 4257 * Send IOCReset request to the MPT adapter. 4258 * 4259 * Returns 0 for success, non-zero for failure. 4260 */ 4261 static int 4262 SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag) 4263 { 4264 int r; 4265 u32 state; 4266 int cntdn, count; 4267 4268 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOC reset(0x%02x)!\n", 4269 ioc->name, reset_type)); 4270 CHIPREG_WRITE32(&ioc->chip->Doorbell, reset_type<<MPI_DOORBELL_FUNCTION_SHIFT); 4271 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) 4272 return r; 4273 4274 /* FW ACK'd request, wait for READY state 4275 */ 4276 count = 0; 4277 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 15; /* 15 seconds */ 4278 4279 while ((state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) { 4280 cntdn--; 4281 count++; 4282 if (!cntdn) { 4283 if (sleepFlag != CAN_SLEEP) 4284 count *= 10; 4285 4286 printk(MYIOC_s_ERR_FMT 4287 "Wait IOC_READY state (0x%x) timeout(%d)!\n", 4288 ioc->name, state, (int)((count+5)/HZ)); 4289 return -ETIME; 4290 } 4291 4292 if (sleepFlag == CAN_SLEEP) { 4293 msleep(1); 4294 } else { 4295 mdelay (1); /* 1 msec delay */ 4296 } 4297 } 4298 4299 /* TODO! 4300 * Cleanup all event stuff for this IOC; re-issue EventNotification 4301 * request if needed. 4302 */ 4303 if (ioc->facts.Function) 4304 ioc->facts.EventState = 0; 4305 4306 return 0; 4307 } 4308 4309 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4310 /** 4311 * initChainBuffers - Allocate memory for and initialize chain buffers 4312 * @ioc: Pointer to MPT_ADAPTER structure 4313 * 4314 * Allocates memory for and initializes chain buffers, 4315 * chain buffer control arrays and spinlock. 4316 */ 4317 static int 4318 initChainBuffers(MPT_ADAPTER *ioc) 4319 { 4320 u8 *mem; 4321 int sz, ii, num_chain; 4322 int scale, num_sge, numSGE; 4323 4324 /* ReqToChain size must equal the req_depth 4325 * index = req_idx 4326 */ 4327 if (ioc->ReqToChain == NULL) { 4328 sz = ioc->req_depth * sizeof(int); 4329 mem = kmalloc(sz, GFP_ATOMIC); 4330 if (mem == NULL) 4331 return -1; 4332 4333 ioc->ReqToChain = (int *) mem; 4334 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReqToChain alloc @ %p, sz=%d bytes\n", 4335 ioc->name, mem, sz)); 4336 mem = kmalloc(sz, GFP_ATOMIC); 4337 if (mem == NULL) 4338 return -1; 4339 4340 ioc->RequestNB = (int *) mem; 4341 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestNB alloc @ %p, sz=%d bytes\n", 4342 ioc->name, mem, sz)); 4343 } 4344 for (ii = 0; ii < ioc->req_depth; ii++) { 4345 ioc->ReqToChain[ii] = MPT_HOST_NO_CHAIN; 4346 } 4347 4348 /* ChainToChain size must equal the total number 4349 * of chain buffers to be allocated. 4350 * index = chain_idx 4351 * 4352 * Calculate the number of chain buffers needed(plus 1) per I/O 4353 * then multiply the maximum number of simultaneous cmds 4354 * 4355 * num_sge = num sge in request frame + last chain buffer 4356 * scale = num sge per chain buffer if no chain element 4357 */ 4358 scale = ioc->req_sz / ioc->SGE_size; 4359 if (ioc->sg_addr_size == sizeof(u64)) 4360 num_sge = scale + (ioc->req_sz - 60) / ioc->SGE_size; 4361 else 4362 num_sge = 1 + scale + (ioc->req_sz - 64) / ioc->SGE_size; 4363 4364 if (ioc->sg_addr_size == sizeof(u64)) { 4365 numSGE = (scale - 1) * (ioc->facts.MaxChainDepth-1) + scale + 4366 (ioc->req_sz - 60) / ioc->SGE_size; 4367 } else { 4368 numSGE = 1 + (scale - 1) * (ioc->facts.MaxChainDepth-1) + 4369 scale + (ioc->req_sz - 64) / ioc->SGE_size; 4370 } 4371 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "num_sge=%d numSGE=%d\n", 4372 ioc->name, num_sge, numSGE)); 4373 4374 if (ioc->bus_type == FC) { 4375 if (numSGE > MPT_SCSI_FC_SG_DEPTH) 4376 numSGE = MPT_SCSI_FC_SG_DEPTH; 4377 } else { 4378 if (numSGE > MPT_SCSI_SG_DEPTH) 4379 numSGE = MPT_SCSI_SG_DEPTH; 4380 } 4381 4382 num_chain = 1; 4383 while (numSGE - num_sge > 0) { 4384 num_chain++; 4385 num_sge += (scale - 1); 4386 } 4387 num_chain++; 4388 4389 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Now numSGE=%d num_sge=%d num_chain=%d\n", 4390 ioc->name, numSGE, num_sge, num_chain)); 4391 4392 if (ioc->bus_type == SPI) 4393 num_chain *= MPT_SCSI_CAN_QUEUE; 4394 else if (ioc->bus_type == SAS) 4395 num_chain *= MPT_SAS_CAN_QUEUE; 4396 else 4397 num_chain *= MPT_FC_CAN_QUEUE; 4398 4399 ioc->num_chain = num_chain; 4400 4401 sz = num_chain * sizeof(int); 4402 if (ioc->ChainToChain == NULL) { 4403 mem = kmalloc(sz, GFP_ATOMIC); 4404 if (mem == NULL) 4405 return -1; 4406 4407 ioc->ChainToChain = (int *) mem; 4408 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainToChain alloc @ %p, sz=%d bytes\n", 4409 ioc->name, mem, sz)); 4410 } else { 4411 mem = (u8 *) ioc->ChainToChain; 4412 } 4413 memset(mem, 0xFF, sz); 4414 return num_chain; 4415 } 4416 4417 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4418 /** 4419 * PrimeIocFifos - Initialize IOC request and reply FIFOs. 4420 * @ioc: Pointer to MPT_ADAPTER structure 4421 * 4422 * This routine allocates memory for the MPT reply and request frame 4423 * pools (if necessary), and primes the IOC reply FIFO with 4424 * reply frames. 4425 * 4426 * Returns 0 for success, non-zero for failure. 4427 */ 4428 static int 4429 PrimeIocFifos(MPT_ADAPTER *ioc) 4430 { 4431 MPT_FRAME_HDR *mf; 4432 unsigned long flags; 4433 dma_addr_t alloc_dma; 4434 u8 *mem; 4435 int i, reply_sz, sz, total_size, num_chain; 4436 u64 dma_mask; 4437 4438 dma_mask = 0; 4439 4440 /* Prime reply FIFO... */ 4441 4442 if (ioc->reply_frames == NULL) { 4443 if ( (num_chain = initChainBuffers(ioc)) < 0) 4444 return -1; 4445 /* 4446 * 1078 errata workaround for the 36GB limitation 4447 */ 4448 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078 && 4449 ioc->dma_mask > DMA_BIT_MASK(35)) { 4450 if (!pci_set_dma_mask(ioc->pcidev, DMA_BIT_MASK(32)) 4451 && !pci_set_consistent_dma_mask(ioc->pcidev, 4452 DMA_BIT_MASK(32))) { 4453 dma_mask = DMA_BIT_MASK(35); 4454 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4455 "setting 35 bit addressing for " 4456 "Request/Reply/Chain and Sense Buffers\n", 4457 ioc->name)); 4458 } else { 4459 /*Reseting DMA mask to 64 bit*/ 4460 pci_set_dma_mask(ioc->pcidev, 4461 DMA_BIT_MASK(64)); 4462 pci_set_consistent_dma_mask(ioc->pcidev, 4463 DMA_BIT_MASK(64)); 4464 4465 printk(MYIOC_s_ERR_FMT 4466 "failed setting 35 bit addressing for " 4467 "Request/Reply/Chain and Sense Buffers\n", 4468 ioc->name); 4469 return -1; 4470 } 4471 } 4472 4473 total_size = reply_sz = (ioc->reply_sz * ioc->reply_depth); 4474 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d bytes, ReplyDepth=%d\n", 4475 ioc->name, ioc->reply_sz, ioc->reply_depth)); 4476 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d[%x] bytes\n", 4477 ioc->name, reply_sz, reply_sz)); 4478 4479 sz = (ioc->req_sz * ioc->req_depth); 4480 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d bytes, RequestDepth=%d\n", 4481 ioc->name, ioc->req_sz, ioc->req_depth)); 4482 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d[%x] bytes\n", 4483 ioc->name, sz, sz)); 4484 total_size += sz; 4485 4486 sz = num_chain * ioc->req_sz; /* chain buffer pool size */ 4487 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d bytes, ChainDepth=%d\n", 4488 ioc->name, ioc->req_sz, num_chain)); 4489 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d[%x] bytes num_chain=%d\n", 4490 ioc->name, sz, sz, num_chain)); 4491 4492 total_size += sz; 4493 mem = dma_alloc_coherent(&ioc->pcidev->dev, total_size, 4494 &alloc_dma, GFP_KERNEL); 4495 if (mem == NULL) { 4496 printk(MYIOC_s_ERR_FMT "Unable to allocate Reply, Request, Chain Buffers!\n", 4497 ioc->name); 4498 goto out_fail; 4499 } 4500 4501 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Total alloc @ %p[%p], sz=%d[%x] bytes\n", 4502 ioc->name, mem, (void *)(ulong)alloc_dma, total_size, total_size)); 4503 4504 memset(mem, 0, total_size); 4505 ioc->alloc_total += total_size; 4506 ioc->alloc = mem; 4507 ioc->alloc_dma = alloc_dma; 4508 ioc->alloc_sz = total_size; 4509 ioc->reply_frames = (MPT_FRAME_HDR *) mem; 4510 ioc->reply_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF); 4511 4512 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n", 4513 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma)); 4514 4515 alloc_dma += reply_sz; 4516 mem += reply_sz; 4517 4518 /* Request FIFO - WE manage this! */ 4519 4520 ioc->req_frames = (MPT_FRAME_HDR *) mem; 4521 ioc->req_frames_dma = alloc_dma; 4522 4523 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffers @ %p[%p]\n", 4524 ioc->name, mem, (void *)(ulong)alloc_dma)); 4525 4526 ioc->req_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF); 4527 4528 for (i = 0; i < ioc->req_depth; i++) { 4529 alloc_dma += ioc->req_sz; 4530 mem += ioc->req_sz; 4531 } 4532 4533 ioc->ChainBuffer = mem; 4534 ioc->ChainBufferDMA = alloc_dma; 4535 4536 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffers @ %p(%p)\n", 4537 ioc->name, ioc->ChainBuffer, (void *)(ulong)ioc->ChainBufferDMA)); 4538 4539 /* Initialize the free chain Q. 4540 */ 4541 4542 INIT_LIST_HEAD(&ioc->FreeChainQ); 4543 4544 /* Post the chain buffers to the FreeChainQ. 4545 */ 4546 mem = (u8 *)ioc->ChainBuffer; 4547 for (i=0; i < num_chain; i++) { 4548 mf = (MPT_FRAME_HDR *) mem; 4549 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeChainQ); 4550 mem += ioc->req_sz; 4551 } 4552 4553 /* Initialize Request frames linked list 4554 */ 4555 alloc_dma = ioc->req_frames_dma; 4556 mem = (u8 *) ioc->req_frames; 4557 4558 spin_lock_irqsave(&ioc->FreeQlock, flags); 4559 INIT_LIST_HEAD(&ioc->FreeQ); 4560 for (i = 0; i < ioc->req_depth; i++) { 4561 mf = (MPT_FRAME_HDR *) mem; 4562 4563 /* Queue REQUESTs *internally*! */ 4564 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeQ); 4565 4566 mem += ioc->req_sz; 4567 } 4568 spin_unlock_irqrestore(&ioc->FreeQlock, flags); 4569 4570 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC); 4571 ioc->sense_buf_pool = dma_alloc_coherent(&ioc->pcidev->dev, sz, 4572 &ioc->sense_buf_pool_dma, GFP_KERNEL); 4573 if (ioc->sense_buf_pool == NULL) { 4574 printk(MYIOC_s_ERR_FMT "Unable to allocate Sense Buffers!\n", 4575 ioc->name); 4576 goto out_fail; 4577 } 4578 4579 ioc->sense_buf_low_dma = (u32) (ioc->sense_buf_pool_dma & 0xFFFFFFFF); 4580 ioc->alloc_total += sz; 4581 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SenseBuffers @ %p[%p]\n", 4582 ioc->name, ioc->sense_buf_pool, (void *)(ulong)ioc->sense_buf_pool_dma)); 4583 4584 } 4585 4586 /* Post Reply frames to FIFO 4587 */ 4588 alloc_dma = ioc->alloc_dma; 4589 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n", 4590 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma)); 4591 4592 for (i = 0; i < ioc->reply_depth; i++) { 4593 /* Write each address to the IOC! */ 4594 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, alloc_dma); 4595 alloc_dma += ioc->reply_sz; 4596 } 4597 4598 if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev, 4599 ioc->dma_mask) && !pci_set_consistent_dma_mask(ioc->pcidev, 4600 ioc->dma_mask)) 4601 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4602 "restoring 64 bit addressing\n", ioc->name)); 4603 4604 return 0; 4605 4606 out_fail: 4607 4608 if (ioc->alloc != NULL) { 4609 sz = ioc->alloc_sz; 4610 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->alloc, 4611 ioc->alloc_dma); 4612 ioc->reply_frames = NULL; 4613 ioc->req_frames = NULL; 4614 ioc->alloc_total -= sz; 4615 } 4616 if (ioc->sense_buf_pool != NULL) { 4617 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC); 4618 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->sense_buf_pool, 4619 ioc->sense_buf_pool_dma); 4620 ioc->sense_buf_pool = NULL; 4621 } 4622 4623 if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev, 4624 DMA_BIT_MASK(64)) && !pci_set_consistent_dma_mask(ioc->pcidev, 4625 DMA_BIT_MASK(64))) 4626 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT 4627 "restoring 64 bit addressing\n", ioc->name)); 4628 4629 return -1; 4630 } 4631 4632 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4633 /** 4634 * mpt_handshake_req_reply_wait - Send MPT request to and receive reply 4635 * from IOC via doorbell handshake method. 4636 * @ioc: Pointer to MPT_ADAPTER structure 4637 * @reqBytes: Size of the request in bytes 4638 * @req: Pointer to MPT request frame 4639 * @replyBytes: Expected size of the reply in bytes 4640 * @u16reply: Pointer to area where reply should be written 4641 * @maxwait: Max wait time for a reply (in seconds) 4642 * @sleepFlag: Specifies whether the process can sleep 4643 * 4644 * NOTES: It is the callers responsibility to byte-swap fields in the 4645 * request which are greater than 1 byte in size. It is also the 4646 * callers responsibility to byte-swap response fields which are 4647 * greater than 1 byte in size. 4648 * 4649 * Returns 0 for success, non-zero for failure. 4650 */ 4651 static int 4652 mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, u32 *req, 4653 int replyBytes, u16 *u16reply, int maxwait, int sleepFlag) 4654 { 4655 MPIDefaultReply_t *mptReply; 4656 int failcnt = 0; 4657 int t; 4658 4659 /* 4660 * Get ready to cache a handshake reply 4661 */ 4662 ioc->hs_reply_idx = 0; 4663 mptReply = (MPIDefaultReply_t *) ioc->hs_reply; 4664 mptReply->MsgLength = 0; 4665 4666 /* 4667 * Make sure there are no doorbells (WRITE 0 to IntStatus reg), 4668 * then tell IOC that we want to handshake a request of N words. 4669 * (WRITE u32val to Doorbell reg). 4670 */ 4671 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4672 CHIPREG_WRITE32(&ioc->chip->Doorbell, 4673 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) | 4674 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT))); 4675 4676 /* 4677 * Wait for IOC's doorbell handshake int 4678 */ 4679 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) 4680 failcnt++; 4681 4682 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request start reqBytes=%d, WaitCnt=%d%s\n", 4683 ioc->name, reqBytes, t, failcnt ? " - MISSING DOORBELL HANDSHAKE!" : "")); 4684 4685 /* Read doorbell and check for active bit */ 4686 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE)) 4687 return -1; 4688 4689 /* 4690 * Clear doorbell int (WRITE 0 to IntStatus reg), 4691 * then wait for IOC to ACKnowledge that it's ready for 4692 * our handshake request. 4693 */ 4694 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4695 if (!failcnt && (t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) 4696 failcnt++; 4697 4698 if (!failcnt) { 4699 int ii; 4700 u8 *req_as_bytes = (u8 *) req; 4701 4702 /* 4703 * Stuff request words via doorbell handshake, 4704 * with ACK from IOC for each. 4705 */ 4706 for (ii = 0; !failcnt && ii < reqBytes/4; ii++) { 4707 u32 word = ((req_as_bytes[(ii*4) + 0] << 0) | 4708 (req_as_bytes[(ii*4) + 1] << 8) | 4709 (req_as_bytes[(ii*4) + 2] << 16) | 4710 (req_as_bytes[(ii*4) + 3] << 24)); 4711 4712 CHIPREG_WRITE32(&ioc->chip->Doorbell, word); 4713 if ((t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) 4714 failcnt++; 4715 } 4716 4717 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Handshake request frame (@%p) header\n", ioc->name, req)); 4718 DBG_DUMP_REQUEST_FRAME_HDR(ioc, (u32 *)req); 4719 4720 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request post done, WaitCnt=%d%s\n", 4721 ioc->name, t, failcnt ? " - MISSING DOORBELL ACK!" : "")); 4722 4723 /* 4724 * Wait for completion of doorbell handshake reply from the IOC 4725 */ 4726 if (!failcnt && (t = WaitForDoorbellReply(ioc, maxwait, sleepFlag)) < 0) 4727 failcnt++; 4728 4729 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake reply count=%d%s\n", 4730 ioc->name, t, failcnt ? " - MISSING DOORBELL REPLY!" : "")); 4731 4732 /* 4733 * Copy out the cached reply... 4734 */ 4735 for (ii=0; ii < min(replyBytes/2,mptReply->MsgLength*2); ii++) 4736 u16reply[ii] = ioc->hs_reply[ii]; 4737 } else { 4738 return -99; 4739 } 4740 4741 return -failcnt; 4742 } 4743 4744 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4745 /** 4746 * WaitForDoorbellAck - Wait for IOC doorbell handshake acknowledge 4747 * @ioc: Pointer to MPT_ADAPTER structure 4748 * @howlong: How long to wait (in seconds) 4749 * @sleepFlag: Specifies whether the process can sleep 4750 * 4751 * This routine waits (up to ~2 seconds max) for IOC doorbell 4752 * handshake ACKnowledge, indicated by the IOP_DOORBELL_STATUS 4753 * bit in its IntStatus register being clear. 4754 * 4755 * Returns a negative value on failure, else wait loop count. 4756 */ 4757 static int 4758 WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag) 4759 { 4760 int cntdn; 4761 int count = 0; 4762 u32 intstat=0; 4763 4764 cntdn = 1000 * howlong; 4765 4766 if (sleepFlag == CAN_SLEEP) { 4767 while (--cntdn) { 4768 msleep (1); 4769 intstat = CHIPREG_READ32(&ioc->chip->IntStatus); 4770 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS)) 4771 break; 4772 count++; 4773 } 4774 } else { 4775 while (--cntdn) { 4776 udelay (1000); 4777 intstat = CHIPREG_READ32(&ioc->chip->IntStatus); 4778 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS)) 4779 break; 4780 count++; 4781 } 4782 } 4783 4784 if (cntdn) { 4785 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell ACK (count=%d)\n", 4786 ioc->name, count)); 4787 return count; 4788 } 4789 4790 printk(MYIOC_s_ERR_FMT "Doorbell ACK timeout (count=%d), IntStatus=%x!\n", 4791 ioc->name, count, intstat); 4792 return -1; 4793 } 4794 4795 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4796 /** 4797 * WaitForDoorbellInt - Wait for IOC to set its doorbell interrupt bit 4798 * @ioc: Pointer to MPT_ADAPTER structure 4799 * @howlong: How long to wait (in seconds) 4800 * @sleepFlag: Specifies whether the process can sleep 4801 * 4802 * This routine waits (up to ~2 seconds max) for IOC doorbell interrupt 4803 * (MPI_HIS_DOORBELL_INTERRUPT) to be set in the IntStatus register. 4804 * 4805 * Returns a negative value on failure, else wait loop count. 4806 */ 4807 static int 4808 WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag) 4809 { 4810 int cntdn; 4811 int count = 0; 4812 u32 intstat=0; 4813 4814 cntdn = 1000 * howlong; 4815 if (sleepFlag == CAN_SLEEP) { 4816 while (--cntdn) { 4817 intstat = CHIPREG_READ32(&ioc->chip->IntStatus); 4818 if (intstat & MPI_HIS_DOORBELL_INTERRUPT) 4819 break; 4820 msleep(1); 4821 count++; 4822 } 4823 } else { 4824 while (--cntdn) { 4825 intstat = CHIPREG_READ32(&ioc->chip->IntStatus); 4826 if (intstat & MPI_HIS_DOORBELL_INTERRUPT) 4827 break; 4828 udelay (1000); 4829 count++; 4830 } 4831 } 4832 4833 if (cntdn) { 4834 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell INT (cnt=%d) howlong=%d\n", 4835 ioc->name, count, howlong)); 4836 return count; 4837 } 4838 4839 printk(MYIOC_s_ERR_FMT "Doorbell INT timeout (count=%d), IntStatus=%x!\n", 4840 ioc->name, count, intstat); 4841 return -1; 4842 } 4843 4844 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4845 /** 4846 * WaitForDoorbellReply - Wait for and capture an IOC handshake reply. 4847 * @ioc: Pointer to MPT_ADAPTER structure 4848 * @howlong: How long to wait (in seconds) 4849 * @sleepFlag: Specifies whether the process can sleep 4850 * 4851 * This routine polls the IOC for a handshake reply, 16 bits at a time. 4852 * Reply is cached to IOC private area large enough to hold a maximum 4853 * of 128 bytes of reply data. 4854 * 4855 * Returns a negative value on failure, else size of reply in WORDS. 4856 */ 4857 static int 4858 WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag) 4859 { 4860 int u16cnt = 0; 4861 int failcnt = 0; 4862 int t; 4863 u16 *hs_reply = ioc->hs_reply; 4864 volatile MPIDefaultReply_t *mptReply = (MPIDefaultReply_t *) ioc->hs_reply; 4865 u16 hword; 4866 4867 hs_reply[0] = hs_reply[1] = hs_reply[7] = 0; 4868 4869 /* 4870 * Get first two u16's so we can look at IOC's intended reply MsgLength 4871 */ 4872 u16cnt=0; 4873 if ((t = WaitForDoorbellInt(ioc, howlong, sleepFlag)) < 0) { 4874 failcnt++; 4875 } else { 4876 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF); 4877 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4878 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) 4879 failcnt++; 4880 else { 4881 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF); 4882 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4883 } 4884 } 4885 4886 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitCnt=%d First handshake reply word=%08x%s\n", 4887 ioc->name, t, le32_to_cpu(*(u32 *)hs_reply), 4888 failcnt ? " - MISSING DOORBELL HANDSHAKE!" : "")); 4889 4890 /* 4891 * If no error (and IOC said MsgLength is > 0), piece together 4892 * reply 16 bits at a time. 4893 */ 4894 for (u16cnt=2; !failcnt && u16cnt < (2 * mptReply->MsgLength); u16cnt++) { 4895 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) 4896 failcnt++; 4897 hword = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF); 4898 /* don't overflow our IOC hs_reply[] buffer! */ 4899 if (u16cnt < ARRAY_SIZE(ioc->hs_reply)) 4900 hs_reply[u16cnt] = hword; 4901 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4902 } 4903 4904 if (!failcnt && (t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) 4905 failcnt++; 4906 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0); 4907 4908 if (failcnt) { 4909 printk(MYIOC_s_ERR_FMT "Handshake reply failure!\n", 4910 ioc->name); 4911 return -failcnt; 4912 } 4913 #if 0 4914 else if (u16cnt != (2 * mptReply->MsgLength)) { 4915 return -101; 4916 } 4917 else if ((mptReply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) { 4918 return -102; 4919 } 4920 #endif 4921 4922 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got Handshake reply:\n", ioc->name)); 4923 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mptReply); 4924 4925 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell REPLY WaitCnt=%d (sz=%d)\n", 4926 ioc->name, t, u16cnt/2)); 4927 return u16cnt/2; 4928 } 4929 4930 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 4931 /** 4932 * GetLanConfigPages - Fetch LANConfig pages. 4933 * @ioc: Pointer to MPT_ADAPTER structure 4934 * 4935 * Return: 0 for success 4936 * -ENOMEM if no memory available 4937 * -EPERM if not allowed due to ISR context 4938 * -EAGAIN if no msg frames currently available 4939 * -EFAULT for non-successful reply or no reply (timeout) 4940 */ 4941 static int 4942 GetLanConfigPages(MPT_ADAPTER *ioc) 4943 { 4944 ConfigPageHeader_t hdr; 4945 CONFIGPARMS cfg; 4946 LANPage0_t *ppage0_alloc; 4947 dma_addr_t page0_dma; 4948 LANPage1_t *ppage1_alloc; 4949 dma_addr_t page1_dma; 4950 int rc = 0; 4951 int data_sz; 4952 int copy_sz; 4953 4954 /* Get LAN Page 0 header */ 4955 hdr.PageVersion = 0; 4956 hdr.PageLength = 0; 4957 hdr.PageNumber = 0; 4958 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN; 4959 cfg.cfghdr.hdr = &hdr; 4960 cfg.physAddr = -1; 4961 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 4962 cfg.dir = 0; 4963 cfg.pageAddr = 0; 4964 cfg.timeout = 0; 4965 4966 if ((rc = mpt_config(ioc, &cfg)) != 0) 4967 return rc; 4968 4969 if (hdr.PageLength > 0) { 4970 data_sz = hdr.PageLength * 4; 4971 ppage0_alloc = pci_alloc_consistent(ioc->pcidev, data_sz, &page0_dma); 4972 rc = -ENOMEM; 4973 if (ppage0_alloc) { 4974 memset((u8 *)ppage0_alloc, 0, data_sz); 4975 cfg.physAddr = page0_dma; 4976 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 4977 4978 if ((rc = mpt_config(ioc, &cfg)) == 0) { 4979 /* save the data */ 4980 copy_sz = min_t(int, sizeof(LANPage0_t), data_sz); 4981 memcpy(&ioc->lan_cnfg_page0, ppage0_alloc, copy_sz); 4982 4983 } 4984 4985 pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage0_alloc, page0_dma); 4986 4987 /* FIXME! 4988 * Normalize endianness of structure data, 4989 * by byte-swapping all > 1 byte fields! 4990 */ 4991 4992 } 4993 4994 if (rc) 4995 return rc; 4996 } 4997 4998 /* Get LAN Page 1 header */ 4999 hdr.PageVersion = 0; 5000 hdr.PageLength = 0; 5001 hdr.PageNumber = 1; 5002 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN; 5003 cfg.cfghdr.hdr = &hdr; 5004 cfg.physAddr = -1; 5005 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5006 cfg.dir = 0; 5007 cfg.pageAddr = 0; 5008 5009 if ((rc = mpt_config(ioc, &cfg)) != 0) 5010 return rc; 5011 5012 if (hdr.PageLength == 0) 5013 return 0; 5014 5015 data_sz = hdr.PageLength * 4; 5016 rc = -ENOMEM; 5017 ppage1_alloc = pci_alloc_consistent(ioc->pcidev, data_sz, &page1_dma); 5018 if (ppage1_alloc) { 5019 memset((u8 *)ppage1_alloc, 0, data_sz); 5020 cfg.physAddr = page1_dma; 5021 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5022 5023 if ((rc = mpt_config(ioc, &cfg)) == 0) { 5024 /* save the data */ 5025 copy_sz = min_t(int, sizeof(LANPage1_t), data_sz); 5026 memcpy(&ioc->lan_cnfg_page1, ppage1_alloc, copy_sz); 5027 } 5028 5029 pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage1_alloc, page1_dma); 5030 5031 /* FIXME! 5032 * Normalize endianness of structure data, 5033 * by byte-swapping all > 1 byte fields! 5034 */ 5035 5036 } 5037 5038 return rc; 5039 } 5040 5041 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5042 /** 5043 * mptbase_sas_persist_operation - Perform operation on SAS Persistent Table 5044 * @ioc: Pointer to MPT_ADAPTER structure 5045 * @persist_opcode: see below 5046 * 5047 * =============================== ====================================== 5048 * MPI_SAS_OP_CLEAR_NOT_PRESENT Free all persist TargetID mappings for 5049 * devices not currently present. 5050 * MPI_SAS_OP_CLEAR_ALL_PERSISTENT Clear al persist TargetID mappings 5051 * =============================== ====================================== 5052 * 5053 * NOTE: Don't use not this function during interrupt time. 5054 * 5055 * Returns 0 for success, non-zero error 5056 */ 5057 5058 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5059 int 5060 mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode) 5061 { 5062 SasIoUnitControlRequest_t *sasIoUnitCntrReq; 5063 SasIoUnitControlReply_t *sasIoUnitCntrReply; 5064 MPT_FRAME_HDR *mf = NULL; 5065 MPIHeader_t *mpi_hdr; 5066 int ret = 0; 5067 unsigned long timeleft; 5068 5069 mutex_lock(&ioc->mptbase_cmds.mutex); 5070 5071 /* init the internal cmd struct */ 5072 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE); 5073 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status) 5074 5075 /* insure garbage is not sent to fw */ 5076 switch(persist_opcode) { 5077 5078 case MPI_SAS_OP_CLEAR_NOT_PRESENT: 5079 case MPI_SAS_OP_CLEAR_ALL_PERSISTENT: 5080 break; 5081 5082 default: 5083 ret = -1; 5084 goto out; 5085 } 5086 5087 printk(KERN_DEBUG "%s: persist_opcode=%x\n", 5088 __func__, persist_opcode); 5089 5090 /* Get a MF for this command. 5091 */ 5092 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) { 5093 printk(KERN_DEBUG "%s: no msg frames!\n", __func__); 5094 ret = -1; 5095 goto out; 5096 } 5097 5098 mpi_hdr = (MPIHeader_t *) mf; 5099 sasIoUnitCntrReq = (SasIoUnitControlRequest_t *)mf; 5100 memset(sasIoUnitCntrReq,0,sizeof(SasIoUnitControlRequest_t)); 5101 sasIoUnitCntrReq->Function = MPI_FUNCTION_SAS_IO_UNIT_CONTROL; 5102 sasIoUnitCntrReq->MsgContext = mpi_hdr->MsgContext; 5103 sasIoUnitCntrReq->Operation = persist_opcode; 5104 5105 mpt_put_msg_frame(mpt_base_index, ioc, mf); 5106 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, 10*HZ); 5107 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { 5108 ret = -ETIME; 5109 printk(KERN_DEBUG "%s: failed\n", __func__); 5110 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) 5111 goto out; 5112 if (!timeleft) { 5113 printk(MYIOC_s_WARN_FMT 5114 "Issuing Reset from %s!!, doorbell=0x%08x\n", 5115 ioc->name, __func__, mpt_GetIocState(ioc, 0)); 5116 mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP); 5117 mpt_free_msg_frame(ioc, mf); 5118 } 5119 goto out; 5120 } 5121 5122 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) { 5123 ret = -1; 5124 goto out; 5125 } 5126 5127 sasIoUnitCntrReply = 5128 (SasIoUnitControlReply_t *)ioc->mptbase_cmds.reply; 5129 if (le16_to_cpu(sasIoUnitCntrReply->IOCStatus) != MPI_IOCSTATUS_SUCCESS) { 5130 printk(KERN_DEBUG "%s: IOCStatus=0x%X IOCLogInfo=0x%X\n", 5131 __func__, sasIoUnitCntrReply->IOCStatus, 5132 sasIoUnitCntrReply->IOCLogInfo); 5133 printk(KERN_DEBUG "%s: failed\n", __func__); 5134 ret = -1; 5135 } else 5136 printk(KERN_DEBUG "%s: success\n", __func__); 5137 out: 5138 5139 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status) 5140 mutex_unlock(&ioc->mptbase_cmds.mutex); 5141 return ret; 5142 } 5143 5144 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5145 5146 static void 5147 mptbase_raid_process_event_data(MPT_ADAPTER *ioc, 5148 MpiEventDataRaid_t * pRaidEventData) 5149 { 5150 int volume; 5151 int reason; 5152 int disk; 5153 int status; 5154 int flags; 5155 int state; 5156 5157 volume = pRaidEventData->VolumeID; 5158 reason = pRaidEventData->ReasonCode; 5159 disk = pRaidEventData->PhysDiskNum; 5160 status = le32_to_cpu(pRaidEventData->SettingsStatus); 5161 flags = (status >> 0) & 0xff; 5162 state = (status >> 8) & 0xff; 5163 5164 if (reason == MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED) { 5165 return; 5166 } 5167 5168 if ((reason >= MPI_EVENT_RAID_RC_PHYSDISK_CREATED && 5169 reason <= MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED) || 5170 (reason == MPI_EVENT_RAID_RC_SMART_DATA)) { 5171 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for PhysDisk %d id=%d\n", 5172 ioc->name, disk, volume); 5173 } else { 5174 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for VolumeID %d\n", 5175 ioc->name, volume); 5176 } 5177 5178 switch(reason) { 5179 case MPI_EVENT_RAID_RC_VOLUME_CREATED: 5180 printk(MYIOC_s_INFO_FMT " volume has been created\n", 5181 ioc->name); 5182 break; 5183 5184 case MPI_EVENT_RAID_RC_VOLUME_DELETED: 5185 5186 printk(MYIOC_s_INFO_FMT " volume has been deleted\n", 5187 ioc->name); 5188 break; 5189 5190 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED: 5191 printk(MYIOC_s_INFO_FMT " volume settings have been changed\n", 5192 ioc->name); 5193 break; 5194 5195 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED: 5196 printk(MYIOC_s_INFO_FMT " volume is now %s%s%s%s\n", 5197 ioc->name, 5198 state == MPI_RAIDVOL0_STATUS_STATE_OPTIMAL 5199 ? "optimal" 5200 : state == MPI_RAIDVOL0_STATUS_STATE_DEGRADED 5201 ? "degraded" 5202 : state == MPI_RAIDVOL0_STATUS_STATE_FAILED 5203 ? "failed" 5204 : "state unknown", 5205 flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED 5206 ? ", enabled" : "", 5207 flags & MPI_RAIDVOL0_STATUS_FLAG_QUIESCED 5208 ? ", quiesced" : "", 5209 flags & MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS 5210 ? ", resync in progress" : "" ); 5211 break; 5212 5213 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED: 5214 printk(MYIOC_s_INFO_FMT " volume membership of PhysDisk %d has changed\n", 5215 ioc->name, disk); 5216 break; 5217 5218 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED: 5219 printk(MYIOC_s_INFO_FMT " PhysDisk has been created\n", 5220 ioc->name); 5221 break; 5222 5223 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED: 5224 printk(MYIOC_s_INFO_FMT " PhysDisk has been deleted\n", 5225 ioc->name); 5226 break; 5227 5228 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED: 5229 printk(MYIOC_s_INFO_FMT " PhysDisk settings have been changed\n", 5230 ioc->name); 5231 break; 5232 5233 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED: 5234 printk(MYIOC_s_INFO_FMT " PhysDisk is now %s%s%s\n", 5235 ioc->name, 5236 state == MPI_PHYSDISK0_STATUS_ONLINE 5237 ? "online" 5238 : state == MPI_PHYSDISK0_STATUS_MISSING 5239 ? "missing" 5240 : state == MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE 5241 ? "not compatible" 5242 : state == MPI_PHYSDISK0_STATUS_FAILED 5243 ? "failed" 5244 : state == MPI_PHYSDISK0_STATUS_INITIALIZING 5245 ? "initializing" 5246 : state == MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED 5247 ? "offline requested" 5248 : state == MPI_PHYSDISK0_STATUS_FAILED_REQUESTED 5249 ? "failed requested" 5250 : state == MPI_PHYSDISK0_STATUS_OTHER_OFFLINE 5251 ? "offline" 5252 : "state unknown", 5253 flags & MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC 5254 ? ", out of sync" : "", 5255 flags & MPI_PHYSDISK0_STATUS_FLAG_QUIESCED 5256 ? ", quiesced" : "" ); 5257 break; 5258 5259 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED: 5260 printk(MYIOC_s_INFO_FMT " Domain Validation needed for PhysDisk %d\n", 5261 ioc->name, disk); 5262 break; 5263 5264 case MPI_EVENT_RAID_RC_SMART_DATA: 5265 printk(MYIOC_s_INFO_FMT " SMART data received, ASC/ASCQ = %02xh/%02xh\n", 5266 ioc->name, pRaidEventData->ASC, pRaidEventData->ASCQ); 5267 break; 5268 5269 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED: 5270 printk(MYIOC_s_INFO_FMT " replacement of PhysDisk %d has started\n", 5271 ioc->name, disk); 5272 break; 5273 } 5274 } 5275 5276 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5277 /** 5278 * GetIoUnitPage2 - Retrieve BIOS version and boot order information. 5279 * @ioc: Pointer to MPT_ADAPTER structure 5280 * 5281 * Returns: 0 for success 5282 * -ENOMEM if no memory available 5283 * -EPERM if not allowed due to ISR context 5284 * -EAGAIN if no msg frames currently available 5285 * -EFAULT for non-successful reply or no reply (timeout) 5286 */ 5287 static int 5288 GetIoUnitPage2(MPT_ADAPTER *ioc) 5289 { 5290 ConfigPageHeader_t hdr; 5291 CONFIGPARMS cfg; 5292 IOUnitPage2_t *ppage_alloc; 5293 dma_addr_t page_dma; 5294 int data_sz; 5295 int rc; 5296 5297 /* Get the page header */ 5298 hdr.PageVersion = 0; 5299 hdr.PageLength = 0; 5300 hdr.PageNumber = 2; 5301 hdr.PageType = MPI_CONFIG_PAGETYPE_IO_UNIT; 5302 cfg.cfghdr.hdr = &hdr; 5303 cfg.physAddr = -1; 5304 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5305 cfg.dir = 0; 5306 cfg.pageAddr = 0; 5307 cfg.timeout = 0; 5308 5309 if ((rc = mpt_config(ioc, &cfg)) != 0) 5310 return rc; 5311 5312 if (hdr.PageLength == 0) 5313 return 0; 5314 5315 /* Read the config page */ 5316 data_sz = hdr.PageLength * 4; 5317 rc = -ENOMEM; 5318 ppage_alloc = pci_alloc_consistent(ioc->pcidev, data_sz, &page_dma); 5319 if (ppage_alloc) { 5320 memset((u8 *)ppage_alloc, 0, data_sz); 5321 cfg.physAddr = page_dma; 5322 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5323 5324 /* If Good, save data */ 5325 if ((rc = mpt_config(ioc, &cfg)) == 0) 5326 ioc->biosVersion = le32_to_cpu(ppage_alloc->BiosVersion); 5327 5328 pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage_alloc, page_dma); 5329 } 5330 5331 return rc; 5332 } 5333 5334 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5335 /** 5336 * mpt_GetScsiPortSettings - read SCSI Port Page 0 and 2 5337 * @ioc: Pointer to a Adapter Strucutre 5338 * @portnum: IOC port number 5339 * 5340 * Return: -EFAULT if read of config page header fails 5341 * or if no nvram 5342 * If read of SCSI Port Page 0 fails, 5343 * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF) 5344 * Adapter settings: async, narrow 5345 * Return 1 5346 * If read of SCSI Port Page 2 fails, 5347 * Adapter settings valid 5348 * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF) 5349 * Return 1 5350 * Else 5351 * Both valid 5352 * Return 0 5353 * CHECK - what type of locking mechanisms should be used???? 5354 */ 5355 static int 5356 mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum) 5357 { 5358 u8 *pbuf; 5359 dma_addr_t buf_dma; 5360 CONFIGPARMS cfg; 5361 ConfigPageHeader_t header; 5362 int ii; 5363 int data, rc = 0; 5364 5365 /* Allocate memory 5366 */ 5367 if (!ioc->spi_data.nvram) { 5368 int sz; 5369 u8 *mem; 5370 sz = MPT_MAX_SCSI_DEVICES * sizeof(int); 5371 mem = kmalloc(sz, GFP_ATOMIC); 5372 if (mem == NULL) 5373 return -EFAULT; 5374 5375 ioc->spi_data.nvram = (int *) mem; 5376 5377 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SCSI device NVRAM settings @ %p, sz=%d\n", 5378 ioc->name, ioc->spi_data.nvram, sz)); 5379 } 5380 5381 /* Invalidate NVRAM information 5382 */ 5383 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) { 5384 ioc->spi_data.nvram[ii] = MPT_HOST_NVRAM_INVALID; 5385 } 5386 5387 /* Read SPP0 header, allocate memory, then read page. 5388 */ 5389 header.PageVersion = 0; 5390 header.PageLength = 0; 5391 header.PageNumber = 0; 5392 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT; 5393 cfg.cfghdr.hdr = &header; 5394 cfg.physAddr = -1; 5395 cfg.pageAddr = portnum; 5396 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5397 cfg.dir = 0; 5398 cfg.timeout = 0; /* use default */ 5399 if (mpt_config(ioc, &cfg) != 0) 5400 return -EFAULT; 5401 5402 if (header.PageLength > 0) { 5403 pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma); 5404 if (pbuf) { 5405 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5406 cfg.physAddr = buf_dma; 5407 if (mpt_config(ioc, &cfg) != 0) { 5408 ioc->spi_data.maxBusWidth = MPT_NARROW; 5409 ioc->spi_data.maxSyncOffset = 0; 5410 ioc->spi_data.minSyncFactor = MPT_ASYNC; 5411 ioc->spi_data.busType = MPT_HOST_BUS_UNKNOWN; 5412 rc = 1; 5413 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT 5414 "Unable to read PortPage0 minSyncFactor=%x\n", 5415 ioc->name, ioc->spi_data.minSyncFactor)); 5416 } else { 5417 /* Save the Port Page 0 data 5418 */ 5419 SCSIPortPage0_t *pPP0 = (SCSIPortPage0_t *) pbuf; 5420 pPP0->Capabilities = le32_to_cpu(pPP0->Capabilities); 5421 pPP0->PhysicalInterface = le32_to_cpu(pPP0->PhysicalInterface); 5422 5423 if ( (pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_QAS) == 0 ) { 5424 ioc->spi_data.noQas |= MPT_TARGET_NO_NEGO_QAS; 5425 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT 5426 "noQas due to Capabilities=%x\n", 5427 ioc->name, pPP0->Capabilities)); 5428 } 5429 ioc->spi_data.maxBusWidth = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_WIDE ? 1 : 0; 5430 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK; 5431 if (data) { 5432 ioc->spi_data.maxSyncOffset = (u8) (data >> 16); 5433 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK; 5434 ioc->spi_data.minSyncFactor = (u8) (data >> 8); 5435 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT 5436 "PortPage0 minSyncFactor=%x\n", 5437 ioc->name, ioc->spi_data.minSyncFactor)); 5438 } else { 5439 ioc->spi_data.maxSyncOffset = 0; 5440 ioc->spi_data.minSyncFactor = MPT_ASYNC; 5441 } 5442 5443 ioc->spi_data.busType = pPP0->PhysicalInterface & MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK; 5444 5445 /* Update the minSyncFactor based on bus type. 5446 */ 5447 if ((ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD) || 5448 (ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE)) { 5449 5450 if (ioc->spi_data.minSyncFactor < MPT_ULTRA) { 5451 ioc->spi_data.minSyncFactor = MPT_ULTRA; 5452 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT 5453 "HVD or SE detected, minSyncFactor=%x\n", 5454 ioc->name, ioc->spi_data.minSyncFactor)); 5455 } 5456 } 5457 } 5458 if (pbuf) { 5459 pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma); 5460 } 5461 } 5462 } 5463 5464 /* SCSI Port Page 2 - Read the header then the page. 5465 */ 5466 header.PageVersion = 0; 5467 header.PageLength = 0; 5468 header.PageNumber = 2; 5469 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT; 5470 cfg.cfghdr.hdr = &header; 5471 cfg.physAddr = -1; 5472 cfg.pageAddr = portnum; 5473 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5474 cfg.dir = 0; 5475 if (mpt_config(ioc, &cfg) != 0) 5476 return -EFAULT; 5477 5478 if (header.PageLength > 0) { 5479 /* Allocate memory and read SCSI Port Page 2 5480 */ 5481 pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma); 5482 if (pbuf) { 5483 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_NVRAM; 5484 cfg.physAddr = buf_dma; 5485 if (mpt_config(ioc, &cfg) != 0) { 5486 /* Nvram data is left with INVALID mark 5487 */ 5488 rc = 1; 5489 } else if (ioc->pcidev->vendor == PCI_VENDOR_ID_ATTO) { 5490 5491 /* This is an ATTO adapter, read Page2 accordingly 5492 */ 5493 ATTO_SCSIPortPage2_t *pPP2 = (ATTO_SCSIPortPage2_t *) pbuf; 5494 ATTODeviceInfo_t *pdevice = NULL; 5495 u16 ATTOFlags; 5496 5497 /* Save the Port Page 2 data 5498 * (reformat into a 32bit quantity) 5499 */ 5500 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) { 5501 pdevice = &pPP2->DeviceSettings[ii]; 5502 ATTOFlags = le16_to_cpu(pdevice->ATTOFlags); 5503 data = 0; 5504 5505 /* Translate ATTO device flags to LSI format 5506 */ 5507 if (ATTOFlags & ATTOFLAG_DISC) 5508 data |= (MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE); 5509 if (ATTOFlags & ATTOFLAG_ID_ENB) 5510 data |= (MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE); 5511 if (ATTOFlags & ATTOFLAG_LUN_ENB) 5512 data |= (MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE); 5513 if (ATTOFlags & ATTOFLAG_TAGGED) 5514 data |= (MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE); 5515 if (!(ATTOFlags & ATTOFLAG_WIDE_ENB)) 5516 data |= (MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE); 5517 5518 data = (data << 16) | (pdevice->Period << 8) | 10; 5519 ioc->spi_data.nvram[ii] = data; 5520 } 5521 } else { 5522 SCSIPortPage2_t *pPP2 = (SCSIPortPage2_t *) pbuf; 5523 MpiDeviceInfo_t *pdevice = NULL; 5524 5525 /* 5526 * Save "Set to Avoid SCSI Bus Resets" flag 5527 */ 5528 ioc->spi_data.bus_reset = 5529 (le32_to_cpu(pPP2->PortFlags) & 5530 MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET) ? 5531 0 : 1 ; 5532 5533 /* Save the Port Page 2 data 5534 * (reformat into a 32bit quantity) 5535 */ 5536 data = le32_to_cpu(pPP2->PortFlags) & MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK; 5537 ioc->spi_data.PortFlags = data; 5538 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) { 5539 pdevice = &pPP2->DeviceSettings[ii]; 5540 data = (le16_to_cpu(pdevice->DeviceFlags) << 16) | 5541 (pdevice->SyncFactor << 8) | pdevice->Timeout; 5542 ioc->spi_data.nvram[ii] = data; 5543 } 5544 } 5545 5546 pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma); 5547 } 5548 } 5549 5550 /* Update Adapter limits with those from NVRAM 5551 * Comment: Don't need to do this. Target performance 5552 * parameters will never exceed the adapters limits. 5553 */ 5554 5555 return rc; 5556 } 5557 5558 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 5559 /** 5560 * mpt_readScsiDevicePageHeaders - save version and length of SDP1 5561 * @ioc: Pointer to a Adapter Strucutre 5562 * @portnum: IOC port number 5563 * 5564 * Return: -EFAULT if read of config page header fails 5565 * or 0 if success. 5566 */ 5567 static int 5568 mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum) 5569 { 5570 CONFIGPARMS cfg; 5571 ConfigPageHeader_t header; 5572 5573 /* Read the SCSI Device Page 1 header 5574 */ 5575 header.PageVersion = 0; 5576 header.PageLength = 0; 5577 header.PageNumber = 1; 5578 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE; 5579 cfg.cfghdr.hdr = &header; 5580 cfg.physAddr = -1; 5581 cfg.pageAddr = portnum; 5582 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5583 cfg.dir = 0; 5584 cfg.timeout = 0; 5585 if (mpt_config(ioc, &cfg) != 0) 5586 return -EFAULT; 5587 5588 ioc->spi_data.sdp1version = cfg.cfghdr.hdr->PageVersion; 5589 ioc->spi_data.sdp1length = cfg.cfghdr.hdr->PageLength; 5590 5591 header.PageVersion = 0; 5592 header.PageLength = 0; 5593 header.PageNumber = 0; 5594 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE; 5595 if (mpt_config(ioc, &cfg) != 0) 5596 return -EFAULT; 5597 5598 ioc->spi_data.sdp0version = cfg.cfghdr.hdr->PageVersion; 5599 ioc->spi_data.sdp0length = cfg.cfghdr.hdr->PageLength; 5600 5601 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 0: version %d length %d\n", 5602 ioc->name, ioc->spi_data.sdp0version, ioc->spi_data.sdp0length)); 5603 5604 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 1: version %d length %d\n", 5605 ioc->name, ioc->spi_data.sdp1version, ioc->spi_data.sdp1length)); 5606 return 0; 5607 } 5608 5609 /** 5610 * mpt_inactive_raid_list_free - This clears this link list. 5611 * @ioc : pointer to per adapter structure 5612 **/ 5613 static void 5614 mpt_inactive_raid_list_free(MPT_ADAPTER *ioc) 5615 { 5616 struct inactive_raid_component_info *component_info, *pNext; 5617 5618 if (list_empty(&ioc->raid_data.inactive_list)) 5619 return; 5620 5621 mutex_lock(&ioc->raid_data.inactive_list_mutex); 5622 list_for_each_entry_safe(component_info, pNext, 5623 &ioc->raid_data.inactive_list, list) { 5624 list_del(&component_info->list); 5625 kfree(component_info); 5626 } 5627 mutex_unlock(&ioc->raid_data.inactive_list_mutex); 5628 } 5629 5630 /** 5631 * mpt_inactive_raid_volumes - sets up link list of phy_disk_nums for devices belonging in an inactive volume 5632 * 5633 * @ioc : pointer to per adapter structure 5634 * @channel : volume channel 5635 * @id : volume target id 5636 **/ 5637 static void 5638 mpt_inactive_raid_volumes(MPT_ADAPTER *ioc, u8 channel, u8 id) 5639 { 5640 CONFIGPARMS cfg; 5641 ConfigPageHeader_t hdr; 5642 dma_addr_t dma_handle; 5643 pRaidVolumePage0_t buffer = NULL; 5644 int i; 5645 RaidPhysDiskPage0_t phys_disk; 5646 struct inactive_raid_component_info *component_info; 5647 int handle_inactive_volumes; 5648 5649 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 5650 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 5651 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_VOLUME; 5652 cfg.pageAddr = (channel << 8) + id; 5653 cfg.cfghdr.hdr = &hdr; 5654 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5655 5656 if (mpt_config(ioc, &cfg) != 0) 5657 goto out; 5658 5659 if (!hdr.PageLength) 5660 goto out; 5661 5662 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, 5663 &dma_handle); 5664 5665 if (!buffer) 5666 goto out; 5667 5668 cfg.physAddr = dma_handle; 5669 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5670 5671 if (mpt_config(ioc, &cfg) != 0) 5672 goto out; 5673 5674 if (!buffer->NumPhysDisks) 5675 goto out; 5676 5677 handle_inactive_volumes = 5678 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE || 5679 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED) == 0 || 5680 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_FAILED || 5681 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_MISSING) ? 1 : 0; 5682 5683 if (!handle_inactive_volumes) 5684 goto out; 5685 5686 mutex_lock(&ioc->raid_data.inactive_list_mutex); 5687 for (i = 0; i < buffer->NumPhysDisks; i++) { 5688 if(mpt_raid_phys_disk_pg0(ioc, 5689 buffer->PhysDisk[i].PhysDiskNum, &phys_disk) != 0) 5690 continue; 5691 5692 if ((component_info = kmalloc(sizeof (*component_info), 5693 GFP_KERNEL)) == NULL) 5694 continue; 5695 5696 component_info->volumeID = id; 5697 component_info->volumeBus = channel; 5698 component_info->d.PhysDiskNum = phys_disk.PhysDiskNum; 5699 component_info->d.PhysDiskBus = phys_disk.PhysDiskBus; 5700 component_info->d.PhysDiskID = phys_disk.PhysDiskID; 5701 component_info->d.PhysDiskIOC = phys_disk.PhysDiskIOC; 5702 5703 list_add_tail(&component_info->list, 5704 &ioc->raid_data.inactive_list); 5705 } 5706 mutex_unlock(&ioc->raid_data.inactive_list_mutex); 5707 5708 out: 5709 if (buffer) 5710 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer, 5711 dma_handle); 5712 } 5713 5714 /** 5715 * mpt_raid_phys_disk_pg0 - returns phys disk page zero 5716 * @ioc: Pointer to a Adapter Structure 5717 * @phys_disk_num: io unit unique phys disk num generated by the ioc 5718 * @phys_disk: requested payload data returned 5719 * 5720 * Return: 5721 * 0 on success 5722 * -EFAULT if read of config page header fails or data pointer not NULL 5723 * -ENOMEM if pci_alloc failed 5724 **/ 5725 int 5726 mpt_raid_phys_disk_pg0(MPT_ADAPTER *ioc, u8 phys_disk_num, 5727 RaidPhysDiskPage0_t *phys_disk) 5728 { 5729 CONFIGPARMS cfg; 5730 ConfigPageHeader_t hdr; 5731 dma_addr_t dma_handle; 5732 pRaidPhysDiskPage0_t buffer = NULL; 5733 int rc; 5734 5735 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 5736 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 5737 memset(phys_disk, 0, sizeof(RaidPhysDiskPage0_t)); 5738 5739 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE0_PAGEVERSION; 5740 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK; 5741 cfg.cfghdr.hdr = &hdr; 5742 cfg.physAddr = -1; 5743 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5744 5745 if (mpt_config(ioc, &cfg) != 0) { 5746 rc = -EFAULT; 5747 goto out; 5748 } 5749 5750 if (!hdr.PageLength) { 5751 rc = -EFAULT; 5752 goto out; 5753 } 5754 5755 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, 5756 &dma_handle); 5757 5758 if (!buffer) { 5759 rc = -ENOMEM; 5760 goto out; 5761 } 5762 5763 cfg.physAddr = dma_handle; 5764 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5765 cfg.pageAddr = phys_disk_num; 5766 5767 if (mpt_config(ioc, &cfg) != 0) { 5768 rc = -EFAULT; 5769 goto out; 5770 } 5771 5772 rc = 0; 5773 memcpy(phys_disk, buffer, sizeof(*buffer)); 5774 phys_disk->MaxLBA = le32_to_cpu(buffer->MaxLBA); 5775 5776 out: 5777 5778 if (buffer) 5779 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer, 5780 dma_handle); 5781 5782 return rc; 5783 } 5784 5785 /** 5786 * mpt_raid_phys_disk_get_num_paths - returns number paths associated to this phys_num 5787 * @ioc: Pointer to a Adapter Structure 5788 * @phys_disk_num: io unit unique phys disk num generated by the ioc 5789 * 5790 * Return: 5791 * returns number paths 5792 **/ 5793 int 5794 mpt_raid_phys_disk_get_num_paths(MPT_ADAPTER *ioc, u8 phys_disk_num) 5795 { 5796 CONFIGPARMS cfg; 5797 ConfigPageHeader_t hdr; 5798 dma_addr_t dma_handle; 5799 pRaidPhysDiskPage1_t buffer = NULL; 5800 int rc; 5801 5802 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 5803 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 5804 5805 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION; 5806 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK; 5807 hdr.PageNumber = 1; 5808 cfg.cfghdr.hdr = &hdr; 5809 cfg.physAddr = -1; 5810 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5811 5812 if (mpt_config(ioc, &cfg) != 0) { 5813 rc = 0; 5814 goto out; 5815 } 5816 5817 if (!hdr.PageLength) { 5818 rc = 0; 5819 goto out; 5820 } 5821 5822 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, 5823 &dma_handle); 5824 5825 if (!buffer) { 5826 rc = 0; 5827 goto out; 5828 } 5829 5830 cfg.physAddr = dma_handle; 5831 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5832 cfg.pageAddr = phys_disk_num; 5833 5834 if (mpt_config(ioc, &cfg) != 0) { 5835 rc = 0; 5836 goto out; 5837 } 5838 5839 rc = buffer->NumPhysDiskPaths; 5840 out: 5841 5842 if (buffer) 5843 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer, 5844 dma_handle); 5845 5846 return rc; 5847 } 5848 EXPORT_SYMBOL(mpt_raid_phys_disk_get_num_paths); 5849 5850 /** 5851 * mpt_raid_phys_disk_pg1 - returns phys disk page 1 5852 * @ioc: Pointer to a Adapter Structure 5853 * @phys_disk_num: io unit unique phys disk num generated by the ioc 5854 * @phys_disk: requested payload data returned 5855 * 5856 * Return: 5857 * 0 on success 5858 * -EFAULT if read of config page header fails or data pointer not NULL 5859 * -ENOMEM if pci_alloc failed 5860 **/ 5861 int 5862 mpt_raid_phys_disk_pg1(MPT_ADAPTER *ioc, u8 phys_disk_num, 5863 RaidPhysDiskPage1_t *phys_disk) 5864 { 5865 CONFIGPARMS cfg; 5866 ConfigPageHeader_t hdr; 5867 dma_addr_t dma_handle; 5868 pRaidPhysDiskPage1_t buffer = NULL; 5869 int rc; 5870 int i; 5871 __le64 sas_address; 5872 5873 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 5874 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 5875 rc = 0; 5876 5877 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION; 5878 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK; 5879 hdr.PageNumber = 1; 5880 cfg.cfghdr.hdr = &hdr; 5881 cfg.physAddr = -1; 5882 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5883 5884 if (mpt_config(ioc, &cfg) != 0) { 5885 rc = -EFAULT; 5886 goto out; 5887 } 5888 5889 if (!hdr.PageLength) { 5890 rc = -EFAULT; 5891 goto out; 5892 } 5893 5894 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, 5895 &dma_handle); 5896 5897 if (!buffer) { 5898 rc = -ENOMEM; 5899 goto out; 5900 } 5901 5902 cfg.physAddr = dma_handle; 5903 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5904 cfg.pageAddr = phys_disk_num; 5905 5906 if (mpt_config(ioc, &cfg) != 0) { 5907 rc = -EFAULT; 5908 goto out; 5909 } 5910 5911 phys_disk->NumPhysDiskPaths = buffer->NumPhysDiskPaths; 5912 phys_disk->PhysDiskNum = phys_disk_num; 5913 for (i = 0; i < phys_disk->NumPhysDiskPaths; i++) { 5914 phys_disk->Path[i].PhysDiskID = buffer->Path[i].PhysDiskID; 5915 phys_disk->Path[i].PhysDiskBus = buffer->Path[i].PhysDiskBus; 5916 phys_disk->Path[i].OwnerIdentifier = 5917 buffer->Path[i].OwnerIdentifier; 5918 phys_disk->Path[i].Flags = le16_to_cpu(buffer->Path[i].Flags); 5919 memcpy(&sas_address, &buffer->Path[i].WWID, sizeof(__le64)); 5920 sas_address = le64_to_cpu(sas_address); 5921 memcpy(&phys_disk->Path[i].WWID, &sas_address, sizeof(__le64)); 5922 memcpy(&sas_address, 5923 &buffer->Path[i].OwnerWWID, sizeof(__le64)); 5924 sas_address = le64_to_cpu(sas_address); 5925 memcpy(&phys_disk->Path[i].OwnerWWID, 5926 &sas_address, sizeof(__le64)); 5927 } 5928 5929 out: 5930 5931 if (buffer) 5932 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer, 5933 dma_handle); 5934 5935 return rc; 5936 } 5937 EXPORT_SYMBOL(mpt_raid_phys_disk_pg1); 5938 5939 5940 /** 5941 * mpt_findImVolumes - Identify IDs of hidden disks and RAID Volumes 5942 * @ioc: Pointer to a Adapter Strucutre 5943 * 5944 * Return: 5945 * 0 on success 5946 * -EFAULT if read of config page header fails or data pointer not NULL 5947 * -ENOMEM if pci_alloc failed 5948 **/ 5949 int 5950 mpt_findImVolumes(MPT_ADAPTER *ioc) 5951 { 5952 IOCPage2_t *pIoc2; 5953 u8 *mem; 5954 dma_addr_t ioc2_dma; 5955 CONFIGPARMS cfg; 5956 ConfigPageHeader_t header; 5957 int rc = 0; 5958 int iocpage2sz; 5959 int i; 5960 5961 if (!ioc->ir_firmware) 5962 return 0; 5963 5964 /* Free the old page 5965 */ 5966 kfree(ioc->raid_data.pIocPg2); 5967 ioc->raid_data.pIocPg2 = NULL; 5968 mpt_inactive_raid_list_free(ioc); 5969 5970 /* Read IOCP2 header then the page. 5971 */ 5972 header.PageVersion = 0; 5973 header.PageLength = 0; 5974 header.PageNumber = 2; 5975 header.PageType = MPI_CONFIG_PAGETYPE_IOC; 5976 cfg.cfghdr.hdr = &header; 5977 cfg.physAddr = -1; 5978 cfg.pageAddr = 0; 5979 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 5980 cfg.dir = 0; 5981 cfg.timeout = 0; 5982 if (mpt_config(ioc, &cfg) != 0) 5983 return -EFAULT; 5984 5985 if (header.PageLength == 0) 5986 return -EFAULT; 5987 5988 iocpage2sz = header.PageLength * 4; 5989 pIoc2 = pci_alloc_consistent(ioc->pcidev, iocpage2sz, &ioc2_dma); 5990 if (!pIoc2) 5991 return -ENOMEM; 5992 5993 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 5994 cfg.physAddr = ioc2_dma; 5995 if (mpt_config(ioc, &cfg) != 0) 5996 goto out; 5997 5998 mem = kmemdup(pIoc2, iocpage2sz, GFP_KERNEL); 5999 if (!mem) { 6000 rc = -ENOMEM; 6001 goto out; 6002 } 6003 6004 ioc->raid_data.pIocPg2 = (IOCPage2_t *) mem; 6005 6006 mpt_read_ioc_pg_3(ioc); 6007 6008 for (i = 0; i < pIoc2->NumActiveVolumes ; i++) 6009 mpt_inactive_raid_volumes(ioc, 6010 pIoc2->RaidVolume[i].VolumeBus, 6011 pIoc2->RaidVolume[i].VolumeID); 6012 6013 out: 6014 pci_free_consistent(ioc->pcidev, iocpage2sz, pIoc2, ioc2_dma); 6015 6016 return rc; 6017 } 6018 6019 static int 6020 mpt_read_ioc_pg_3(MPT_ADAPTER *ioc) 6021 { 6022 IOCPage3_t *pIoc3; 6023 u8 *mem; 6024 CONFIGPARMS cfg; 6025 ConfigPageHeader_t header; 6026 dma_addr_t ioc3_dma; 6027 int iocpage3sz = 0; 6028 6029 /* Free the old page 6030 */ 6031 kfree(ioc->raid_data.pIocPg3); 6032 ioc->raid_data.pIocPg3 = NULL; 6033 6034 /* There is at least one physical disk. 6035 * Read and save IOC Page 3 6036 */ 6037 header.PageVersion = 0; 6038 header.PageLength = 0; 6039 header.PageNumber = 3; 6040 header.PageType = MPI_CONFIG_PAGETYPE_IOC; 6041 cfg.cfghdr.hdr = &header; 6042 cfg.physAddr = -1; 6043 cfg.pageAddr = 0; 6044 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 6045 cfg.dir = 0; 6046 cfg.timeout = 0; 6047 if (mpt_config(ioc, &cfg) != 0) 6048 return 0; 6049 6050 if (header.PageLength == 0) 6051 return 0; 6052 6053 /* Read Header good, alloc memory 6054 */ 6055 iocpage3sz = header.PageLength * 4; 6056 pIoc3 = pci_alloc_consistent(ioc->pcidev, iocpage3sz, &ioc3_dma); 6057 if (!pIoc3) 6058 return 0; 6059 6060 /* Read the Page and save the data 6061 * into malloc'd memory. 6062 */ 6063 cfg.physAddr = ioc3_dma; 6064 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 6065 if (mpt_config(ioc, &cfg) == 0) { 6066 mem = kmalloc(iocpage3sz, GFP_KERNEL); 6067 if (mem) { 6068 memcpy(mem, (u8 *)pIoc3, iocpage3sz); 6069 ioc->raid_data.pIocPg3 = (IOCPage3_t *) mem; 6070 } 6071 } 6072 6073 pci_free_consistent(ioc->pcidev, iocpage3sz, pIoc3, ioc3_dma); 6074 6075 return 0; 6076 } 6077 6078 static void 6079 mpt_read_ioc_pg_4(MPT_ADAPTER *ioc) 6080 { 6081 IOCPage4_t *pIoc4; 6082 CONFIGPARMS cfg; 6083 ConfigPageHeader_t header; 6084 dma_addr_t ioc4_dma; 6085 int iocpage4sz; 6086 6087 /* Read and save IOC Page 4 6088 */ 6089 header.PageVersion = 0; 6090 header.PageLength = 0; 6091 header.PageNumber = 4; 6092 header.PageType = MPI_CONFIG_PAGETYPE_IOC; 6093 cfg.cfghdr.hdr = &header; 6094 cfg.physAddr = -1; 6095 cfg.pageAddr = 0; 6096 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 6097 cfg.dir = 0; 6098 cfg.timeout = 0; 6099 if (mpt_config(ioc, &cfg) != 0) 6100 return; 6101 6102 if (header.PageLength == 0) 6103 return; 6104 6105 if ( (pIoc4 = ioc->spi_data.pIocPg4) == NULL ) { 6106 iocpage4sz = (header.PageLength + 4) * 4; /* Allow 4 additional SEP's */ 6107 pIoc4 = pci_alloc_consistent(ioc->pcidev, iocpage4sz, &ioc4_dma); 6108 if (!pIoc4) 6109 return; 6110 ioc->alloc_total += iocpage4sz; 6111 } else { 6112 ioc4_dma = ioc->spi_data.IocPg4_dma; 6113 iocpage4sz = ioc->spi_data.IocPg4Sz; 6114 } 6115 6116 /* Read the Page into dma memory. 6117 */ 6118 cfg.physAddr = ioc4_dma; 6119 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 6120 if (mpt_config(ioc, &cfg) == 0) { 6121 ioc->spi_data.pIocPg4 = (IOCPage4_t *) pIoc4; 6122 ioc->spi_data.IocPg4_dma = ioc4_dma; 6123 ioc->spi_data.IocPg4Sz = iocpage4sz; 6124 } else { 6125 pci_free_consistent(ioc->pcidev, iocpage4sz, pIoc4, ioc4_dma); 6126 ioc->spi_data.pIocPg4 = NULL; 6127 ioc->alloc_total -= iocpage4sz; 6128 } 6129 } 6130 6131 static void 6132 mpt_read_ioc_pg_1(MPT_ADAPTER *ioc) 6133 { 6134 IOCPage1_t *pIoc1; 6135 CONFIGPARMS cfg; 6136 ConfigPageHeader_t header; 6137 dma_addr_t ioc1_dma; 6138 int iocpage1sz = 0; 6139 u32 tmp; 6140 6141 /* Check the Coalescing Timeout in IOC Page 1 6142 */ 6143 header.PageVersion = 0; 6144 header.PageLength = 0; 6145 header.PageNumber = 1; 6146 header.PageType = MPI_CONFIG_PAGETYPE_IOC; 6147 cfg.cfghdr.hdr = &header; 6148 cfg.physAddr = -1; 6149 cfg.pageAddr = 0; 6150 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 6151 cfg.dir = 0; 6152 cfg.timeout = 0; 6153 if (mpt_config(ioc, &cfg) != 0) 6154 return; 6155 6156 if (header.PageLength == 0) 6157 return; 6158 6159 /* Read Header good, alloc memory 6160 */ 6161 iocpage1sz = header.PageLength * 4; 6162 pIoc1 = pci_alloc_consistent(ioc->pcidev, iocpage1sz, &ioc1_dma); 6163 if (!pIoc1) 6164 return; 6165 6166 /* Read the Page and check coalescing timeout 6167 */ 6168 cfg.physAddr = ioc1_dma; 6169 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 6170 if (mpt_config(ioc, &cfg) == 0) { 6171 6172 tmp = le32_to_cpu(pIoc1->Flags) & MPI_IOCPAGE1_REPLY_COALESCING; 6173 if (tmp == MPI_IOCPAGE1_REPLY_COALESCING) { 6174 tmp = le32_to_cpu(pIoc1->CoalescingTimeout); 6175 6176 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Coalescing Enabled Timeout = %d\n", 6177 ioc->name, tmp)); 6178 6179 if (tmp > MPT_COALESCING_TIMEOUT) { 6180 pIoc1->CoalescingTimeout = cpu_to_le32(MPT_COALESCING_TIMEOUT); 6181 6182 /* Write NVRAM and current 6183 */ 6184 cfg.dir = 1; 6185 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT; 6186 if (mpt_config(ioc, &cfg) == 0) { 6187 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Reset Current Coalescing Timeout to = %d\n", 6188 ioc->name, MPT_COALESCING_TIMEOUT)); 6189 6190 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM; 6191 if (mpt_config(ioc, &cfg) == 0) { 6192 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6193 "Reset NVRAM Coalescing Timeout to = %d\n", 6194 ioc->name, MPT_COALESCING_TIMEOUT)); 6195 } else { 6196 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6197 "Reset NVRAM Coalescing Timeout Failed\n", 6198 ioc->name)); 6199 } 6200 6201 } else { 6202 dprintk(ioc, printk(MYIOC_s_WARN_FMT 6203 "Reset of Current Coalescing Timeout Failed!\n", 6204 ioc->name)); 6205 } 6206 } 6207 6208 } else { 6209 dprintk(ioc, printk(MYIOC_s_WARN_FMT "Coalescing Disabled\n", ioc->name)); 6210 } 6211 } 6212 6213 pci_free_consistent(ioc->pcidev, iocpage1sz, pIoc1, ioc1_dma); 6214 6215 return; 6216 } 6217 6218 static void 6219 mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc) 6220 { 6221 CONFIGPARMS cfg; 6222 ConfigPageHeader_t hdr; 6223 dma_addr_t buf_dma; 6224 ManufacturingPage0_t *pbuf = NULL; 6225 6226 memset(&cfg, 0 , sizeof(CONFIGPARMS)); 6227 memset(&hdr, 0 , sizeof(ConfigPageHeader_t)); 6228 6229 hdr.PageType = MPI_CONFIG_PAGETYPE_MANUFACTURING; 6230 cfg.cfghdr.hdr = &hdr; 6231 cfg.physAddr = -1; 6232 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER; 6233 cfg.timeout = 10; 6234 6235 if (mpt_config(ioc, &cfg) != 0) 6236 goto out; 6237 6238 if (!cfg.cfghdr.hdr->PageLength) 6239 goto out; 6240 6241 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT; 6242 pbuf = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, &buf_dma); 6243 if (!pbuf) 6244 goto out; 6245 6246 cfg.physAddr = buf_dma; 6247 6248 if (mpt_config(ioc, &cfg) != 0) 6249 goto out; 6250 6251 memcpy(ioc->board_name, pbuf->BoardName, sizeof(ioc->board_name)); 6252 memcpy(ioc->board_assembly, pbuf->BoardAssembly, sizeof(ioc->board_assembly)); 6253 memcpy(ioc->board_tracer, pbuf->BoardTracerNumber, sizeof(ioc->board_tracer)); 6254 6255 out: 6256 6257 if (pbuf) 6258 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, pbuf, buf_dma); 6259 } 6260 6261 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6262 /** 6263 * SendEventNotification - Send EventNotification (on or off) request to adapter 6264 * @ioc: Pointer to MPT_ADAPTER structure 6265 * @EvSwitch: Event switch flags 6266 * @sleepFlag: Specifies whether the process can sleep 6267 */ 6268 static int 6269 SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch, int sleepFlag) 6270 { 6271 EventNotification_t evn; 6272 MPIDefaultReply_t reply_buf; 6273 6274 memset(&evn, 0, sizeof(EventNotification_t)); 6275 memset(&reply_buf, 0, sizeof(MPIDefaultReply_t)); 6276 6277 evn.Function = MPI_FUNCTION_EVENT_NOTIFICATION; 6278 evn.Switch = EvSwitch; 6279 evn.MsgContext = cpu_to_le32(mpt_base_index << 16); 6280 6281 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6282 "Sending EventNotification (%d) request %p\n", 6283 ioc->name, EvSwitch, &evn)); 6284 6285 return mpt_handshake_req_reply_wait(ioc, sizeof(EventNotification_t), 6286 (u32 *)&evn, sizeof(MPIDefaultReply_t), (u16 *)&reply_buf, 30, 6287 sleepFlag); 6288 } 6289 6290 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6291 /** 6292 * SendEventAck - Send EventAck request to MPT adapter. 6293 * @ioc: Pointer to MPT_ADAPTER structure 6294 * @evnp: Pointer to original EventNotification request 6295 */ 6296 static int 6297 SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp) 6298 { 6299 EventAck_t *pAck; 6300 6301 if ((pAck = (EventAck_t *) mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) { 6302 dfailprintk(ioc, printk(MYIOC_s_WARN_FMT "%s, no msg frames!!\n", 6303 ioc->name, __func__)); 6304 return -1; 6305 } 6306 6307 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending EventAck\n", ioc->name)); 6308 6309 pAck->Function = MPI_FUNCTION_EVENT_ACK; 6310 pAck->ChainOffset = 0; 6311 pAck->Reserved[0] = pAck->Reserved[1] = 0; 6312 pAck->MsgFlags = 0; 6313 pAck->Reserved1[0] = pAck->Reserved1[1] = pAck->Reserved1[2] = 0; 6314 pAck->Event = evnp->Event; 6315 pAck->EventContext = evnp->EventContext; 6316 6317 mpt_put_msg_frame(mpt_base_index, ioc, (MPT_FRAME_HDR *)pAck); 6318 6319 return 0; 6320 } 6321 6322 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6323 /** 6324 * mpt_config - Generic function to issue config message 6325 * @ioc: Pointer to an adapter structure 6326 * @pCfg: Pointer to a configuration structure. Struct contains 6327 * action, page address, direction, physical address 6328 * and pointer to a configuration page header 6329 * Page header is updated. 6330 * 6331 * Returns 0 for success 6332 * -EAGAIN if no msg frames currently available 6333 * -EFAULT for non-successful reply or no reply (timeout) 6334 */ 6335 int 6336 mpt_config(MPT_ADAPTER *ioc, CONFIGPARMS *pCfg) 6337 { 6338 Config_t *pReq; 6339 ConfigReply_t *pReply; 6340 ConfigExtendedPageHeader_t *pExtHdr = NULL; 6341 MPT_FRAME_HDR *mf; 6342 int ii; 6343 int flagsLength; 6344 long timeout; 6345 int ret; 6346 u8 page_type = 0, extend_page; 6347 unsigned long timeleft; 6348 unsigned long flags; 6349 u8 issue_hard_reset = 0; 6350 u8 retry_count = 0; 6351 6352 might_sleep(); 6353 6354 /* don't send a config page during diag reset */ 6355 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6356 if (ioc->ioc_reset_in_progress) { 6357 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6358 "%s: busy with host reset\n", ioc->name, __func__)); 6359 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6360 return -EBUSY; 6361 } 6362 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6363 6364 /* don't send if no chance of success */ 6365 if (!ioc->active || 6366 mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_OPERATIONAL) { 6367 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6368 "%s: ioc not operational, %d, %xh\n", 6369 ioc->name, __func__, ioc->active, 6370 mpt_GetIocState(ioc, 0))); 6371 return -EFAULT; 6372 } 6373 6374 retry_config: 6375 mutex_lock(&ioc->mptbase_cmds.mutex); 6376 /* init the internal cmd struct */ 6377 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE); 6378 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status) 6379 6380 /* Get and Populate a free Frame 6381 */ 6382 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) { 6383 dcprintk(ioc, printk(MYIOC_s_WARN_FMT 6384 "mpt_config: no msg frames!\n", ioc->name)); 6385 ret = -EAGAIN; 6386 goto out; 6387 } 6388 6389 pReq = (Config_t *)mf; 6390 pReq->Action = pCfg->action; 6391 pReq->Reserved = 0; 6392 pReq->ChainOffset = 0; 6393 pReq->Function = MPI_FUNCTION_CONFIG; 6394 6395 /* Assume page type is not extended and clear "reserved" fields. */ 6396 pReq->ExtPageLength = 0; 6397 pReq->ExtPageType = 0; 6398 pReq->MsgFlags = 0; 6399 6400 for (ii=0; ii < 8; ii++) 6401 pReq->Reserved2[ii] = 0; 6402 6403 pReq->Header.PageVersion = pCfg->cfghdr.hdr->PageVersion; 6404 pReq->Header.PageLength = pCfg->cfghdr.hdr->PageLength; 6405 pReq->Header.PageNumber = pCfg->cfghdr.hdr->PageNumber; 6406 pReq->Header.PageType = (pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK); 6407 6408 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == MPI_CONFIG_PAGETYPE_EXTENDED) { 6409 pExtHdr = (ConfigExtendedPageHeader_t *)pCfg->cfghdr.ehdr; 6410 pReq->ExtPageLength = cpu_to_le16(pExtHdr->ExtPageLength); 6411 pReq->ExtPageType = pExtHdr->ExtPageType; 6412 pReq->Header.PageType = MPI_CONFIG_PAGETYPE_EXTENDED; 6413 6414 /* Page Length must be treated as a reserved field for the 6415 * extended header. 6416 */ 6417 pReq->Header.PageLength = 0; 6418 } 6419 6420 pReq->PageAddress = cpu_to_le32(pCfg->pageAddr); 6421 6422 /* Add a SGE to the config request. 6423 */ 6424 if (pCfg->dir) 6425 flagsLength = MPT_SGE_FLAGS_SSIMPLE_WRITE; 6426 else 6427 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ; 6428 6429 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == 6430 MPI_CONFIG_PAGETYPE_EXTENDED) { 6431 flagsLength |= pExtHdr->ExtPageLength * 4; 6432 page_type = pReq->ExtPageType; 6433 extend_page = 1; 6434 } else { 6435 flagsLength |= pCfg->cfghdr.hdr->PageLength * 4; 6436 page_type = pReq->Header.PageType; 6437 extend_page = 0; 6438 } 6439 6440 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6441 "Sending Config request type 0x%x, page 0x%x and action %d\n", 6442 ioc->name, page_type, pReq->Header.PageNumber, pReq->Action)); 6443 6444 ioc->add_sge((char *)&pReq->PageBufferSGE, flagsLength, pCfg->physAddr); 6445 timeout = (pCfg->timeout < 15) ? HZ*15 : HZ*pCfg->timeout; 6446 mpt_put_msg_frame(mpt_base_index, ioc, mf); 6447 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, 6448 timeout); 6449 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) { 6450 ret = -ETIME; 6451 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6452 "Failed Sending Config request type 0x%x, page 0x%x," 6453 " action %d, status %xh, time left %ld\n\n", 6454 ioc->name, page_type, pReq->Header.PageNumber, 6455 pReq->Action, ioc->mptbase_cmds.status, timeleft)); 6456 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET) 6457 goto out; 6458 if (!timeleft) { 6459 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6460 if (ioc->ioc_reset_in_progress) { 6461 spin_unlock_irqrestore(&ioc->taskmgmt_lock, 6462 flags); 6463 printk(MYIOC_s_INFO_FMT "%s: host reset in" 6464 " progress mpt_config timed out.!!\n", 6465 __func__, ioc->name); 6466 mutex_unlock(&ioc->mptbase_cmds.mutex); 6467 return -EFAULT; 6468 } 6469 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6470 issue_hard_reset = 1; 6471 } 6472 goto out; 6473 } 6474 6475 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) { 6476 ret = -1; 6477 goto out; 6478 } 6479 pReply = (ConfigReply_t *)ioc->mptbase_cmds.reply; 6480 ret = le16_to_cpu(pReply->IOCStatus) & MPI_IOCSTATUS_MASK; 6481 if (ret == MPI_IOCSTATUS_SUCCESS) { 6482 if (extend_page) { 6483 pCfg->cfghdr.ehdr->ExtPageLength = 6484 le16_to_cpu(pReply->ExtPageLength); 6485 pCfg->cfghdr.ehdr->ExtPageType = 6486 pReply->ExtPageType; 6487 } 6488 pCfg->cfghdr.hdr->PageVersion = pReply->Header.PageVersion; 6489 pCfg->cfghdr.hdr->PageLength = pReply->Header.PageLength; 6490 pCfg->cfghdr.hdr->PageNumber = pReply->Header.PageNumber; 6491 pCfg->cfghdr.hdr->PageType = pReply->Header.PageType; 6492 6493 } 6494 6495 if (retry_count) 6496 printk(MYIOC_s_INFO_FMT "Retry completed " 6497 "ret=0x%x timeleft=%ld\n", 6498 ioc->name, ret, timeleft); 6499 6500 dcprintk(ioc, printk(KERN_DEBUG "IOCStatus=%04xh, IOCLogInfo=%08xh\n", 6501 ret, le32_to_cpu(pReply->IOCLogInfo))); 6502 6503 out: 6504 6505 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status) 6506 mutex_unlock(&ioc->mptbase_cmds.mutex); 6507 if (issue_hard_reset) { 6508 issue_hard_reset = 0; 6509 printk(MYIOC_s_WARN_FMT 6510 "Issuing Reset from %s!!, doorbell=0x%08x\n", 6511 ioc->name, __func__, mpt_GetIocState(ioc, 0)); 6512 if (retry_count == 0) { 6513 if (mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP) != 0) 6514 retry_count++; 6515 } else 6516 mpt_HardResetHandler(ioc, CAN_SLEEP); 6517 6518 mpt_free_msg_frame(ioc, mf); 6519 /* attempt one retry for a timed out command */ 6520 if (retry_count < 2) { 6521 printk(MYIOC_s_INFO_FMT 6522 "Attempting Retry Config request" 6523 " type 0x%x, page 0x%x," 6524 " action %d\n", ioc->name, page_type, 6525 pCfg->cfghdr.hdr->PageNumber, pCfg->action); 6526 retry_count++; 6527 goto retry_config; 6528 } 6529 } 6530 return ret; 6531 6532 } 6533 6534 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6535 /** 6536 * mpt_ioc_reset - Base cleanup for hard reset 6537 * @ioc: Pointer to the adapter structure 6538 * @reset_phase: Indicates pre- or post-reset functionality 6539 * 6540 * Remark: Frees resources with internally generated commands. 6541 */ 6542 static int 6543 mpt_ioc_reset(MPT_ADAPTER *ioc, int reset_phase) 6544 { 6545 switch (reset_phase) { 6546 case MPT_IOC_SETUP_RESET: 6547 ioc->taskmgmt_quiesce_io = 1; 6548 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6549 "%s: MPT_IOC_SETUP_RESET\n", ioc->name, __func__)); 6550 break; 6551 case MPT_IOC_PRE_RESET: 6552 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6553 "%s: MPT_IOC_PRE_RESET\n", ioc->name, __func__)); 6554 break; 6555 case MPT_IOC_POST_RESET: 6556 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6557 "%s: MPT_IOC_POST_RESET\n", ioc->name, __func__)); 6558 /* wake up mptbase_cmds */ 6559 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) { 6560 ioc->mptbase_cmds.status |= 6561 MPT_MGMT_STATUS_DID_IOCRESET; 6562 complete(&ioc->mptbase_cmds.done); 6563 } 6564 /* wake up taskmgmt_cmds */ 6565 if (ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_PENDING) { 6566 ioc->taskmgmt_cmds.status |= 6567 MPT_MGMT_STATUS_DID_IOCRESET; 6568 complete(&ioc->taskmgmt_cmds.done); 6569 } 6570 break; 6571 default: 6572 break; 6573 } 6574 6575 return 1; /* currently means nothing really */ 6576 } 6577 6578 6579 #ifdef CONFIG_PROC_FS /* { */ 6580 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6581 /* 6582 * procfs (%MPT_PROCFS_MPTBASEDIR/...) support stuff... 6583 */ 6584 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6585 /** 6586 * procmpt_create - Create %MPT_PROCFS_MPTBASEDIR entries. 6587 * 6588 * Returns 0 for success, non-zero for failure. 6589 */ 6590 static int 6591 procmpt_create(void) 6592 { 6593 mpt_proc_root_dir = proc_mkdir(MPT_PROCFS_MPTBASEDIR, NULL); 6594 if (mpt_proc_root_dir == NULL) 6595 return -ENOTDIR; 6596 6597 proc_create_single("summary", S_IRUGO, mpt_proc_root_dir, 6598 mpt_summary_proc_show); 6599 proc_create_single("version", S_IRUGO, mpt_proc_root_dir, 6600 mpt_version_proc_show); 6601 return 0; 6602 } 6603 6604 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6605 /** 6606 * procmpt_destroy - Tear down %MPT_PROCFS_MPTBASEDIR entries. 6607 * 6608 * Returns 0 for success, non-zero for failure. 6609 */ 6610 static void 6611 procmpt_destroy(void) 6612 { 6613 remove_proc_entry("version", mpt_proc_root_dir); 6614 remove_proc_entry("summary", mpt_proc_root_dir); 6615 remove_proc_entry(MPT_PROCFS_MPTBASEDIR, NULL); 6616 } 6617 6618 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6619 /* 6620 * Handles read request from /proc/mpt/summary or /proc/mpt/iocN/summary. 6621 */ 6622 static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan); 6623 6624 static int mpt_summary_proc_show(struct seq_file *m, void *v) 6625 { 6626 MPT_ADAPTER *ioc = m->private; 6627 6628 if (ioc) { 6629 seq_mpt_print_ioc_summary(ioc, m, 1); 6630 } else { 6631 list_for_each_entry(ioc, &ioc_list, list) { 6632 seq_mpt_print_ioc_summary(ioc, m, 1); 6633 } 6634 } 6635 6636 return 0; 6637 } 6638 6639 static int mpt_version_proc_show(struct seq_file *m, void *v) 6640 { 6641 u8 cb_idx; 6642 int scsi, fc, sas, lan, ctl, targ, dmp; 6643 char *drvname; 6644 6645 seq_printf(m, "%s-%s\n", "mptlinux", MPT_LINUX_VERSION_COMMON); 6646 seq_printf(m, " Fusion MPT base driver\n"); 6647 6648 scsi = fc = sas = lan = ctl = targ = dmp = 0; 6649 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 6650 drvname = NULL; 6651 if (MptCallbacks[cb_idx]) { 6652 switch (MptDriverClass[cb_idx]) { 6653 case MPTSPI_DRIVER: 6654 if (!scsi++) drvname = "SPI host"; 6655 break; 6656 case MPTFC_DRIVER: 6657 if (!fc++) drvname = "FC host"; 6658 break; 6659 case MPTSAS_DRIVER: 6660 if (!sas++) drvname = "SAS host"; 6661 break; 6662 case MPTLAN_DRIVER: 6663 if (!lan++) drvname = "LAN"; 6664 break; 6665 case MPTSTM_DRIVER: 6666 if (!targ++) drvname = "SCSI target"; 6667 break; 6668 case MPTCTL_DRIVER: 6669 if (!ctl++) drvname = "ioctl"; 6670 break; 6671 } 6672 6673 if (drvname) 6674 seq_printf(m, " Fusion MPT %s driver\n", drvname); 6675 } 6676 } 6677 6678 return 0; 6679 } 6680 6681 static int mpt_iocinfo_proc_show(struct seq_file *m, void *v) 6682 { 6683 MPT_ADAPTER *ioc = m->private; 6684 char expVer[32]; 6685 int sz; 6686 int p; 6687 6688 mpt_get_fw_exp_ver(expVer, ioc); 6689 6690 seq_printf(m, "%s:", ioc->name); 6691 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT) 6692 seq_printf(m, " (f/w download boot flag set)"); 6693 // if (ioc->facts.IOCExceptions & MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL) 6694 // seq_printf(m, " CONFIG_CHECKSUM_FAIL!"); 6695 6696 seq_printf(m, "\n ProductID = 0x%04x (%s)\n", 6697 ioc->facts.ProductID, 6698 ioc->prod_name); 6699 seq_printf(m, " FWVersion = 0x%08x%s", ioc->facts.FWVersion.Word, expVer); 6700 if (ioc->facts.FWImageSize) 6701 seq_printf(m, " (fw_size=%d)", ioc->facts.FWImageSize); 6702 seq_printf(m, "\n MsgVersion = 0x%04x\n", ioc->facts.MsgVersion); 6703 seq_printf(m, " FirstWhoInit = 0x%02x\n", ioc->FirstWhoInit); 6704 seq_printf(m, " EventState = 0x%02x\n", ioc->facts.EventState); 6705 6706 seq_printf(m, " CurrentHostMfaHighAddr = 0x%08x\n", 6707 ioc->facts.CurrentHostMfaHighAddr); 6708 seq_printf(m, " CurrentSenseBufferHighAddr = 0x%08x\n", 6709 ioc->facts.CurrentSenseBufferHighAddr); 6710 6711 seq_printf(m, " MaxChainDepth = 0x%02x frames\n", ioc->facts.MaxChainDepth); 6712 seq_printf(m, " MinBlockSize = 0x%02x bytes\n", 4*ioc->facts.BlockSize); 6713 6714 seq_printf(m, " RequestFrames @ 0x%p (Dma @ 0x%p)\n", 6715 (void *)ioc->req_frames, (void *)(ulong)ioc->req_frames_dma); 6716 /* 6717 * Rounding UP to nearest 4-kB boundary here... 6718 */ 6719 sz = (ioc->req_sz * ioc->req_depth) + 128; 6720 sz = ((sz + 0x1000UL - 1UL) / 0x1000) * 0x1000; 6721 seq_printf(m, " {CurReqSz=%d} x {CurReqDepth=%d} = %d bytes ^= 0x%x\n", 6722 ioc->req_sz, ioc->req_depth, ioc->req_sz*ioc->req_depth, sz); 6723 seq_printf(m, " {MaxReqSz=%d} {MaxReqDepth=%d}\n", 6724 4*ioc->facts.RequestFrameSize, 6725 ioc->facts.GlobalCredits); 6726 6727 seq_printf(m, " Frames @ 0x%p (Dma @ 0x%p)\n", 6728 (void *)ioc->alloc, (void *)(ulong)ioc->alloc_dma); 6729 sz = (ioc->reply_sz * ioc->reply_depth) + 128; 6730 seq_printf(m, " {CurRepSz=%d} x {CurRepDepth=%d} = %d bytes ^= 0x%x\n", 6731 ioc->reply_sz, ioc->reply_depth, ioc->reply_sz*ioc->reply_depth, sz); 6732 seq_printf(m, " {MaxRepSz=%d} {MaxRepDepth=%d}\n", 6733 ioc->facts.CurReplyFrameSize, 6734 ioc->facts.ReplyQueueDepth); 6735 6736 seq_printf(m, " MaxDevices = %d\n", 6737 (ioc->facts.MaxDevices==0) ? 255 : ioc->facts.MaxDevices); 6738 seq_printf(m, " MaxBuses = %d\n", ioc->facts.MaxBuses); 6739 6740 /* per-port info */ 6741 for (p=0; p < ioc->facts.NumberOfPorts; p++) { 6742 seq_printf(m, " PortNumber = %d (of %d)\n", 6743 p+1, 6744 ioc->facts.NumberOfPorts); 6745 if (ioc->bus_type == FC) { 6746 if (ioc->pfacts[p].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) { 6747 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow; 6748 seq_printf(m, " LanAddr = %pMR\n", a); 6749 } 6750 seq_printf(m, " WWN = %08X%08X:%08X%08X\n", 6751 ioc->fc_port_page0[p].WWNN.High, 6752 ioc->fc_port_page0[p].WWNN.Low, 6753 ioc->fc_port_page0[p].WWPN.High, 6754 ioc->fc_port_page0[p].WWPN.Low); 6755 } 6756 } 6757 6758 return 0; 6759 } 6760 #endif /* CONFIG_PROC_FS } */ 6761 6762 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6763 static void 6764 mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc) 6765 { 6766 buf[0] ='\0'; 6767 if ((ioc->facts.FWVersion.Word >> 24) == 0x0E) { 6768 sprintf(buf, " (Exp %02d%02d)", 6769 (ioc->facts.FWVersion.Word >> 16) & 0x00FF, /* Month */ 6770 (ioc->facts.FWVersion.Word >> 8) & 0x1F); /* Day */ 6771 6772 /* insider hack! */ 6773 if ((ioc->facts.FWVersion.Word >> 8) & 0x80) 6774 strcat(buf, " [MDBG]"); 6775 } 6776 } 6777 6778 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 6779 /** 6780 * mpt_print_ioc_summary - Write ASCII summary of IOC to a buffer. 6781 * @ioc: Pointer to MPT_ADAPTER structure 6782 * @buffer: Pointer to buffer where IOC summary info should be written 6783 * @size: Pointer to number of bytes we wrote (set by this routine) 6784 * @len: Offset at which to start writing in buffer 6785 * @showlan: Display LAN stuff? 6786 * 6787 * This routine writes (english readable) ASCII text, which represents 6788 * a summary of IOC information, to a buffer. 6789 */ 6790 void 6791 mpt_print_ioc_summary(MPT_ADAPTER *ioc, char *buffer, int *size, int len, int showlan) 6792 { 6793 char expVer[32]; 6794 int y; 6795 6796 mpt_get_fw_exp_ver(expVer, ioc); 6797 6798 /* 6799 * Shorter summary of attached ioc's... 6800 */ 6801 y = sprintf(buffer+len, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d", 6802 ioc->name, 6803 ioc->prod_name, 6804 MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */ 6805 ioc->facts.FWVersion.Word, 6806 expVer, 6807 ioc->facts.NumberOfPorts, 6808 ioc->req_depth); 6809 6810 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) { 6811 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow; 6812 y += sprintf(buffer+len+y, ", LanAddr=%pMR", a); 6813 } 6814 6815 y += sprintf(buffer+len+y, ", IRQ=%d", ioc->pci_irq); 6816 6817 if (!ioc->active) 6818 y += sprintf(buffer+len+y, " (disabled)"); 6819 6820 y += sprintf(buffer+len+y, "\n"); 6821 6822 *size = y; 6823 } 6824 6825 #ifdef CONFIG_PROC_FS 6826 static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan) 6827 { 6828 char expVer[32]; 6829 6830 mpt_get_fw_exp_ver(expVer, ioc); 6831 6832 /* 6833 * Shorter summary of attached ioc's... 6834 */ 6835 seq_printf(m, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d", 6836 ioc->name, 6837 ioc->prod_name, 6838 MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */ 6839 ioc->facts.FWVersion.Word, 6840 expVer, 6841 ioc->facts.NumberOfPorts, 6842 ioc->req_depth); 6843 6844 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) { 6845 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow; 6846 seq_printf(m, ", LanAddr=%pMR", a); 6847 } 6848 6849 seq_printf(m, ", IRQ=%d", ioc->pci_irq); 6850 6851 if (!ioc->active) 6852 seq_printf(m, " (disabled)"); 6853 6854 seq_putc(m, '\n'); 6855 } 6856 #endif 6857 6858 /** 6859 * mpt_set_taskmgmt_in_progress_flag - set flags associated with task management 6860 * @ioc: Pointer to MPT_ADAPTER structure 6861 * 6862 * Returns 0 for SUCCESS or -1 if FAILED. 6863 * 6864 * If -1 is return, then it was not possible to set the flags 6865 **/ 6866 int 6867 mpt_set_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc) 6868 { 6869 unsigned long flags; 6870 int retval; 6871 6872 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6873 if (ioc->ioc_reset_in_progress || ioc->taskmgmt_in_progress || 6874 (ioc->alt_ioc && ioc->alt_ioc->taskmgmt_in_progress)) { 6875 retval = -1; 6876 goto out; 6877 } 6878 retval = 0; 6879 ioc->taskmgmt_in_progress = 1; 6880 ioc->taskmgmt_quiesce_io = 1; 6881 if (ioc->alt_ioc) { 6882 ioc->alt_ioc->taskmgmt_in_progress = 1; 6883 ioc->alt_ioc->taskmgmt_quiesce_io = 1; 6884 } 6885 out: 6886 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6887 return retval; 6888 } 6889 EXPORT_SYMBOL(mpt_set_taskmgmt_in_progress_flag); 6890 6891 /** 6892 * mpt_clear_taskmgmt_in_progress_flag - clear flags associated with task management 6893 * @ioc: Pointer to MPT_ADAPTER structure 6894 * 6895 **/ 6896 void 6897 mpt_clear_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc) 6898 { 6899 unsigned long flags; 6900 6901 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6902 ioc->taskmgmt_in_progress = 0; 6903 ioc->taskmgmt_quiesce_io = 0; 6904 if (ioc->alt_ioc) { 6905 ioc->alt_ioc->taskmgmt_in_progress = 0; 6906 ioc->alt_ioc->taskmgmt_quiesce_io = 0; 6907 } 6908 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6909 } 6910 EXPORT_SYMBOL(mpt_clear_taskmgmt_in_progress_flag); 6911 6912 6913 /** 6914 * mpt_halt_firmware - Halts the firmware if it is operational and panic 6915 * the kernel 6916 * @ioc: Pointer to MPT_ADAPTER structure 6917 * 6918 **/ 6919 void 6920 mpt_halt_firmware(MPT_ADAPTER *ioc) 6921 { 6922 u32 ioc_raw_state; 6923 6924 ioc_raw_state = mpt_GetIocState(ioc, 0); 6925 6926 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) { 6927 printk(MYIOC_s_ERR_FMT "IOC is in FAULT state (%04xh)!!!\n", 6928 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK); 6929 panic("%s: IOC Fault (%04xh)!!!\n", ioc->name, 6930 ioc_raw_state & MPI_DOORBELL_DATA_MASK); 6931 } else { 6932 CHIPREG_WRITE32(&ioc->chip->Doorbell, 0xC0FFEE00); 6933 panic("%s: Firmware is halted due to command timeout\n", 6934 ioc->name); 6935 } 6936 } 6937 EXPORT_SYMBOL(mpt_halt_firmware); 6938 6939 /** 6940 * mpt_SoftResetHandler - Issues a less expensive reset 6941 * @ioc: Pointer to MPT_ADAPTER structure 6942 * @sleepFlag: Indicates if sleep or schedule must be called. 6943 * 6944 * Returns 0 for SUCCESS or -1 if FAILED. 6945 * 6946 * Message Unit Reset - instructs the IOC to reset the Reply Post and 6947 * Free FIFO's. All the Message Frames on Reply Free FIFO are discarded. 6948 * All posted buffers are freed, and event notification is turned off. 6949 * IOC doesn't reply to any outstanding request. This will transfer IOC 6950 * to READY state. 6951 **/ 6952 static int 6953 mpt_SoftResetHandler(MPT_ADAPTER *ioc, int sleepFlag) 6954 { 6955 int rc; 6956 int ii; 6957 u8 cb_idx; 6958 unsigned long flags; 6959 u32 ioc_state; 6960 unsigned long time_count; 6961 6962 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SoftResetHandler Entered!\n", 6963 ioc->name)); 6964 6965 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK; 6966 6967 if (mpt_fwfault_debug) 6968 mpt_halt_firmware(ioc); 6969 6970 if (ioc_state == MPI_IOC_STATE_FAULT || 6971 ioc_state == MPI_IOC_STATE_RESET) { 6972 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6973 "skipping, either in FAULT or RESET state!\n", ioc->name)); 6974 return -1; 6975 } 6976 6977 if (ioc->bus_type == FC) { 6978 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 6979 "skipping, because the bus type is FC!\n", ioc->name)); 6980 return -1; 6981 } 6982 6983 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6984 if (ioc->ioc_reset_in_progress) { 6985 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6986 return -1; 6987 } 6988 ioc->ioc_reset_in_progress = 1; 6989 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 6990 6991 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 6992 if (MptResetHandlers[cb_idx]) 6993 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET); 6994 } 6995 6996 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 6997 if (ioc->taskmgmt_in_progress) { 6998 ioc->ioc_reset_in_progress = 0; 6999 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7000 return -1; 7001 } 7002 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7003 /* Disable reply interrupts (also blocks FreeQ) */ 7004 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF); 7005 ioc->active = 0; 7006 time_count = jiffies; 7007 7008 rc = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag); 7009 7010 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7011 if (MptResetHandlers[cb_idx]) 7012 mpt_signal_reset(cb_idx, ioc, MPT_IOC_PRE_RESET); 7013 } 7014 7015 if (rc) 7016 goto out; 7017 7018 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK; 7019 if (ioc_state != MPI_IOC_STATE_READY) 7020 goto out; 7021 7022 for (ii = 0; ii < 5; ii++) { 7023 /* Get IOC facts! Allow 5 retries */ 7024 rc = GetIocFacts(ioc, sleepFlag, 7025 MPT_HOSTEVENT_IOC_RECOVER); 7026 if (rc == 0) 7027 break; 7028 if (sleepFlag == CAN_SLEEP) 7029 msleep(100); 7030 else 7031 mdelay(100); 7032 } 7033 if (ii == 5) 7034 goto out; 7035 7036 rc = PrimeIocFifos(ioc); 7037 if (rc != 0) 7038 goto out; 7039 7040 rc = SendIocInit(ioc, sleepFlag); 7041 if (rc != 0) 7042 goto out; 7043 7044 rc = SendEventNotification(ioc, 1, sleepFlag); 7045 if (rc != 0) 7046 goto out; 7047 7048 if (ioc->hard_resets < -1) 7049 ioc->hard_resets++; 7050 7051 /* 7052 * At this point, we know soft reset succeeded. 7053 */ 7054 7055 ioc->active = 1; 7056 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM); 7057 7058 out: 7059 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 7060 ioc->ioc_reset_in_progress = 0; 7061 ioc->taskmgmt_quiesce_io = 0; 7062 ioc->taskmgmt_in_progress = 0; 7063 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7064 7065 if (ioc->active) { /* otherwise, hard reset coming */ 7066 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7067 if (MptResetHandlers[cb_idx]) 7068 mpt_signal_reset(cb_idx, ioc, 7069 MPT_IOC_POST_RESET); 7070 } 7071 } 7072 7073 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT 7074 "SoftResetHandler: completed (%d seconds): %s\n", 7075 ioc->name, jiffies_to_msecs(jiffies - time_count)/1000, 7076 ((rc == 0) ? "SUCCESS" : "FAILED"))); 7077 7078 return rc; 7079 } 7080 7081 /** 7082 * mpt_Soft_Hard_ResetHandler - Try less expensive reset 7083 * @ioc: Pointer to MPT_ADAPTER structure 7084 * @sleepFlag: Indicates if sleep or schedule must be called. 7085 * 7086 * Returns 0 for SUCCESS or -1 if FAILED. 7087 * Try for softreset first, only if it fails go for expensive 7088 * HardReset. 7089 **/ 7090 int 7091 mpt_Soft_Hard_ResetHandler(MPT_ADAPTER *ioc, int sleepFlag) { 7092 int ret = -1; 7093 7094 ret = mpt_SoftResetHandler(ioc, sleepFlag); 7095 if (ret == 0) 7096 return ret; 7097 ret = mpt_HardResetHandler(ioc, sleepFlag); 7098 return ret; 7099 } 7100 EXPORT_SYMBOL(mpt_Soft_Hard_ResetHandler); 7101 7102 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7103 /* 7104 * Reset Handling 7105 */ 7106 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7107 /** 7108 * mpt_HardResetHandler - Generic reset handler 7109 * @ioc: Pointer to MPT_ADAPTER structure 7110 * @sleepFlag: Indicates if sleep or schedule must be called. 7111 * 7112 * Issues SCSI Task Management call based on input arg values. 7113 * If TaskMgmt fails, returns associated SCSI request. 7114 * 7115 * Remark: _HardResetHandler can be invoked from an interrupt thread (timer) 7116 * or a non-interrupt thread. In the former, must not call schedule(). 7117 * 7118 * Note: A return of -1 is a FATAL error case, as it means a 7119 * FW reload/initialization failed. 7120 * 7121 * Returns 0 for SUCCESS or -1 if FAILED. 7122 */ 7123 int 7124 mpt_HardResetHandler(MPT_ADAPTER *ioc, int sleepFlag) 7125 { 7126 int rc; 7127 u8 cb_idx; 7128 unsigned long flags; 7129 unsigned long time_count; 7130 7131 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HardResetHandler Entered!\n", ioc->name)); 7132 #ifdef MFCNT 7133 printk(MYIOC_s_INFO_FMT "HardResetHandler Entered!\n", ioc->name); 7134 printk("MF count 0x%x !\n", ioc->mfcnt); 7135 #endif 7136 if (mpt_fwfault_debug) 7137 mpt_halt_firmware(ioc); 7138 7139 /* Reset the adapter. Prevent more than 1 call to 7140 * mpt_do_ioc_recovery at any instant in time. 7141 */ 7142 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 7143 if (ioc->ioc_reset_in_progress) { 7144 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7145 ioc->wait_on_reset_completion = 1; 7146 do { 7147 ssleep(1); 7148 } while (ioc->ioc_reset_in_progress == 1); 7149 ioc->wait_on_reset_completion = 0; 7150 return ioc->reset_status; 7151 } 7152 if (ioc->wait_on_reset_completion) { 7153 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7154 rc = 0; 7155 time_count = jiffies; 7156 goto exit; 7157 } 7158 ioc->ioc_reset_in_progress = 1; 7159 if (ioc->alt_ioc) 7160 ioc->alt_ioc->ioc_reset_in_progress = 1; 7161 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7162 7163 7164 /* The SCSI driver needs to adjust timeouts on all current 7165 * commands prior to the diagnostic reset being issued. 7166 * Prevents timeouts occurring during a diagnostic reset...very bad. 7167 * For all other protocol drivers, this is a no-op. 7168 */ 7169 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7170 if (MptResetHandlers[cb_idx]) { 7171 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET); 7172 if (ioc->alt_ioc) 7173 mpt_signal_reset(cb_idx, ioc->alt_ioc, 7174 MPT_IOC_SETUP_RESET); 7175 } 7176 } 7177 7178 time_count = jiffies; 7179 rc = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_RECOVER, sleepFlag); 7180 if (rc != 0) { 7181 printk(KERN_WARNING MYNAM 7182 ": WARNING - (%d) Cannot recover %s, doorbell=0x%08x\n", 7183 rc, ioc->name, mpt_GetIocState(ioc, 0)); 7184 } else { 7185 if (ioc->hard_resets < -1) 7186 ioc->hard_resets++; 7187 } 7188 7189 spin_lock_irqsave(&ioc->taskmgmt_lock, flags); 7190 ioc->ioc_reset_in_progress = 0; 7191 ioc->taskmgmt_quiesce_io = 0; 7192 ioc->taskmgmt_in_progress = 0; 7193 ioc->reset_status = rc; 7194 if (ioc->alt_ioc) { 7195 ioc->alt_ioc->ioc_reset_in_progress = 0; 7196 ioc->alt_ioc->taskmgmt_quiesce_io = 0; 7197 ioc->alt_ioc->taskmgmt_in_progress = 0; 7198 } 7199 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags); 7200 7201 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7202 if (MptResetHandlers[cb_idx]) { 7203 mpt_signal_reset(cb_idx, ioc, MPT_IOC_POST_RESET); 7204 if (ioc->alt_ioc) 7205 mpt_signal_reset(cb_idx, 7206 ioc->alt_ioc, MPT_IOC_POST_RESET); 7207 } 7208 } 7209 exit: 7210 dtmprintk(ioc, 7211 printk(MYIOC_s_DEBUG_FMT 7212 "HardResetHandler: completed (%d seconds): %s\n", ioc->name, 7213 jiffies_to_msecs(jiffies - time_count)/1000, ((rc == 0) ? 7214 "SUCCESS" : "FAILED"))); 7215 7216 return rc; 7217 } 7218 7219 #ifdef CONFIG_FUSION_LOGGING 7220 static void 7221 mpt_display_event_info(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply) 7222 { 7223 char *ds = NULL; 7224 u32 evData0; 7225 int ii; 7226 u8 event; 7227 char *evStr = ioc->evStr; 7228 7229 event = le32_to_cpu(pEventReply->Event) & 0xFF; 7230 evData0 = le32_to_cpu(pEventReply->Data[0]); 7231 7232 switch(event) { 7233 case MPI_EVENT_NONE: 7234 ds = "None"; 7235 break; 7236 case MPI_EVENT_LOG_DATA: 7237 ds = "Log Data"; 7238 break; 7239 case MPI_EVENT_STATE_CHANGE: 7240 ds = "State Change"; 7241 break; 7242 case MPI_EVENT_UNIT_ATTENTION: 7243 ds = "Unit Attention"; 7244 break; 7245 case MPI_EVENT_IOC_BUS_RESET: 7246 ds = "IOC Bus Reset"; 7247 break; 7248 case MPI_EVENT_EXT_BUS_RESET: 7249 ds = "External Bus Reset"; 7250 break; 7251 case MPI_EVENT_RESCAN: 7252 ds = "Bus Rescan Event"; 7253 break; 7254 case MPI_EVENT_LINK_STATUS_CHANGE: 7255 if (evData0 == MPI_EVENT_LINK_STATUS_FAILURE) 7256 ds = "Link Status(FAILURE) Change"; 7257 else 7258 ds = "Link Status(ACTIVE) Change"; 7259 break; 7260 case MPI_EVENT_LOOP_STATE_CHANGE: 7261 if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LIP) 7262 ds = "Loop State(LIP) Change"; 7263 else if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LPE) 7264 ds = "Loop State(LPE) Change"; 7265 else 7266 ds = "Loop State(LPB) Change"; 7267 break; 7268 case MPI_EVENT_LOGOUT: 7269 ds = "Logout"; 7270 break; 7271 case MPI_EVENT_EVENT_CHANGE: 7272 if (evData0) 7273 ds = "Events ON"; 7274 else 7275 ds = "Events OFF"; 7276 break; 7277 case MPI_EVENT_INTEGRATED_RAID: 7278 { 7279 u8 ReasonCode = (u8)(evData0 >> 16); 7280 switch (ReasonCode) { 7281 case MPI_EVENT_RAID_RC_VOLUME_CREATED : 7282 ds = "Integrated Raid: Volume Created"; 7283 break; 7284 case MPI_EVENT_RAID_RC_VOLUME_DELETED : 7285 ds = "Integrated Raid: Volume Deleted"; 7286 break; 7287 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED : 7288 ds = "Integrated Raid: Volume Settings Changed"; 7289 break; 7290 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED : 7291 ds = "Integrated Raid: Volume Status Changed"; 7292 break; 7293 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED : 7294 ds = "Integrated Raid: Volume Physdisk Changed"; 7295 break; 7296 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED : 7297 ds = "Integrated Raid: Physdisk Created"; 7298 break; 7299 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED : 7300 ds = "Integrated Raid: Physdisk Deleted"; 7301 break; 7302 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED : 7303 ds = "Integrated Raid: Physdisk Settings Changed"; 7304 break; 7305 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED : 7306 ds = "Integrated Raid: Physdisk Status Changed"; 7307 break; 7308 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED : 7309 ds = "Integrated Raid: Domain Validation Needed"; 7310 break; 7311 case MPI_EVENT_RAID_RC_SMART_DATA : 7312 ds = "Integrated Raid; Smart Data"; 7313 break; 7314 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED : 7315 ds = "Integrated Raid: Replace Action Started"; 7316 break; 7317 default: 7318 ds = "Integrated Raid"; 7319 break; 7320 } 7321 break; 7322 } 7323 case MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE: 7324 ds = "SCSI Device Status Change"; 7325 break; 7326 case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE: 7327 { 7328 u8 id = (u8)(evData0); 7329 u8 channel = (u8)(evData0 >> 8); 7330 u8 ReasonCode = (u8)(evData0 >> 16); 7331 switch (ReasonCode) { 7332 case MPI_EVENT_SAS_DEV_STAT_RC_ADDED: 7333 snprintf(evStr, EVENT_DESCR_STR_SZ, 7334 "SAS Device Status Change: Added: " 7335 "id=%d channel=%d", id, channel); 7336 break; 7337 case MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING: 7338 snprintf(evStr, EVENT_DESCR_STR_SZ, 7339 "SAS Device Status Change: Deleted: " 7340 "id=%d channel=%d", id, channel); 7341 break; 7342 case MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA: 7343 snprintf(evStr, EVENT_DESCR_STR_SZ, 7344 "SAS Device Status Change: SMART Data: " 7345 "id=%d channel=%d", id, channel); 7346 break; 7347 case MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED: 7348 snprintf(evStr, EVENT_DESCR_STR_SZ, 7349 "SAS Device Status Change: No Persistency: " 7350 "id=%d channel=%d", id, channel); 7351 break; 7352 case MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED: 7353 snprintf(evStr, EVENT_DESCR_STR_SZ, 7354 "SAS Device Status Change: Unsupported Device " 7355 "Discovered : id=%d channel=%d", id, channel); 7356 break; 7357 case MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET: 7358 snprintf(evStr, EVENT_DESCR_STR_SZ, 7359 "SAS Device Status Change: Internal Device " 7360 "Reset : id=%d channel=%d", id, channel); 7361 break; 7362 case MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL: 7363 snprintf(evStr, EVENT_DESCR_STR_SZ, 7364 "SAS Device Status Change: Internal Task " 7365 "Abort : id=%d channel=%d", id, channel); 7366 break; 7367 case MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL: 7368 snprintf(evStr, EVENT_DESCR_STR_SZ, 7369 "SAS Device Status Change: Internal Abort " 7370 "Task Set : id=%d channel=%d", id, channel); 7371 break; 7372 case MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL: 7373 snprintf(evStr, EVENT_DESCR_STR_SZ, 7374 "SAS Device Status Change: Internal Clear " 7375 "Task Set : id=%d channel=%d", id, channel); 7376 break; 7377 case MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL: 7378 snprintf(evStr, EVENT_DESCR_STR_SZ, 7379 "SAS Device Status Change: Internal Query " 7380 "Task : id=%d channel=%d", id, channel); 7381 break; 7382 default: 7383 snprintf(evStr, EVENT_DESCR_STR_SZ, 7384 "SAS Device Status Change: Unknown: " 7385 "id=%d channel=%d", id, channel); 7386 break; 7387 } 7388 break; 7389 } 7390 case MPI_EVENT_ON_BUS_TIMER_EXPIRED: 7391 ds = "Bus Timer Expired"; 7392 break; 7393 case MPI_EVENT_QUEUE_FULL: 7394 { 7395 u16 curr_depth = (u16)(evData0 >> 16); 7396 u8 channel = (u8)(evData0 >> 8); 7397 u8 id = (u8)(evData0); 7398 7399 snprintf(evStr, EVENT_DESCR_STR_SZ, 7400 "Queue Full: channel=%d id=%d depth=%d", 7401 channel, id, curr_depth); 7402 break; 7403 } 7404 case MPI_EVENT_SAS_SES: 7405 ds = "SAS SES Event"; 7406 break; 7407 case MPI_EVENT_PERSISTENT_TABLE_FULL: 7408 ds = "Persistent Table Full"; 7409 break; 7410 case MPI_EVENT_SAS_PHY_LINK_STATUS: 7411 { 7412 u8 LinkRates = (u8)(evData0 >> 8); 7413 u8 PhyNumber = (u8)(evData0); 7414 LinkRates = (LinkRates & MPI_EVENT_SAS_PLS_LR_CURRENT_MASK) >> 7415 MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT; 7416 switch (LinkRates) { 7417 case MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN: 7418 snprintf(evStr, EVENT_DESCR_STR_SZ, 7419 "SAS PHY Link Status: Phy=%d:" 7420 " Rate Unknown",PhyNumber); 7421 break; 7422 case MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED: 7423 snprintf(evStr, EVENT_DESCR_STR_SZ, 7424 "SAS PHY Link Status: Phy=%d:" 7425 " Phy Disabled",PhyNumber); 7426 break; 7427 case MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION: 7428 snprintf(evStr, EVENT_DESCR_STR_SZ, 7429 "SAS PHY Link Status: Phy=%d:" 7430 " Failed Speed Nego",PhyNumber); 7431 break; 7432 case MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE: 7433 snprintf(evStr, EVENT_DESCR_STR_SZ, 7434 "SAS PHY Link Status: Phy=%d:" 7435 " Sata OOB Completed",PhyNumber); 7436 break; 7437 case MPI_EVENT_SAS_PLS_LR_RATE_1_5: 7438 snprintf(evStr, EVENT_DESCR_STR_SZ, 7439 "SAS PHY Link Status: Phy=%d:" 7440 " Rate 1.5 Gbps",PhyNumber); 7441 break; 7442 case MPI_EVENT_SAS_PLS_LR_RATE_3_0: 7443 snprintf(evStr, EVENT_DESCR_STR_SZ, 7444 "SAS PHY Link Status: Phy=%d:" 7445 " Rate 3.0 Gbps", PhyNumber); 7446 break; 7447 case MPI_EVENT_SAS_PLS_LR_RATE_6_0: 7448 snprintf(evStr, EVENT_DESCR_STR_SZ, 7449 "SAS PHY Link Status: Phy=%d:" 7450 " Rate 6.0 Gbps", PhyNumber); 7451 break; 7452 default: 7453 snprintf(evStr, EVENT_DESCR_STR_SZ, 7454 "SAS PHY Link Status: Phy=%d", PhyNumber); 7455 break; 7456 } 7457 break; 7458 } 7459 case MPI_EVENT_SAS_DISCOVERY_ERROR: 7460 ds = "SAS Discovery Error"; 7461 break; 7462 case MPI_EVENT_IR_RESYNC_UPDATE: 7463 { 7464 u8 resync_complete = (u8)(evData0 >> 16); 7465 snprintf(evStr, EVENT_DESCR_STR_SZ, 7466 "IR Resync Update: Complete = %d:",resync_complete); 7467 break; 7468 } 7469 case MPI_EVENT_IR2: 7470 { 7471 u8 id = (u8)(evData0); 7472 u8 channel = (u8)(evData0 >> 8); 7473 u8 phys_num = (u8)(evData0 >> 24); 7474 u8 ReasonCode = (u8)(evData0 >> 16); 7475 7476 switch (ReasonCode) { 7477 case MPI_EVENT_IR2_RC_LD_STATE_CHANGED: 7478 snprintf(evStr, EVENT_DESCR_STR_SZ, 7479 "IR2: LD State Changed: " 7480 "id=%d channel=%d phys_num=%d", 7481 id, channel, phys_num); 7482 break; 7483 case MPI_EVENT_IR2_RC_PD_STATE_CHANGED: 7484 snprintf(evStr, EVENT_DESCR_STR_SZ, 7485 "IR2: PD State Changed " 7486 "id=%d channel=%d phys_num=%d", 7487 id, channel, phys_num); 7488 break; 7489 case MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL: 7490 snprintf(evStr, EVENT_DESCR_STR_SZ, 7491 "IR2: Bad Block Table Full: " 7492 "id=%d channel=%d phys_num=%d", 7493 id, channel, phys_num); 7494 break; 7495 case MPI_EVENT_IR2_RC_PD_INSERTED: 7496 snprintf(evStr, EVENT_DESCR_STR_SZ, 7497 "IR2: PD Inserted: " 7498 "id=%d channel=%d phys_num=%d", 7499 id, channel, phys_num); 7500 break; 7501 case MPI_EVENT_IR2_RC_PD_REMOVED: 7502 snprintf(evStr, EVENT_DESCR_STR_SZ, 7503 "IR2: PD Removed: " 7504 "id=%d channel=%d phys_num=%d", 7505 id, channel, phys_num); 7506 break; 7507 case MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED: 7508 snprintf(evStr, EVENT_DESCR_STR_SZ, 7509 "IR2: Foreign CFG Detected: " 7510 "id=%d channel=%d phys_num=%d", 7511 id, channel, phys_num); 7512 break; 7513 case MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR: 7514 snprintf(evStr, EVENT_DESCR_STR_SZ, 7515 "IR2: Rebuild Medium Error: " 7516 "id=%d channel=%d phys_num=%d", 7517 id, channel, phys_num); 7518 break; 7519 case MPI_EVENT_IR2_RC_DUAL_PORT_ADDED: 7520 snprintf(evStr, EVENT_DESCR_STR_SZ, 7521 "IR2: Dual Port Added: " 7522 "id=%d channel=%d phys_num=%d", 7523 id, channel, phys_num); 7524 break; 7525 case MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED: 7526 snprintf(evStr, EVENT_DESCR_STR_SZ, 7527 "IR2: Dual Port Removed: " 7528 "id=%d channel=%d phys_num=%d", 7529 id, channel, phys_num); 7530 break; 7531 default: 7532 ds = "IR2"; 7533 break; 7534 } 7535 break; 7536 } 7537 case MPI_EVENT_SAS_DISCOVERY: 7538 { 7539 if (evData0) 7540 ds = "SAS Discovery: Start"; 7541 else 7542 ds = "SAS Discovery: Stop"; 7543 break; 7544 } 7545 case MPI_EVENT_LOG_ENTRY_ADDED: 7546 ds = "SAS Log Entry Added"; 7547 break; 7548 7549 case MPI_EVENT_SAS_BROADCAST_PRIMITIVE: 7550 { 7551 u8 phy_num = (u8)(evData0); 7552 u8 port_num = (u8)(evData0 >> 8); 7553 u8 port_width = (u8)(evData0 >> 16); 7554 u8 primitive = (u8)(evData0 >> 24); 7555 snprintf(evStr, EVENT_DESCR_STR_SZ, 7556 "SAS Broadcast Primitive: phy=%d port=%d " 7557 "width=%d primitive=0x%02x", 7558 phy_num, port_num, port_width, primitive); 7559 break; 7560 } 7561 7562 case MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 7563 { 7564 u8 reason = (u8)(evData0); 7565 7566 switch (reason) { 7567 case MPI_EVENT_SAS_INIT_RC_ADDED: 7568 ds = "SAS Initiator Status Change: Added"; 7569 break; 7570 case MPI_EVENT_SAS_INIT_RC_REMOVED: 7571 ds = "SAS Initiator Status Change: Deleted"; 7572 break; 7573 default: 7574 ds = "SAS Initiator Status Change"; 7575 break; 7576 } 7577 break; 7578 } 7579 7580 case MPI_EVENT_SAS_INIT_TABLE_OVERFLOW: 7581 { 7582 u8 max_init = (u8)(evData0); 7583 u8 current_init = (u8)(evData0 >> 8); 7584 7585 snprintf(evStr, EVENT_DESCR_STR_SZ, 7586 "SAS Initiator Device Table Overflow: max initiators=%02d " 7587 "current initiators=%02d", 7588 max_init, current_init); 7589 break; 7590 } 7591 case MPI_EVENT_SAS_SMP_ERROR: 7592 { 7593 u8 status = (u8)(evData0); 7594 u8 port_num = (u8)(evData0 >> 8); 7595 u8 result = (u8)(evData0 >> 16); 7596 7597 if (status == MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID) 7598 snprintf(evStr, EVENT_DESCR_STR_SZ, 7599 "SAS SMP Error: port=%d result=0x%02x", 7600 port_num, result); 7601 else if (status == MPI_EVENT_SAS_SMP_CRC_ERROR) 7602 snprintf(evStr, EVENT_DESCR_STR_SZ, 7603 "SAS SMP Error: port=%d : CRC Error", 7604 port_num); 7605 else if (status == MPI_EVENT_SAS_SMP_TIMEOUT) 7606 snprintf(evStr, EVENT_DESCR_STR_SZ, 7607 "SAS SMP Error: port=%d : Timeout", 7608 port_num); 7609 else if (status == MPI_EVENT_SAS_SMP_NO_DESTINATION) 7610 snprintf(evStr, EVENT_DESCR_STR_SZ, 7611 "SAS SMP Error: port=%d : No Destination", 7612 port_num); 7613 else if (status == MPI_EVENT_SAS_SMP_BAD_DESTINATION) 7614 snprintf(evStr, EVENT_DESCR_STR_SZ, 7615 "SAS SMP Error: port=%d : Bad Destination", 7616 port_num); 7617 else 7618 snprintf(evStr, EVENT_DESCR_STR_SZ, 7619 "SAS SMP Error: port=%d : status=0x%02x", 7620 port_num, status); 7621 break; 7622 } 7623 7624 case MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE: 7625 { 7626 u8 reason = (u8)(evData0); 7627 7628 switch (reason) { 7629 case MPI_EVENT_SAS_EXP_RC_ADDED: 7630 ds = "Expander Status Change: Added"; 7631 break; 7632 case MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING: 7633 ds = "Expander Status Change: Deleted"; 7634 break; 7635 default: 7636 ds = "Expander Status Change"; 7637 break; 7638 } 7639 break; 7640 } 7641 7642 /* 7643 * MPT base "custom" events may be added here... 7644 */ 7645 default: 7646 ds = "Unknown"; 7647 break; 7648 } 7649 if (ds) 7650 strlcpy(evStr, ds, EVENT_DESCR_STR_SZ); 7651 7652 7653 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT 7654 "MPT event:(%02Xh) : %s\n", 7655 ioc->name, event, evStr)); 7656 7657 devtverboseprintk(ioc, printk(KERN_DEBUG MYNAM 7658 ": Event data:\n")); 7659 for (ii = 0; ii < le16_to_cpu(pEventReply->EventDataLength); ii++) 7660 devtverboseprintk(ioc, printk(" %08x", 7661 le32_to_cpu(pEventReply->Data[ii]))); 7662 devtverboseprintk(ioc, printk(KERN_DEBUG "\n")); 7663 } 7664 #endif 7665 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7666 /** 7667 * ProcessEventNotification - Route EventNotificationReply to all event handlers 7668 * @ioc: Pointer to MPT_ADAPTER structure 7669 * @pEventReply: Pointer to EventNotification reply frame 7670 * @evHandlers: Pointer to integer, number of event handlers 7671 * 7672 * Routes a received EventNotificationReply to all currently registered 7673 * event handlers. 7674 * Returns sum of event handlers return values. 7675 */ 7676 static int 7677 ProcessEventNotification(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply, int *evHandlers) 7678 { 7679 u16 evDataLen; 7680 u32 evData0 = 0; 7681 int ii; 7682 u8 cb_idx; 7683 int r = 0; 7684 int handlers = 0; 7685 u8 event; 7686 7687 /* 7688 * Do platform normalization of values 7689 */ 7690 event = le32_to_cpu(pEventReply->Event) & 0xFF; 7691 evDataLen = le16_to_cpu(pEventReply->EventDataLength); 7692 if (evDataLen) { 7693 evData0 = le32_to_cpu(pEventReply->Data[0]); 7694 } 7695 7696 #ifdef CONFIG_FUSION_LOGGING 7697 if (evDataLen) 7698 mpt_display_event_info(ioc, pEventReply); 7699 #endif 7700 7701 /* 7702 * Do general / base driver event processing 7703 */ 7704 switch(event) { 7705 case MPI_EVENT_EVENT_CHANGE: /* 0A */ 7706 if (evDataLen) { 7707 u8 evState = evData0 & 0xFF; 7708 7709 /* CHECKME! What if evState unexpectedly says OFF (0)? */ 7710 7711 /* Update EventState field in cached IocFacts */ 7712 if (ioc->facts.Function) { 7713 ioc->facts.EventState = evState; 7714 } 7715 } 7716 break; 7717 case MPI_EVENT_INTEGRATED_RAID: 7718 mptbase_raid_process_event_data(ioc, 7719 (MpiEventDataRaid_t *)pEventReply->Data); 7720 break; 7721 default: 7722 break; 7723 } 7724 7725 /* 7726 * Should this event be logged? Events are written sequentially. 7727 * When buffer is full, start again at the top. 7728 */ 7729 if (ioc->events && (ioc->eventTypes & ( 1 << event))) { 7730 int idx; 7731 7732 idx = ioc->eventContext % MPTCTL_EVENT_LOG_SIZE; 7733 7734 ioc->events[idx].event = event; 7735 ioc->events[idx].eventContext = ioc->eventContext; 7736 7737 for (ii = 0; ii < 2; ii++) { 7738 if (ii < evDataLen) 7739 ioc->events[idx].data[ii] = le32_to_cpu(pEventReply->Data[ii]); 7740 else 7741 ioc->events[idx].data[ii] = 0; 7742 } 7743 7744 ioc->eventContext++; 7745 } 7746 7747 7748 /* 7749 * Call each currently registered protocol event handler. 7750 */ 7751 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) { 7752 if (MptEvHandlers[cb_idx]) { 7753 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT 7754 "Routing Event to event handler #%d\n", 7755 ioc->name, cb_idx)); 7756 r += (*(MptEvHandlers[cb_idx]))(ioc, pEventReply); 7757 handlers++; 7758 } 7759 } 7760 /* FIXME? Examine results here? */ 7761 7762 /* 7763 * If needed, send (a single) EventAck. 7764 */ 7765 if (pEventReply->AckRequired == MPI_EVENT_NOTIFICATION_ACK_REQUIRED) { 7766 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT 7767 "EventAck required\n",ioc->name)); 7768 if ((ii = SendEventAck(ioc, pEventReply)) != 0) { 7769 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SendEventAck returned %d\n", 7770 ioc->name, ii)); 7771 } 7772 } 7773 7774 *evHandlers = handlers; 7775 return r; 7776 } 7777 7778 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7779 /** 7780 * mpt_fc_log_info - Log information returned from Fibre Channel IOC. 7781 * @ioc: Pointer to MPT_ADAPTER structure 7782 * @log_info: U32 LogInfo reply word from the IOC 7783 * 7784 * Refer to lsi/mpi_log_fc.h. 7785 */ 7786 static void 7787 mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info) 7788 { 7789 char *desc = "unknown"; 7790 7791 switch (log_info & 0xFF000000) { 7792 case MPI_IOCLOGINFO_FC_INIT_BASE: 7793 desc = "FCP Initiator"; 7794 break; 7795 case MPI_IOCLOGINFO_FC_TARGET_BASE: 7796 desc = "FCP Target"; 7797 break; 7798 case MPI_IOCLOGINFO_FC_LAN_BASE: 7799 desc = "LAN"; 7800 break; 7801 case MPI_IOCLOGINFO_FC_MSG_BASE: 7802 desc = "MPI Message Layer"; 7803 break; 7804 case MPI_IOCLOGINFO_FC_LINK_BASE: 7805 desc = "FC Link"; 7806 break; 7807 case MPI_IOCLOGINFO_FC_CTX_BASE: 7808 desc = "Context Manager"; 7809 break; 7810 case MPI_IOCLOGINFO_FC_INVALID_FIELD_BYTE_OFFSET: 7811 desc = "Invalid Field Offset"; 7812 break; 7813 case MPI_IOCLOGINFO_FC_STATE_CHANGE: 7814 desc = "State Change Info"; 7815 break; 7816 } 7817 7818 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): SubClass={%s}, Value=(0x%06x)\n", 7819 ioc->name, log_info, desc, (log_info & 0xFFFFFF)); 7820 } 7821 7822 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 7823 /** 7824 * mpt_spi_log_info - Log information returned from SCSI Parallel IOC. 7825 * @ioc: Pointer to MPT_ADAPTER structure 7826 * @log_info: U32 LogInfo word from the IOC 7827 * 7828 * Refer to lsi/sp_log.h. 7829 */ 7830 static void 7831 mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info) 7832 { 7833 u32 info = log_info & 0x00FF0000; 7834 char *desc = "unknown"; 7835 7836 switch (info) { 7837 case 0x00010000: 7838 desc = "bug! MID not found"; 7839 break; 7840 7841 case 0x00020000: 7842 desc = "Parity Error"; 7843 break; 7844 7845 case 0x00030000: 7846 desc = "ASYNC Outbound Overrun"; 7847 break; 7848 7849 case 0x00040000: 7850 desc = "SYNC Offset Error"; 7851 break; 7852 7853 case 0x00050000: 7854 desc = "BM Change"; 7855 break; 7856 7857 case 0x00060000: 7858 desc = "Msg In Overflow"; 7859 break; 7860 7861 case 0x00070000: 7862 desc = "DMA Error"; 7863 break; 7864 7865 case 0x00080000: 7866 desc = "Outbound DMA Overrun"; 7867 break; 7868 7869 case 0x00090000: 7870 desc = "Task Management"; 7871 break; 7872 7873 case 0x000A0000: 7874 desc = "Device Problem"; 7875 break; 7876 7877 case 0x000B0000: 7878 desc = "Invalid Phase Change"; 7879 break; 7880 7881 case 0x000C0000: 7882 desc = "Untagged Table Size"; 7883 break; 7884 7885 } 7886 7887 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): F/W: %s\n", ioc->name, log_info, desc); 7888 } 7889 7890 /* strings for sas loginfo */ 7891 static char *originator_str[] = { 7892 "IOP", /* 00h */ 7893 "PL", /* 01h */ 7894 "IR" /* 02h */ 7895 }; 7896 static char *iop_code_str[] = { 7897 NULL, /* 00h */ 7898 "Invalid SAS Address", /* 01h */ 7899 NULL, /* 02h */ 7900 "Invalid Page", /* 03h */ 7901 "Diag Message Error", /* 04h */ 7902 "Task Terminated", /* 05h */ 7903 "Enclosure Management", /* 06h */ 7904 "Target Mode" /* 07h */ 7905 }; 7906 static char *pl_code_str[] = { 7907 NULL, /* 00h */ 7908 "Open Failure", /* 01h */ 7909 "Invalid Scatter Gather List", /* 02h */ 7910 "Wrong Relative Offset or Frame Length", /* 03h */ 7911 "Frame Transfer Error", /* 04h */ 7912 "Transmit Frame Connected Low", /* 05h */ 7913 "SATA Non-NCQ RW Error Bit Set", /* 06h */ 7914 "SATA Read Log Receive Data Error", /* 07h */ 7915 "SATA NCQ Fail All Commands After Error", /* 08h */ 7916 "SATA Error in Receive Set Device Bit FIS", /* 09h */ 7917 "Receive Frame Invalid Message", /* 0Ah */ 7918 "Receive Context Message Valid Error", /* 0Bh */ 7919 "Receive Frame Current Frame Error", /* 0Ch */ 7920 "SATA Link Down", /* 0Dh */ 7921 "Discovery SATA Init W IOS", /* 0Eh */ 7922 "Config Invalid Page", /* 0Fh */ 7923 "Discovery SATA Init Timeout", /* 10h */ 7924 "Reset", /* 11h */ 7925 "Abort", /* 12h */ 7926 "IO Not Yet Executed", /* 13h */ 7927 "IO Executed", /* 14h */ 7928 "Persistent Reservation Out Not Affiliation " 7929 "Owner", /* 15h */ 7930 "Open Transmit DMA Abort", /* 16h */ 7931 "IO Device Missing Delay Retry", /* 17h */ 7932 "IO Cancelled Due to Receive Error", /* 18h */ 7933 NULL, /* 19h */ 7934 NULL, /* 1Ah */ 7935 NULL, /* 1Bh */ 7936 NULL, /* 1Ch */ 7937 NULL, /* 1Dh */ 7938 NULL, /* 1Eh */ 7939 NULL, /* 1Fh */ 7940 "Enclosure Management" /* 20h */ 7941 }; 7942 static char *ir_code_str[] = { 7943 "Raid Action Error", /* 00h */ 7944 NULL, /* 00h */ 7945 NULL, /* 01h */ 7946 NULL, /* 02h */ 7947 NULL, /* 03h */ 7948 NULL, /* 04h */ 7949 NULL, /* 05h */ 7950 NULL, /* 06h */ 7951 NULL /* 07h */ 7952 }; 7953 static char *raid_sub_code_str[] = { 7954 NULL, /* 00h */ 7955 "Volume Creation Failed: Data Passed too " 7956 "Large", /* 01h */ 7957 "Volume Creation Failed: Duplicate Volumes " 7958 "Attempted", /* 02h */ 7959 "Volume Creation Failed: Max Number " 7960 "Supported Volumes Exceeded", /* 03h */ 7961 "Volume Creation Failed: DMA Error", /* 04h */ 7962 "Volume Creation Failed: Invalid Volume Type", /* 05h */ 7963 "Volume Creation Failed: Error Reading " 7964 "MFG Page 4", /* 06h */ 7965 "Volume Creation Failed: Creating Internal " 7966 "Structures", /* 07h */ 7967 NULL, /* 08h */ 7968 NULL, /* 09h */ 7969 NULL, /* 0Ah */ 7970 NULL, /* 0Bh */ 7971 NULL, /* 0Ch */ 7972 NULL, /* 0Dh */ 7973 NULL, /* 0Eh */ 7974 NULL, /* 0Fh */ 7975 "Activation failed: Already Active Volume", /* 10h */ 7976 "Activation failed: Unsupported Volume Type", /* 11h */ 7977 "Activation failed: Too Many Active Volumes", /* 12h */ 7978 "Activation failed: Volume ID in Use", /* 13h */ 7979 "Activation failed: Reported Failure", /* 14h */ 7980 "Activation failed: Importing a Volume", /* 15h */ 7981 NULL, /* 16h */ 7982 NULL, /* 17h */ 7983 NULL, /* 18h */ 7984 NULL, /* 19h */ 7985 NULL, /* 1Ah */ 7986 NULL, /* 1Bh */ 7987 NULL, /* 1Ch */ 7988 NULL, /* 1Dh */ 7989 NULL, /* 1Eh */ 7990 NULL, /* 1Fh */ 7991 "Phys Disk failed: Too Many Phys Disks", /* 20h */ 7992 "Phys Disk failed: Data Passed too Large", /* 21h */ 7993 "Phys Disk failed: DMA Error", /* 22h */ 7994 "Phys Disk failed: Invalid <channel:id>", /* 23h */ 7995 "Phys Disk failed: Creating Phys Disk Config " 7996 "Page", /* 24h */ 7997 NULL, /* 25h */ 7998 NULL, /* 26h */ 7999 NULL, /* 27h */ 8000 NULL, /* 28h */ 8001 NULL, /* 29h */ 8002 NULL, /* 2Ah */ 8003 NULL, /* 2Bh */ 8004 NULL, /* 2Ch */ 8005 NULL, /* 2Dh */ 8006 NULL, /* 2Eh */ 8007 NULL, /* 2Fh */ 8008 "Compatibility Error: IR Disabled", /* 30h */ 8009 "Compatibility Error: Inquiry Command Failed", /* 31h */ 8010 "Compatibility Error: Device not Direct Access " 8011 "Device ", /* 32h */ 8012 "Compatibility Error: Removable Device Found", /* 33h */ 8013 "Compatibility Error: Device SCSI Version not " 8014 "2 or Higher", /* 34h */ 8015 "Compatibility Error: SATA Device, 48 BIT LBA " 8016 "not Supported", /* 35h */ 8017 "Compatibility Error: Device doesn't have " 8018 "512 Byte Block Sizes", /* 36h */ 8019 "Compatibility Error: Volume Type Check Failed", /* 37h */ 8020 "Compatibility Error: Volume Type is " 8021 "Unsupported by FW", /* 38h */ 8022 "Compatibility Error: Disk Drive too Small for " 8023 "use in Volume", /* 39h */ 8024 "Compatibility Error: Phys Disk for Create " 8025 "Volume not Found", /* 3Ah */ 8026 "Compatibility Error: Too Many or too Few " 8027 "Disks for Volume Type", /* 3Bh */ 8028 "Compatibility Error: Disk stripe Sizes " 8029 "Must be 64KB", /* 3Ch */ 8030 "Compatibility Error: IME Size Limited to < 2TB", /* 3Dh */ 8031 }; 8032 8033 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8034 /** 8035 * mpt_sas_log_info - Log information returned from SAS IOC. 8036 * @ioc: Pointer to MPT_ADAPTER structure 8037 * @log_info: U32 LogInfo reply word from the IOC 8038 * @cb_idx: callback function's handle 8039 * 8040 * Refer to lsi/mpi_log_sas.h. 8041 **/ 8042 static void 8043 mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info, u8 cb_idx) 8044 { 8045 union loginfo_type { 8046 u32 loginfo; 8047 struct { 8048 u32 subcode:16; 8049 u32 code:8; 8050 u32 originator:4; 8051 u32 bus_type:4; 8052 } dw; 8053 }; 8054 union loginfo_type sas_loginfo; 8055 char *originator_desc = NULL; 8056 char *code_desc = NULL; 8057 char *sub_code_desc = NULL; 8058 8059 sas_loginfo.loginfo = log_info; 8060 if ((sas_loginfo.dw.bus_type != 3 /*SAS*/) && 8061 (sas_loginfo.dw.originator < ARRAY_SIZE(originator_str))) 8062 return; 8063 8064 originator_desc = originator_str[sas_loginfo.dw.originator]; 8065 8066 switch (sas_loginfo.dw.originator) { 8067 8068 case 0: /* IOP */ 8069 if (sas_loginfo.dw.code < 8070 ARRAY_SIZE(iop_code_str)) 8071 code_desc = iop_code_str[sas_loginfo.dw.code]; 8072 break; 8073 case 1: /* PL */ 8074 if (sas_loginfo.dw.code < 8075 ARRAY_SIZE(pl_code_str)) 8076 code_desc = pl_code_str[sas_loginfo.dw.code]; 8077 break; 8078 case 2: /* IR */ 8079 if (sas_loginfo.dw.code >= 8080 ARRAY_SIZE(ir_code_str)) 8081 break; 8082 code_desc = ir_code_str[sas_loginfo.dw.code]; 8083 if (sas_loginfo.dw.subcode >= 8084 ARRAY_SIZE(raid_sub_code_str)) 8085 break; 8086 if (sas_loginfo.dw.code == 0) 8087 sub_code_desc = 8088 raid_sub_code_str[sas_loginfo.dw.subcode]; 8089 break; 8090 default: 8091 return; 8092 } 8093 8094 if (sub_code_desc != NULL) 8095 printk(MYIOC_s_INFO_FMT 8096 "LogInfo(0x%08x): Originator={%s}, Code={%s}," 8097 " SubCode={%s} cb_idx %s\n", 8098 ioc->name, log_info, originator_desc, code_desc, 8099 sub_code_desc, MptCallbacksName[cb_idx]); 8100 else if (code_desc != NULL) 8101 printk(MYIOC_s_INFO_FMT 8102 "LogInfo(0x%08x): Originator={%s}, Code={%s}," 8103 " SubCode(0x%04x) cb_idx %s\n", 8104 ioc->name, log_info, originator_desc, code_desc, 8105 sas_loginfo.dw.subcode, MptCallbacksName[cb_idx]); 8106 else 8107 printk(MYIOC_s_INFO_FMT 8108 "LogInfo(0x%08x): Originator={%s}, Code=(0x%02x)," 8109 " SubCode(0x%04x) cb_idx %s\n", 8110 ioc->name, log_info, originator_desc, 8111 sas_loginfo.dw.code, sas_loginfo.dw.subcode, 8112 MptCallbacksName[cb_idx]); 8113 } 8114 8115 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8116 /** 8117 * mpt_iocstatus_info_config - IOCSTATUS information for config pages 8118 * @ioc: Pointer to MPT_ADAPTER structure 8119 * @ioc_status: U32 IOCStatus word from IOC 8120 * @mf: Pointer to MPT request frame 8121 * 8122 * Refer to lsi/mpi.h. 8123 **/ 8124 static void 8125 mpt_iocstatus_info_config(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf) 8126 { 8127 Config_t *pReq = (Config_t *)mf; 8128 char extend_desc[EVENT_DESCR_STR_SZ]; 8129 char *desc = NULL; 8130 u32 form; 8131 u8 page_type; 8132 8133 if (pReq->Header.PageType == MPI_CONFIG_PAGETYPE_EXTENDED) 8134 page_type = pReq->ExtPageType; 8135 else 8136 page_type = pReq->Header.PageType; 8137 8138 /* 8139 * ignore invalid page messages for GET_NEXT_HANDLE 8140 */ 8141 form = le32_to_cpu(pReq->PageAddress); 8142 if (ioc_status == MPI_IOCSTATUS_CONFIG_INVALID_PAGE) { 8143 if (page_type == MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE || 8144 page_type == MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER || 8145 page_type == MPI_CONFIG_EXTPAGETYPE_ENCLOSURE) { 8146 if ((form >> MPI_SAS_DEVICE_PGAD_FORM_SHIFT) == 8147 MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE) 8148 return; 8149 } 8150 if (page_type == MPI_CONFIG_PAGETYPE_FC_DEVICE) 8151 if ((form & MPI_FC_DEVICE_PGAD_FORM_MASK) == 8152 MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 8153 return; 8154 } 8155 8156 snprintf(extend_desc, EVENT_DESCR_STR_SZ, 8157 "type=%02Xh, page=%02Xh, action=%02Xh, form=%08Xh", 8158 page_type, pReq->Header.PageNumber, pReq->Action, form); 8159 8160 switch (ioc_status) { 8161 8162 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */ 8163 desc = "Config Page Invalid Action"; 8164 break; 8165 8166 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */ 8167 desc = "Config Page Invalid Type"; 8168 break; 8169 8170 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */ 8171 desc = "Config Page Invalid Page"; 8172 break; 8173 8174 case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */ 8175 desc = "Config Page Invalid Data"; 8176 break; 8177 8178 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */ 8179 desc = "Config Page No Defaults"; 8180 break; 8181 8182 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */ 8183 desc = "Config Page Can't Commit"; 8184 break; 8185 } 8186 8187 if (!desc) 8188 return; 8189 8190 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s: %s\n", 8191 ioc->name, ioc_status, desc, extend_desc)); 8192 } 8193 8194 /** 8195 * mpt_iocstatus_info - IOCSTATUS information returned from IOC. 8196 * @ioc: Pointer to MPT_ADAPTER structure 8197 * @ioc_status: U32 IOCStatus word from IOC 8198 * @mf: Pointer to MPT request frame 8199 * 8200 * Refer to lsi/mpi.h. 8201 **/ 8202 static void 8203 mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf) 8204 { 8205 u32 status = ioc_status & MPI_IOCSTATUS_MASK; 8206 char *desc = NULL; 8207 8208 switch (status) { 8209 8210 /****************************************************************************/ 8211 /* Common IOCStatus values for all replies */ 8212 /****************************************************************************/ 8213 8214 case MPI_IOCSTATUS_INVALID_FUNCTION: /* 0x0001 */ 8215 desc = "Invalid Function"; 8216 break; 8217 8218 case MPI_IOCSTATUS_BUSY: /* 0x0002 */ 8219 desc = "Busy"; 8220 break; 8221 8222 case MPI_IOCSTATUS_INVALID_SGL: /* 0x0003 */ 8223 desc = "Invalid SGL"; 8224 break; 8225 8226 case MPI_IOCSTATUS_INTERNAL_ERROR: /* 0x0004 */ 8227 desc = "Internal Error"; 8228 break; 8229 8230 case MPI_IOCSTATUS_RESERVED: /* 0x0005 */ 8231 desc = "Reserved"; 8232 break; 8233 8234 case MPI_IOCSTATUS_INSUFFICIENT_RESOURCES: /* 0x0006 */ 8235 desc = "Insufficient Resources"; 8236 break; 8237 8238 case MPI_IOCSTATUS_INVALID_FIELD: /* 0x0007 */ 8239 desc = "Invalid Field"; 8240 break; 8241 8242 case MPI_IOCSTATUS_INVALID_STATE: /* 0x0008 */ 8243 desc = "Invalid State"; 8244 break; 8245 8246 /****************************************************************************/ 8247 /* Config IOCStatus values */ 8248 /****************************************************************************/ 8249 8250 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */ 8251 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */ 8252 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */ 8253 case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */ 8254 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */ 8255 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */ 8256 mpt_iocstatus_info_config(ioc, status, mf); 8257 break; 8258 8259 /****************************************************************************/ 8260 /* SCSIIO Reply (SPI, FCP, SAS) initiator values */ 8261 /* */ 8262 /* Look at mptscsih_iocstatus_info_scsiio in mptscsih.c */ 8263 /* */ 8264 /****************************************************************************/ 8265 8266 case MPI_IOCSTATUS_SCSI_RECOVERED_ERROR: /* 0x0040 */ 8267 case MPI_IOCSTATUS_SCSI_DATA_UNDERRUN: /* 0x0045 */ 8268 case MPI_IOCSTATUS_SCSI_INVALID_BUS: /* 0x0041 */ 8269 case MPI_IOCSTATUS_SCSI_INVALID_TARGETID: /* 0x0042 */ 8270 case MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE: /* 0x0043 */ 8271 case MPI_IOCSTATUS_SCSI_DATA_OVERRUN: /* 0x0044 */ 8272 case MPI_IOCSTATUS_SCSI_IO_DATA_ERROR: /* 0x0046 */ 8273 case MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR: /* 0x0047 */ 8274 case MPI_IOCSTATUS_SCSI_TASK_TERMINATED: /* 0x0048 */ 8275 case MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: /* 0x0049 */ 8276 case MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED: /* 0x004A */ 8277 case MPI_IOCSTATUS_SCSI_IOC_TERMINATED: /* 0x004B */ 8278 case MPI_IOCSTATUS_SCSI_EXT_TERMINATED: /* 0x004C */ 8279 break; 8280 8281 /****************************************************************************/ 8282 /* SCSI Target values */ 8283 /****************************************************************************/ 8284 8285 case MPI_IOCSTATUS_TARGET_PRIORITY_IO: /* 0x0060 */ 8286 desc = "Target: Priority IO"; 8287 break; 8288 8289 case MPI_IOCSTATUS_TARGET_INVALID_PORT: /* 0x0061 */ 8290 desc = "Target: Invalid Port"; 8291 break; 8292 8293 case MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX: /* 0x0062 */ 8294 desc = "Target Invalid IO Index:"; 8295 break; 8296 8297 case MPI_IOCSTATUS_TARGET_ABORTED: /* 0x0063 */ 8298 desc = "Target: Aborted"; 8299 break; 8300 8301 case MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: /* 0x0064 */ 8302 desc = "Target: No Conn Retryable"; 8303 break; 8304 8305 case MPI_IOCSTATUS_TARGET_NO_CONNECTION: /* 0x0065 */ 8306 desc = "Target: No Connection"; 8307 break; 8308 8309 case MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: /* 0x006A */ 8310 desc = "Target: Transfer Count Mismatch"; 8311 break; 8312 8313 case MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT: /* 0x006B */ 8314 desc = "Target: STS Data not Sent"; 8315 break; 8316 8317 case MPI_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: /* 0x006D */ 8318 desc = "Target: Data Offset Error"; 8319 break; 8320 8321 case MPI_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: /* 0x006E */ 8322 desc = "Target: Too Much Write Data"; 8323 break; 8324 8325 case MPI_IOCSTATUS_TARGET_IU_TOO_SHORT: /* 0x006F */ 8326 desc = "Target: IU Too Short"; 8327 break; 8328 8329 case MPI_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: /* 0x0070 */ 8330 desc = "Target: ACK NAK Timeout"; 8331 break; 8332 8333 case MPI_IOCSTATUS_TARGET_NAK_RECEIVED: /* 0x0071 */ 8334 desc = "Target: Nak Received"; 8335 break; 8336 8337 /****************************************************************************/ 8338 /* Fibre Channel Direct Access values */ 8339 /****************************************************************************/ 8340 8341 case MPI_IOCSTATUS_FC_ABORTED: /* 0x0066 */ 8342 desc = "FC: Aborted"; 8343 break; 8344 8345 case MPI_IOCSTATUS_FC_RX_ID_INVALID: /* 0x0067 */ 8346 desc = "FC: RX ID Invalid"; 8347 break; 8348 8349 case MPI_IOCSTATUS_FC_DID_INVALID: /* 0x0068 */ 8350 desc = "FC: DID Invalid"; 8351 break; 8352 8353 case MPI_IOCSTATUS_FC_NODE_LOGGED_OUT: /* 0x0069 */ 8354 desc = "FC: Node Logged Out"; 8355 break; 8356 8357 case MPI_IOCSTATUS_FC_EXCHANGE_CANCELED: /* 0x006C */ 8358 desc = "FC: Exchange Canceled"; 8359 break; 8360 8361 /****************************************************************************/ 8362 /* LAN values */ 8363 /****************************************************************************/ 8364 8365 case MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND: /* 0x0080 */ 8366 desc = "LAN: Device not Found"; 8367 break; 8368 8369 case MPI_IOCSTATUS_LAN_DEVICE_FAILURE: /* 0x0081 */ 8370 desc = "LAN: Device Failure"; 8371 break; 8372 8373 case MPI_IOCSTATUS_LAN_TRANSMIT_ERROR: /* 0x0082 */ 8374 desc = "LAN: Transmit Error"; 8375 break; 8376 8377 case MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED: /* 0x0083 */ 8378 desc = "LAN: Transmit Aborted"; 8379 break; 8380 8381 case MPI_IOCSTATUS_LAN_RECEIVE_ERROR: /* 0x0084 */ 8382 desc = "LAN: Receive Error"; 8383 break; 8384 8385 case MPI_IOCSTATUS_LAN_RECEIVE_ABORTED: /* 0x0085 */ 8386 desc = "LAN: Receive Aborted"; 8387 break; 8388 8389 case MPI_IOCSTATUS_LAN_PARTIAL_PACKET: /* 0x0086 */ 8390 desc = "LAN: Partial Packet"; 8391 break; 8392 8393 case MPI_IOCSTATUS_LAN_CANCELED: /* 0x0087 */ 8394 desc = "LAN: Canceled"; 8395 break; 8396 8397 /****************************************************************************/ 8398 /* Serial Attached SCSI values */ 8399 /****************************************************************************/ 8400 8401 case MPI_IOCSTATUS_SAS_SMP_REQUEST_FAILED: /* 0x0090 */ 8402 desc = "SAS: SMP Request Failed"; 8403 break; 8404 8405 case MPI_IOCSTATUS_SAS_SMP_DATA_OVERRUN: /* 0x0090 */ 8406 desc = "SAS: SMP Data Overrun"; 8407 break; 8408 8409 default: 8410 desc = "Others"; 8411 break; 8412 } 8413 8414 if (!desc) 8415 return; 8416 8417 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s\n", 8418 ioc->name, status, desc)); 8419 } 8420 8421 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8422 EXPORT_SYMBOL(mpt_attach); 8423 EXPORT_SYMBOL(mpt_detach); 8424 #ifdef CONFIG_PM 8425 EXPORT_SYMBOL(mpt_resume); 8426 EXPORT_SYMBOL(mpt_suspend); 8427 #endif 8428 EXPORT_SYMBOL(ioc_list); 8429 EXPORT_SYMBOL(mpt_register); 8430 EXPORT_SYMBOL(mpt_deregister); 8431 EXPORT_SYMBOL(mpt_event_register); 8432 EXPORT_SYMBOL(mpt_event_deregister); 8433 EXPORT_SYMBOL(mpt_reset_register); 8434 EXPORT_SYMBOL(mpt_reset_deregister); 8435 EXPORT_SYMBOL(mpt_device_driver_register); 8436 EXPORT_SYMBOL(mpt_device_driver_deregister); 8437 EXPORT_SYMBOL(mpt_get_msg_frame); 8438 EXPORT_SYMBOL(mpt_put_msg_frame); 8439 EXPORT_SYMBOL(mpt_put_msg_frame_hi_pri); 8440 EXPORT_SYMBOL(mpt_free_msg_frame); 8441 EXPORT_SYMBOL(mpt_send_handshake_request); 8442 EXPORT_SYMBOL(mpt_verify_adapter); 8443 EXPORT_SYMBOL(mpt_GetIocState); 8444 EXPORT_SYMBOL(mpt_print_ioc_summary); 8445 EXPORT_SYMBOL(mpt_HardResetHandler); 8446 EXPORT_SYMBOL(mpt_config); 8447 EXPORT_SYMBOL(mpt_findImVolumes); 8448 EXPORT_SYMBOL(mpt_alloc_fw_memory); 8449 EXPORT_SYMBOL(mpt_free_fw_memory); 8450 EXPORT_SYMBOL(mptbase_sas_persist_operation); 8451 EXPORT_SYMBOL(mpt_raid_phys_disk_pg0); 8452 8453 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8454 /** 8455 * fusion_init - Fusion MPT base driver initialization routine. 8456 * 8457 * Returns 0 for success, non-zero for failure. 8458 */ 8459 static int __init 8460 fusion_init(void) 8461 { 8462 u8 cb_idx; 8463 8464 show_mptmod_ver(my_NAME, my_VERSION); 8465 printk(KERN_INFO COPYRIGHT "\n"); 8466 8467 for (cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) { 8468 MptCallbacks[cb_idx] = NULL; 8469 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER; 8470 MptEvHandlers[cb_idx] = NULL; 8471 MptResetHandlers[cb_idx] = NULL; 8472 } 8473 8474 /* Register ourselves (mptbase) in order to facilitate 8475 * EventNotification handling. 8476 */ 8477 mpt_base_index = mpt_register(mptbase_reply, MPTBASE_DRIVER, 8478 "mptbase_reply"); 8479 8480 /* Register for hard reset handling callbacks. 8481 */ 8482 mpt_reset_register(mpt_base_index, mpt_ioc_reset); 8483 8484 #ifdef CONFIG_PROC_FS 8485 (void) procmpt_create(); 8486 #endif 8487 return 0; 8488 } 8489 8490 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 8491 /** 8492 * fusion_exit - Perform driver unload cleanup. 8493 * 8494 * This routine frees all resources associated with each MPT adapter 8495 * and removes all %MPT_PROCFS_MPTBASEDIR entries. 8496 */ 8497 static void __exit 8498 fusion_exit(void) 8499 { 8500 8501 mpt_reset_deregister(mpt_base_index); 8502 8503 #ifdef CONFIG_PROC_FS 8504 procmpt_destroy(); 8505 #endif 8506 } 8507 8508 module_init(fusion_init); 8509 module_exit(fusion_exit); 8510