1 /* 2 * Copyright (C) 2010 - Maxim Levitsky 3 * driver for Ricoh memstick readers 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #ifndef R592_H 11 12 #include <linux/memstick.h> 13 #include <linux/spinlock.h> 14 #include <linux/interrupt.h> 15 #include <linux/workqueue.h> 16 #include <linux/kfifo.h> 17 #include <linux/ctype.h> 18 19 /* write to this reg (number,len) triggers TPC execution */ 20 #define R592_TPC_EXEC 0x00 21 #define R592_TPC_EXEC_LEN_SHIFT 16 /* Bits 16..25 are TPC len */ 22 #define R592_TPC_EXEC_BIG_FIFO (1 << 26) /* If bit 26 is set, large fifo is used (reg 48) */ 23 #define R592_TPC_EXEC_TPC_SHIFT 28 /* Bits 28..31 are the TPC number */ 24 25 26 /* Window for small TPC fifo (big endian)*/ 27 /* reads and writes always are done in 8 byte chunks */ 28 /* Not used in driver, because large fifo does better job */ 29 #define R592_SFIFO 0x08 30 31 32 /* Status register (ms int, small fifo, IO)*/ 33 #define R592_STATUS 0x10 34 /* Parallel INT bits */ 35 #define R592_STATUS_P_CMDNACK (1 << 16) /* INT reg: NACK (parallel mode) */ 36 #define R592_STATUS_P_BREQ (1 << 17) /* INT reg: card ready (parallel mode)*/ 37 #define R592_STATUS_P_INTERR (1 << 18) /* INT reg: int error (parallel mode)*/ 38 #define R592_STATUS_P_CED (1 << 19) /* INT reg: command done (parallel mode) */ 39 40 /* Fifo status */ 41 #define R592_STATUS_SFIFO_FULL (1 << 20) /* Small Fifo almost full (last chunk is written) */ 42 #define R592_STATUS_SFIFO_EMPTY (1 << 21) /* Small Fifo empty */ 43 44 /* Error detection via CRC */ 45 #define R592_STATUS_SEND_ERR (1 << 24) /* Send failed */ 46 #define R592_STATUS_RECV_ERR (1 << 25) /* Receive failed */ 47 48 /* Card state */ 49 #define R592_STATUS_RDY (1 << 28) /* RDY signal received */ 50 #define R592_STATUS_CED (1 << 29) /* INT: Command done (serial mode)*/ 51 #define R592_STATUS_SFIFO_INPUT (1 << 30) /* Small fifo received data*/ 52 53 #define R592_SFIFO_SIZE 32 /* total size of small fifo is 32 bytes */ 54 #define R592_SFIFO_PACKET 8 /* packet size of small fifo */ 55 56 /* IO control */ 57 #define R592_IO 0x18 58 #define R592_IO_16 (1 << 16) /* Set by default, can be cleared */ 59 #define R592_IO_18 (1 << 18) /* Set by default, can be cleared */ 60 #define R592_IO_SERIAL1 (1 << 20) /* Set by default, can be cleared, (cleared on parallel) */ 61 #define R592_IO_22 (1 << 22) /* Set by default, can be cleared */ 62 #define R592_IO_DIRECTION (1 << 24) /* TPC direction (1 write 0 read) */ 63 #define R592_IO_26 (1 << 26) /* Set by default, can be cleared */ 64 #define R592_IO_SERIAL2 (1 << 30) /* Set by default, can be cleared (cleared on parallel), serial doesn't work if unset */ 65 #define R592_IO_RESET (1 << 31) /* Reset, sets defaults*/ 66 67 68 /* Turns hardware on/off */ 69 #define R592_POWER 0x20 /* bits 0-7 writeable */ 70 #define R592_POWER_0 (1 << 0) /* set on start, cleared on stop - must be set*/ 71 #define R592_POWER_1 (1 << 1) /* set on start, cleared on stop - must be set*/ 72 #define R592_POWER_3 (1 << 3) /* must be clear */ 73 #define R592_POWER_20 (1 << 5) /* set before switch to parallel */ 74 75 /* IO mode*/ 76 #define R592_IO_MODE 0x24 77 #define R592_IO_MODE_SERIAL 1 78 #define R592_IO_MODE_PARALLEL 3 79 80 81 /* IRQ,card detection,large fifo (first word irq status, second enable) */ 82 /* IRQs are ACKed by clearing the bits */ 83 #define R592_REG_MSC 0x28 84 #define R592_REG_MSC_PRSNT (1 << 1) /* card present (only status)*/ 85 #define R592_REG_MSC_IRQ_INSERT (1 << 8) /* detect insert / card insered */ 86 #define R592_REG_MSC_IRQ_REMOVE (1 << 9) /* detect removal / card removed */ 87 #define R592_REG_MSC_FIFO_EMPTY (1 << 10) /* fifo is empty */ 88 #define R592_REG_MSC_FIFO_DMA_DONE (1 << 11) /* dma enable / dma done */ 89 90 #define R592_REG_MSC_FIFO_USER_ORN (1 << 12) /* set if software reads empty fifo (if R592_REG_MSC_FIFO_EMPTY is set) */ 91 #define R592_REG_MSC_FIFO_MISMATH (1 << 13) /* set if amount of data in fifo doesn't match amount in TPC */ 92 #define R592_REG_MSC_FIFO_DMA_ERR (1 << 14) /* IO failure */ 93 #define R592_REG_MSC_LED (1 << 15) /* clear to turn led off (only status)*/ 94 95 #define DMA_IRQ_ACK_MASK \ 96 (R592_REG_MSC_FIFO_DMA_DONE | R592_REG_MSC_FIFO_DMA_ERR) 97 98 #define DMA_IRQ_EN_MASK (DMA_IRQ_ACK_MASK << 16) 99 100 #define IRQ_ALL_ACK_MASK 0x00007F00 101 #define IRQ_ALL_EN_MASK (IRQ_ALL_ACK_MASK << 16) 102 103 /* DMA address for large FIFO read/writes*/ 104 #define R592_FIFO_DMA 0x2C 105 106 /* PIO access to large FIFO (512 bytes) (big endian)*/ 107 #define R592_FIFO_PIO 0x30 108 #define R592_LFIFO_SIZE 512 /* large fifo size */ 109 110 111 /* large FIFO DMA settings */ 112 #define R592_FIFO_DMA_SETTINGS 0x34 113 #define R592_FIFO_DMA_SETTINGS_EN (1 << 0) /* DMA enabled */ 114 #define R592_FIFO_DMA_SETTINGS_DIR (1 << 1) /* Dma direction (1 read, 0 write) */ 115 #define R592_FIFO_DMA_SETTINGS_CAP (1 << 24) /* Dma is aviable */ 116 117 /* Maybe just an delay */ 118 /* Bits 17..19 are just number */ 119 /* bit 16 is set, then bit 20 is waited */ 120 /* time to wait is about 50 spins * 2 ^ (bits 17..19) */ 121 /* seems to be possible just to ignore */ 122 /* Probably debug register */ 123 #define R592_REG38 0x38 124 #define R592_REG38_CHANGE (1 << 16) /* Start bit */ 125 #define R592_REG38_DONE (1 << 20) /* HW set this after the delay */ 126 #define R592_REG38_SHIFT 17 127 128 /* Debug register, written (0xABCDEF00) when error happens - not used*/ 129 #define R592_REG_3C 0x3C 130 131 struct r592_device { 132 struct pci_dev *pci_dev; 133 struct memstick_host *host; /* host backpointer */ 134 struct memstick_request *req; /* current request */ 135 136 /* Registers, IRQ */ 137 void __iomem *mmio; 138 int irq; 139 spinlock_t irq_lock; 140 spinlock_t io_thread_lock; 141 struct timer_list detect_timer; 142 143 struct task_struct *io_thread; 144 bool parallel_mode; 145 146 DECLARE_KFIFO(pio_fifo, u8, sizeof(u32)); 147 148 /* DMA area */ 149 int dma_capable; 150 int dma_error; 151 struct completion dma_done; 152 void *dummy_dma_page; 153 dma_addr_t dummy_dma_page_physical_address; 154 155 }; 156 157 #define DRV_NAME "r592" 158 159 160 #define message(format, ...) \ 161 printk(KERN_INFO DRV_NAME ": " format "\n", ## __VA_ARGS__) 162 163 #define __dbg(level, format, ...) \ 164 do { \ 165 if (debug >= level) \ 166 printk(KERN_DEBUG DRV_NAME \ 167 ": " format "\n", ## __VA_ARGS__); \ 168 } while (0) 169 170 171 #define dbg(format, ...) __dbg(1, format, ## __VA_ARGS__) 172 #define dbg_verbose(format, ...) __dbg(2, format, ## __VA_ARGS__) 173 #define dbg_reg(format, ...) __dbg(3, format, ## __VA_ARGS__) 174 175 #endif 176