1 /* 2 * jmb38x_ms.c - JMicron jmb38x MemoryStick card reader 3 * 4 * Copyright (C) 2008 Alex Dubov <oakad@yahoo.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 */ 11 12 #include <linux/spinlock.h> 13 #include <linux/interrupt.h> 14 #include <linux/pci.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/memstick.h> 19 #include <linux/slab.h> 20 21 #define DRIVER_NAME "jmb38x_ms" 22 23 static int no_dma; 24 module_param(no_dma, bool, 0644); 25 26 enum { 27 DMA_ADDRESS = 0x00, 28 BLOCK = 0x04, 29 DMA_CONTROL = 0x08, 30 TPC_P0 = 0x0c, 31 TPC_P1 = 0x10, 32 TPC = 0x14, 33 HOST_CONTROL = 0x18, 34 DATA = 0x1c, 35 STATUS = 0x20, 36 INT_STATUS = 0x24, 37 INT_STATUS_ENABLE = 0x28, 38 INT_SIGNAL_ENABLE = 0x2c, 39 TIMER = 0x30, 40 TIMER_CONTROL = 0x34, 41 PAD_OUTPUT_ENABLE = 0x38, 42 PAD_PU_PD = 0x3c, 43 CLOCK_DELAY = 0x40, 44 ADMA_ADDRESS = 0x44, 45 CLOCK_CONTROL = 0x48, 46 LED_CONTROL = 0x4c, 47 VERSION = 0x50 48 }; 49 50 struct jmb38x_ms_host { 51 struct jmb38x_ms *chip; 52 void __iomem *addr; 53 spinlock_t lock; 54 struct tasklet_struct notify; 55 int id; 56 char host_id[32]; 57 int irq; 58 unsigned int block_pos; 59 unsigned long timeout_jiffies; 60 struct timer_list timer; 61 struct memstick_request *req; 62 unsigned char cmd_flags; 63 unsigned char io_pos; 64 unsigned int io_word[2]; 65 }; 66 67 struct jmb38x_ms { 68 struct pci_dev *pdev; 69 int host_cnt; 70 struct memstick_host *hosts[]; 71 }; 72 73 #define BLOCK_COUNT_MASK 0xffff0000 74 #define BLOCK_SIZE_MASK 0x00000fff 75 76 #define DMA_CONTROL_ENABLE 0x00000001 77 78 #define TPC_DATA_SEL 0x00008000 79 #define TPC_DIR 0x00004000 80 #define TPC_WAIT_INT 0x00002000 81 #define TPC_GET_INT 0x00000800 82 #define TPC_CODE_SZ_MASK 0x00000700 83 #define TPC_DATA_SZ_MASK 0x00000007 84 85 #define HOST_CONTROL_TDELAY_EN 0x00040000 86 #define HOST_CONTROL_HW_OC_P 0x00010000 87 #define HOST_CONTROL_RESET_REQ 0x00008000 88 #define HOST_CONTROL_REI 0x00004000 89 #define HOST_CONTROL_LED 0x00000400 90 #define HOST_CONTROL_FAST_CLK 0x00000200 91 #define HOST_CONTROL_RESET 0x00000100 92 #define HOST_CONTROL_POWER_EN 0x00000080 93 #define HOST_CONTROL_CLOCK_EN 0x00000040 94 #define HOST_CONTROL_REO 0x00000008 95 #define HOST_CONTROL_IF_SHIFT 4 96 97 #define HOST_CONTROL_IF_SERIAL 0x0 98 #define HOST_CONTROL_IF_PAR4 0x1 99 #define HOST_CONTROL_IF_PAR8 0x3 100 101 #define STATUS_BUSY 0x00080000 102 #define STATUS_MS_DAT7 0x00040000 103 #define STATUS_MS_DAT6 0x00020000 104 #define STATUS_MS_DAT5 0x00010000 105 #define STATUS_MS_DAT4 0x00008000 106 #define STATUS_MS_DAT3 0x00004000 107 #define STATUS_MS_DAT2 0x00002000 108 #define STATUS_MS_DAT1 0x00001000 109 #define STATUS_MS_DAT0 0x00000800 110 #define STATUS_HAS_MEDIA 0x00000400 111 #define STATUS_FIFO_EMPTY 0x00000200 112 #define STATUS_FIFO_FULL 0x00000100 113 #define STATUS_MS_CED 0x00000080 114 #define STATUS_MS_ERR 0x00000040 115 #define STATUS_MS_BRQ 0x00000020 116 #define STATUS_MS_CNK 0x00000001 117 118 #define INT_STATUS_TPC_ERR 0x00080000 119 #define INT_STATUS_CRC_ERR 0x00040000 120 #define INT_STATUS_TIMER_TO 0x00020000 121 #define INT_STATUS_HSK_TO 0x00010000 122 #define INT_STATUS_ANY_ERR 0x00008000 123 #define INT_STATUS_FIFO_WRDY 0x00000080 124 #define INT_STATUS_FIFO_RRDY 0x00000040 125 #define INT_STATUS_MEDIA_OUT 0x00000010 126 #define INT_STATUS_MEDIA_IN 0x00000008 127 #define INT_STATUS_DMA_BOUNDARY 0x00000004 128 #define INT_STATUS_EOTRAN 0x00000002 129 #define INT_STATUS_EOTPC 0x00000001 130 131 #define INT_STATUS_ALL 0x000f801f 132 133 #define PAD_OUTPUT_ENABLE_MS 0x0F3F 134 135 #define PAD_PU_PD_OFF 0x7FFF0000 136 #define PAD_PU_PD_ON_MS_SOCK0 0x5f8f0000 137 #define PAD_PU_PD_ON_MS_SOCK1 0x0f0f0000 138 139 #define CLOCK_CONTROL_40MHZ 0x00000001 140 #define CLOCK_CONTROL_50MHZ 0x0000000a 141 #define CLOCK_CONTROL_60MHZ 0x00000008 142 #define CLOCK_CONTROL_62_5MHZ 0x0000000c 143 #define CLOCK_CONTROL_OFF 0x00000000 144 145 #define PCI_CTL_CLOCK_DLY_ADDR 0x000000b0 146 #define PCI_CTL_CLOCK_DLY_MASK_A 0x00000f00 147 #define PCI_CTL_CLOCK_DLY_MASK_B 0x0000f000 148 149 enum { 150 CMD_READY = 0x01, 151 FIFO_READY = 0x02, 152 REG_DATA = 0x04, 153 DMA_DATA = 0x08 154 }; 155 156 static unsigned int jmb38x_ms_read_data(struct jmb38x_ms_host *host, 157 unsigned char *buf, unsigned int length) 158 { 159 unsigned int off = 0; 160 161 while (host->io_pos && length) { 162 buf[off++] = host->io_word[0] & 0xff; 163 host->io_word[0] >>= 8; 164 length--; 165 host->io_pos--; 166 } 167 168 if (!length) 169 return off; 170 171 while (!(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) { 172 if (length < 4) 173 break; 174 *(unsigned int *)(buf + off) = __raw_readl(host->addr + DATA); 175 length -= 4; 176 off += 4; 177 } 178 179 if (length 180 && !(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) { 181 host->io_word[0] = readl(host->addr + DATA); 182 for (host->io_pos = 4; host->io_pos; --host->io_pos) { 183 buf[off++] = host->io_word[0] & 0xff; 184 host->io_word[0] >>= 8; 185 length--; 186 if (!length) 187 break; 188 } 189 } 190 191 return off; 192 } 193 194 static unsigned int jmb38x_ms_read_reg_data(struct jmb38x_ms_host *host, 195 unsigned char *buf, 196 unsigned int length) 197 { 198 unsigned int off = 0; 199 200 while (host->io_pos > 4 && length) { 201 buf[off++] = host->io_word[0] & 0xff; 202 host->io_word[0] >>= 8; 203 length--; 204 host->io_pos--; 205 } 206 207 if (!length) 208 return off; 209 210 while (host->io_pos && length) { 211 buf[off++] = host->io_word[1] & 0xff; 212 host->io_word[1] >>= 8; 213 length--; 214 host->io_pos--; 215 } 216 217 return off; 218 } 219 220 static unsigned int jmb38x_ms_write_data(struct jmb38x_ms_host *host, 221 unsigned char *buf, 222 unsigned int length) 223 { 224 unsigned int off = 0; 225 226 if (host->io_pos) { 227 while (host->io_pos < 4 && length) { 228 host->io_word[0] |= buf[off++] << (host->io_pos * 8); 229 host->io_pos++; 230 length--; 231 } 232 } 233 234 if (host->io_pos == 4 235 && !(STATUS_FIFO_FULL & readl(host->addr + STATUS))) { 236 writel(host->io_word[0], host->addr + DATA); 237 host->io_pos = 0; 238 host->io_word[0] = 0; 239 } else if (host->io_pos) { 240 return off; 241 } 242 243 if (!length) 244 return off; 245 246 while (!(STATUS_FIFO_FULL & readl(host->addr + STATUS))) { 247 if (length < 4) 248 break; 249 250 __raw_writel(*(unsigned int *)(buf + off), 251 host->addr + DATA); 252 length -= 4; 253 off += 4; 254 } 255 256 switch (length) { 257 case 3: 258 host->io_word[0] |= buf[off + 2] << 16; 259 host->io_pos++; 260 case 2: 261 host->io_word[0] |= buf[off + 1] << 8; 262 host->io_pos++; 263 case 1: 264 host->io_word[0] |= buf[off]; 265 host->io_pos++; 266 } 267 268 off += host->io_pos; 269 270 return off; 271 } 272 273 static unsigned int jmb38x_ms_write_reg_data(struct jmb38x_ms_host *host, 274 unsigned char *buf, 275 unsigned int length) 276 { 277 unsigned int off = 0; 278 279 while (host->io_pos < 4 && length) { 280 host->io_word[0] &= ~(0xff << (host->io_pos * 8)); 281 host->io_word[0] |= buf[off++] << (host->io_pos * 8); 282 host->io_pos++; 283 length--; 284 } 285 286 if (!length) 287 return off; 288 289 while (host->io_pos < 8 && length) { 290 host->io_word[1] &= ~(0xff << (host->io_pos * 8)); 291 host->io_word[1] |= buf[off++] << (host->io_pos * 8); 292 host->io_pos++; 293 length--; 294 } 295 296 return off; 297 } 298 299 static int jmb38x_ms_transfer_data(struct jmb38x_ms_host *host) 300 { 301 unsigned int length; 302 unsigned int off; 303 unsigned int t_size, p_cnt; 304 unsigned char *buf; 305 struct page *pg; 306 unsigned long flags = 0; 307 308 if (host->req->long_data) { 309 length = host->req->sg.length - host->block_pos; 310 off = host->req->sg.offset + host->block_pos; 311 } else { 312 length = host->req->data_len - host->block_pos; 313 off = 0; 314 } 315 316 while (length) { 317 unsigned int uninitialized_var(p_off); 318 319 if (host->req->long_data) { 320 pg = nth_page(sg_page(&host->req->sg), 321 off >> PAGE_SHIFT); 322 p_off = offset_in_page(off); 323 p_cnt = PAGE_SIZE - p_off; 324 p_cnt = min(p_cnt, length); 325 326 local_irq_save(flags); 327 buf = kmap_atomic(pg, KM_BIO_SRC_IRQ) + p_off; 328 } else { 329 buf = host->req->data + host->block_pos; 330 p_cnt = host->req->data_len - host->block_pos; 331 } 332 333 if (host->req->data_dir == WRITE) 334 t_size = !(host->cmd_flags & REG_DATA) 335 ? jmb38x_ms_write_data(host, buf, p_cnt) 336 : jmb38x_ms_write_reg_data(host, buf, p_cnt); 337 else 338 t_size = !(host->cmd_flags & REG_DATA) 339 ? jmb38x_ms_read_data(host, buf, p_cnt) 340 : jmb38x_ms_read_reg_data(host, buf, p_cnt); 341 342 if (host->req->long_data) { 343 kunmap_atomic(buf - p_off, KM_BIO_SRC_IRQ); 344 local_irq_restore(flags); 345 } 346 347 if (!t_size) 348 break; 349 host->block_pos += t_size; 350 length -= t_size; 351 off += t_size; 352 } 353 354 if (!length && host->req->data_dir == WRITE) { 355 if (host->cmd_flags & REG_DATA) { 356 writel(host->io_word[0], host->addr + TPC_P0); 357 writel(host->io_word[1], host->addr + TPC_P1); 358 } else if (host->io_pos) { 359 writel(host->io_word[0], host->addr + DATA); 360 } 361 } 362 363 return length; 364 } 365 366 static int jmb38x_ms_issue_cmd(struct memstick_host *msh) 367 { 368 struct jmb38x_ms_host *host = memstick_priv(msh); 369 unsigned char *data; 370 unsigned int data_len, cmd, t_val; 371 372 if (!(STATUS_HAS_MEDIA & readl(host->addr + STATUS))) { 373 dev_dbg(&msh->dev, "no media status\n"); 374 host->req->error = -ETIME; 375 return host->req->error; 376 } 377 378 dev_dbg(&msh->dev, "control %08x\n", readl(host->addr + HOST_CONTROL)); 379 dev_dbg(&msh->dev, "status %08x\n", readl(host->addr + INT_STATUS)); 380 dev_dbg(&msh->dev, "hstatus %08x\n", readl(host->addr + STATUS)); 381 382 host->cmd_flags = 0; 383 host->block_pos = 0; 384 host->io_pos = 0; 385 host->io_word[0] = 0; 386 host->io_word[1] = 0; 387 388 cmd = host->req->tpc << 16; 389 cmd |= TPC_DATA_SEL; 390 391 if (host->req->data_dir == READ) 392 cmd |= TPC_DIR; 393 if (host->req->need_card_int) 394 cmd |= TPC_WAIT_INT; 395 396 data = host->req->data; 397 398 if (!no_dma) 399 host->cmd_flags |= DMA_DATA; 400 401 if (host->req->long_data) { 402 data_len = host->req->sg.length; 403 } else { 404 data_len = host->req->data_len; 405 host->cmd_flags &= ~DMA_DATA; 406 } 407 408 if (data_len <= 8) { 409 cmd &= ~(TPC_DATA_SEL | 0xf); 410 host->cmd_flags |= REG_DATA; 411 cmd |= data_len & 0xf; 412 host->cmd_flags &= ~DMA_DATA; 413 } 414 415 if (host->cmd_flags & DMA_DATA) { 416 if (1 != pci_map_sg(host->chip->pdev, &host->req->sg, 1, 417 host->req->data_dir == READ 418 ? PCI_DMA_FROMDEVICE 419 : PCI_DMA_TODEVICE)) { 420 host->req->error = -ENOMEM; 421 return host->req->error; 422 } 423 data_len = sg_dma_len(&host->req->sg); 424 writel(sg_dma_address(&host->req->sg), 425 host->addr + DMA_ADDRESS); 426 writel(((1 << 16) & BLOCK_COUNT_MASK) 427 | (data_len & BLOCK_SIZE_MASK), 428 host->addr + BLOCK); 429 writel(DMA_CONTROL_ENABLE, host->addr + DMA_CONTROL); 430 } else if (!(host->cmd_flags & REG_DATA)) { 431 writel(((1 << 16) & BLOCK_COUNT_MASK) 432 | (data_len & BLOCK_SIZE_MASK), 433 host->addr + BLOCK); 434 t_val = readl(host->addr + INT_STATUS_ENABLE); 435 t_val |= host->req->data_dir == READ 436 ? INT_STATUS_FIFO_RRDY 437 : INT_STATUS_FIFO_WRDY; 438 439 writel(t_val, host->addr + INT_STATUS_ENABLE); 440 writel(t_val, host->addr + INT_SIGNAL_ENABLE); 441 } else { 442 cmd &= ~(TPC_DATA_SEL | 0xf); 443 host->cmd_flags |= REG_DATA; 444 cmd |= data_len & 0xf; 445 446 if (host->req->data_dir == WRITE) { 447 jmb38x_ms_transfer_data(host); 448 writel(host->io_word[0], host->addr + TPC_P0); 449 writel(host->io_word[1], host->addr + TPC_P1); 450 } 451 } 452 453 mod_timer(&host->timer, jiffies + host->timeout_jiffies); 454 writel(HOST_CONTROL_LED | readl(host->addr + HOST_CONTROL), 455 host->addr + HOST_CONTROL); 456 host->req->error = 0; 457 458 writel(cmd, host->addr + TPC); 459 dev_dbg(&msh->dev, "executing TPC %08x, len %x\n", cmd, data_len); 460 461 return 0; 462 } 463 464 static void jmb38x_ms_complete_cmd(struct memstick_host *msh, int last) 465 { 466 struct jmb38x_ms_host *host = memstick_priv(msh); 467 unsigned int t_val = 0; 468 int rc; 469 470 del_timer(&host->timer); 471 472 dev_dbg(&msh->dev, "c control %08x\n", 473 readl(host->addr + HOST_CONTROL)); 474 dev_dbg(&msh->dev, "c status %08x\n", 475 readl(host->addr + INT_STATUS)); 476 dev_dbg(&msh->dev, "c hstatus %08x\n", readl(host->addr + STATUS)); 477 478 host->req->int_reg = readl(host->addr + STATUS) & 0xff; 479 480 writel(0, host->addr + BLOCK); 481 writel(0, host->addr + DMA_CONTROL); 482 483 if (host->cmd_flags & DMA_DATA) { 484 pci_unmap_sg(host->chip->pdev, &host->req->sg, 1, 485 host->req->data_dir == READ 486 ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE); 487 } else { 488 t_val = readl(host->addr + INT_STATUS_ENABLE); 489 if (host->req->data_dir == READ) 490 t_val &= ~INT_STATUS_FIFO_RRDY; 491 else 492 t_val &= ~INT_STATUS_FIFO_WRDY; 493 494 writel(t_val, host->addr + INT_STATUS_ENABLE); 495 writel(t_val, host->addr + INT_SIGNAL_ENABLE); 496 } 497 498 writel((~HOST_CONTROL_LED) & readl(host->addr + HOST_CONTROL), 499 host->addr + HOST_CONTROL); 500 501 if (!last) { 502 do { 503 rc = memstick_next_req(msh, &host->req); 504 } while (!rc && jmb38x_ms_issue_cmd(msh)); 505 } else { 506 do { 507 rc = memstick_next_req(msh, &host->req); 508 if (!rc) 509 host->req->error = -ETIME; 510 } while (!rc); 511 } 512 } 513 514 static irqreturn_t jmb38x_ms_isr(int irq, void *dev_id) 515 { 516 struct memstick_host *msh = dev_id; 517 struct jmb38x_ms_host *host = memstick_priv(msh); 518 unsigned int irq_status; 519 520 spin_lock(&host->lock); 521 irq_status = readl(host->addr + INT_STATUS); 522 dev_dbg(&host->chip->pdev->dev, "irq_status = %08x\n", irq_status); 523 if (irq_status == 0 || irq_status == (~0)) { 524 spin_unlock(&host->lock); 525 return IRQ_NONE; 526 } 527 528 if (host->req) { 529 if (irq_status & INT_STATUS_ANY_ERR) { 530 if (irq_status & INT_STATUS_CRC_ERR) 531 host->req->error = -EILSEQ; 532 else 533 host->req->error = -ETIME; 534 } else { 535 if (host->cmd_flags & DMA_DATA) { 536 if (irq_status & INT_STATUS_EOTRAN) 537 host->cmd_flags |= FIFO_READY; 538 } else { 539 if (irq_status & (INT_STATUS_FIFO_RRDY 540 | INT_STATUS_FIFO_WRDY)) 541 jmb38x_ms_transfer_data(host); 542 543 if (irq_status & INT_STATUS_EOTRAN) { 544 jmb38x_ms_transfer_data(host); 545 host->cmd_flags |= FIFO_READY; 546 } 547 } 548 549 if (irq_status & INT_STATUS_EOTPC) { 550 host->cmd_flags |= CMD_READY; 551 if (host->cmd_flags & REG_DATA) { 552 if (host->req->data_dir == READ) { 553 host->io_word[0] 554 = readl(host->addr 555 + TPC_P0); 556 host->io_word[1] 557 = readl(host->addr 558 + TPC_P1); 559 host->io_pos = 8; 560 561 jmb38x_ms_transfer_data(host); 562 } 563 host->cmd_flags |= FIFO_READY; 564 } 565 } 566 } 567 } 568 569 if (irq_status & (INT_STATUS_MEDIA_IN | INT_STATUS_MEDIA_OUT)) { 570 dev_dbg(&host->chip->pdev->dev, "media changed\n"); 571 memstick_detect_change(msh); 572 } 573 574 writel(irq_status, host->addr + INT_STATUS); 575 576 if (host->req 577 && (((host->cmd_flags & CMD_READY) 578 && (host->cmd_flags & FIFO_READY)) 579 || host->req->error)) 580 jmb38x_ms_complete_cmd(msh, 0); 581 582 spin_unlock(&host->lock); 583 return IRQ_HANDLED; 584 } 585 586 static void jmb38x_ms_abort(unsigned long data) 587 { 588 struct memstick_host *msh = (struct memstick_host *)data; 589 struct jmb38x_ms_host *host = memstick_priv(msh); 590 unsigned long flags; 591 592 dev_dbg(&host->chip->pdev->dev, "abort\n"); 593 spin_lock_irqsave(&host->lock, flags); 594 if (host->req) { 595 host->req->error = -ETIME; 596 jmb38x_ms_complete_cmd(msh, 0); 597 } 598 spin_unlock_irqrestore(&host->lock, flags); 599 } 600 601 static void jmb38x_ms_req_tasklet(unsigned long data) 602 { 603 struct memstick_host *msh = (struct memstick_host *)data; 604 struct jmb38x_ms_host *host = memstick_priv(msh); 605 unsigned long flags; 606 int rc; 607 608 spin_lock_irqsave(&host->lock, flags); 609 if (!host->req) { 610 do { 611 rc = memstick_next_req(msh, &host->req); 612 dev_dbg(&host->chip->pdev->dev, "tasklet req %d\n", rc); 613 } while (!rc && jmb38x_ms_issue_cmd(msh)); 614 } 615 spin_unlock_irqrestore(&host->lock, flags); 616 } 617 618 static void jmb38x_ms_dummy_submit(struct memstick_host *msh) 619 { 620 return; 621 } 622 623 static void jmb38x_ms_submit_req(struct memstick_host *msh) 624 { 625 struct jmb38x_ms_host *host = memstick_priv(msh); 626 627 tasklet_schedule(&host->notify); 628 } 629 630 static int jmb38x_ms_reset(struct jmb38x_ms_host *host) 631 { 632 int cnt; 633 634 writel(HOST_CONTROL_RESET_REQ | HOST_CONTROL_CLOCK_EN 635 | readl(host->addr + HOST_CONTROL), 636 host->addr + HOST_CONTROL); 637 mmiowb(); 638 639 for (cnt = 0; cnt < 20; ++cnt) { 640 if (!(HOST_CONTROL_RESET_REQ 641 & readl(host->addr + HOST_CONTROL))) 642 goto reset_next; 643 644 ndelay(20); 645 } 646 dev_dbg(&host->chip->pdev->dev, "reset_req timeout\n"); 647 /* return -EIO; */ 648 649 reset_next: 650 writel(HOST_CONTROL_RESET | HOST_CONTROL_CLOCK_EN 651 | readl(host->addr + HOST_CONTROL), 652 host->addr + HOST_CONTROL); 653 mmiowb(); 654 655 for (cnt = 0; cnt < 20; ++cnt) { 656 if (!(HOST_CONTROL_RESET 657 & readl(host->addr + HOST_CONTROL))) 658 goto reset_ok; 659 660 ndelay(20); 661 } 662 dev_dbg(&host->chip->pdev->dev, "reset timeout\n"); 663 return -EIO; 664 665 reset_ok: 666 mmiowb(); 667 writel(INT_STATUS_ALL, host->addr + INT_SIGNAL_ENABLE); 668 writel(INT_STATUS_ALL, host->addr + INT_STATUS_ENABLE); 669 return 0; 670 } 671 672 static int jmb38x_ms_set_param(struct memstick_host *msh, 673 enum memstick_param param, 674 int value) 675 { 676 struct jmb38x_ms_host *host = memstick_priv(msh); 677 unsigned int host_ctl = readl(host->addr + HOST_CONTROL); 678 unsigned int clock_ctl = CLOCK_CONTROL_40MHZ, clock_delay = 0; 679 int rc = 0; 680 681 switch (param) { 682 case MEMSTICK_POWER: 683 if (value == MEMSTICK_POWER_ON) { 684 rc = jmb38x_ms_reset(host); 685 if (rc) 686 return rc; 687 688 host_ctl = 7; 689 host_ctl |= HOST_CONTROL_POWER_EN 690 | HOST_CONTROL_CLOCK_EN 691 | HOST_CONTROL_HW_OC_P 692 | HOST_CONTROL_TDELAY_EN; 693 writel(host_ctl, host->addr + HOST_CONTROL); 694 695 writel(host->id ? PAD_PU_PD_ON_MS_SOCK1 696 : PAD_PU_PD_ON_MS_SOCK0, 697 host->addr + PAD_PU_PD); 698 699 writel(PAD_OUTPUT_ENABLE_MS, 700 host->addr + PAD_OUTPUT_ENABLE); 701 702 msleep(10); 703 dev_dbg(&host->chip->pdev->dev, "power on\n"); 704 } else if (value == MEMSTICK_POWER_OFF) { 705 host_ctl &= ~(HOST_CONTROL_POWER_EN 706 | HOST_CONTROL_CLOCK_EN); 707 writel(host_ctl, host->addr + HOST_CONTROL); 708 writel(0, host->addr + PAD_OUTPUT_ENABLE); 709 writel(PAD_PU_PD_OFF, host->addr + PAD_PU_PD); 710 dev_dbg(&host->chip->pdev->dev, "power off\n"); 711 } else 712 return -EINVAL; 713 break; 714 case MEMSTICK_INTERFACE: 715 host_ctl &= ~(3 << HOST_CONTROL_IF_SHIFT); 716 pci_read_config_dword(host->chip->pdev, 717 PCI_CTL_CLOCK_DLY_ADDR, 718 &clock_delay); 719 clock_delay &= host->id ? ~PCI_CTL_CLOCK_DLY_MASK_B 720 : ~PCI_CTL_CLOCK_DLY_MASK_A; 721 722 if (value == MEMSTICK_SERIAL) { 723 host_ctl &= ~HOST_CONTROL_FAST_CLK; 724 host_ctl &= ~HOST_CONTROL_REO; 725 host_ctl |= HOST_CONTROL_IF_SERIAL 726 << HOST_CONTROL_IF_SHIFT; 727 host_ctl |= HOST_CONTROL_REI; 728 clock_ctl = CLOCK_CONTROL_40MHZ; 729 } else if (value == MEMSTICK_PAR4) { 730 host_ctl |= HOST_CONTROL_FAST_CLK | HOST_CONTROL_REO; 731 host_ctl |= HOST_CONTROL_IF_PAR4 732 << HOST_CONTROL_IF_SHIFT; 733 host_ctl &= ~HOST_CONTROL_REI; 734 clock_ctl = CLOCK_CONTROL_40MHZ; 735 clock_delay |= host->id ? (4 << 12) : (4 << 8); 736 } else if (value == MEMSTICK_PAR8) { 737 host_ctl |= HOST_CONTROL_FAST_CLK; 738 host_ctl |= HOST_CONTROL_IF_PAR8 739 << HOST_CONTROL_IF_SHIFT; 740 host_ctl &= ~(HOST_CONTROL_REI | HOST_CONTROL_REO); 741 clock_ctl = CLOCK_CONTROL_50MHZ; 742 } else 743 return -EINVAL; 744 745 writel(host_ctl, host->addr + HOST_CONTROL); 746 writel(clock_ctl, host->addr + CLOCK_CONTROL); 747 pci_write_config_dword(host->chip->pdev, 748 PCI_CTL_CLOCK_DLY_ADDR, 749 clock_delay); 750 break; 751 }; 752 return 0; 753 } 754 755 #ifdef CONFIG_PM 756 757 static int jmb38x_ms_suspend(struct pci_dev *dev, pm_message_t state) 758 { 759 struct jmb38x_ms *jm = pci_get_drvdata(dev); 760 int cnt; 761 762 for (cnt = 0; cnt < jm->host_cnt; ++cnt) { 763 if (!jm->hosts[cnt]) 764 break; 765 memstick_suspend_host(jm->hosts[cnt]); 766 } 767 768 pci_save_state(dev); 769 pci_enable_wake(dev, pci_choose_state(dev, state), 0); 770 pci_disable_device(dev); 771 pci_set_power_state(dev, pci_choose_state(dev, state)); 772 return 0; 773 } 774 775 static int jmb38x_ms_resume(struct pci_dev *dev) 776 { 777 struct jmb38x_ms *jm = pci_get_drvdata(dev); 778 int rc; 779 780 pci_set_power_state(dev, PCI_D0); 781 pci_restore_state(dev); 782 rc = pci_enable_device(dev); 783 if (rc) 784 return rc; 785 pci_set_master(dev); 786 787 pci_read_config_dword(dev, 0xac, &rc); 788 pci_write_config_dword(dev, 0xac, rc | 0x00470000); 789 790 for (rc = 0; rc < jm->host_cnt; ++rc) { 791 if (!jm->hosts[rc]) 792 break; 793 memstick_resume_host(jm->hosts[rc]); 794 memstick_detect_change(jm->hosts[rc]); 795 } 796 797 return 0; 798 } 799 800 #else 801 802 #define jmb38x_ms_suspend NULL 803 #define jmb38x_ms_resume NULL 804 805 #endif /* CONFIG_PM */ 806 807 static int jmb38x_ms_count_slots(struct pci_dev *pdev) 808 { 809 int cnt, rc = 0; 810 811 for (cnt = 0; cnt < PCI_ROM_RESOURCE; ++cnt) { 812 if (!(IORESOURCE_MEM & pci_resource_flags(pdev, cnt))) 813 break; 814 815 if (256 != pci_resource_len(pdev, cnt)) 816 break; 817 818 ++rc; 819 } 820 return rc; 821 } 822 823 static struct memstick_host *jmb38x_ms_alloc_host(struct jmb38x_ms *jm, int cnt) 824 { 825 struct memstick_host *msh; 826 struct jmb38x_ms_host *host; 827 828 msh = memstick_alloc_host(sizeof(struct jmb38x_ms_host), 829 &jm->pdev->dev); 830 if (!msh) 831 return NULL; 832 833 host = memstick_priv(msh); 834 host->chip = jm; 835 host->addr = ioremap(pci_resource_start(jm->pdev, cnt), 836 pci_resource_len(jm->pdev, cnt)); 837 if (!host->addr) 838 goto err_out_free; 839 840 spin_lock_init(&host->lock); 841 host->id = cnt; 842 snprintf(host->host_id, sizeof(host->host_id), DRIVER_NAME ":slot%d", 843 host->id); 844 host->irq = jm->pdev->irq; 845 host->timeout_jiffies = msecs_to_jiffies(1000); 846 847 tasklet_init(&host->notify, jmb38x_ms_req_tasklet, (unsigned long)msh); 848 msh->request = jmb38x_ms_submit_req; 849 msh->set_param = jmb38x_ms_set_param; 850 851 msh->caps = MEMSTICK_CAP_PAR4 | MEMSTICK_CAP_PAR8; 852 853 setup_timer(&host->timer, jmb38x_ms_abort, (unsigned long)msh); 854 855 if (!request_irq(host->irq, jmb38x_ms_isr, IRQF_SHARED, host->host_id, 856 msh)) 857 return msh; 858 859 iounmap(host->addr); 860 err_out_free: 861 kfree(msh); 862 return NULL; 863 } 864 865 static void jmb38x_ms_free_host(struct memstick_host *msh) 866 { 867 struct jmb38x_ms_host *host = memstick_priv(msh); 868 869 free_irq(host->irq, msh); 870 iounmap(host->addr); 871 memstick_free_host(msh); 872 } 873 874 static int jmb38x_ms_probe(struct pci_dev *pdev, 875 const struct pci_device_id *dev_id) 876 { 877 struct jmb38x_ms *jm; 878 int pci_dev_busy = 0; 879 int rc, cnt; 880 881 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 882 if (rc) 883 return rc; 884 885 rc = pci_enable_device(pdev); 886 if (rc) 887 return rc; 888 889 pci_set_master(pdev); 890 891 rc = pci_request_regions(pdev, DRIVER_NAME); 892 if (rc) { 893 pci_dev_busy = 1; 894 goto err_out; 895 } 896 897 pci_read_config_dword(pdev, 0xac, &rc); 898 pci_write_config_dword(pdev, 0xac, rc | 0x00470000); 899 900 cnt = jmb38x_ms_count_slots(pdev); 901 if (!cnt) { 902 rc = -ENODEV; 903 pci_dev_busy = 1; 904 goto err_out; 905 } 906 907 jm = kzalloc(sizeof(struct jmb38x_ms) 908 + cnt * sizeof(struct memstick_host *), GFP_KERNEL); 909 if (!jm) { 910 rc = -ENOMEM; 911 goto err_out_int; 912 } 913 914 jm->pdev = pdev; 915 jm->host_cnt = cnt; 916 pci_set_drvdata(pdev, jm); 917 918 for (cnt = 0; cnt < jm->host_cnt; ++cnt) { 919 jm->hosts[cnt] = jmb38x_ms_alloc_host(jm, cnt); 920 if (!jm->hosts[cnt]) 921 break; 922 923 rc = memstick_add_host(jm->hosts[cnt]); 924 925 if (rc) { 926 jmb38x_ms_free_host(jm->hosts[cnt]); 927 jm->hosts[cnt] = NULL; 928 break; 929 } 930 } 931 932 if (cnt) 933 return 0; 934 935 rc = -ENODEV; 936 937 pci_set_drvdata(pdev, NULL); 938 kfree(jm); 939 err_out_int: 940 pci_release_regions(pdev); 941 err_out: 942 if (!pci_dev_busy) 943 pci_disable_device(pdev); 944 return rc; 945 } 946 947 static void jmb38x_ms_remove(struct pci_dev *dev) 948 { 949 struct jmb38x_ms *jm = pci_get_drvdata(dev); 950 struct jmb38x_ms_host *host; 951 int cnt; 952 unsigned long flags; 953 954 for (cnt = 0; cnt < jm->host_cnt; ++cnt) { 955 if (!jm->hosts[cnt]) 956 break; 957 958 host = memstick_priv(jm->hosts[cnt]); 959 960 jm->hosts[cnt]->request = jmb38x_ms_dummy_submit; 961 tasklet_kill(&host->notify); 962 writel(0, host->addr + INT_SIGNAL_ENABLE); 963 writel(0, host->addr + INT_STATUS_ENABLE); 964 mmiowb(); 965 dev_dbg(&jm->pdev->dev, "interrupts off\n"); 966 spin_lock_irqsave(&host->lock, flags); 967 if (host->req) { 968 host->req->error = -ETIME; 969 jmb38x_ms_complete_cmd(jm->hosts[cnt], 1); 970 } 971 spin_unlock_irqrestore(&host->lock, flags); 972 973 memstick_remove_host(jm->hosts[cnt]); 974 dev_dbg(&jm->pdev->dev, "host removed\n"); 975 976 jmb38x_ms_free_host(jm->hosts[cnt]); 977 } 978 979 pci_set_drvdata(dev, NULL); 980 pci_release_regions(dev); 981 pci_disable_device(dev); 982 kfree(jm); 983 } 984 985 static struct pci_device_id jmb38x_ms_id_tbl [] = { 986 { PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_MS, PCI_ANY_ID, 987 PCI_ANY_ID, 0, 0, 0 }, 988 { } 989 }; 990 991 static struct pci_driver jmb38x_ms_driver = { 992 .name = DRIVER_NAME, 993 .id_table = jmb38x_ms_id_tbl, 994 .probe = jmb38x_ms_probe, 995 .remove = jmb38x_ms_remove, 996 .suspend = jmb38x_ms_suspend, 997 .resume = jmb38x_ms_resume 998 }; 999 1000 static int __init jmb38x_ms_init(void) 1001 { 1002 return pci_register_driver(&jmb38x_ms_driver); 1003 } 1004 1005 static void __exit jmb38x_ms_exit(void) 1006 { 1007 pci_unregister_driver(&jmb38x_ms_driver); 1008 } 1009 1010 MODULE_AUTHOR("Alex Dubov"); 1011 MODULE_DESCRIPTION("JMicron jmb38x MemoryStick driver"); 1012 MODULE_LICENSE("GPL"); 1013 MODULE_DEVICE_TABLE(pci, jmb38x_ms_id_tbl); 1014 1015 module_init(jmb38x_ms_init); 1016 module_exit(jmb38x_ms_exit); 1017