1 /* 2 * jmb38x_ms.c - JMicron jmb38x MemoryStick card reader 3 * 4 * Copyright (C) 2008 Alex Dubov <oakad@yahoo.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 */ 11 12 #include <linux/spinlock.h> 13 #include <linux/interrupt.h> 14 #include <linux/pci.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/delay.h> 17 #include <linux/highmem.h> 18 #include <linux/memstick.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 22 #define DRIVER_NAME "jmb38x_ms" 23 24 static bool no_dma; 25 module_param(no_dma, bool, 0644); 26 27 enum { 28 DMA_ADDRESS = 0x00, 29 BLOCK = 0x04, 30 DMA_CONTROL = 0x08, 31 TPC_P0 = 0x0c, 32 TPC_P1 = 0x10, 33 TPC = 0x14, 34 HOST_CONTROL = 0x18, 35 DATA = 0x1c, 36 STATUS = 0x20, 37 INT_STATUS = 0x24, 38 INT_STATUS_ENABLE = 0x28, 39 INT_SIGNAL_ENABLE = 0x2c, 40 TIMER = 0x30, 41 TIMER_CONTROL = 0x34, 42 PAD_OUTPUT_ENABLE = 0x38, 43 PAD_PU_PD = 0x3c, 44 CLOCK_DELAY = 0x40, 45 ADMA_ADDRESS = 0x44, 46 CLOCK_CONTROL = 0x48, 47 LED_CONTROL = 0x4c, 48 VERSION = 0x50 49 }; 50 51 struct jmb38x_ms_host { 52 struct jmb38x_ms *chip; 53 void __iomem *addr; 54 spinlock_t lock; 55 struct tasklet_struct notify; 56 int id; 57 char host_id[32]; 58 int irq; 59 unsigned int block_pos; 60 unsigned long timeout_jiffies; 61 struct timer_list timer; 62 struct memstick_host *msh; 63 struct memstick_request *req; 64 unsigned char cmd_flags; 65 unsigned char io_pos; 66 unsigned char ifmode; 67 unsigned int io_word[2]; 68 }; 69 70 struct jmb38x_ms { 71 struct pci_dev *pdev; 72 int host_cnt; 73 struct memstick_host *hosts[]; 74 }; 75 76 #define BLOCK_COUNT_MASK 0xffff0000 77 #define BLOCK_SIZE_MASK 0x00000fff 78 79 #define DMA_CONTROL_ENABLE 0x00000001 80 81 #define TPC_DATA_SEL 0x00008000 82 #define TPC_DIR 0x00004000 83 #define TPC_WAIT_INT 0x00002000 84 #define TPC_GET_INT 0x00000800 85 #define TPC_CODE_SZ_MASK 0x00000700 86 #define TPC_DATA_SZ_MASK 0x00000007 87 88 #define HOST_CONTROL_TDELAY_EN 0x00040000 89 #define HOST_CONTROL_HW_OC_P 0x00010000 90 #define HOST_CONTROL_RESET_REQ 0x00008000 91 #define HOST_CONTROL_REI 0x00004000 92 #define HOST_CONTROL_LED 0x00000400 93 #define HOST_CONTROL_FAST_CLK 0x00000200 94 #define HOST_CONTROL_RESET 0x00000100 95 #define HOST_CONTROL_POWER_EN 0x00000080 96 #define HOST_CONTROL_CLOCK_EN 0x00000040 97 #define HOST_CONTROL_REO 0x00000008 98 #define HOST_CONTROL_IF_SHIFT 4 99 100 #define HOST_CONTROL_IF_SERIAL 0x0 101 #define HOST_CONTROL_IF_PAR4 0x1 102 #define HOST_CONTROL_IF_PAR8 0x3 103 104 #define STATUS_BUSY 0x00080000 105 #define STATUS_MS_DAT7 0x00040000 106 #define STATUS_MS_DAT6 0x00020000 107 #define STATUS_MS_DAT5 0x00010000 108 #define STATUS_MS_DAT4 0x00008000 109 #define STATUS_MS_DAT3 0x00004000 110 #define STATUS_MS_DAT2 0x00002000 111 #define STATUS_MS_DAT1 0x00001000 112 #define STATUS_MS_DAT0 0x00000800 113 #define STATUS_HAS_MEDIA 0x00000400 114 #define STATUS_FIFO_EMPTY 0x00000200 115 #define STATUS_FIFO_FULL 0x00000100 116 #define STATUS_MS_CED 0x00000080 117 #define STATUS_MS_ERR 0x00000040 118 #define STATUS_MS_BRQ 0x00000020 119 #define STATUS_MS_CNK 0x00000001 120 121 #define INT_STATUS_TPC_ERR 0x00080000 122 #define INT_STATUS_CRC_ERR 0x00040000 123 #define INT_STATUS_TIMER_TO 0x00020000 124 #define INT_STATUS_HSK_TO 0x00010000 125 #define INT_STATUS_ANY_ERR 0x00008000 126 #define INT_STATUS_FIFO_WRDY 0x00000080 127 #define INT_STATUS_FIFO_RRDY 0x00000040 128 #define INT_STATUS_MEDIA_OUT 0x00000010 129 #define INT_STATUS_MEDIA_IN 0x00000008 130 #define INT_STATUS_DMA_BOUNDARY 0x00000004 131 #define INT_STATUS_EOTRAN 0x00000002 132 #define INT_STATUS_EOTPC 0x00000001 133 134 #define INT_STATUS_ALL 0x000f801f 135 136 #define PAD_OUTPUT_ENABLE_MS 0x0F3F 137 138 #define PAD_PU_PD_OFF 0x7FFF0000 139 #define PAD_PU_PD_ON_MS_SOCK0 0x5f8f0000 140 #define PAD_PU_PD_ON_MS_SOCK1 0x0f0f0000 141 142 #define CLOCK_CONTROL_BY_MMIO 0x00000008 143 #define CLOCK_CONTROL_40MHZ 0x00000001 144 #define CLOCK_CONTROL_50MHZ 0x00000002 145 #define CLOCK_CONTROL_60MHZ 0x00000010 146 #define CLOCK_CONTROL_62_5MHZ 0x00000004 147 #define CLOCK_CONTROL_OFF 0x00000000 148 149 #define PCI_CTL_CLOCK_DLY_ADDR 0x000000b0 150 151 enum { 152 CMD_READY = 0x01, 153 FIFO_READY = 0x02, 154 REG_DATA = 0x04, 155 DMA_DATA = 0x08 156 }; 157 158 static unsigned int jmb38x_ms_read_data(struct jmb38x_ms_host *host, 159 unsigned char *buf, unsigned int length) 160 { 161 unsigned int off = 0; 162 163 while (host->io_pos && length) { 164 buf[off++] = host->io_word[0] & 0xff; 165 host->io_word[0] >>= 8; 166 length--; 167 host->io_pos--; 168 } 169 170 if (!length) 171 return off; 172 173 while (!(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) { 174 if (length < 4) 175 break; 176 *(unsigned int *)(buf + off) = __raw_readl(host->addr + DATA); 177 length -= 4; 178 off += 4; 179 } 180 181 if (length 182 && !(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) { 183 host->io_word[0] = readl(host->addr + DATA); 184 for (host->io_pos = 4; host->io_pos; --host->io_pos) { 185 buf[off++] = host->io_word[0] & 0xff; 186 host->io_word[0] >>= 8; 187 length--; 188 if (!length) 189 break; 190 } 191 } 192 193 return off; 194 } 195 196 static unsigned int jmb38x_ms_read_reg_data(struct jmb38x_ms_host *host, 197 unsigned char *buf, 198 unsigned int length) 199 { 200 unsigned int off = 0; 201 202 while (host->io_pos > 4 && length) { 203 buf[off++] = host->io_word[0] & 0xff; 204 host->io_word[0] >>= 8; 205 length--; 206 host->io_pos--; 207 } 208 209 if (!length) 210 return off; 211 212 while (host->io_pos && length) { 213 buf[off++] = host->io_word[1] & 0xff; 214 host->io_word[1] >>= 8; 215 length--; 216 host->io_pos--; 217 } 218 219 return off; 220 } 221 222 static unsigned int jmb38x_ms_write_data(struct jmb38x_ms_host *host, 223 unsigned char *buf, 224 unsigned int length) 225 { 226 unsigned int off = 0; 227 228 if (host->io_pos) { 229 while (host->io_pos < 4 && length) { 230 host->io_word[0] |= buf[off++] << (host->io_pos * 8); 231 host->io_pos++; 232 length--; 233 } 234 } 235 236 if (host->io_pos == 4 237 && !(STATUS_FIFO_FULL & readl(host->addr + STATUS))) { 238 writel(host->io_word[0], host->addr + DATA); 239 host->io_pos = 0; 240 host->io_word[0] = 0; 241 } else if (host->io_pos) { 242 return off; 243 } 244 245 if (!length) 246 return off; 247 248 while (!(STATUS_FIFO_FULL & readl(host->addr + STATUS))) { 249 if (length < 4) 250 break; 251 252 __raw_writel(*(unsigned int *)(buf + off), 253 host->addr + DATA); 254 length -= 4; 255 off += 4; 256 } 257 258 switch (length) { 259 case 3: 260 host->io_word[0] |= buf[off + 2] << 16; 261 host->io_pos++; 262 /* fall through */ 263 case 2: 264 host->io_word[0] |= buf[off + 1] << 8; 265 host->io_pos++; 266 /* fall through */ 267 case 1: 268 host->io_word[0] |= buf[off]; 269 host->io_pos++; 270 } 271 272 off += host->io_pos; 273 274 return off; 275 } 276 277 static unsigned int jmb38x_ms_write_reg_data(struct jmb38x_ms_host *host, 278 unsigned char *buf, 279 unsigned int length) 280 { 281 unsigned int off = 0; 282 283 while (host->io_pos < 4 && length) { 284 host->io_word[0] &= ~(0xff << (host->io_pos * 8)); 285 host->io_word[0] |= buf[off++] << (host->io_pos * 8); 286 host->io_pos++; 287 length--; 288 } 289 290 if (!length) 291 return off; 292 293 while (host->io_pos < 8 && length) { 294 host->io_word[1] &= ~(0xff << (host->io_pos * 8)); 295 host->io_word[1] |= buf[off++] << (host->io_pos * 8); 296 host->io_pos++; 297 length--; 298 } 299 300 return off; 301 } 302 303 static int jmb38x_ms_transfer_data(struct jmb38x_ms_host *host) 304 { 305 unsigned int length; 306 unsigned int off; 307 unsigned int t_size, p_cnt; 308 unsigned char *buf; 309 struct page *pg; 310 unsigned long flags = 0; 311 312 if (host->req->long_data) { 313 length = host->req->sg.length - host->block_pos; 314 off = host->req->sg.offset + host->block_pos; 315 } else { 316 length = host->req->data_len - host->block_pos; 317 off = 0; 318 } 319 320 while (length) { 321 unsigned int uninitialized_var(p_off); 322 323 if (host->req->long_data) { 324 pg = nth_page(sg_page(&host->req->sg), 325 off >> PAGE_SHIFT); 326 p_off = offset_in_page(off); 327 p_cnt = PAGE_SIZE - p_off; 328 p_cnt = min(p_cnt, length); 329 330 local_irq_save(flags); 331 buf = kmap_atomic(pg) + p_off; 332 } else { 333 buf = host->req->data + host->block_pos; 334 p_cnt = host->req->data_len - host->block_pos; 335 } 336 337 if (host->req->data_dir == WRITE) 338 t_size = !(host->cmd_flags & REG_DATA) 339 ? jmb38x_ms_write_data(host, buf, p_cnt) 340 : jmb38x_ms_write_reg_data(host, buf, p_cnt); 341 else 342 t_size = !(host->cmd_flags & REG_DATA) 343 ? jmb38x_ms_read_data(host, buf, p_cnt) 344 : jmb38x_ms_read_reg_data(host, buf, p_cnt); 345 346 if (host->req->long_data) { 347 kunmap_atomic(buf - p_off); 348 local_irq_restore(flags); 349 } 350 351 if (!t_size) 352 break; 353 host->block_pos += t_size; 354 length -= t_size; 355 off += t_size; 356 } 357 358 if (!length && host->req->data_dir == WRITE) { 359 if (host->cmd_flags & REG_DATA) { 360 writel(host->io_word[0], host->addr + TPC_P0); 361 writel(host->io_word[1], host->addr + TPC_P1); 362 } else if (host->io_pos) { 363 writel(host->io_word[0], host->addr + DATA); 364 } 365 } 366 367 return length; 368 } 369 370 static int jmb38x_ms_issue_cmd(struct memstick_host *msh) 371 { 372 struct jmb38x_ms_host *host = memstick_priv(msh); 373 unsigned int data_len, cmd, t_val; 374 375 if (!(STATUS_HAS_MEDIA & readl(host->addr + STATUS))) { 376 dev_dbg(&msh->dev, "no media status\n"); 377 host->req->error = -ETIME; 378 return host->req->error; 379 } 380 381 dev_dbg(&msh->dev, "control %08x\n", readl(host->addr + HOST_CONTROL)); 382 dev_dbg(&msh->dev, "status %08x\n", readl(host->addr + INT_STATUS)); 383 dev_dbg(&msh->dev, "hstatus %08x\n", readl(host->addr + STATUS)); 384 385 host->cmd_flags = 0; 386 host->block_pos = 0; 387 host->io_pos = 0; 388 host->io_word[0] = 0; 389 host->io_word[1] = 0; 390 391 cmd = host->req->tpc << 16; 392 cmd |= TPC_DATA_SEL; 393 394 if (host->req->data_dir == READ) 395 cmd |= TPC_DIR; 396 397 if (host->req->need_card_int) { 398 if (host->ifmode == MEMSTICK_SERIAL) 399 cmd |= TPC_GET_INT; 400 else 401 cmd |= TPC_WAIT_INT; 402 } 403 404 if (!no_dma) 405 host->cmd_flags |= DMA_DATA; 406 407 if (host->req->long_data) { 408 data_len = host->req->sg.length; 409 } else { 410 data_len = host->req->data_len; 411 host->cmd_flags &= ~DMA_DATA; 412 } 413 414 if (data_len <= 8) { 415 cmd &= ~(TPC_DATA_SEL | 0xf); 416 host->cmd_flags |= REG_DATA; 417 cmd |= data_len & 0xf; 418 host->cmd_flags &= ~DMA_DATA; 419 } 420 421 if (host->cmd_flags & DMA_DATA) { 422 if (1 != dma_map_sg(&host->chip->pdev->dev, &host->req->sg, 1, 423 host->req->data_dir == READ 424 ? DMA_FROM_DEVICE 425 : DMA_TO_DEVICE)) { 426 host->req->error = -ENOMEM; 427 return host->req->error; 428 } 429 data_len = sg_dma_len(&host->req->sg); 430 writel(sg_dma_address(&host->req->sg), 431 host->addr + DMA_ADDRESS); 432 writel(((1 << 16) & BLOCK_COUNT_MASK) 433 | (data_len & BLOCK_SIZE_MASK), 434 host->addr + BLOCK); 435 writel(DMA_CONTROL_ENABLE, host->addr + DMA_CONTROL); 436 } else if (!(host->cmd_flags & REG_DATA)) { 437 writel(((1 << 16) & BLOCK_COUNT_MASK) 438 | (data_len & BLOCK_SIZE_MASK), 439 host->addr + BLOCK); 440 t_val = readl(host->addr + INT_STATUS_ENABLE); 441 t_val |= host->req->data_dir == READ 442 ? INT_STATUS_FIFO_RRDY 443 : INT_STATUS_FIFO_WRDY; 444 445 writel(t_val, host->addr + INT_STATUS_ENABLE); 446 writel(t_val, host->addr + INT_SIGNAL_ENABLE); 447 } else { 448 cmd &= ~(TPC_DATA_SEL | 0xf); 449 host->cmd_flags |= REG_DATA; 450 cmd |= data_len & 0xf; 451 452 if (host->req->data_dir == WRITE) { 453 jmb38x_ms_transfer_data(host); 454 writel(host->io_word[0], host->addr + TPC_P0); 455 writel(host->io_word[1], host->addr + TPC_P1); 456 } 457 } 458 459 mod_timer(&host->timer, jiffies + host->timeout_jiffies); 460 writel(HOST_CONTROL_LED | readl(host->addr + HOST_CONTROL), 461 host->addr + HOST_CONTROL); 462 host->req->error = 0; 463 464 writel(cmd, host->addr + TPC); 465 dev_dbg(&msh->dev, "executing TPC %08x, len %x\n", cmd, data_len); 466 467 return 0; 468 } 469 470 static void jmb38x_ms_complete_cmd(struct memstick_host *msh, int last) 471 { 472 struct jmb38x_ms_host *host = memstick_priv(msh); 473 unsigned int t_val = 0; 474 int rc; 475 476 del_timer(&host->timer); 477 478 dev_dbg(&msh->dev, "c control %08x\n", 479 readl(host->addr + HOST_CONTROL)); 480 dev_dbg(&msh->dev, "c status %08x\n", 481 readl(host->addr + INT_STATUS)); 482 dev_dbg(&msh->dev, "c hstatus %08x\n", readl(host->addr + STATUS)); 483 484 host->req->int_reg = readl(host->addr + STATUS) & 0xff; 485 486 writel(0, host->addr + BLOCK); 487 writel(0, host->addr + DMA_CONTROL); 488 489 if (host->cmd_flags & DMA_DATA) { 490 dma_unmap_sg(&host->chip->pdev->dev, &host->req->sg, 1, 491 host->req->data_dir == READ 492 ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 493 } else { 494 t_val = readl(host->addr + INT_STATUS_ENABLE); 495 if (host->req->data_dir == READ) 496 t_val &= ~INT_STATUS_FIFO_RRDY; 497 else 498 t_val &= ~INT_STATUS_FIFO_WRDY; 499 500 writel(t_val, host->addr + INT_STATUS_ENABLE); 501 writel(t_val, host->addr + INT_SIGNAL_ENABLE); 502 } 503 504 writel((~HOST_CONTROL_LED) & readl(host->addr + HOST_CONTROL), 505 host->addr + HOST_CONTROL); 506 507 if (!last) { 508 do { 509 rc = memstick_next_req(msh, &host->req); 510 } while (!rc && jmb38x_ms_issue_cmd(msh)); 511 } else { 512 do { 513 rc = memstick_next_req(msh, &host->req); 514 if (!rc) 515 host->req->error = -ETIME; 516 } while (!rc); 517 } 518 } 519 520 static irqreturn_t jmb38x_ms_isr(int irq, void *dev_id) 521 { 522 struct memstick_host *msh = dev_id; 523 struct jmb38x_ms_host *host = memstick_priv(msh); 524 unsigned int irq_status; 525 526 spin_lock(&host->lock); 527 irq_status = readl(host->addr + INT_STATUS); 528 dev_dbg(&host->chip->pdev->dev, "irq_status = %08x\n", irq_status); 529 if (irq_status == 0 || irq_status == (~0)) { 530 spin_unlock(&host->lock); 531 return IRQ_NONE; 532 } 533 534 if (host->req) { 535 if (irq_status & INT_STATUS_ANY_ERR) { 536 if (irq_status & INT_STATUS_CRC_ERR) 537 host->req->error = -EILSEQ; 538 else if (irq_status & INT_STATUS_TPC_ERR) { 539 dev_dbg(&host->chip->pdev->dev, "TPC_ERR\n"); 540 jmb38x_ms_complete_cmd(msh, 0); 541 } else 542 host->req->error = -ETIME; 543 } else { 544 if (host->cmd_flags & DMA_DATA) { 545 if (irq_status & INT_STATUS_EOTRAN) 546 host->cmd_flags |= FIFO_READY; 547 } else { 548 if (irq_status & (INT_STATUS_FIFO_RRDY 549 | INT_STATUS_FIFO_WRDY)) 550 jmb38x_ms_transfer_data(host); 551 552 if (irq_status & INT_STATUS_EOTRAN) { 553 jmb38x_ms_transfer_data(host); 554 host->cmd_flags |= FIFO_READY; 555 } 556 } 557 558 if (irq_status & INT_STATUS_EOTPC) { 559 host->cmd_flags |= CMD_READY; 560 if (host->cmd_flags & REG_DATA) { 561 if (host->req->data_dir == READ) { 562 host->io_word[0] 563 = readl(host->addr 564 + TPC_P0); 565 host->io_word[1] 566 = readl(host->addr 567 + TPC_P1); 568 host->io_pos = 8; 569 570 jmb38x_ms_transfer_data(host); 571 } 572 host->cmd_flags |= FIFO_READY; 573 } 574 } 575 } 576 } 577 578 if (irq_status & (INT_STATUS_MEDIA_IN | INT_STATUS_MEDIA_OUT)) { 579 dev_dbg(&host->chip->pdev->dev, "media changed\n"); 580 memstick_detect_change(msh); 581 } 582 583 writel(irq_status, host->addr + INT_STATUS); 584 585 if (host->req 586 && (((host->cmd_flags & CMD_READY) 587 && (host->cmd_flags & FIFO_READY)) 588 || host->req->error)) 589 jmb38x_ms_complete_cmd(msh, 0); 590 591 spin_unlock(&host->lock); 592 return IRQ_HANDLED; 593 } 594 595 static void jmb38x_ms_abort(struct timer_list *t) 596 { 597 struct jmb38x_ms_host *host = from_timer(host, t, timer); 598 struct memstick_host *msh = host->msh; 599 unsigned long flags; 600 601 dev_dbg(&host->chip->pdev->dev, "abort\n"); 602 spin_lock_irqsave(&host->lock, flags); 603 if (host->req) { 604 host->req->error = -ETIME; 605 jmb38x_ms_complete_cmd(msh, 0); 606 } 607 spin_unlock_irqrestore(&host->lock, flags); 608 } 609 610 static void jmb38x_ms_req_tasklet(unsigned long data) 611 { 612 struct memstick_host *msh = (struct memstick_host *)data; 613 struct jmb38x_ms_host *host = memstick_priv(msh); 614 unsigned long flags; 615 int rc; 616 617 spin_lock_irqsave(&host->lock, flags); 618 if (!host->req) { 619 do { 620 rc = memstick_next_req(msh, &host->req); 621 dev_dbg(&host->chip->pdev->dev, "tasklet req %d\n", rc); 622 } while (!rc && jmb38x_ms_issue_cmd(msh)); 623 } 624 spin_unlock_irqrestore(&host->lock, flags); 625 } 626 627 static void jmb38x_ms_dummy_submit(struct memstick_host *msh) 628 { 629 return; 630 } 631 632 static void jmb38x_ms_submit_req(struct memstick_host *msh) 633 { 634 struct jmb38x_ms_host *host = memstick_priv(msh); 635 636 tasklet_schedule(&host->notify); 637 } 638 639 static int jmb38x_ms_reset(struct jmb38x_ms_host *host) 640 { 641 int cnt; 642 643 writel(HOST_CONTROL_RESET_REQ | HOST_CONTROL_CLOCK_EN 644 | readl(host->addr + HOST_CONTROL), 645 host->addr + HOST_CONTROL); 646 647 for (cnt = 0; cnt < 20; ++cnt) { 648 if (!(HOST_CONTROL_RESET_REQ 649 & readl(host->addr + HOST_CONTROL))) 650 goto reset_next; 651 652 ndelay(20); 653 } 654 dev_dbg(&host->chip->pdev->dev, "reset_req timeout\n"); 655 656 reset_next: 657 writel(HOST_CONTROL_RESET | HOST_CONTROL_CLOCK_EN 658 | readl(host->addr + HOST_CONTROL), 659 host->addr + HOST_CONTROL); 660 661 for (cnt = 0; cnt < 20; ++cnt) { 662 if (!(HOST_CONTROL_RESET 663 & readl(host->addr + HOST_CONTROL))) 664 goto reset_ok; 665 666 ndelay(20); 667 } 668 dev_dbg(&host->chip->pdev->dev, "reset timeout\n"); 669 return -EIO; 670 671 reset_ok: 672 writel(INT_STATUS_ALL, host->addr + INT_SIGNAL_ENABLE); 673 writel(INT_STATUS_ALL, host->addr + INT_STATUS_ENABLE); 674 return 0; 675 } 676 677 static int jmb38x_ms_set_param(struct memstick_host *msh, 678 enum memstick_param param, 679 int value) 680 { 681 struct jmb38x_ms_host *host = memstick_priv(msh); 682 unsigned int host_ctl = readl(host->addr + HOST_CONTROL); 683 unsigned int clock_ctl = CLOCK_CONTROL_BY_MMIO, clock_delay = 0; 684 int rc = 0; 685 686 switch (param) { 687 case MEMSTICK_POWER: 688 if (value == MEMSTICK_POWER_ON) { 689 rc = jmb38x_ms_reset(host); 690 if (rc) 691 return rc; 692 693 host_ctl = 7; 694 host_ctl |= HOST_CONTROL_POWER_EN 695 | HOST_CONTROL_CLOCK_EN; 696 writel(host_ctl, host->addr + HOST_CONTROL); 697 698 writel(host->id ? PAD_PU_PD_ON_MS_SOCK1 699 : PAD_PU_PD_ON_MS_SOCK0, 700 host->addr + PAD_PU_PD); 701 702 writel(PAD_OUTPUT_ENABLE_MS, 703 host->addr + PAD_OUTPUT_ENABLE); 704 705 msleep(10); 706 dev_dbg(&host->chip->pdev->dev, "power on\n"); 707 } else if (value == MEMSTICK_POWER_OFF) { 708 host_ctl &= ~(HOST_CONTROL_POWER_EN 709 | HOST_CONTROL_CLOCK_EN); 710 writel(host_ctl, host->addr + HOST_CONTROL); 711 writel(0, host->addr + PAD_OUTPUT_ENABLE); 712 writel(PAD_PU_PD_OFF, host->addr + PAD_PU_PD); 713 dev_dbg(&host->chip->pdev->dev, "power off\n"); 714 } else 715 return -EINVAL; 716 break; 717 case MEMSTICK_INTERFACE: 718 dev_dbg(&host->chip->pdev->dev, 719 "Set Host Interface Mode to %d\n", value); 720 host_ctl &= ~(HOST_CONTROL_FAST_CLK | HOST_CONTROL_REI | 721 HOST_CONTROL_REO); 722 host_ctl |= HOST_CONTROL_TDELAY_EN | HOST_CONTROL_HW_OC_P; 723 host_ctl &= ~(3 << HOST_CONTROL_IF_SHIFT); 724 725 if (value == MEMSTICK_SERIAL) { 726 host_ctl |= HOST_CONTROL_IF_SERIAL 727 << HOST_CONTROL_IF_SHIFT; 728 host_ctl |= HOST_CONTROL_REI; 729 clock_ctl |= CLOCK_CONTROL_40MHZ; 730 clock_delay = 0; 731 } else if (value == MEMSTICK_PAR4) { 732 host_ctl |= HOST_CONTROL_FAST_CLK; 733 host_ctl |= HOST_CONTROL_IF_PAR4 734 << HOST_CONTROL_IF_SHIFT; 735 host_ctl |= HOST_CONTROL_REO; 736 clock_ctl |= CLOCK_CONTROL_40MHZ; 737 clock_delay = 4; 738 } else if (value == MEMSTICK_PAR8) { 739 host_ctl |= HOST_CONTROL_FAST_CLK; 740 host_ctl |= HOST_CONTROL_IF_PAR8 741 << HOST_CONTROL_IF_SHIFT; 742 clock_ctl |= CLOCK_CONTROL_50MHZ; 743 clock_delay = 0; 744 } else 745 return -EINVAL; 746 747 writel(host_ctl, host->addr + HOST_CONTROL); 748 writel(CLOCK_CONTROL_OFF, host->addr + CLOCK_CONTROL); 749 writel(clock_ctl, host->addr + CLOCK_CONTROL); 750 pci_write_config_byte(host->chip->pdev, 751 PCI_CTL_CLOCK_DLY_ADDR + 1, 752 clock_delay); 753 host->ifmode = value; 754 break; 755 }; 756 return 0; 757 } 758 759 #define PCI_PMOS0_CONTROL 0xae 760 #define PMOS0_ENABLE 0x01 761 #define PMOS0_OVERCURRENT_LEVEL_2_4V 0x06 762 #define PMOS0_EN_OVERCURRENT_DEBOUNCE 0x40 763 #define PMOS0_SW_LED_POLARITY_ENABLE 0x80 764 #define PMOS0_ACTIVE_BITS (PMOS0_ENABLE | PMOS0_EN_OVERCURRENT_DEBOUNCE | \ 765 PMOS0_OVERCURRENT_LEVEL_2_4V) 766 #define PCI_PMOS1_CONTROL 0xbd 767 #define PMOS1_ACTIVE_BITS 0x4a 768 #define PCI_CLOCK_CTL 0xb9 769 770 static int jmb38x_ms_pmos(struct pci_dev *pdev, int flag) 771 { 772 unsigned char val; 773 774 pci_read_config_byte(pdev, PCI_PMOS0_CONTROL, &val); 775 if (flag) 776 val |= PMOS0_ACTIVE_BITS; 777 else 778 val &= ~PMOS0_ACTIVE_BITS; 779 pci_write_config_byte(pdev, PCI_PMOS0_CONTROL, val); 780 dev_dbg(&pdev->dev, "JMB38x: set PMOS0 val 0x%x\n", val); 781 782 if (pci_resource_flags(pdev, 1)) { 783 pci_read_config_byte(pdev, PCI_PMOS1_CONTROL, &val); 784 if (flag) 785 val |= PMOS1_ACTIVE_BITS; 786 else 787 val &= ~PMOS1_ACTIVE_BITS; 788 pci_write_config_byte(pdev, PCI_PMOS1_CONTROL, val); 789 dev_dbg(&pdev->dev, "JMB38x: set PMOS1 val 0x%x\n", val); 790 } 791 792 pci_read_config_byte(pdev, PCI_CLOCK_CTL, &val); 793 pci_write_config_byte(pdev, PCI_CLOCK_CTL, val & ~0x0f); 794 pci_write_config_byte(pdev, PCI_CLOCK_CTL, val | 0x01); 795 dev_dbg(&pdev->dev, "Clock Control by PCI config is disabled!\n"); 796 797 return 0; 798 } 799 800 #ifdef CONFIG_PM 801 802 static int jmb38x_ms_suspend(struct pci_dev *dev, pm_message_t state) 803 { 804 struct jmb38x_ms *jm = pci_get_drvdata(dev); 805 int cnt; 806 807 for (cnt = 0; cnt < jm->host_cnt; ++cnt) { 808 if (!jm->hosts[cnt]) 809 break; 810 memstick_suspend_host(jm->hosts[cnt]); 811 } 812 813 pci_save_state(dev); 814 pci_enable_wake(dev, pci_choose_state(dev, state), 0); 815 pci_disable_device(dev); 816 pci_set_power_state(dev, pci_choose_state(dev, state)); 817 return 0; 818 } 819 820 static int jmb38x_ms_resume(struct pci_dev *dev) 821 { 822 struct jmb38x_ms *jm = pci_get_drvdata(dev); 823 int rc; 824 825 pci_set_power_state(dev, PCI_D0); 826 pci_restore_state(dev); 827 rc = pci_enable_device(dev); 828 if (rc) 829 return rc; 830 pci_set_master(dev); 831 832 jmb38x_ms_pmos(dev, 1); 833 834 for (rc = 0; rc < jm->host_cnt; ++rc) { 835 if (!jm->hosts[rc]) 836 break; 837 memstick_resume_host(jm->hosts[rc]); 838 memstick_detect_change(jm->hosts[rc]); 839 } 840 841 return 0; 842 } 843 844 #else 845 846 #define jmb38x_ms_suspend NULL 847 #define jmb38x_ms_resume NULL 848 849 #endif /* CONFIG_PM */ 850 851 static int jmb38x_ms_count_slots(struct pci_dev *pdev) 852 { 853 int cnt, rc = 0; 854 855 for (cnt = 0; cnt < PCI_ROM_RESOURCE; ++cnt) { 856 if (!(IORESOURCE_MEM & pci_resource_flags(pdev, cnt))) 857 break; 858 859 if (256 != pci_resource_len(pdev, cnt)) 860 break; 861 862 ++rc; 863 } 864 return rc; 865 } 866 867 static struct memstick_host *jmb38x_ms_alloc_host(struct jmb38x_ms *jm, int cnt) 868 { 869 struct memstick_host *msh; 870 struct jmb38x_ms_host *host; 871 872 msh = memstick_alloc_host(sizeof(struct jmb38x_ms_host), 873 &jm->pdev->dev); 874 if (!msh) 875 return NULL; 876 877 host = memstick_priv(msh); 878 host->msh = msh; 879 host->chip = jm; 880 host->addr = ioremap(pci_resource_start(jm->pdev, cnt), 881 pci_resource_len(jm->pdev, cnt)); 882 if (!host->addr) 883 goto err_out_free; 884 885 spin_lock_init(&host->lock); 886 host->id = cnt; 887 snprintf(host->host_id, sizeof(host->host_id), DRIVER_NAME ":slot%d", 888 host->id); 889 host->irq = jm->pdev->irq; 890 host->timeout_jiffies = msecs_to_jiffies(1000); 891 892 tasklet_init(&host->notify, jmb38x_ms_req_tasklet, (unsigned long)msh); 893 msh->request = jmb38x_ms_submit_req; 894 msh->set_param = jmb38x_ms_set_param; 895 896 msh->caps = MEMSTICK_CAP_PAR4 | MEMSTICK_CAP_PAR8; 897 898 timer_setup(&host->timer, jmb38x_ms_abort, 0); 899 900 if (!request_irq(host->irq, jmb38x_ms_isr, IRQF_SHARED, host->host_id, 901 msh)) 902 return msh; 903 904 iounmap(host->addr); 905 err_out_free: 906 kfree(msh); 907 return NULL; 908 } 909 910 static void jmb38x_ms_free_host(struct memstick_host *msh) 911 { 912 struct jmb38x_ms_host *host = memstick_priv(msh); 913 914 free_irq(host->irq, msh); 915 iounmap(host->addr); 916 memstick_free_host(msh); 917 } 918 919 static int jmb38x_ms_probe(struct pci_dev *pdev, 920 const struct pci_device_id *dev_id) 921 { 922 struct jmb38x_ms *jm; 923 int pci_dev_busy = 0; 924 int rc, cnt; 925 926 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 927 if (rc) 928 return rc; 929 930 rc = pci_enable_device(pdev); 931 if (rc) 932 return rc; 933 934 pci_set_master(pdev); 935 936 rc = pci_request_regions(pdev, DRIVER_NAME); 937 if (rc) { 938 pci_dev_busy = 1; 939 goto err_out; 940 } 941 942 jmb38x_ms_pmos(pdev, 1); 943 944 cnt = jmb38x_ms_count_slots(pdev); 945 if (!cnt) { 946 rc = -ENODEV; 947 pci_dev_busy = 1; 948 goto err_out; 949 } 950 951 jm = kzalloc(sizeof(struct jmb38x_ms) 952 + cnt * sizeof(struct memstick_host *), GFP_KERNEL); 953 if (!jm) { 954 rc = -ENOMEM; 955 goto err_out_int; 956 } 957 958 jm->pdev = pdev; 959 jm->host_cnt = cnt; 960 pci_set_drvdata(pdev, jm); 961 962 for (cnt = 0; cnt < jm->host_cnt; ++cnt) { 963 jm->hosts[cnt] = jmb38x_ms_alloc_host(jm, cnt); 964 if (!jm->hosts[cnt]) 965 break; 966 967 rc = memstick_add_host(jm->hosts[cnt]); 968 969 if (rc) { 970 jmb38x_ms_free_host(jm->hosts[cnt]); 971 jm->hosts[cnt] = NULL; 972 break; 973 } 974 } 975 976 if (cnt) 977 return 0; 978 979 rc = -ENODEV; 980 981 pci_set_drvdata(pdev, NULL); 982 kfree(jm); 983 err_out_int: 984 pci_release_regions(pdev); 985 err_out: 986 if (!pci_dev_busy) 987 pci_disable_device(pdev); 988 return rc; 989 } 990 991 static void jmb38x_ms_remove(struct pci_dev *dev) 992 { 993 struct jmb38x_ms *jm = pci_get_drvdata(dev); 994 struct jmb38x_ms_host *host; 995 int cnt; 996 unsigned long flags; 997 998 for (cnt = 0; cnt < jm->host_cnt; ++cnt) { 999 if (!jm->hosts[cnt]) 1000 break; 1001 1002 host = memstick_priv(jm->hosts[cnt]); 1003 1004 jm->hosts[cnt]->request = jmb38x_ms_dummy_submit; 1005 tasklet_kill(&host->notify); 1006 writel(0, host->addr + INT_SIGNAL_ENABLE); 1007 writel(0, host->addr + INT_STATUS_ENABLE); 1008 dev_dbg(&jm->pdev->dev, "interrupts off\n"); 1009 spin_lock_irqsave(&host->lock, flags); 1010 if (host->req) { 1011 host->req->error = -ETIME; 1012 jmb38x_ms_complete_cmd(jm->hosts[cnt], 1); 1013 } 1014 spin_unlock_irqrestore(&host->lock, flags); 1015 1016 memstick_remove_host(jm->hosts[cnt]); 1017 dev_dbg(&jm->pdev->dev, "host removed\n"); 1018 1019 jmb38x_ms_free_host(jm->hosts[cnt]); 1020 } 1021 1022 jmb38x_ms_pmos(dev, 0); 1023 1024 pci_set_drvdata(dev, NULL); 1025 pci_release_regions(dev); 1026 pci_disable_device(dev); 1027 kfree(jm); 1028 } 1029 1030 static struct pci_device_id jmb38x_ms_id_tbl [] = { 1031 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_MS) }, 1032 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB385_MS) }, 1033 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB390_MS) }, 1034 { } 1035 }; 1036 1037 static struct pci_driver jmb38x_ms_driver = { 1038 .name = DRIVER_NAME, 1039 .id_table = jmb38x_ms_id_tbl, 1040 .probe = jmb38x_ms_probe, 1041 .remove = jmb38x_ms_remove, 1042 .suspend = jmb38x_ms_suspend, 1043 .resume = jmb38x_ms_resume 1044 }; 1045 1046 module_pci_driver(jmb38x_ms_driver); 1047 1048 MODULE_AUTHOR("Alex Dubov"); 1049 MODULE_DESCRIPTION("JMicron jmb38x MemoryStick driver"); 1050 MODULE_LICENSE("GPL"); 1051 MODULE_DEVICE_TABLE(pci, jmb38x_ms_id_tbl); 1052