1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2021-2022, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <soc/tegra/mc.h> 7 8 #include <dt-bindings/memory/tegra234-mc.h> 9 10 #include "mc.h" 11 12 static const struct tegra_mc_client tegra234_mc_clients[] = { 13 { 14 .id = TEGRA234_MEMORY_CLIENT_MGBEARD, 15 .name = "mgbeard", 16 .sid = TEGRA234_SID_MGBE, 17 .regs = { 18 .sid = { 19 .override = 0x2c0, 20 .security = 0x2c4, 21 }, 22 }, 23 }, { 24 .id = TEGRA234_MEMORY_CLIENT_MGBEBRD, 25 .name = "mgbebrd", 26 .sid = TEGRA234_SID_MGBE_VF1, 27 .regs = { 28 .sid = { 29 .override = 0x2c8, 30 .security = 0x2cc, 31 }, 32 }, 33 }, { 34 .id = TEGRA234_MEMORY_CLIENT_MGBECRD, 35 .name = "mgbecrd", 36 .sid = TEGRA234_SID_MGBE_VF2, 37 .regs = { 38 .sid = { 39 .override = 0x2d0, 40 .security = 0x2d4, 41 }, 42 }, 43 }, { 44 .id = TEGRA234_MEMORY_CLIENT_MGBEDRD, 45 .name = "mgbedrd", 46 .sid = TEGRA234_SID_MGBE_VF3, 47 .regs = { 48 .sid = { 49 .override = 0x2d8, 50 .security = 0x2dc, 51 }, 52 }, 53 }, { 54 .id = TEGRA234_MEMORY_CLIENT_MGBEAWR, 55 .name = "mgbeawr", 56 .sid = TEGRA234_SID_MGBE, 57 .regs = { 58 .sid = { 59 .override = 0x2e0, 60 .security = 0x2e4, 61 }, 62 }, 63 }, { 64 .id = TEGRA234_MEMORY_CLIENT_MGBEBWR, 65 .name = "mgbebwr", 66 .sid = TEGRA234_SID_MGBE_VF1, 67 .regs = { 68 .sid = { 69 .override = 0x2f8, 70 .security = 0x2fc, 71 }, 72 }, 73 }, { 74 .id = TEGRA234_MEMORY_CLIENT_MGBECWR, 75 .name = "mgbecwr", 76 .sid = TEGRA234_SID_MGBE_VF2, 77 .regs = { 78 .sid = { 79 .override = 0x308, 80 .security = 0x30c, 81 }, 82 }, 83 }, { 84 .id = TEGRA234_MEMORY_CLIENT_SDMMCRAB, 85 .name = "sdmmcrab", 86 .sid = TEGRA234_SID_SDMMC4, 87 .regs = { 88 .sid = { 89 .override = 0x318, 90 .security = 0x31c, 91 }, 92 }, 93 }, { 94 .id = TEGRA234_MEMORY_CLIENT_MGBEDWR, 95 .name = "mgbedwr", 96 .sid = TEGRA234_SID_MGBE_VF3, 97 .regs = { 98 .sid = { 99 .override = 0x328, 100 .security = 0x32c, 101 }, 102 }, 103 }, { 104 .id = TEGRA234_MEMORY_CLIENT_SDMMCWAB, 105 .name = "sdmmcwab", 106 .sid = TEGRA234_SID_SDMMC4, 107 .regs = { 108 .sid = { 109 .override = 0x338, 110 .security = 0x33c, 111 }, 112 }, 113 }, { 114 .id = TEGRA234_MEMORY_CLIENT_BPMPR, 115 .name = "bpmpr", 116 .sid = TEGRA234_SID_BPMP, 117 .regs = { 118 .sid = { 119 .override = 0x498, 120 .security = 0x49c, 121 }, 122 }, 123 }, { 124 .id = TEGRA234_MEMORY_CLIENT_BPMPW, 125 .name = "bpmpw", 126 .sid = TEGRA234_SID_BPMP, 127 .regs = { 128 .sid = { 129 .override = 0x4a0, 130 .security = 0x4a4, 131 }, 132 }, 133 }, { 134 .id = TEGRA234_MEMORY_CLIENT_BPMPDMAR, 135 .name = "bpmpdmar", 136 .sid = TEGRA234_SID_BPMP, 137 .regs = { 138 .sid = { 139 .override = 0x4a8, 140 .security = 0x4ac, 141 }, 142 }, 143 }, { 144 .id = TEGRA234_MEMORY_CLIENT_BPMPDMAW, 145 .name = "bpmpdmaw", 146 .sid = TEGRA234_SID_BPMP, 147 .regs = { 148 .sid = { 149 .override = 0x4b0, 150 .security = 0x4b4, 151 }, 152 }, 153 }, { 154 .id = TEGRA234_MEMORY_CLIENT_APEDMAR, 155 .name = "apedmar", 156 .sid = TEGRA234_SID_APE, 157 .regs = { 158 .sid = { 159 .override = 0x4f8, 160 .security = 0x4fc, 161 }, 162 }, 163 }, { 164 .id = TEGRA234_MEMORY_CLIENT_APEDMAW, 165 .name = "apedmaw", 166 .sid = TEGRA234_SID_APE, 167 .regs = { 168 .sid = { 169 .override = 0x500, 170 .security = 0x504, 171 }, 172 }, 173 }, 174 }; 175 176 const struct tegra_mc_soc tegra234_mc_soc = { 177 .num_clients = ARRAY_SIZE(tegra234_mc_clients), 178 .clients = tegra234_mc_clients, 179 .num_address_bits = 40, 180 .num_channels = 16, 181 .client_id_mask = 0x1ff, 182 .intmask = MC_INT_DECERR_ROUTE_SANITY | 183 MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | 184 MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | 185 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, 186 .has_addr_hi_reg = true, 187 .ops = &tegra186_mc_ops, 188 .ch_intmask = 0x0000ff00, 189 .global_intstatus_channel_shift = 8, 190 }; 191