xref: /openbmc/linux/drivers/memory/tegra/tegra234.c (revision 31ceedee) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2022-2023, NVIDIA CORPORATION.  All rights reserved.
4  */
5 
6 #include <soc/tegra/mc.h>
7 
8 #include <dt-bindings/memory/tegra234-mc.h>
9 #include <linux/interconnect.h>
10 #include <linux/tegra-icc.h>
11 
12 #include <soc/tegra/bpmp.h>
13 #include "mc.h"
14 
15 static const struct tegra_mc_client tegra234_mc_clients[] = {
16 	{
17 		.id = TEGRA234_MEMORY_CLIENT_HDAR,
18 		.name = "hdar",
19 		.bpmp_id = TEGRA_ICC_BPMP_HDA,
20 		.type = TEGRA_ICC_ISO_AUDIO,
21 		.sid = TEGRA234_SID_HDA,
22 		.regs = {
23 			.sid = {
24 				.override = 0xa8,
25 				.security = 0xac,
26 			},
27 		},
28 	}, {
29 		.id = TEGRA234_MEMORY_CLIENT_HDAW,
30 		.name = "hdaw",
31 		.bpmp_id = TEGRA_ICC_BPMP_HDA,
32 		.type = TEGRA_ICC_ISO_AUDIO,
33 		.sid = TEGRA234_SID_HDA,
34 		.regs = {
35 			.sid = {
36 				.override = 0x1a8,
37 				.security = 0x1ac,
38 			},
39 		},
40 	}, {
41 		.id = TEGRA234_MEMORY_CLIENT_MGBEARD,
42 		.name = "mgbeard",
43 		.bpmp_id = TEGRA_ICC_BPMP_EQOS,
44 		.type = TEGRA_ICC_NISO,
45 		.sid = TEGRA234_SID_MGBE,
46 		.regs = {
47 			.sid = {
48 				.override = 0x2c0,
49 				.security = 0x2c4,
50 			},
51 		},
52 	}, {
53 		.id = TEGRA234_MEMORY_CLIENT_MGBEBRD,
54 		.name = "mgbebrd",
55 		.bpmp_id = TEGRA_ICC_BPMP_EQOS,
56 		.type = TEGRA_ICC_NISO,
57 		.sid = TEGRA234_SID_MGBE_VF1,
58 		.regs = {
59 			.sid = {
60 				.override = 0x2c8,
61 				.security = 0x2cc,
62 			},
63 		},
64 	}, {
65 		.id = TEGRA234_MEMORY_CLIENT_MGBECRD,
66 		.name = "mgbecrd",
67 		.bpmp_id = TEGRA_ICC_BPMP_EQOS,
68 		.type = TEGRA_ICC_NISO,
69 		.sid = TEGRA234_SID_MGBE_VF2,
70 		.regs = {
71 			.sid = {
72 				.override = 0x2d0,
73 				.security = 0x2d4,
74 			},
75 		},
76 	}, {
77 		.id = TEGRA234_MEMORY_CLIENT_MGBEDRD,
78 		.name = "mgbedrd",
79 		.bpmp_id = TEGRA_ICC_BPMP_EQOS,
80 		.type = TEGRA_ICC_NISO,
81 		.sid = TEGRA234_SID_MGBE_VF3,
82 		.regs = {
83 			.sid = {
84 				.override = 0x2d8,
85 				.security = 0x2dc,
86 			},
87 		},
88 	}, {
89 		.id = TEGRA234_MEMORY_CLIENT_MGBEAWR,
90 		.bpmp_id = TEGRA_ICC_BPMP_EQOS,
91 		.type = TEGRA_ICC_NISO,
92 		.name = "mgbeawr",
93 		.sid = TEGRA234_SID_MGBE,
94 		.regs = {
95 			.sid = {
96 				.override = 0x2e0,
97 				.security = 0x2e4,
98 			},
99 		},
100 	}, {
101 		.id = TEGRA234_MEMORY_CLIENT_MGBEBWR,
102 		.name = "mgbebwr",
103 		.bpmp_id = TEGRA_ICC_BPMP_EQOS,
104 		.type = TEGRA_ICC_NISO,
105 		.sid = TEGRA234_SID_MGBE_VF1,
106 		.regs = {
107 			.sid = {
108 				.override = 0x2f8,
109 				.security = 0x2fc,
110 			},
111 		},
112 	}, {
113 		.id = TEGRA234_MEMORY_CLIENT_MGBECWR,
114 		.name = "mgbecwr",
115 		.bpmp_id = TEGRA_ICC_BPMP_EQOS,
116 		.type = TEGRA_ICC_NISO,
117 		.sid = TEGRA234_SID_MGBE_VF2,
118 		.regs = {
119 			.sid = {
120 				.override = 0x308,
121 				.security = 0x30c,
122 			},
123 		},
124 	}, {
125 		.id = TEGRA234_MEMORY_CLIENT_SDMMCRAB,
126 		.name = "sdmmcrab",
127 		.bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,
128 		.type = TEGRA_ICC_NISO,
129 		.sid = TEGRA234_SID_SDMMC4,
130 		.regs = {
131 			.sid = {
132 				.override = 0x318,
133 				.security = 0x31c,
134 			},
135 		},
136 	}, {
137 		.id = TEGRA234_MEMORY_CLIENT_MGBEDWR,
138 		.name = "mgbedwr",
139 		.bpmp_id = TEGRA_ICC_BPMP_EQOS,
140 		.type = TEGRA_ICC_NISO,
141 		.sid = TEGRA234_SID_MGBE_VF3,
142 		.regs = {
143 			.sid = {
144 				.override = 0x328,
145 				.security = 0x32c,
146 			},
147 		},
148 	}, {
149 		.id = TEGRA234_MEMORY_CLIENT_SDMMCWAB,
150 		.name = "sdmmcwab",
151 		.bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,
152 		.type = TEGRA_ICC_NISO,
153 		.sid = TEGRA234_SID_SDMMC4,
154 		.regs = {
155 			.sid = {
156 				.override = 0x338,
157 				.security = 0x33c,
158 			},
159 		},
160 	}, {
161 		.id = TEGRA234_MEMORY_CLIENT_VI2W,
162 		.name = "vi2w",
163 		.bpmp_id = TEGRA_ICC_BPMP_VI2,
164 		.type = TEGRA_ICC_ISO_VI,
165 		.sid = TEGRA234_SID_ISO_VI2,
166 		.regs = {
167 			.sid = {
168 				.override = 0x380,
169 				.security = 0x384,
170 			},
171 		},
172 	}, {
173 		.id = TEGRA234_MEMORY_CLIENT_VI2FALR,
174 		.name = "vi2falr",
175 		.bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
176 		.type = TEGRA_ICC_ISO_VIFAL,
177 		.sid = TEGRA234_SID_ISO_VI2FALC,
178 		.regs = {
179 			.sid = {
180 				.override = 0x388,
181 				.security = 0x38c,
182 			},
183 		},
184 	}, {
185 		.id = TEGRA234_MEMORY_CLIENT_VI2FALW,
186 		.name = "vi2falw",
187 		.bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
188 		.type = TEGRA_ICC_ISO_VIFAL,
189 		.sid = TEGRA234_SID_ISO_VI2FALC,
190 		.regs = {
191 			.sid = {
192 				.override = 0x3e0,
193 				.security = 0x3e4,
194 			},
195 		},
196 	}, {
197 		.id = TEGRA234_MEMORY_CLIENT_APER,
198 		.name = "aper",
199 		.bpmp_id = TEGRA_ICC_BPMP_APE,
200 		.type = TEGRA_ICC_ISO_AUDIO,
201 		.sid = TEGRA234_SID_APE,
202 		.regs = {
203 			.sid = {
204 				.override = 0x3d0,
205 				.security = 0x3d4,
206 			},
207 		},
208 	}, {
209 		.id = TEGRA234_MEMORY_CLIENT_APEW,
210 		.name = "apew",
211 		.bpmp_id = TEGRA_ICC_BPMP_APE,
212 		.type = TEGRA_ICC_ISO_AUDIO,
213 		.sid = TEGRA234_SID_APE,
214 		.regs = {
215 			.sid = {
216 				.override = 0x3d8,
217 				.security = 0x3dc,
218 			},
219 		},
220 	}, {
221 		.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,
222 		.name = "nvdisplayr",
223 		.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
224 		.type = TEGRA_ICC_ISO_DISPLAY,
225 		.sid = TEGRA234_SID_ISO_NVDISPLAY,
226 		.regs = {
227 			.sid = {
228 				.override = 0x490,
229 				.security = 0x494,
230 			},
231 		},
232 	}, {
233 		.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
234 		.name = "nvdisplayr1",
235 		.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
236 		.type = TEGRA_ICC_ISO_DISPLAY,
237 		.sid = TEGRA234_SID_ISO_NVDISPLAY,
238 		.regs = {
239 			.sid = {
240 				.override = 0x508,
241 				.security = 0x50c,
242 			},
243 		},
244 	}, {
245 		.id = TEGRA234_MEMORY_CLIENT_BPMPR,
246 		.name = "bpmpr",
247 		.sid = TEGRA234_SID_BPMP,
248 		.regs = {
249 			.sid = {
250 				.override = 0x498,
251 				.security = 0x49c,
252 			},
253 		},
254 	}, {
255 		.id = TEGRA234_MEMORY_CLIENT_BPMPW,
256 		.name = "bpmpw",
257 		.sid = TEGRA234_SID_BPMP,
258 		.regs = {
259 			.sid = {
260 				.override = 0x4a0,
261 				.security = 0x4a4,
262 			},
263 		},
264 	}, {
265 		.id = TEGRA234_MEMORY_CLIENT_BPMPDMAR,
266 		.name = "bpmpdmar",
267 		.sid = TEGRA234_SID_BPMP,
268 		.regs = {
269 			.sid = {
270 				.override = 0x4a8,
271 				.security = 0x4ac,
272 			},
273 		},
274 	}, {
275 		.id = TEGRA234_MEMORY_CLIENT_BPMPDMAW,
276 		.name = "bpmpdmaw",
277 		.sid = TEGRA234_SID_BPMP,
278 		.regs = {
279 			.sid = {
280 				.override = 0x4b0,
281 				.security = 0x4b4,
282 			},
283 		},
284 	}, {
285 		.id = TEGRA234_MEMORY_CLIENT_APEDMAR,
286 		.name = "apedmar",
287 		.bpmp_id = TEGRA_ICC_BPMP_APEDMA,
288 		.type = TEGRA_ICC_ISO_AUDIO,
289 		.sid = TEGRA234_SID_APE,
290 		.regs = {
291 			.sid = {
292 				.override = 0x4f8,
293 				.security = 0x4fc,
294 			},
295 		},
296 	}, {
297 		.id = TEGRA234_MEMORY_CLIENT_APEDMAW,
298 		.name = "apedmaw",
299 		.bpmp_id = TEGRA_ICC_BPMP_APEDMA,
300 		.type = TEGRA_ICC_ISO_AUDIO,
301 		.sid = TEGRA234_SID_APE,
302 		.regs = {
303 			.sid = {
304 				.override = 0x500,
305 				.security = 0x504,
306 			},
307 		},
308 	}, {
309 		.id = TEGRA234_MEMORY_CLIENT_DLA0RDA,
310 		.name = "dla0rda",
311 		.sid = TEGRA234_SID_NVDLA0,
312 		.regs = {
313 			.sid = {
314 				.override = 0x5f0,
315 				.security = 0x5f4,
316 			},
317 		},
318 	}, {
319 		.id = TEGRA234_MEMORY_CLIENT_DLA0FALRDB,
320 		.name = "dla0falrdb",
321 		.sid = TEGRA234_SID_NVDLA0,
322 		.regs = {
323 			.sid = {
324 				.override = 0x5f8,
325 				.security = 0x5fc,
326 			},
327 		},
328 	}, {
329 		.id = TEGRA234_MEMORY_CLIENT_DLA0WRA,
330 		.name = "dla0wra",
331 		.sid = TEGRA234_SID_NVDLA0,
332 		.regs = {
333 			.sid = {
334 				.override = 0x600,
335 				.security = 0x604,
336 			},
337 		},
338 	}, {
339 		.id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
340 		.name = "dla0rdb",
341 		.sid = TEGRA234_SID_NVDLA0,
342 		.regs = {
343 			.sid = {
344 				.override = 0x160,
345 				.security = 0x164,
346 			},
347 		},
348 	}, {
349 		.id = TEGRA234_MEMORY_CLIENT_DLA0RDA1,
350 		.name = "dla0rda1",
351 		.sid = TEGRA234_SID_NVDLA0,
352 		.regs = {
353 			.sid = {
354 				.override = 0x748,
355 				.security = 0x74c,
356 			},
357 		},
358 	}, {
359 		.id = TEGRA234_MEMORY_CLIENT_DLA0FALWRB,
360 		.name = "dla0falwrb",
361 		.sid = TEGRA234_SID_NVDLA0,
362 		.regs = {
363 			.sid = {
364 				.override = 0x608,
365 				.security = 0x60c,
366 			},
367 		},
368 	}, {
369 		.id = TEGRA234_MEMORY_CLIENT_DLA0RDB1,
370 		.name = "dla0rdb1",
371 		.sid = TEGRA234_SID_NVDLA0,
372 		.regs = {
373 			.sid = {
374 				.override = 0x168,
375 				.security = 0x16c,
376 			},
377 		},
378 	}, {
379 		.id = TEGRA234_MEMORY_CLIENT_DLA0WRB,
380 		.name = "dla0wrb",
381 		.sid = TEGRA234_SID_NVDLA0,
382 		.regs = {
383 			.sid = {
384 				.override = 0x170,
385 				.security = 0x174,
386 			},
387 		},
388 	}, {
389 		.id = TEGRA234_MEMORY_CLIENT_DLA1RDA,
390 		.name = "dla0rda",
391 		.sid = TEGRA234_SID_NVDLA1,
392 		.regs = {
393 			.sid = {
394 				.override = 0x610,
395 				.security = 0x614,
396 			},
397 		},
398 	}, {
399 		.id = TEGRA234_MEMORY_CLIENT_DLA1FALRDB,
400 		.name = "dla0falrdb",
401 		.sid = TEGRA234_SID_NVDLA1,
402 		.regs = {
403 			.sid = {
404 				.override = 0x618,
405 				.security = 0x61c,
406 			},
407 		},
408 	}, {
409 		.id = TEGRA234_MEMORY_CLIENT_DLA1WRA,
410 		.name = "dla0wra",
411 		.sid = TEGRA234_SID_NVDLA1,
412 		.regs = {
413 			.sid = {
414 				.override = 0x620,
415 				.security = 0x624,
416 			},
417 		},
418 	}, {
419 		.id = TEGRA234_MEMORY_CLIENT_DLA1RDB,
420 		.name = "dla0rdb",
421 		.sid = TEGRA234_SID_NVDLA1,
422 		.regs = {
423 			.sid = {
424 				.override = 0x178,
425 				.security = 0x17c,
426 			},
427 		},
428 	}, {
429 		.id = TEGRA234_MEMORY_CLIENT_DLA1RDA1,
430 		.name = "dla0rda1",
431 		.sid = TEGRA234_SID_NVDLA1,
432 		.regs = {
433 			.sid = {
434 				.override = 0x750,
435 				.security = 0x754,
436 			},
437 		},
438 	}, {
439 		.id = TEGRA234_MEMORY_CLIENT_DLA1FALWRB,
440 		.name = "dla0falwrb",
441 		.sid = TEGRA234_SID_NVDLA1,
442 		.regs = {
443 			.sid = {
444 				.override = 0x628,
445 				.security = 0x62c,
446 			},
447 		},
448 	}, {
449 		.id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
450 		.name = "dla0rdb1",
451 		.sid = TEGRA234_SID_NVDLA1,
452 		.regs = {
453 			.sid = {
454 				.override = 0x370,
455 				.security = 0x374,
456 			},
457 		},
458 	}, {
459 		.id = TEGRA234_MEMORY_CLIENT_DLA1WRB,
460 		.name = "dla0wrb",
461 		.sid = TEGRA234_SID_NVDLA1,
462 		.regs = {
463 			.sid = {
464 				.override = 0x378,
465 				.security = 0x37c,
466 			},
467 		},
468 	}, {
469 		.id = TEGRA234_MEMORY_CLIENT_PCIE0R,
470 		.name = "pcie0r",
471 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
472 		.type = TEGRA_ICC_NISO,
473 		.sid = TEGRA234_SID_PCIE0,
474 		.regs = {
475 			.sid = {
476 				.override = 0x6c0,
477 				.security = 0x6c4,
478 			},
479 		},
480 	}, {
481 		.id = TEGRA234_MEMORY_CLIENT_PCIE0W,
482 		.name = "pcie0w",
483 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
484 		.type = TEGRA_ICC_NISO,
485 		.sid = TEGRA234_SID_PCIE0,
486 		.regs = {
487 			.sid = {
488 				.override = 0x6c8,
489 				.security = 0x6cc,
490 			},
491 		},
492 	}, {
493 		.id = TEGRA234_MEMORY_CLIENT_PCIE1R,
494 		.name = "pcie1r",
495 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_1,
496 		.type = TEGRA_ICC_NISO,
497 		.sid = TEGRA234_SID_PCIE1,
498 		.regs = {
499 			.sid = {
500 				.override = 0x6d0,
501 				.security = 0x6d4,
502 			},
503 		},
504 	}, {
505 		.id = TEGRA234_MEMORY_CLIENT_PCIE1W,
506 		.name = "pcie1w",
507 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_1,
508 		.type = TEGRA_ICC_NISO,
509 		.sid = TEGRA234_SID_PCIE1,
510 		.regs = {
511 			.sid = {
512 				.override = 0x6d8,
513 				.security = 0x6dc,
514 			},
515 		},
516 	}, {
517 		.id = TEGRA234_MEMORY_CLIENT_PCIE2AR,
518 		.name = "pcie2ar",
519 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_2,
520 		.type = TEGRA_ICC_NISO,
521 		.sid = TEGRA234_SID_PCIE2,
522 		.regs = {
523 			.sid = {
524 				.override = 0x6e0,
525 				.security = 0x6e4,
526 			},
527 		},
528 	}, {
529 		.id = TEGRA234_MEMORY_CLIENT_PCIE2AW,
530 		.name = "pcie2aw",
531 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_2,
532 		.type = TEGRA_ICC_NISO,
533 		.sid = TEGRA234_SID_PCIE2,
534 		.regs = {
535 			.sid = {
536 				.override = 0x6e8,
537 				.security = 0x6ec,
538 			},
539 		},
540 	}, {
541 		.id = TEGRA234_MEMORY_CLIENT_PCIE3R,
542 		.name = "pcie3r",
543 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_3,
544 		.type = TEGRA_ICC_NISO,
545 		.sid = TEGRA234_SID_PCIE3,
546 		.regs = {
547 			.sid = {
548 				.override = 0x6f0,
549 				.security = 0x6f4,
550 			},
551 		},
552 	}, {
553 		.id = TEGRA234_MEMORY_CLIENT_PCIE3W,
554 		.name = "pcie3w",
555 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_3,
556 		.type = TEGRA_ICC_NISO,
557 		.sid = TEGRA234_SID_PCIE3,
558 		.regs = {
559 			.sid = {
560 				.override = 0x6f8,
561 				.security = 0x6fc,
562 			},
563 		},
564 	}, {
565 		.id = TEGRA234_MEMORY_CLIENT_PCIE4R,
566 		.name = "pcie4r",
567 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_4,
568 		.type = TEGRA_ICC_NISO,
569 		.sid = TEGRA234_SID_PCIE4,
570 		.regs = {
571 			.sid = {
572 				.override = 0x700,
573 				.security = 0x704,
574 			},
575 		},
576 	}, {
577 		.id = TEGRA234_MEMORY_CLIENT_PCIE4W,
578 		.name = "pcie4w",
579 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_4,
580 		.type = TEGRA_ICC_NISO,
581 		.sid = TEGRA234_SID_PCIE4,
582 		.regs = {
583 			.sid = {
584 				.override = 0x708,
585 				.security = 0x70c,
586 			},
587 		},
588 	}, {
589 		.id = TEGRA234_MEMORY_CLIENT_PCIE5R,
590 		.name = "pcie5r",
591 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
592 		.type = TEGRA_ICC_NISO,
593 		.sid = TEGRA234_SID_PCIE5,
594 		.regs = {
595 			.sid = {
596 				.override = 0x710,
597 				.security = 0x714,
598 			},
599 		},
600 	}, {
601 		.id = TEGRA234_MEMORY_CLIENT_PCIE5W,
602 		.name = "pcie5w",
603 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
604 		.type = TEGRA_ICC_NISO,
605 		.sid = TEGRA234_SID_PCIE5,
606 		.regs = {
607 			.sid = {
608 				.override = 0x718,
609 				.security = 0x71c,
610 			},
611 		},
612 	}, {
613 		.id = TEGRA234_MEMORY_CLIENT_PCIE5R1,
614 		.name = "pcie5r1",
615 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
616 		.type = TEGRA_ICC_NISO,
617 		.sid = TEGRA234_SID_PCIE5,
618 		.regs = {
619 			.sid = {
620 				.override = 0x778,
621 				.security = 0x77c,
622 			},
623 		},
624 	}, {
625 		.id = TEGRA234_MEMORY_CLIENT_PCIE6AR,
626 		.name = "pcie6ar",
627 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
628 		.type = TEGRA_ICC_NISO,
629 		.sid = TEGRA234_SID_PCIE6,
630 		.regs = {
631 			.sid = {
632 				.override = 0x140,
633 				.security = 0x144,
634 			},
635 		},
636 	}, {
637 		.id = TEGRA234_MEMORY_CLIENT_PCIE6AW,
638 		.name = "pcie6aw",
639 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
640 		.type = TEGRA_ICC_NISO,
641 		.sid = TEGRA234_SID_PCIE6,
642 		.regs = {
643 			.sid = {
644 				.override = 0x148,
645 				.security = 0x14c,
646 			},
647 		},
648 	}, {
649 		.id = TEGRA234_MEMORY_CLIENT_PCIE6AR1,
650 		.name = "pcie6ar1",
651 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
652 		.type = TEGRA_ICC_NISO,
653 		.sid = TEGRA234_SID_PCIE6,
654 		.regs = {
655 			.sid = {
656 				.override = 0x1e8,
657 				.security = 0x1ec,
658 			},
659 		},
660 	}, {
661 		.id = TEGRA234_MEMORY_CLIENT_PCIE7AR,
662 		.name = "pcie7ar",
663 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
664 		.type = TEGRA_ICC_NISO,
665 		.sid = TEGRA234_SID_PCIE7,
666 		.regs = {
667 			.sid = {
668 				.override = 0x150,
669 				.security = 0x154,
670 			},
671 		},
672 	}, {
673 		.id = TEGRA234_MEMORY_CLIENT_PCIE7AW,
674 		.name = "pcie7aw",
675 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
676 		.type = TEGRA_ICC_NISO,
677 		.sid = TEGRA234_SID_PCIE7,
678 		.regs = {
679 			.sid = {
680 				.override = 0x180,
681 				.security = 0x184,
682 			},
683 		},
684 	}, {
685 		.id = TEGRA234_MEMORY_CLIENT_PCIE7AR1,
686 		.name = "pcie7ar1",
687 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
688 		.type = TEGRA_ICC_NISO,
689 		.sid = TEGRA234_SID_PCIE7,
690 		.regs = {
691 			.sid = {
692 				.override = 0x248,
693 				.security = 0x24c,
694 			},
695 		},
696 	}, {
697 		.id = TEGRA234_MEMORY_CLIENT_PCIE8AR,
698 		.name = "pcie8ar",
699 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
700 		.type = TEGRA_ICC_NISO,
701 		.sid = TEGRA234_SID_PCIE8,
702 		.regs = {
703 			.sid = {
704 				.override = 0x190,
705 				.security = 0x194,
706 			},
707 		},
708 	}, {
709 		.id = TEGRA234_MEMORY_CLIENT_PCIE8AW,
710 		.name = "pcie8aw",
711 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
712 		.type = TEGRA_ICC_NISO,
713 		.sid = TEGRA234_SID_PCIE8,
714 		.regs = {
715 			.sid = {
716 				.override = 0x1d8,
717 				.security = 0x1dc,
718 			},
719 		},
720 	}, {
721 		.id = TEGRA234_MEMORY_CLIENT_PCIE9AR,
722 		.name = "pcie9ar",
723 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
724 		.type = TEGRA_ICC_NISO,
725 		.sid = TEGRA234_SID_PCIE9,
726 		.regs = {
727 			.sid = {
728 				.override = 0x1e0,
729 				.security = 0x1e4,
730 			},
731 		},
732 	}, {
733 		.id = TEGRA234_MEMORY_CLIENT_PCIE9AW,
734 		.name = "pcie9aw",
735 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
736 		.type = TEGRA_ICC_NISO,
737 		.sid = TEGRA234_SID_PCIE9,
738 		.regs = {
739 			.sid = {
740 				.override = 0x1f0,
741 				.security = 0x1f4,
742 			},
743 		},
744 	}, {
745 		.id = TEGRA234_MEMORY_CLIENT_PCIE10AR,
746 		.name = "pcie10ar",
747 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
748 		.type = TEGRA_ICC_NISO,
749 		.sid = TEGRA234_SID_PCIE10,
750 		.regs = {
751 			.sid = {
752 				.override = 0x1f8,
753 				.security = 0x1fc,
754 			},
755 		},
756 	}, {
757 		.id = TEGRA234_MEMORY_CLIENT_PCIE10AW,
758 		.name = "pcie10aw",
759 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
760 		.type = TEGRA_ICC_NISO,
761 		.sid = TEGRA234_SID_PCIE10,
762 		.regs = {
763 			.sid = {
764 				.override = 0x200,
765 				.security = 0x204,
766 			},
767 		},
768 	}, {
769 		.id = TEGRA234_MEMORY_CLIENT_PCIE10AR1,
770 		.name = "pcie10ar1",
771 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
772 		.type = TEGRA_ICC_NISO,
773 		.sid = TEGRA234_SID_PCIE10,
774 		.regs = {
775 			.sid = {
776 				.override = 0x240,
777 				.security = 0x244,
778 			},
779 		},
780 	}, {
781 		.id = TEGRA_ICC_MC_CPU_CLUSTER0,
782 		.name = "sw_cluster0",
783 		.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER0,
784 		.type = TEGRA_ICC_NISO,
785 	}, {
786 		.id = TEGRA_ICC_MC_CPU_CLUSTER1,
787 		.name = "sw_cluster1",
788 		.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER1,
789 		.type = TEGRA_ICC_NISO,
790 	}, {
791 		.id = TEGRA_ICC_MC_CPU_CLUSTER2,
792 		.name = "sw_cluster2",
793 		.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER2,
794 		.type = TEGRA_ICC_NISO,
795 	},
796 };
797 
798 /*
799  * tegra234_mc_icc_set() - Pass MC client info to the BPMP-FW
800  * @src: ICC node for Memory Controller's (MC) Client
801  * @dst: ICC node for Memory Controller (MC)
802  *
803  * Passing the current request info from the MC to the BPMP-FW where
804  * LA and PTSA registers are accessed and the final EMC freq is set
805  * based on client_id, type, latency and bandwidth.
806  * icc_set_bw() makes set_bw calls for both MC and EMC providers in
807  * sequence. Both the calls are protected by 'mutex_lock(&icc_lock)'.
808  * So, the data passed won't be updated by concurrent set calls from
809  * other clients.
810  */
811 static int tegra234_mc_icc_set(struct icc_node *src, struct icc_node *dst)
812 {
813 	struct tegra_mc *mc = icc_provider_to_tegra_mc(dst->provider);
814 	struct mrq_bwmgr_int_request bwmgr_req = { 0 };
815 	struct mrq_bwmgr_int_response bwmgr_resp = { 0 };
816 	const struct tegra_mc_client *pclient = src->data;
817 	struct tegra_bpmp_message msg;
818 	int ret;
819 
820 	/*
821 	 * Same Src and Dst node will happen during boot from icc_node_add().
822 	 * This can be used to pre-initialize and set bandwidth for all clients
823 	 * before their drivers are loaded. We are skipping this case as for us,
824 	 * the pre-initialization already happened in Bootloader(MB2) and BPMP-FW.
825 	 */
826 	if (src->id == dst->id)
827 		return 0;
828 
829 	if (!mc->bwmgr_mrq_supported)
830 		return -EINVAL;
831 
832 	if (!mc->bpmp) {
833 		dev_err(mc->dev, "BPMP reference NULL\n");
834 		return -ENOENT;
835 	}
836 
837 	if (pclient->type == TEGRA_ICC_NISO)
838 		bwmgr_req.bwmgr_calc_set_req.niso_bw = src->avg_bw;
839 	else
840 		bwmgr_req.bwmgr_calc_set_req.iso_bw = src->avg_bw;
841 
842 	bwmgr_req.bwmgr_calc_set_req.client_id = pclient->bpmp_id;
843 
844 	bwmgr_req.cmd = CMD_BWMGR_INT_CALC_AND_SET;
845 	bwmgr_req.bwmgr_calc_set_req.mc_floor = src->peak_bw;
846 	bwmgr_req.bwmgr_calc_set_req.floor_unit = BWMGR_INT_UNIT_KBPS;
847 
848 	memset(&msg, 0, sizeof(msg));
849 	msg.mrq = MRQ_BWMGR_INT;
850 	msg.tx.data = &bwmgr_req;
851 	msg.tx.size = sizeof(bwmgr_req);
852 	msg.rx.data = &bwmgr_resp;
853 	msg.rx.size = sizeof(bwmgr_resp);
854 
855 	ret = tegra_bpmp_transfer(mc->bpmp, &msg);
856 	if (ret < 0) {
857 		dev_err(mc->dev, "BPMP transfer failed: %d\n", ret);
858 		goto error;
859 	}
860 	if (msg.rx.ret < 0) {
861 		pr_err("failed to set bandwidth for %u: %d\n",
862 		       bwmgr_req.bwmgr_calc_set_req.client_id, msg.rx.ret);
863 		ret = -EINVAL;
864 	}
865 
866 error:
867 	return ret;
868 }
869 
870 static int tegra234_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
871 				     u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
872 {
873 	struct icc_provider *p = node->provider;
874 	struct tegra_mc *mc = icc_provider_to_tegra_mc(p);
875 
876 	if (!mc->bwmgr_mrq_supported)
877 		return -EINVAL;
878 
879 	if (node->id == TEGRA_ICC_MC_CPU_CLUSTER0 ||
880 	    node->id == TEGRA_ICC_MC_CPU_CLUSTER1 ||
881 	    node->id == TEGRA_ICC_MC_CPU_CLUSTER2) {
882 		if (mc)
883 			peak_bw = peak_bw * mc->num_channels;
884 	}
885 
886 	*agg_avg += avg_bw;
887 	*agg_peak = max(*agg_peak, peak_bw);
888 
889 	return 0;
890 }
891 
892 static struct icc_node*
893 tegra234_mc_of_icc_xlate(struct of_phandle_args *spec, void *data)
894 {
895 	struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
896 	unsigned int cl_id = spec->args[0];
897 	struct icc_node *node;
898 
899 	list_for_each_entry(node, &mc->provider.nodes, node_list) {
900 		if (node->id != cl_id)
901 			continue;
902 
903 		return node;
904 	}
905 
906 	/*
907 	 * If a client driver calls devm_of_icc_get() before the MC driver
908 	 * is probed, then return EPROBE_DEFER to the client driver.
909 	 */
910 	return ERR_PTR(-EPROBE_DEFER);
911 }
912 
913 static int tegra234_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak)
914 {
915 	*avg = 0;
916 	*peak = 0;
917 
918 	return 0;
919 }
920 
921 static const struct tegra_mc_icc_ops tegra234_mc_icc_ops = {
922 	.xlate = tegra234_mc_of_icc_xlate,
923 	.aggregate = tegra234_mc_icc_aggregate,
924 	.get_bw = tegra234_mc_icc_get_init_bw,
925 	.set = tegra234_mc_icc_set,
926 };
927 
928 const struct tegra_mc_soc tegra234_mc_soc = {
929 	.num_clients = ARRAY_SIZE(tegra234_mc_clients),
930 	.clients = tegra234_mc_clients,
931 	.num_address_bits = 40,
932 	.num_channels = 16,
933 	.client_id_mask = 0x1ff,
934 	.intmask = MC_INT_DECERR_ROUTE_SANITY |
935 		   MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
936 		   MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
937 		   MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
938 	.has_addr_hi_reg = true,
939 	.ops = &tegra186_mc_ops,
940 	.icc_ops = &tegra234_mc_icc_ops,
941 	.ch_intmask = 0x0000ff00,
942 	.global_intstatus_channel_shift = 8,
943 	/*
944 	 * Additionally, there are lite carveouts but those are not currently
945 	 * supported.
946 	 */
947 	.num_carveouts = 32,
948 };
949