196e5da7cSDmitry Osipenko // SPDX-License-Identifier: GPL-2.0 296e5da7cSDmitry Osipenko /* 396e5da7cSDmitry Osipenko * Tegra20 External Memory Controller driver 496e5da7cSDmitry Osipenko * 596e5da7cSDmitry Osipenko * Author: Dmitry Osipenko <digetx@gmail.com> 696e5da7cSDmitry Osipenko */ 796e5da7cSDmitry Osipenko 896e5da7cSDmitry Osipenko #include <linux/clk.h> 977ab499dSDmitry Osipenko #include <linux/clk/tegra.h> 1096e5da7cSDmitry Osipenko #include <linux/completion.h> 1196e5da7cSDmitry Osipenko #include <linux/err.h> 1296e5da7cSDmitry Osipenko #include <linux/interrupt.h> 13d039cf28SDmitry Osipenko #include <linux/io.h> 1496e5da7cSDmitry Osipenko #include <linux/kernel.h> 1596e5da7cSDmitry Osipenko #include <linux/module.h> 1696e5da7cSDmitry Osipenko #include <linux/of.h> 1796e5da7cSDmitry Osipenko #include <linux/platform_device.h> 1896e5da7cSDmitry Osipenko #include <linux/sort.h> 1996e5da7cSDmitry Osipenko #include <linux/types.h> 2096e5da7cSDmitry Osipenko 2196e5da7cSDmitry Osipenko #include <soc/tegra/fuse.h> 2296e5da7cSDmitry Osipenko 2396e5da7cSDmitry Osipenko #define EMC_INTSTATUS 0x000 2496e5da7cSDmitry Osipenko #define EMC_INTMASK 0x004 25c72396f9SDmitry Osipenko #define EMC_DBG 0x008 2696e5da7cSDmitry Osipenko #define EMC_TIMING_CONTROL 0x028 2796e5da7cSDmitry Osipenko #define EMC_RC 0x02c 2896e5da7cSDmitry Osipenko #define EMC_RFC 0x030 2996e5da7cSDmitry Osipenko #define EMC_RAS 0x034 3096e5da7cSDmitry Osipenko #define EMC_RP 0x038 3196e5da7cSDmitry Osipenko #define EMC_R2W 0x03c 3296e5da7cSDmitry Osipenko #define EMC_W2R 0x040 3396e5da7cSDmitry Osipenko #define EMC_R2P 0x044 3496e5da7cSDmitry Osipenko #define EMC_W2P 0x048 3596e5da7cSDmitry Osipenko #define EMC_RD_RCD 0x04c 3696e5da7cSDmitry Osipenko #define EMC_WR_RCD 0x050 3796e5da7cSDmitry Osipenko #define EMC_RRD 0x054 3896e5da7cSDmitry Osipenko #define EMC_REXT 0x058 3996e5da7cSDmitry Osipenko #define EMC_WDV 0x05c 4096e5da7cSDmitry Osipenko #define EMC_QUSE 0x060 4196e5da7cSDmitry Osipenko #define EMC_QRST 0x064 4296e5da7cSDmitry Osipenko #define EMC_QSAFE 0x068 4396e5da7cSDmitry Osipenko #define EMC_RDV 0x06c 4496e5da7cSDmitry Osipenko #define EMC_REFRESH 0x070 4596e5da7cSDmitry Osipenko #define EMC_BURST_REFRESH_NUM 0x074 4696e5da7cSDmitry Osipenko #define EMC_PDEX2WR 0x078 4796e5da7cSDmitry Osipenko #define EMC_PDEX2RD 0x07c 4896e5da7cSDmitry Osipenko #define EMC_PCHG2PDEN 0x080 4996e5da7cSDmitry Osipenko #define EMC_ACT2PDEN 0x084 5096e5da7cSDmitry Osipenko #define EMC_AR2PDEN 0x088 5196e5da7cSDmitry Osipenko #define EMC_RW2PDEN 0x08c 5296e5da7cSDmitry Osipenko #define EMC_TXSR 0x090 5396e5da7cSDmitry Osipenko #define EMC_TCKE 0x094 5496e5da7cSDmitry Osipenko #define EMC_TFAW 0x098 5596e5da7cSDmitry Osipenko #define EMC_TRPAB 0x09c 5696e5da7cSDmitry Osipenko #define EMC_TCLKSTABLE 0x0a0 5796e5da7cSDmitry Osipenko #define EMC_TCLKSTOP 0x0a4 5896e5da7cSDmitry Osipenko #define EMC_TREFBW 0x0a8 5996e5da7cSDmitry Osipenko #define EMC_QUSE_EXTRA 0x0ac 6096e5da7cSDmitry Osipenko #define EMC_ODT_WRITE 0x0b0 6196e5da7cSDmitry Osipenko #define EMC_ODT_READ 0x0b4 6296e5da7cSDmitry Osipenko #define EMC_FBIO_CFG5 0x104 6396e5da7cSDmitry Osipenko #define EMC_FBIO_CFG6 0x114 6496e5da7cSDmitry Osipenko #define EMC_AUTO_CAL_INTERVAL 0x2a8 6596e5da7cSDmitry Osipenko #define EMC_CFG_2 0x2b8 6696e5da7cSDmitry Osipenko #define EMC_CFG_DIG_DLL 0x2bc 6796e5da7cSDmitry Osipenko #define EMC_DLL_XFORM_DQS 0x2c0 6896e5da7cSDmitry Osipenko #define EMC_DLL_XFORM_QUSE 0x2c4 6996e5da7cSDmitry Osipenko #define EMC_ZCAL_REF_CNT 0x2e0 7096e5da7cSDmitry Osipenko #define EMC_ZCAL_WAIT_CNT 0x2e4 7196e5da7cSDmitry Osipenko #define EMC_CFG_CLKTRIM_0 0x2d0 7296e5da7cSDmitry Osipenko #define EMC_CFG_CLKTRIM_1 0x2d4 7396e5da7cSDmitry Osipenko #define EMC_CFG_CLKTRIM_2 0x2d8 7496e5da7cSDmitry Osipenko 7596e5da7cSDmitry Osipenko #define EMC_CLKCHANGE_REQ_ENABLE BIT(0) 7696e5da7cSDmitry Osipenko #define EMC_CLKCHANGE_PD_ENABLE BIT(1) 7796e5da7cSDmitry Osipenko #define EMC_CLKCHANGE_SR_ENABLE BIT(2) 7896e5da7cSDmitry Osipenko 7996e5da7cSDmitry Osipenko #define EMC_TIMING_UPDATE BIT(0) 8096e5da7cSDmitry Osipenko 8196e5da7cSDmitry Osipenko #define EMC_REFRESH_OVERFLOW_INT BIT(3) 8296e5da7cSDmitry Osipenko #define EMC_CLKCHANGE_COMPLETE_INT BIT(4) 8396e5da7cSDmitry Osipenko 84c72396f9SDmitry Osipenko #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0) 85c72396f9SDmitry Osipenko #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) 86c72396f9SDmitry Osipenko #define EMC_DBG_FORCE_UPDATE BIT(2) 87c72396f9SDmitry Osipenko #define EMC_DBG_READ_DQM_CTRL BIT(9) 88c72396f9SDmitry Osipenko #define EMC_DBG_CFG_PRIORITY BIT(24) 89c72396f9SDmitry Osipenko 9096e5da7cSDmitry Osipenko static const u16 emc_timing_registers[] = { 9196e5da7cSDmitry Osipenko EMC_RC, 9296e5da7cSDmitry Osipenko EMC_RFC, 9396e5da7cSDmitry Osipenko EMC_RAS, 9496e5da7cSDmitry Osipenko EMC_RP, 9596e5da7cSDmitry Osipenko EMC_R2W, 9696e5da7cSDmitry Osipenko EMC_W2R, 9796e5da7cSDmitry Osipenko EMC_R2P, 9896e5da7cSDmitry Osipenko EMC_W2P, 9996e5da7cSDmitry Osipenko EMC_RD_RCD, 10096e5da7cSDmitry Osipenko EMC_WR_RCD, 10196e5da7cSDmitry Osipenko EMC_RRD, 10296e5da7cSDmitry Osipenko EMC_REXT, 10396e5da7cSDmitry Osipenko EMC_WDV, 10496e5da7cSDmitry Osipenko EMC_QUSE, 10596e5da7cSDmitry Osipenko EMC_QRST, 10696e5da7cSDmitry Osipenko EMC_QSAFE, 10796e5da7cSDmitry Osipenko EMC_RDV, 10896e5da7cSDmitry Osipenko EMC_REFRESH, 10996e5da7cSDmitry Osipenko EMC_BURST_REFRESH_NUM, 11096e5da7cSDmitry Osipenko EMC_PDEX2WR, 11196e5da7cSDmitry Osipenko EMC_PDEX2RD, 11296e5da7cSDmitry Osipenko EMC_PCHG2PDEN, 11396e5da7cSDmitry Osipenko EMC_ACT2PDEN, 11496e5da7cSDmitry Osipenko EMC_AR2PDEN, 11596e5da7cSDmitry Osipenko EMC_RW2PDEN, 11696e5da7cSDmitry Osipenko EMC_TXSR, 11796e5da7cSDmitry Osipenko EMC_TCKE, 11896e5da7cSDmitry Osipenko EMC_TFAW, 11996e5da7cSDmitry Osipenko EMC_TRPAB, 12096e5da7cSDmitry Osipenko EMC_TCLKSTABLE, 12196e5da7cSDmitry Osipenko EMC_TCLKSTOP, 12296e5da7cSDmitry Osipenko EMC_TREFBW, 12396e5da7cSDmitry Osipenko EMC_QUSE_EXTRA, 12496e5da7cSDmitry Osipenko EMC_FBIO_CFG6, 12596e5da7cSDmitry Osipenko EMC_ODT_WRITE, 12696e5da7cSDmitry Osipenko EMC_ODT_READ, 12796e5da7cSDmitry Osipenko EMC_FBIO_CFG5, 12896e5da7cSDmitry Osipenko EMC_CFG_DIG_DLL, 12996e5da7cSDmitry Osipenko EMC_DLL_XFORM_DQS, 13096e5da7cSDmitry Osipenko EMC_DLL_XFORM_QUSE, 13196e5da7cSDmitry Osipenko EMC_ZCAL_REF_CNT, 13296e5da7cSDmitry Osipenko EMC_ZCAL_WAIT_CNT, 13396e5da7cSDmitry Osipenko EMC_AUTO_CAL_INTERVAL, 13496e5da7cSDmitry Osipenko EMC_CFG_CLKTRIM_0, 13596e5da7cSDmitry Osipenko EMC_CFG_CLKTRIM_1, 13696e5da7cSDmitry Osipenko EMC_CFG_CLKTRIM_2, 13796e5da7cSDmitry Osipenko }; 13896e5da7cSDmitry Osipenko 13996e5da7cSDmitry Osipenko struct emc_timing { 14096e5da7cSDmitry Osipenko unsigned long rate; 14196e5da7cSDmitry Osipenko u32 data[ARRAY_SIZE(emc_timing_registers)]; 14296e5da7cSDmitry Osipenko }; 14396e5da7cSDmitry Osipenko 14496e5da7cSDmitry Osipenko struct tegra_emc { 14596e5da7cSDmitry Osipenko struct device *dev; 14696e5da7cSDmitry Osipenko struct completion clk_handshake_complete; 14796e5da7cSDmitry Osipenko struct notifier_block clk_nb; 14896e5da7cSDmitry Osipenko struct clk *clk; 14996e5da7cSDmitry Osipenko void __iomem *regs; 15096e5da7cSDmitry Osipenko 15196e5da7cSDmitry Osipenko struct emc_timing *timings; 15296e5da7cSDmitry Osipenko unsigned int num_timings; 15396e5da7cSDmitry Osipenko }; 15496e5da7cSDmitry Osipenko 15596e5da7cSDmitry Osipenko static irqreturn_t tegra_emc_isr(int irq, void *data) 15696e5da7cSDmitry Osipenko { 15796e5da7cSDmitry Osipenko struct tegra_emc *emc = data; 15896e5da7cSDmitry Osipenko u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT; 15996e5da7cSDmitry Osipenko u32 status; 16096e5da7cSDmitry Osipenko 16196e5da7cSDmitry Osipenko status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; 16296e5da7cSDmitry Osipenko if (!status) 16396e5da7cSDmitry Osipenko return IRQ_NONE; 16496e5da7cSDmitry Osipenko 16596e5da7cSDmitry Osipenko /* notify about EMC-CAR handshake completion */ 16696e5da7cSDmitry Osipenko if (status & EMC_CLKCHANGE_COMPLETE_INT) 16796e5da7cSDmitry Osipenko complete(&emc->clk_handshake_complete); 16896e5da7cSDmitry Osipenko 16996e5da7cSDmitry Osipenko /* notify about HW problem */ 17096e5da7cSDmitry Osipenko if (status & EMC_REFRESH_OVERFLOW_INT) 17196e5da7cSDmitry Osipenko dev_err_ratelimited(emc->dev, 17296e5da7cSDmitry Osipenko "refresh request overflow timeout\n"); 17396e5da7cSDmitry Osipenko 17496e5da7cSDmitry Osipenko /* clear interrupts */ 17596e5da7cSDmitry Osipenko writel_relaxed(status, emc->regs + EMC_INTSTATUS); 17696e5da7cSDmitry Osipenko 17796e5da7cSDmitry Osipenko return IRQ_HANDLED; 17896e5da7cSDmitry Osipenko } 17996e5da7cSDmitry Osipenko 18096e5da7cSDmitry Osipenko static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, 18196e5da7cSDmitry Osipenko unsigned long rate) 18296e5da7cSDmitry Osipenko { 18396e5da7cSDmitry Osipenko struct emc_timing *timing = NULL; 18496e5da7cSDmitry Osipenko unsigned int i; 18596e5da7cSDmitry Osipenko 18696e5da7cSDmitry Osipenko for (i = 0; i < emc->num_timings; i++) { 18796e5da7cSDmitry Osipenko if (emc->timings[i].rate >= rate) { 18896e5da7cSDmitry Osipenko timing = &emc->timings[i]; 18996e5da7cSDmitry Osipenko break; 19096e5da7cSDmitry Osipenko } 19196e5da7cSDmitry Osipenko } 19296e5da7cSDmitry Osipenko 19396e5da7cSDmitry Osipenko if (!timing) { 19496e5da7cSDmitry Osipenko dev_err(emc->dev, "no timing for rate %lu\n", rate); 19596e5da7cSDmitry Osipenko return NULL; 19696e5da7cSDmitry Osipenko } 19796e5da7cSDmitry Osipenko 19896e5da7cSDmitry Osipenko return timing; 19996e5da7cSDmitry Osipenko } 20096e5da7cSDmitry Osipenko 20196e5da7cSDmitry Osipenko static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) 20296e5da7cSDmitry Osipenko { 20396e5da7cSDmitry Osipenko struct emc_timing *timing = tegra_emc_find_timing(emc, rate); 20496e5da7cSDmitry Osipenko unsigned int i; 20596e5da7cSDmitry Osipenko 20696e5da7cSDmitry Osipenko if (!timing) 20796e5da7cSDmitry Osipenko return -EINVAL; 20896e5da7cSDmitry Osipenko 20996e5da7cSDmitry Osipenko dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", 21096e5da7cSDmitry Osipenko __func__, timing->rate, rate); 21196e5da7cSDmitry Osipenko 21296e5da7cSDmitry Osipenko /* program shadow registers */ 21396e5da7cSDmitry Osipenko for (i = 0; i < ARRAY_SIZE(timing->data); i++) 21496e5da7cSDmitry Osipenko writel_relaxed(timing->data[i], 21596e5da7cSDmitry Osipenko emc->regs + emc_timing_registers[i]); 21696e5da7cSDmitry Osipenko 21796e5da7cSDmitry Osipenko /* wait until programming has settled */ 21896e5da7cSDmitry Osipenko readl_relaxed(emc->regs + emc_timing_registers[i - 1]); 21996e5da7cSDmitry Osipenko 22096e5da7cSDmitry Osipenko reinit_completion(&emc->clk_handshake_complete); 22196e5da7cSDmitry Osipenko 22296e5da7cSDmitry Osipenko return 0; 22396e5da7cSDmitry Osipenko } 22496e5da7cSDmitry Osipenko 22596e5da7cSDmitry Osipenko static int emc_complete_timing_change(struct tegra_emc *emc, bool flush) 22696e5da7cSDmitry Osipenko { 22788c5bfecSDmitry Osipenko unsigned long timeout; 22896e5da7cSDmitry Osipenko 22996e5da7cSDmitry Osipenko dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush); 23096e5da7cSDmitry Osipenko 23196e5da7cSDmitry Osipenko if (flush) { 23296e5da7cSDmitry Osipenko /* manually initiate memory timing update */ 23396e5da7cSDmitry Osipenko writel_relaxed(EMC_TIMING_UPDATE, 23496e5da7cSDmitry Osipenko emc->regs + EMC_TIMING_CONTROL); 23596e5da7cSDmitry Osipenko return 0; 23696e5da7cSDmitry Osipenko } 23796e5da7cSDmitry Osipenko 23896e5da7cSDmitry Osipenko timeout = wait_for_completion_timeout(&emc->clk_handshake_complete, 239b56563d0SDmitry Osipenko msecs_to_jiffies(100)); 24096e5da7cSDmitry Osipenko if (timeout == 0) { 24196e5da7cSDmitry Osipenko dev_err(emc->dev, "EMC-CAR handshake failed\n"); 24296e5da7cSDmitry Osipenko return -EIO; 24396e5da7cSDmitry Osipenko } 24496e5da7cSDmitry Osipenko 24596e5da7cSDmitry Osipenko return 0; 24696e5da7cSDmitry Osipenko } 24796e5da7cSDmitry Osipenko 24896e5da7cSDmitry Osipenko static int tegra_emc_clk_change_notify(struct notifier_block *nb, 24996e5da7cSDmitry Osipenko unsigned long msg, void *data) 25096e5da7cSDmitry Osipenko { 25196e5da7cSDmitry Osipenko struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); 25296e5da7cSDmitry Osipenko struct clk_notifier_data *cnd = data; 25396e5da7cSDmitry Osipenko int err; 25496e5da7cSDmitry Osipenko 25596e5da7cSDmitry Osipenko switch (msg) { 25696e5da7cSDmitry Osipenko case PRE_RATE_CHANGE: 25796e5da7cSDmitry Osipenko err = emc_prepare_timing_change(emc, cnd->new_rate); 25896e5da7cSDmitry Osipenko break; 25996e5da7cSDmitry Osipenko 26096e5da7cSDmitry Osipenko case ABORT_RATE_CHANGE: 26196e5da7cSDmitry Osipenko err = emc_prepare_timing_change(emc, cnd->old_rate); 26296e5da7cSDmitry Osipenko if (err) 26396e5da7cSDmitry Osipenko break; 26496e5da7cSDmitry Osipenko 26596e5da7cSDmitry Osipenko err = emc_complete_timing_change(emc, true); 26696e5da7cSDmitry Osipenko break; 26796e5da7cSDmitry Osipenko 26896e5da7cSDmitry Osipenko case POST_RATE_CHANGE: 26996e5da7cSDmitry Osipenko err = emc_complete_timing_change(emc, false); 27096e5da7cSDmitry Osipenko break; 27196e5da7cSDmitry Osipenko 27296e5da7cSDmitry Osipenko default: 27396e5da7cSDmitry Osipenko return NOTIFY_DONE; 27496e5da7cSDmitry Osipenko } 27596e5da7cSDmitry Osipenko 27696e5da7cSDmitry Osipenko return notifier_from_errno(err); 27796e5da7cSDmitry Osipenko } 27896e5da7cSDmitry Osipenko 27996e5da7cSDmitry Osipenko static int load_one_timing_from_dt(struct tegra_emc *emc, 28096e5da7cSDmitry Osipenko struct emc_timing *timing, 28196e5da7cSDmitry Osipenko struct device_node *node) 28296e5da7cSDmitry Osipenko { 28396e5da7cSDmitry Osipenko u32 rate; 28496e5da7cSDmitry Osipenko int err; 28596e5da7cSDmitry Osipenko 28696e5da7cSDmitry Osipenko if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) { 28796e5da7cSDmitry Osipenko dev_err(emc->dev, "incompatible DT node: %pOF\n", node); 28896e5da7cSDmitry Osipenko return -EINVAL; 28996e5da7cSDmitry Osipenko } 29096e5da7cSDmitry Osipenko 29196e5da7cSDmitry Osipenko err = of_property_read_u32(node, "clock-frequency", &rate); 29296e5da7cSDmitry Osipenko if (err) { 29396e5da7cSDmitry Osipenko dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n", 29496e5da7cSDmitry Osipenko node, err); 29596e5da7cSDmitry Osipenko return err; 29696e5da7cSDmitry Osipenko } 29796e5da7cSDmitry Osipenko 29896e5da7cSDmitry Osipenko err = of_property_read_u32_array(node, "nvidia,emc-registers", 29996e5da7cSDmitry Osipenko timing->data, 30096e5da7cSDmitry Osipenko ARRAY_SIZE(emc_timing_registers)); 30196e5da7cSDmitry Osipenko if (err) { 30296e5da7cSDmitry Osipenko dev_err(emc->dev, 30396e5da7cSDmitry Osipenko "timing %pOF: failed to read emc timing data: %d\n", 30496e5da7cSDmitry Osipenko node, err); 30596e5da7cSDmitry Osipenko return err; 30696e5da7cSDmitry Osipenko } 30796e5da7cSDmitry Osipenko 30896e5da7cSDmitry Osipenko /* 30996e5da7cSDmitry Osipenko * The EMC clock rate is twice the bus rate, and the bus rate is 31096e5da7cSDmitry Osipenko * measured in kHz. 31196e5da7cSDmitry Osipenko */ 31296e5da7cSDmitry Osipenko timing->rate = rate * 2 * 1000; 31396e5da7cSDmitry Osipenko 31496e5da7cSDmitry Osipenko dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n", 31596e5da7cSDmitry Osipenko __func__, node, timing->rate); 31696e5da7cSDmitry Osipenko 31796e5da7cSDmitry Osipenko return 0; 31896e5da7cSDmitry Osipenko } 31996e5da7cSDmitry Osipenko 32096e5da7cSDmitry Osipenko static int cmp_timings(const void *_a, const void *_b) 32196e5da7cSDmitry Osipenko { 32296e5da7cSDmitry Osipenko const struct emc_timing *a = _a; 32396e5da7cSDmitry Osipenko const struct emc_timing *b = _b; 32496e5da7cSDmitry Osipenko 32596e5da7cSDmitry Osipenko if (a->rate < b->rate) 32696e5da7cSDmitry Osipenko return -1; 32796e5da7cSDmitry Osipenko 32896e5da7cSDmitry Osipenko if (a->rate > b->rate) 32996e5da7cSDmitry Osipenko return 1; 33096e5da7cSDmitry Osipenko 33196e5da7cSDmitry Osipenko return 0; 33296e5da7cSDmitry Osipenko } 33396e5da7cSDmitry Osipenko 33496e5da7cSDmitry Osipenko static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc, 33596e5da7cSDmitry Osipenko struct device_node *node) 33696e5da7cSDmitry Osipenko { 33796e5da7cSDmitry Osipenko struct device_node *child; 33896e5da7cSDmitry Osipenko struct emc_timing *timing; 33996e5da7cSDmitry Osipenko int child_count; 34096e5da7cSDmitry Osipenko int err; 34196e5da7cSDmitry Osipenko 34296e5da7cSDmitry Osipenko child_count = of_get_child_count(node); 34396e5da7cSDmitry Osipenko if (!child_count) { 34496e5da7cSDmitry Osipenko dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node); 34596e5da7cSDmitry Osipenko return -EINVAL; 34696e5da7cSDmitry Osipenko } 34796e5da7cSDmitry Osipenko 34896e5da7cSDmitry Osipenko emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), 34996e5da7cSDmitry Osipenko GFP_KERNEL); 35096e5da7cSDmitry Osipenko if (!emc->timings) 35196e5da7cSDmitry Osipenko return -ENOMEM; 35296e5da7cSDmitry Osipenko 35396e5da7cSDmitry Osipenko emc->num_timings = child_count; 35496e5da7cSDmitry Osipenko timing = emc->timings; 35596e5da7cSDmitry Osipenko 35696e5da7cSDmitry Osipenko for_each_child_of_node(node, child) { 35796e5da7cSDmitry Osipenko err = load_one_timing_from_dt(emc, timing++, child); 35896e5da7cSDmitry Osipenko if (err) { 35996e5da7cSDmitry Osipenko of_node_put(child); 36096e5da7cSDmitry Osipenko return err; 36196e5da7cSDmitry Osipenko } 36296e5da7cSDmitry Osipenko } 36396e5da7cSDmitry Osipenko 36496e5da7cSDmitry Osipenko sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, 36596e5da7cSDmitry Osipenko NULL); 36696e5da7cSDmitry Osipenko 367f541efaaSDmitry Osipenko dev_info(emc->dev, 368f541efaaSDmitry Osipenko "got %u timings for RAM code %u (min %luMHz max %luMHz)\n", 369f541efaaSDmitry Osipenko emc->num_timings, 370f541efaaSDmitry Osipenko tegra_read_ram_code(), 371f541efaaSDmitry Osipenko emc->timings[0].rate / 1000000, 372f541efaaSDmitry Osipenko emc->timings[emc->num_timings - 1].rate / 1000000); 373f541efaaSDmitry Osipenko 37496e5da7cSDmitry Osipenko return 0; 37596e5da7cSDmitry Osipenko } 37696e5da7cSDmitry Osipenko 37796e5da7cSDmitry Osipenko static struct device_node * 37896e5da7cSDmitry Osipenko tegra_emc_find_node_by_ram_code(struct device *dev) 37996e5da7cSDmitry Osipenko { 38096e5da7cSDmitry Osipenko struct device_node *np; 38196e5da7cSDmitry Osipenko u32 value, ram_code; 38296e5da7cSDmitry Osipenko int err; 38396e5da7cSDmitry Osipenko 38496e5da7cSDmitry Osipenko if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code")) 38596e5da7cSDmitry Osipenko return of_node_get(dev->of_node); 38696e5da7cSDmitry Osipenko 38796e5da7cSDmitry Osipenko ram_code = tegra_read_ram_code(); 38896e5da7cSDmitry Osipenko 38996e5da7cSDmitry Osipenko for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np; 39096e5da7cSDmitry Osipenko np = of_find_node_by_name(np, "emc-tables")) { 39196e5da7cSDmitry Osipenko err = of_property_read_u32(np, "nvidia,ram-code", &value); 39296e5da7cSDmitry Osipenko if (err || value != ram_code) { 39396e5da7cSDmitry Osipenko of_node_put(np); 39496e5da7cSDmitry Osipenko continue; 39596e5da7cSDmitry Osipenko } 39696e5da7cSDmitry Osipenko 39796e5da7cSDmitry Osipenko return np; 39896e5da7cSDmitry Osipenko } 39996e5da7cSDmitry Osipenko 40096e5da7cSDmitry Osipenko dev_err(dev, "no memory timings for RAM code %u found in device tree\n", 40196e5da7cSDmitry Osipenko ram_code); 40296e5da7cSDmitry Osipenko 40396e5da7cSDmitry Osipenko return NULL; 40496e5da7cSDmitry Osipenko } 40596e5da7cSDmitry Osipenko 40696e5da7cSDmitry Osipenko static int emc_setup_hw(struct tegra_emc *emc) 40796e5da7cSDmitry Osipenko { 40896e5da7cSDmitry Osipenko u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT; 409c72396f9SDmitry Osipenko u32 emc_cfg, emc_dbg; 41096e5da7cSDmitry Osipenko 41196e5da7cSDmitry Osipenko emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); 41296e5da7cSDmitry Osipenko 41396e5da7cSDmitry Osipenko /* 41496e5da7cSDmitry Osipenko * Depending on a memory type, DRAM should enter either self-refresh 41596e5da7cSDmitry Osipenko * or power-down state on EMC clock change. 41696e5da7cSDmitry Osipenko */ 41796e5da7cSDmitry Osipenko if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) && 41896e5da7cSDmitry Osipenko !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) { 41996e5da7cSDmitry Osipenko dev_err(emc->dev, 42096e5da7cSDmitry Osipenko "bootloader didn't specify DRAM auto-suspend mode\n"); 42196e5da7cSDmitry Osipenko return -EINVAL; 42296e5da7cSDmitry Osipenko } 42396e5da7cSDmitry Osipenko 42496e5da7cSDmitry Osipenko /* enable EMC and CAR to handshake on PLL divider/source changes */ 42596e5da7cSDmitry Osipenko emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE; 42696e5da7cSDmitry Osipenko writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); 42796e5da7cSDmitry Osipenko 42896e5da7cSDmitry Osipenko /* initialize interrupt */ 42996e5da7cSDmitry Osipenko writel_relaxed(intmask, emc->regs + EMC_INTMASK); 43096e5da7cSDmitry Osipenko writel_relaxed(intmask, emc->regs + EMC_INTSTATUS); 43196e5da7cSDmitry Osipenko 432c72396f9SDmitry Osipenko /* ensure that unwanted debug features are disabled */ 433c72396f9SDmitry Osipenko emc_dbg = readl_relaxed(emc->regs + EMC_DBG); 434c72396f9SDmitry Osipenko emc_dbg |= EMC_DBG_CFG_PRIORITY; 435c72396f9SDmitry Osipenko emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY; 436c72396f9SDmitry Osipenko emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; 437c72396f9SDmitry Osipenko emc_dbg &= ~EMC_DBG_FORCE_UPDATE; 438c72396f9SDmitry Osipenko writel_relaxed(emc_dbg, emc->regs + EMC_DBG); 439c72396f9SDmitry Osipenko 44096e5da7cSDmitry Osipenko return 0; 44196e5da7cSDmitry Osipenko } 44296e5da7cSDmitry Osipenko 44377ab499dSDmitry Osipenko static long emc_round_rate(unsigned long rate, 44477ab499dSDmitry Osipenko unsigned long min_rate, 44577ab499dSDmitry Osipenko unsigned long max_rate, 44677ab499dSDmitry Osipenko void *arg) 44777ab499dSDmitry Osipenko { 44877ab499dSDmitry Osipenko struct emc_timing *timing = NULL; 44977ab499dSDmitry Osipenko struct tegra_emc *emc = arg; 45077ab499dSDmitry Osipenko unsigned int i; 45177ab499dSDmitry Osipenko 45277ab499dSDmitry Osipenko min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); 45377ab499dSDmitry Osipenko 45477ab499dSDmitry Osipenko for (i = 0; i < emc->num_timings; i++) { 45577ab499dSDmitry Osipenko if (emc->timings[i].rate < rate && i != emc->num_timings - 1) 45677ab499dSDmitry Osipenko continue; 45777ab499dSDmitry Osipenko 45877ab499dSDmitry Osipenko if (emc->timings[i].rate > max_rate) { 45977ab499dSDmitry Osipenko i = max(i, 1u) - 1; 46077ab499dSDmitry Osipenko 46177ab499dSDmitry Osipenko if (emc->timings[i].rate < min_rate) 46277ab499dSDmitry Osipenko break; 46377ab499dSDmitry Osipenko } 46477ab499dSDmitry Osipenko 46577ab499dSDmitry Osipenko if (emc->timings[i].rate < min_rate) 46677ab499dSDmitry Osipenko continue; 46777ab499dSDmitry Osipenko 46877ab499dSDmitry Osipenko timing = &emc->timings[i]; 46977ab499dSDmitry Osipenko break; 47077ab499dSDmitry Osipenko } 47177ab499dSDmitry Osipenko 47277ab499dSDmitry Osipenko if (!timing) { 47377ab499dSDmitry Osipenko dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n", 47477ab499dSDmitry Osipenko rate, min_rate, max_rate); 47577ab499dSDmitry Osipenko return -EINVAL; 47677ab499dSDmitry Osipenko } 47777ab499dSDmitry Osipenko 47877ab499dSDmitry Osipenko return timing->rate; 47977ab499dSDmitry Osipenko } 48077ab499dSDmitry Osipenko 48196e5da7cSDmitry Osipenko static int tegra_emc_probe(struct platform_device *pdev) 48296e5da7cSDmitry Osipenko { 48396e5da7cSDmitry Osipenko struct device_node *np; 48496e5da7cSDmitry Osipenko struct tegra_emc *emc; 48596e5da7cSDmitry Osipenko struct resource *res; 48696e5da7cSDmitry Osipenko int irq, err; 48796e5da7cSDmitry Osipenko 48896e5da7cSDmitry Osipenko /* driver has nothing to do in a case of memory timing absence */ 48996e5da7cSDmitry Osipenko if (of_get_child_count(pdev->dev.of_node) == 0) { 49096e5da7cSDmitry Osipenko dev_info(&pdev->dev, 49196e5da7cSDmitry Osipenko "EMC device tree node doesn't have memory timings\n"); 49296e5da7cSDmitry Osipenko return 0; 49396e5da7cSDmitry Osipenko } 49496e5da7cSDmitry Osipenko 49596e5da7cSDmitry Osipenko irq = platform_get_irq(pdev, 0); 49696e5da7cSDmitry Osipenko if (irq < 0) { 49796e5da7cSDmitry Osipenko dev_err(&pdev->dev, "interrupt not specified\n"); 49896e5da7cSDmitry Osipenko dev_err(&pdev->dev, "please update your device tree\n"); 49996e5da7cSDmitry Osipenko return irq; 50096e5da7cSDmitry Osipenko } 50196e5da7cSDmitry Osipenko 50296e5da7cSDmitry Osipenko np = tegra_emc_find_node_by_ram_code(&pdev->dev); 50396e5da7cSDmitry Osipenko if (!np) 50496e5da7cSDmitry Osipenko return -EINVAL; 50596e5da7cSDmitry Osipenko 50696e5da7cSDmitry Osipenko emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); 50796e5da7cSDmitry Osipenko if (!emc) { 50896e5da7cSDmitry Osipenko of_node_put(np); 50996e5da7cSDmitry Osipenko return -ENOMEM; 51096e5da7cSDmitry Osipenko } 51196e5da7cSDmitry Osipenko 51296e5da7cSDmitry Osipenko init_completion(&emc->clk_handshake_complete); 51396e5da7cSDmitry Osipenko emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; 51496e5da7cSDmitry Osipenko emc->dev = &pdev->dev; 51596e5da7cSDmitry Osipenko 51696e5da7cSDmitry Osipenko err = tegra_emc_load_timings_from_dt(emc, np); 51796e5da7cSDmitry Osipenko of_node_put(np); 51896e5da7cSDmitry Osipenko if (err) 51996e5da7cSDmitry Osipenko return err; 52096e5da7cSDmitry Osipenko 52196e5da7cSDmitry Osipenko res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 52296e5da7cSDmitry Osipenko emc->regs = devm_ioremap_resource(&pdev->dev, res); 52396e5da7cSDmitry Osipenko if (IS_ERR(emc->regs)) 52496e5da7cSDmitry Osipenko return PTR_ERR(emc->regs); 52596e5da7cSDmitry Osipenko 52696e5da7cSDmitry Osipenko err = emc_setup_hw(emc); 52796e5da7cSDmitry Osipenko if (err) 52896e5da7cSDmitry Osipenko return err; 52996e5da7cSDmitry Osipenko 53096e5da7cSDmitry Osipenko err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0, 53196e5da7cSDmitry Osipenko dev_name(&pdev->dev), emc); 53296e5da7cSDmitry Osipenko if (err) { 53396e5da7cSDmitry Osipenko dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err); 53496e5da7cSDmitry Osipenko return err; 53596e5da7cSDmitry Osipenko } 53696e5da7cSDmitry Osipenko 53777ab499dSDmitry Osipenko tegra20_clk_set_emc_round_callback(emc_round_rate, emc); 53877ab499dSDmitry Osipenko 53996e5da7cSDmitry Osipenko emc->clk = devm_clk_get(&pdev->dev, "emc"); 54096e5da7cSDmitry Osipenko if (IS_ERR(emc->clk)) { 54196e5da7cSDmitry Osipenko err = PTR_ERR(emc->clk); 54296e5da7cSDmitry Osipenko dev_err(&pdev->dev, "failed to get emc clock: %d\n", err); 54377ab499dSDmitry Osipenko goto unset_cb; 54496e5da7cSDmitry Osipenko } 54596e5da7cSDmitry Osipenko 54696e5da7cSDmitry Osipenko err = clk_notifier_register(emc->clk, &emc->clk_nb); 54796e5da7cSDmitry Osipenko if (err) { 54896e5da7cSDmitry Osipenko dev_err(&pdev->dev, "failed to register clk notifier: %d\n", 54996e5da7cSDmitry Osipenko err); 55077ab499dSDmitry Osipenko goto unset_cb; 55196e5da7cSDmitry Osipenko } 55296e5da7cSDmitry Osipenko 55396e5da7cSDmitry Osipenko return 0; 55477ab499dSDmitry Osipenko 55577ab499dSDmitry Osipenko unset_cb: 55677ab499dSDmitry Osipenko tegra20_clk_set_emc_round_callback(NULL, NULL); 55777ab499dSDmitry Osipenko 55877ab499dSDmitry Osipenko return err; 55996e5da7cSDmitry Osipenko } 56096e5da7cSDmitry Osipenko 56196e5da7cSDmitry Osipenko static const struct of_device_id tegra_emc_of_match[] = { 56296e5da7cSDmitry Osipenko { .compatible = "nvidia,tegra20-emc", }, 56396e5da7cSDmitry Osipenko {}, 56496e5da7cSDmitry Osipenko }; 56596e5da7cSDmitry Osipenko 56696e5da7cSDmitry Osipenko static struct platform_driver tegra_emc_driver = { 56796e5da7cSDmitry Osipenko .probe = tegra_emc_probe, 56896e5da7cSDmitry Osipenko .driver = { 56996e5da7cSDmitry Osipenko .name = "tegra20-emc", 57096e5da7cSDmitry Osipenko .of_match_table = tegra_emc_of_match, 57196e5da7cSDmitry Osipenko .suppress_bind_attrs = true, 57296e5da7cSDmitry Osipenko }, 57396e5da7cSDmitry Osipenko }; 57496e5da7cSDmitry Osipenko 57596e5da7cSDmitry Osipenko static int __init tegra_emc_init(void) 57696e5da7cSDmitry Osipenko { 57796e5da7cSDmitry Osipenko return platform_driver_register(&tegra_emc_driver); 57896e5da7cSDmitry Osipenko } 57996e5da7cSDmitry Osipenko subsys_initcall(tegra_emc_init); 580