196e5da7cSDmitry Osipenko // SPDX-License-Identifier: GPL-2.0 296e5da7cSDmitry Osipenko /* 396e5da7cSDmitry Osipenko * Tegra20 External Memory Controller driver 496e5da7cSDmitry Osipenko * 596e5da7cSDmitry Osipenko * Author: Dmitry Osipenko <digetx@gmail.com> 696e5da7cSDmitry Osipenko */ 796e5da7cSDmitry Osipenko 896e5da7cSDmitry Osipenko #include <linux/clk.h> 977ab499dSDmitry Osipenko #include <linux/clk/tegra.h> 1096e5da7cSDmitry Osipenko #include <linux/completion.h> 118209eefaSThierry Reding #include <linux/debugfs.h> 1296e5da7cSDmitry Osipenko #include <linux/err.h> 1396e5da7cSDmitry Osipenko #include <linux/interrupt.h> 14d039cf28SDmitry Osipenko #include <linux/io.h> 1596e5da7cSDmitry Osipenko #include <linux/kernel.h> 1696e5da7cSDmitry Osipenko #include <linux/module.h> 1796e5da7cSDmitry Osipenko #include <linux/of.h> 1896e5da7cSDmitry Osipenko #include <linux/platform_device.h> 1996e5da7cSDmitry Osipenko #include <linux/sort.h> 2096e5da7cSDmitry Osipenko #include <linux/types.h> 2196e5da7cSDmitry Osipenko 2296e5da7cSDmitry Osipenko #include <soc/tegra/fuse.h> 2396e5da7cSDmitry Osipenko 2496e5da7cSDmitry Osipenko #define EMC_INTSTATUS 0x000 2596e5da7cSDmitry Osipenko #define EMC_INTMASK 0x004 26c72396f9SDmitry Osipenko #define EMC_DBG 0x008 2796e5da7cSDmitry Osipenko #define EMC_TIMING_CONTROL 0x028 2896e5da7cSDmitry Osipenko #define EMC_RC 0x02c 2996e5da7cSDmitry Osipenko #define EMC_RFC 0x030 3096e5da7cSDmitry Osipenko #define EMC_RAS 0x034 3196e5da7cSDmitry Osipenko #define EMC_RP 0x038 3296e5da7cSDmitry Osipenko #define EMC_R2W 0x03c 3396e5da7cSDmitry Osipenko #define EMC_W2R 0x040 3496e5da7cSDmitry Osipenko #define EMC_R2P 0x044 3596e5da7cSDmitry Osipenko #define EMC_W2P 0x048 3696e5da7cSDmitry Osipenko #define EMC_RD_RCD 0x04c 3796e5da7cSDmitry Osipenko #define EMC_WR_RCD 0x050 3896e5da7cSDmitry Osipenko #define EMC_RRD 0x054 3996e5da7cSDmitry Osipenko #define EMC_REXT 0x058 4096e5da7cSDmitry Osipenko #define EMC_WDV 0x05c 4196e5da7cSDmitry Osipenko #define EMC_QUSE 0x060 4296e5da7cSDmitry Osipenko #define EMC_QRST 0x064 4396e5da7cSDmitry Osipenko #define EMC_QSAFE 0x068 4496e5da7cSDmitry Osipenko #define EMC_RDV 0x06c 4596e5da7cSDmitry Osipenko #define EMC_REFRESH 0x070 4696e5da7cSDmitry Osipenko #define EMC_BURST_REFRESH_NUM 0x074 4796e5da7cSDmitry Osipenko #define EMC_PDEX2WR 0x078 4896e5da7cSDmitry Osipenko #define EMC_PDEX2RD 0x07c 4996e5da7cSDmitry Osipenko #define EMC_PCHG2PDEN 0x080 5096e5da7cSDmitry Osipenko #define EMC_ACT2PDEN 0x084 5196e5da7cSDmitry Osipenko #define EMC_AR2PDEN 0x088 5296e5da7cSDmitry Osipenko #define EMC_RW2PDEN 0x08c 5396e5da7cSDmitry Osipenko #define EMC_TXSR 0x090 5496e5da7cSDmitry Osipenko #define EMC_TCKE 0x094 5596e5da7cSDmitry Osipenko #define EMC_TFAW 0x098 5696e5da7cSDmitry Osipenko #define EMC_TRPAB 0x09c 5796e5da7cSDmitry Osipenko #define EMC_TCLKSTABLE 0x0a0 5896e5da7cSDmitry Osipenko #define EMC_TCLKSTOP 0x0a4 5996e5da7cSDmitry Osipenko #define EMC_TREFBW 0x0a8 6096e5da7cSDmitry Osipenko #define EMC_QUSE_EXTRA 0x0ac 6196e5da7cSDmitry Osipenko #define EMC_ODT_WRITE 0x0b0 6296e5da7cSDmitry Osipenko #define EMC_ODT_READ 0x0b4 6396e5da7cSDmitry Osipenko #define EMC_FBIO_CFG5 0x104 6496e5da7cSDmitry Osipenko #define EMC_FBIO_CFG6 0x114 6596e5da7cSDmitry Osipenko #define EMC_AUTO_CAL_INTERVAL 0x2a8 6696e5da7cSDmitry Osipenko #define EMC_CFG_2 0x2b8 6796e5da7cSDmitry Osipenko #define EMC_CFG_DIG_DLL 0x2bc 6896e5da7cSDmitry Osipenko #define EMC_DLL_XFORM_DQS 0x2c0 6996e5da7cSDmitry Osipenko #define EMC_DLL_XFORM_QUSE 0x2c4 7096e5da7cSDmitry Osipenko #define EMC_ZCAL_REF_CNT 0x2e0 7196e5da7cSDmitry Osipenko #define EMC_ZCAL_WAIT_CNT 0x2e4 7296e5da7cSDmitry Osipenko #define EMC_CFG_CLKTRIM_0 0x2d0 7396e5da7cSDmitry Osipenko #define EMC_CFG_CLKTRIM_1 0x2d4 7496e5da7cSDmitry Osipenko #define EMC_CFG_CLKTRIM_2 0x2d8 7596e5da7cSDmitry Osipenko 7696e5da7cSDmitry Osipenko #define EMC_CLKCHANGE_REQ_ENABLE BIT(0) 7796e5da7cSDmitry Osipenko #define EMC_CLKCHANGE_PD_ENABLE BIT(1) 7896e5da7cSDmitry Osipenko #define EMC_CLKCHANGE_SR_ENABLE BIT(2) 7996e5da7cSDmitry Osipenko 8096e5da7cSDmitry Osipenko #define EMC_TIMING_UPDATE BIT(0) 8196e5da7cSDmitry Osipenko 8296e5da7cSDmitry Osipenko #define EMC_REFRESH_OVERFLOW_INT BIT(3) 8396e5da7cSDmitry Osipenko #define EMC_CLKCHANGE_COMPLETE_INT BIT(4) 8496e5da7cSDmitry Osipenko 85c72396f9SDmitry Osipenko #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0) 86c72396f9SDmitry Osipenko #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) 87c72396f9SDmitry Osipenko #define EMC_DBG_FORCE_UPDATE BIT(2) 88c72396f9SDmitry Osipenko #define EMC_DBG_READ_DQM_CTRL BIT(9) 89c72396f9SDmitry Osipenko #define EMC_DBG_CFG_PRIORITY BIT(24) 90c72396f9SDmitry Osipenko 9196e5da7cSDmitry Osipenko static const u16 emc_timing_registers[] = { 9296e5da7cSDmitry Osipenko EMC_RC, 9396e5da7cSDmitry Osipenko EMC_RFC, 9496e5da7cSDmitry Osipenko EMC_RAS, 9596e5da7cSDmitry Osipenko EMC_RP, 9696e5da7cSDmitry Osipenko EMC_R2W, 9796e5da7cSDmitry Osipenko EMC_W2R, 9896e5da7cSDmitry Osipenko EMC_R2P, 9996e5da7cSDmitry Osipenko EMC_W2P, 10096e5da7cSDmitry Osipenko EMC_RD_RCD, 10196e5da7cSDmitry Osipenko EMC_WR_RCD, 10296e5da7cSDmitry Osipenko EMC_RRD, 10396e5da7cSDmitry Osipenko EMC_REXT, 10496e5da7cSDmitry Osipenko EMC_WDV, 10596e5da7cSDmitry Osipenko EMC_QUSE, 10696e5da7cSDmitry Osipenko EMC_QRST, 10796e5da7cSDmitry Osipenko EMC_QSAFE, 10896e5da7cSDmitry Osipenko EMC_RDV, 10996e5da7cSDmitry Osipenko EMC_REFRESH, 11096e5da7cSDmitry Osipenko EMC_BURST_REFRESH_NUM, 11196e5da7cSDmitry Osipenko EMC_PDEX2WR, 11296e5da7cSDmitry Osipenko EMC_PDEX2RD, 11396e5da7cSDmitry Osipenko EMC_PCHG2PDEN, 11496e5da7cSDmitry Osipenko EMC_ACT2PDEN, 11596e5da7cSDmitry Osipenko EMC_AR2PDEN, 11696e5da7cSDmitry Osipenko EMC_RW2PDEN, 11796e5da7cSDmitry Osipenko EMC_TXSR, 11896e5da7cSDmitry Osipenko EMC_TCKE, 11996e5da7cSDmitry Osipenko EMC_TFAW, 12096e5da7cSDmitry Osipenko EMC_TRPAB, 12196e5da7cSDmitry Osipenko EMC_TCLKSTABLE, 12296e5da7cSDmitry Osipenko EMC_TCLKSTOP, 12396e5da7cSDmitry Osipenko EMC_TREFBW, 12496e5da7cSDmitry Osipenko EMC_QUSE_EXTRA, 12596e5da7cSDmitry Osipenko EMC_FBIO_CFG6, 12696e5da7cSDmitry Osipenko EMC_ODT_WRITE, 12796e5da7cSDmitry Osipenko EMC_ODT_READ, 12896e5da7cSDmitry Osipenko EMC_FBIO_CFG5, 12996e5da7cSDmitry Osipenko EMC_CFG_DIG_DLL, 13096e5da7cSDmitry Osipenko EMC_DLL_XFORM_DQS, 13196e5da7cSDmitry Osipenko EMC_DLL_XFORM_QUSE, 13296e5da7cSDmitry Osipenko EMC_ZCAL_REF_CNT, 13396e5da7cSDmitry Osipenko EMC_ZCAL_WAIT_CNT, 13496e5da7cSDmitry Osipenko EMC_AUTO_CAL_INTERVAL, 13596e5da7cSDmitry Osipenko EMC_CFG_CLKTRIM_0, 13696e5da7cSDmitry Osipenko EMC_CFG_CLKTRIM_1, 13796e5da7cSDmitry Osipenko EMC_CFG_CLKTRIM_2, 13896e5da7cSDmitry Osipenko }; 13996e5da7cSDmitry Osipenko 14096e5da7cSDmitry Osipenko struct emc_timing { 14196e5da7cSDmitry Osipenko unsigned long rate; 14296e5da7cSDmitry Osipenko u32 data[ARRAY_SIZE(emc_timing_registers)]; 14396e5da7cSDmitry Osipenko }; 14496e5da7cSDmitry Osipenko 14596e5da7cSDmitry Osipenko struct tegra_emc { 14696e5da7cSDmitry Osipenko struct device *dev; 14796e5da7cSDmitry Osipenko struct completion clk_handshake_complete; 14896e5da7cSDmitry Osipenko struct notifier_block clk_nb; 14996e5da7cSDmitry Osipenko struct clk *clk; 15096e5da7cSDmitry Osipenko void __iomem *regs; 15196e5da7cSDmitry Osipenko 15296e5da7cSDmitry Osipenko struct emc_timing *timings; 15396e5da7cSDmitry Osipenko unsigned int num_timings; 1548209eefaSThierry Reding 1558209eefaSThierry Reding struct { 1568209eefaSThierry Reding struct dentry *root; 1578209eefaSThierry Reding unsigned long min_rate; 1588209eefaSThierry Reding unsigned long max_rate; 1598209eefaSThierry Reding } debugfs; 16096e5da7cSDmitry Osipenko }; 16196e5da7cSDmitry Osipenko 16296e5da7cSDmitry Osipenko static irqreturn_t tegra_emc_isr(int irq, void *data) 16396e5da7cSDmitry Osipenko { 16496e5da7cSDmitry Osipenko struct tegra_emc *emc = data; 16596e5da7cSDmitry Osipenko u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT; 16696e5da7cSDmitry Osipenko u32 status; 16796e5da7cSDmitry Osipenko 16896e5da7cSDmitry Osipenko status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; 16996e5da7cSDmitry Osipenko if (!status) 17096e5da7cSDmitry Osipenko return IRQ_NONE; 17196e5da7cSDmitry Osipenko 17296e5da7cSDmitry Osipenko /* notify about EMC-CAR handshake completion */ 17396e5da7cSDmitry Osipenko if (status & EMC_CLKCHANGE_COMPLETE_INT) 17496e5da7cSDmitry Osipenko complete(&emc->clk_handshake_complete); 17596e5da7cSDmitry Osipenko 17696e5da7cSDmitry Osipenko /* notify about HW problem */ 17796e5da7cSDmitry Osipenko if (status & EMC_REFRESH_OVERFLOW_INT) 17896e5da7cSDmitry Osipenko dev_err_ratelimited(emc->dev, 17996e5da7cSDmitry Osipenko "refresh request overflow timeout\n"); 18096e5da7cSDmitry Osipenko 18196e5da7cSDmitry Osipenko /* clear interrupts */ 18296e5da7cSDmitry Osipenko writel_relaxed(status, emc->regs + EMC_INTSTATUS); 18396e5da7cSDmitry Osipenko 18496e5da7cSDmitry Osipenko return IRQ_HANDLED; 18596e5da7cSDmitry Osipenko } 18696e5da7cSDmitry Osipenko 18796e5da7cSDmitry Osipenko static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, 18896e5da7cSDmitry Osipenko unsigned long rate) 18996e5da7cSDmitry Osipenko { 19096e5da7cSDmitry Osipenko struct emc_timing *timing = NULL; 19196e5da7cSDmitry Osipenko unsigned int i; 19296e5da7cSDmitry Osipenko 19396e5da7cSDmitry Osipenko for (i = 0; i < emc->num_timings; i++) { 19496e5da7cSDmitry Osipenko if (emc->timings[i].rate >= rate) { 19596e5da7cSDmitry Osipenko timing = &emc->timings[i]; 19696e5da7cSDmitry Osipenko break; 19796e5da7cSDmitry Osipenko } 19896e5da7cSDmitry Osipenko } 19996e5da7cSDmitry Osipenko 20096e5da7cSDmitry Osipenko if (!timing) { 20196e5da7cSDmitry Osipenko dev_err(emc->dev, "no timing for rate %lu\n", rate); 20296e5da7cSDmitry Osipenko return NULL; 20396e5da7cSDmitry Osipenko } 20496e5da7cSDmitry Osipenko 20596e5da7cSDmitry Osipenko return timing; 20696e5da7cSDmitry Osipenko } 20796e5da7cSDmitry Osipenko 20896e5da7cSDmitry Osipenko static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) 20996e5da7cSDmitry Osipenko { 21096e5da7cSDmitry Osipenko struct emc_timing *timing = tegra_emc_find_timing(emc, rate); 21196e5da7cSDmitry Osipenko unsigned int i; 21296e5da7cSDmitry Osipenko 21396e5da7cSDmitry Osipenko if (!timing) 21496e5da7cSDmitry Osipenko return -EINVAL; 21596e5da7cSDmitry Osipenko 21696e5da7cSDmitry Osipenko dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", 21796e5da7cSDmitry Osipenko __func__, timing->rate, rate); 21896e5da7cSDmitry Osipenko 21996e5da7cSDmitry Osipenko /* program shadow registers */ 22096e5da7cSDmitry Osipenko for (i = 0; i < ARRAY_SIZE(timing->data); i++) 22196e5da7cSDmitry Osipenko writel_relaxed(timing->data[i], 22296e5da7cSDmitry Osipenko emc->regs + emc_timing_registers[i]); 22396e5da7cSDmitry Osipenko 22496e5da7cSDmitry Osipenko /* wait until programming has settled */ 22596e5da7cSDmitry Osipenko readl_relaxed(emc->regs + emc_timing_registers[i - 1]); 22696e5da7cSDmitry Osipenko 22796e5da7cSDmitry Osipenko reinit_completion(&emc->clk_handshake_complete); 22896e5da7cSDmitry Osipenko 22996e5da7cSDmitry Osipenko return 0; 23096e5da7cSDmitry Osipenko } 23196e5da7cSDmitry Osipenko 23296e5da7cSDmitry Osipenko static int emc_complete_timing_change(struct tegra_emc *emc, bool flush) 23396e5da7cSDmitry Osipenko { 23488c5bfecSDmitry Osipenko unsigned long timeout; 23596e5da7cSDmitry Osipenko 23696e5da7cSDmitry Osipenko dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush); 23796e5da7cSDmitry Osipenko 23896e5da7cSDmitry Osipenko if (flush) { 23996e5da7cSDmitry Osipenko /* manually initiate memory timing update */ 24096e5da7cSDmitry Osipenko writel_relaxed(EMC_TIMING_UPDATE, 24196e5da7cSDmitry Osipenko emc->regs + EMC_TIMING_CONTROL); 24296e5da7cSDmitry Osipenko return 0; 24396e5da7cSDmitry Osipenko } 24496e5da7cSDmitry Osipenko 24596e5da7cSDmitry Osipenko timeout = wait_for_completion_timeout(&emc->clk_handshake_complete, 246b56563d0SDmitry Osipenko msecs_to_jiffies(100)); 24796e5da7cSDmitry Osipenko if (timeout == 0) { 24896e5da7cSDmitry Osipenko dev_err(emc->dev, "EMC-CAR handshake failed\n"); 24996e5da7cSDmitry Osipenko return -EIO; 25096e5da7cSDmitry Osipenko } 25196e5da7cSDmitry Osipenko 25296e5da7cSDmitry Osipenko return 0; 25396e5da7cSDmitry Osipenko } 25496e5da7cSDmitry Osipenko 25596e5da7cSDmitry Osipenko static int tegra_emc_clk_change_notify(struct notifier_block *nb, 25696e5da7cSDmitry Osipenko unsigned long msg, void *data) 25796e5da7cSDmitry Osipenko { 25896e5da7cSDmitry Osipenko struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); 25996e5da7cSDmitry Osipenko struct clk_notifier_data *cnd = data; 26096e5da7cSDmitry Osipenko int err; 26196e5da7cSDmitry Osipenko 26296e5da7cSDmitry Osipenko switch (msg) { 26396e5da7cSDmitry Osipenko case PRE_RATE_CHANGE: 26496e5da7cSDmitry Osipenko err = emc_prepare_timing_change(emc, cnd->new_rate); 26596e5da7cSDmitry Osipenko break; 26696e5da7cSDmitry Osipenko 26796e5da7cSDmitry Osipenko case ABORT_RATE_CHANGE: 26896e5da7cSDmitry Osipenko err = emc_prepare_timing_change(emc, cnd->old_rate); 26996e5da7cSDmitry Osipenko if (err) 27096e5da7cSDmitry Osipenko break; 27196e5da7cSDmitry Osipenko 27296e5da7cSDmitry Osipenko err = emc_complete_timing_change(emc, true); 27396e5da7cSDmitry Osipenko break; 27496e5da7cSDmitry Osipenko 27596e5da7cSDmitry Osipenko case POST_RATE_CHANGE: 27696e5da7cSDmitry Osipenko err = emc_complete_timing_change(emc, false); 27796e5da7cSDmitry Osipenko break; 27896e5da7cSDmitry Osipenko 27996e5da7cSDmitry Osipenko default: 28096e5da7cSDmitry Osipenko return NOTIFY_DONE; 28196e5da7cSDmitry Osipenko } 28296e5da7cSDmitry Osipenko 28396e5da7cSDmitry Osipenko return notifier_from_errno(err); 28496e5da7cSDmitry Osipenko } 28596e5da7cSDmitry Osipenko 28696e5da7cSDmitry Osipenko static int load_one_timing_from_dt(struct tegra_emc *emc, 28796e5da7cSDmitry Osipenko struct emc_timing *timing, 28896e5da7cSDmitry Osipenko struct device_node *node) 28996e5da7cSDmitry Osipenko { 29096e5da7cSDmitry Osipenko u32 rate; 29196e5da7cSDmitry Osipenko int err; 29296e5da7cSDmitry Osipenko 29396e5da7cSDmitry Osipenko if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) { 29496e5da7cSDmitry Osipenko dev_err(emc->dev, "incompatible DT node: %pOF\n", node); 29596e5da7cSDmitry Osipenko return -EINVAL; 29696e5da7cSDmitry Osipenko } 29796e5da7cSDmitry Osipenko 29896e5da7cSDmitry Osipenko err = of_property_read_u32(node, "clock-frequency", &rate); 29996e5da7cSDmitry Osipenko if (err) { 30096e5da7cSDmitry Osipenko dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n", 30196e5da7cSDmitry Osipenko node, err); 30296e5da7cSDmitry Osipenko return err; 30396e5da7cSDmitry Osipenko } 30496e5da7cSDmitry Osipenko 30596e5da7cSDmitry Osipenko err = of_property_read_u32_array(node, "nvidia,emc-registers", 30696e5da7cSDmitry Osipenko timing->data, 30796e5da7cSDmitry Osipenko ARRAY_SIZE(emc_timing_registers)); 30896e5da7cSDmitry Osipenko if (err) { 30996e5da7cSDmitry Osipenko dev_err(emc->dev, 31096e5da7cSDmitry Osipenko "timing %pOF: failed to read emc timing data: %d\n", 31196e5da7cSDmitry Osipenko node, err); 31296e5da7cSDmitry Osipenko return err; 31396e5da7cSDmitry Osipenko } 31496e5da7cSDmitry Osipenko 31596e5da7cSDmitry Osipenko /* 31696e5da7cSDmitry Osipenko * The EMC clock rate is twice the bus rate, and the bus rate is 31796e5da7cSDmitry Osipenko * measured in kHz. 31896e5da7cSDmitry Osipenko */ 31996e5da7cSDmitry Osipenko timing->rate = rate * 2 * 1000; 32096e5da7cSDmitry Osipenko 32196e5da7cSDmitry Osipenko dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n", 32296e5da7cSDmitry Osipenko __func__, node, timing->rate); 32396e5da7cSDmitry Osipenko 32496e5da7cSDmitry Osipenko return 0; 32596e5da7cSDmitry Osipenko } 32696e5da7cSDmitry Osipenko 32796e5da7cSDmitry Osipenko static int cmp_timings(const void *_a, const void *_b) 32896e5da7cSDmitry Osipenko { 32996e5da7cSDmitry Osipenko const struct emc_timing *a = _a; 33096e5da7cSDmitry Osipenko const struct emc_timing *b = _b; 33196e5da7cSDmitry Osipenko 33296e5da7cSDmitry Osipenko if (a->rate < b->rate) 33396e5da7cSDmitry Osipenko return -1; 33496e5da7cSDmitry Osipenko 33596e5da7cSDmitry Osipenko if (a->rate > b->rate) 33696e5da7cSDmitry Osipenko return 1; 33796e5da7cSDmitry Osipenko 33896e5da7cSDmitry Osipenko return 0; 33996e5da7cSDmitry Osipenko } 34096e5da7cSDmitry Osipenko 34196e5da7cSDmitry Osipenko static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc, 34296e5da7cSDmitry Osipenko struct device_node *node) 34396e5da7cSDmitry Osipenko { 34496e5da7cSDmitry Osipenko struct device_node *child; 34596e5da7cSDmitry Osipenko struct emc_timing *timing; 34696e5da7cSDmitry Osipenko int child_count; 34796e5da7cSDmitry Osipenko int err; 34896e5da7cSDmitry Osipenko 34996e5da7cSDmitry Osipenko child_count = of_get_child_count(node); 35096e5da7cSDmitry Osipenko if (!child_count) { 35196e5da7cSDmitry Osipenko dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node); 35296e5da7cSDmitry Osipenko return -EINVAL; 35396e5da7cSDmitry Osipenko } 35496e5da7cSDmitry Osipenko 35596e5da7cSDmitry Osipenko emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), 35696e5da7cSDmitry Osipenko GFP_KERNEL); 35796e5da7cSDmitry Osipenko if (!emc->timings) 35896e5da7cSDmitry Osipenko return -ENOMEM; 35996e5da7cSDmitry Osipenko 36096e5da7cSDmitry Osipenko emc->num_timings = child_count; 36196e5da7cSDmitry Osipenko timing = emc->timings; 36296e5da7cSDmitry Osipenko 36396e5da7cSDmitry Osipenko for_each_child_of_node(node, child) { 36496e5da7cSDmitry Osipenko err = load_one_timing_from_dt(emc, timing++, child); 36596e5da7cSDmitry Osipenko if (err) { 36696e5da7cSDmitry Osipenko of_node_put(child); 36796e5da7cSDmitry Osipenko return err; 36896e5da7cSDmitry Osipenko } 36996e5da7cSDmitry Osipenko } 37096e5da7cSDmitry Osipenko 37196e5da7cSDmitry Osipenko sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, 37296e5da7cSDmitry Osipenko NULL); 37396e5da7cSDmitry Osipenko 374f541efaaSDmitry Osipenko dev_info(emc->dev, 375f541efaaSDmitry Osipenko "got %u timings for RAM code %u (min %luMHz max %luMHz)\n", 376f541efaaSDmitry Osipenko emc->num_timings, 377f541efaaSDmitry Osipenko tegra_read_ram_code(), 378f541efaaSDmitry Osipenko emc->timings[0].rate / 1000000, 379f541efaaSDmitry Osipenko emc->timings[emc->num_timings - 1].rate / 1000000); 380f541efaaSDmitry Osipenko 38196e5da7cSDmitry Osipenko return 0; 38296e5da7cSDmitry Osipenko } 38396e5da7cSDmitry Osipenko 38496e5da7cSDmitry Osipenko static struct device_node * 38596e5da7cSDmitry Osipenko tegra_emc_find_node_by_ram_code(struct device *dev) 38696e5da7cSDmitry Osipenko { 38796e5da7cSDmitry Osipenko struct device_node *np; 38896e5da7cSDmitry Osipenko u32 value, ram_code; 38996e5da7cSDmitry Osipenko int err; 39096e5da7cSDmitry Osipenko 39196e5da7cSDmitry Osipenko if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code")) 39296e5da7cSDmitry Osipenko return of_node_get(dev->of_node); 39396e5da7cSDmitry Osipenko 39496e5da7cSDmitry Osipenko ram_code = tegra_read_ram_code(); 39596e5da7cSDmitry Osipenko 39696e5da7cSDmitry Osipenko for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np; 39796e5da7cSDmitry Osipenko np = of_find_node_by_name(np, "emc-tables")) { 39896e5da7cSDmitry Osipenko err = of_property_read_u32(np, "nvidia,ram-code", &value); 39996e5da7cSDmitry Osipenko if (err || value != ram_code) { 40096e5da7cSDmitry Osipenko of_node_put(np); 40196e5da7cSDmitry Osipenko continue; 40296e5da7cSDmitry Osipenko } 40396e5da7cSDmitry Osipenko 40496e5da7cSDmitry Osipenko return np; 40596e5da7cSDmitry Osipenko } 40696e5da7cSDmitry Osipenko 40796e5da7cSDmitry Osipenko dev_err(dev, "no memory timings for RAM code %u found in device tree\n", 40896e5da7cSDmitry Osipenko ram_code); 40996e5da7cSDmitry Osipenko 41096e5da7cSDmitry Osipenko return NULL; 41196e5da7cSDmitry Osipenko } 41296e5da7cSDmitry Osipenko 41396e5da7cSDmitry Osipenko static int emc_setup_hw(struct tegra_emc *emc) 41496e5da7cSDmitry Osipenko { 41596e5da7cSDmitry Osipenko u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT; 416c72396f9SDmitry Osipenko u32 emc_cfg, emc_dbg; 41796e5da7cSDmitry Osipenko 41896e5da7cSDmitry Osipenko emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); 41996e5da7cSDmitry Osipenko 42096e5da7cSDmitry Osipenko /* 42196e5da7cSDmitry Osipenko * Depending on a memory type, DRAM should enter either self-refresh 42296e5da7cSDmitry Osipenko * or power-down state on EMC clock change. 42396e5da7cSDmitry Osipenko */ 42496e5da7cSDmitry Osipenko if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) && 42596e5da7cSDmitry Osipenko !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) { 42696e5da7cSDmitry Osipenko dev_err(emc->dev, 42796e5da7cSDmitry Osipenko "bootloader didn't specify DRAM auto-suspend mode\n"); 42896e5da7cSDmitry Osipenko return -EINVAL; 42996e5da7cSDmitry Osipenko } 43096e5da7cSDmitry Osipenko 43196e5da7cSDmitry Osipenko /* enable EMC and CAR to handshake on PLL divider/source changes */ 43296e5da7cSDmitry Osipenko emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE; 43396e5da7cSDmitry Osipenko writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); 43496e5da7cSDmitry Osipenko 43596e5da7cSDmitry Osipenko /* initialize interrupt */ 43696e5da7cSDmitry Osipenko writel_relaxed(intmask, emc->regs + EMC_INTMASK); 43796e5da7cSDmitry Osipenko writel_relaxed(intmask, emc->regs + EMC_INTSTATUS); 43896e5da7cSDmitry Osipenko 439c72396f9SDmitry Osipenko /* ensure that unwanted debug features are disabled */ 440c72396f9SDmitry Osipenko emc_dbg = readl_relaxed(emc->regs + EMC_DBG); 441c72396f9SDmitry Osipenko emc_dbg |= EMC_DBG_CFG_PRIORITY; 442c72396f9SDmitry Osipenko emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY; 443c72396f9SDmitry Osipenko emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; 444c72396f9SDmitry Osipenko emc_dbg &= ~EMC_DBG_FORCE_UPDATE; 445c72396f9SDmitry Osipenko writel_relaxed(emc_dbg, emc->regs + EMC_DBG); 446c72396f9SDmitry Osipenko 44796e5da7cSDmitry Osipenko return 0; 44896e5da7cSDmitry Osipenko } 44996e5da7cSDmitry Osipenko 45077ab499dSDmitry Osipenko static long emc_round_rate(unsigned long rate, 45177ab499dSDmitry Osipenko unsigned long min_rate, 45277ab499dSDmitry Osipenko unsigned long max_rate, 45377ab499dSDmitry Osipenko void *arg) 45477ab499dSDmitry Osipenko { 45577ab499dSDmitry Osipenko struct emc_timing *timing = NULL; 45677ab499dSDmitry Osipenko struct tegra_emc *emc = arg; 45777ab499dSDmitry Osipenko unsigned int i; 45877ab499dSDmitry Osipenko 45977ab499dSDmitry Osipenko min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); 46077ab499dSDmitry Osipenko 46177ab499dSDmitry Osipenko for (i = 0; i < emc->num_timings; i++) { 46277ab499dSDmitry Osipenko if (emc->timings[i].rate < rate && i != emc->num_timings - 1) 46377ab499dSDmitry Osipenko continue; 46477ab499dSDmitry Osipenko 46577ab499dSDmitry Osipenko if (emc->timings[i].rate > max_rate) { 46677ab499dSDmitry Osipenko i = max(i, 1u) - 1; 46777ab499dSDmitry Osipenko 46877ab499dSDmitry Osipenko if (emc->timings[i].rate < min_rate) 46977ab499dSDmitry Osipenko break; 47077ab499dSDmitry Osipenko } 47177ab499dSDmitry Osipenko 47277ab499dSDmitry Osipenko if (emc->timings[i].rate < min_rate) 47377ab499dSDmitry Osipenko continue; 47477ab499dSDmitry Osipenko 47577ab499dSDmitry Osipenko timing = &emc->timings[i]; 47677ab499dSDmitry Osipenko break; 47777ab499dSDmitry Osipenko } 47877ab499dSDmitry Osipenko 47977ab499dSDmitry Osipenko if (!timing) { 48077ab499dSDmitry Osipenko dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n", 48177ab499dSDmitry Osipenko rate, min_rate, max_rate); 48277ab499dSDmitry Osipenko return -EINVAL; 48377ab499dSDmitry Osipenko } 48477ab499dSDmitry Osipenko 48577ab499dSDmitry Osipenko return timing->rate; 48677ab499dSDmitry Osipenko } 48777ab499dSDmitry Osipenko 4888209eefaSThierry Reding /* 4898209eefaSThierry Reding * debugfs interface 4908209eefaSThierry Reding * 4918209eefaSThierry Reding * The memory controller driver exposes some files in debugfs that can be used 4928209eefaSThierry Reding * to control the EMC frequency. The top-level directory can be found here: 4938209eefaSThierry Reding * 4948209eefaSThierry Reding * /sys/kernel/debug/emc 4958209eefaSThierry Reding * 4968209eefaSThierry Reding * It contains the following files: 4978209eefaSThierry Reding * 4988209eefaSThierry Reding * - available_rates: This file contains a list of valid, space-separated 4998209eefaSThierry Reding * EMC frequencies. 5008209eefaSThierry Reding * 5018209eefaSThierry Reding * - min_rate: Writing a value to this file sets the given frequency as the 5028209eefaSThierry Reding * floor of the permitted range. If this is higher than the currently 5038209eefaSThierry Reding * configured EMC frequency, this will cause the frequency to be 5048209eefaSThierry Reding * increased so that it stays within the valid range. 5058209eefaSThierry Reding * 5068209eefaSThierry Reding * - max_rate: Similarily to the min_rate file, writing a value to this file 5078209eefaSThierry Reding * sets the given frequency as the ceiling of the permitted range. If 5088209eefaSThierry Reding * the value is lower than the currently configured EMC frequency, this 5098209eefaSThierry Reding * will cause the frequency to be decreased so that it stays within the 5108209eefaSThierry Reding * valid range. 5118209eefaSThierry Reding */ 5128209eefaSThierry Reding 5138209eefaSThierry Reding static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) 5148209eefaSThierry Reding { 5158209eefaSThierry Reding unsigned int i; 5168209eefaSThierry Reding 5178209eefaSThierry Reding for (i = 0; i < emc->num_timings; i++) 5188209eefaSThierry Reding if (rate == emc->timings[i].rate) 5198209eefaSThierry Reding return true; 5208209eefaSThierry Reding 5218209eefaSThierry Reding return false; 5228209eefaSThierry Reding } 5238209eefaSThierry Reding 5248209eefaSThierry Reding static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data) 5258209eefaSThierry Reding { 5268209eefaSThierry Reding struct tegra_emc *emc = s->private; 5278209eefaSThierry Reding const char *prefix = ""; 5288209eefaSThierry Reding unsigned int i; 5298209eefaSThierry Reding 5308209eefaSThierry Reding for (i = 0; i < emc->num_timings; i++) { 5318209eefaSThierry Reding seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); 5328209eefaSThierry Reding prefix = " "; 5338209eefaSThierry Reding } 5348209eefaSThierry Reding 5358209eefaSThierry Reding seq_puts(s, "\n"); 5368209eefaSThierry Reding 5378209eefaSThierry Reding return 0; 5388209eefaSThierry Reding } 5398209eefaSThierry Reding 5408209eefaSThierry Reding static int tegra_emc_debug_available_rates_open(struct inode *inode, 5418209eefaSThierry Reding struct file *file) 5428209eefaSThierry Reding { 5438209eefaSThierry Reding return single_open(file, tegra_emc_debug_available_rates_show, 5448209eefaSThierry Reding inode->i_private); 5458209eefaSThierry Reding } 5468209eefaSThierry Reding 5478209eefaSThierry Reding static const struct file_operations tegra_emc_debug_available_rates_fops = { 5488209eefaSThierry Reding .open = tegra_emc_debug_available_rates_open, 5498209eefaSThierry Reding .read = seq_read, 5508209eefaSThierry Reding .llseek = seq_lseek, 5518209eefaSThierry Reding .release = single_release, 5528209eefaSThierry Reding }; 5538209eefaSThierry Reding 5548209eefaSThierry Reding static int tegra_emc_debug_min_rate_get(void *data, u64 *rate) 5558209eefaSThierry Reding { 5568209eefaSThierry Reding struct tegra_emc *emc = data; 5578209eefaSThierry Reding 5588209eefaSThierry Reding *rate = emc->debugfs.min_rate; 5598209eefaSThierry Reding 5608209eefaSThierry Reding return 0; 5618209eefaSThierry Reding } 5628209eefaSThierry Reding 5638209eefaSThierry Reding static int tegra_emc_debug_min_rate_set(void *data, u64 rate) 5648209eefaSThierry Reding { 5658209eefaSThierry Reding struct tegra_emc *emc = data; 5668209eefaSThierry Reding int err; 5678209eefaSThierry Reding 5688209eefaSThierry Reding if (!tegra_emc_validate_rate(emc, rate)) 5698209eefaSThierry Reding return -EINVAL; 5708209eefaSThierry Reding 5718209eefaSThierry Reding err = clk_set_min_rate(emc->clk, rate); 5728209eefaSThierry Reding if (err < 0) 5738209eefaSThierry Reding return err; 5748209eefaSThierry Reding 5758209eefaSThierry Reding emc->debugfs.min_rate = rate; 5768209eefaSThierry Reding 5778209eefaSThierry Reding return 0; 5788209eefaSThierry Reding } 5798209eefaSThierry Reding 5808209eefaSThierry Reding DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_min_rate_fops, 5818209eefaSThierry Reding tegra_emc_debug_min_rate_get, 5828209eefaSThierry Reding tegra_emc_debug_min_rate_set, "%llu\n"); 5838209eefaSThierry Reding 5848209eefaSThierry Reding static int tegra_emc_debug_max_rate_get(void *data, u64 *rate) 5858209eefaSThierry Reding { 5868209eefaSThierry Reding struct tegra_emc *emc = data; 5878209eefaSThierry Reding 5888209eefaSThierry Reding *rate = emc->debugfs.max_rate; 5898209eefaSThierry Reding 5908209eefaSThierry Reding return 0; 5918209eefaSThierry Reding } 5928209eefaSThierry Reding 5938209eefaSThierry Reding static int tegra_emc_debug_max_rate_set(void *data, u64 rate) 5948209eefaSThierry Reding { 5958209eefaSThierry Reding struct tegra_emc *emc = data; 5968209eefaSThierry Reding int err; 5978209eefaSThierry Reding 5988209eefaSThierry Reding if (!tegra_emc_validate_rate(emc, rate)) 5998209eefaSThierry Reding return -EINVAL; 6008209eefaSThierry Reding 6018209eefaSThierry Reding err = clk_set_max_rate(emc->clk, rate); 6028209eefaSThierry Reding if (err < 0) 6038209eefaSThierry Reding return err; 6048209eefaSThierry Reding 6058209eefaSThierry Reding emc->debugfs.max_rate = rate; 6068209eefaSThierry Reding 6078209eefaSThierry Reding return 0; 6088209eefaSThierry Reding } 6098209eefaSThierry Reding 6108209eefaSThierry Reding DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_max_rate_fops, 6118209eefaSThierry Reding tegra_emc_debug_max_rate_get, 6128209eefaSThierry Reding tegra_emc_debug_max_rate_set, "%llu\n"); 6138209eefaSThierry Reding 6148209eefaSThierry Reding static void tegra_emc_debugfs_init(struct tegra_emc *emc) 6158209eefaSThierry Reding { 6168209eefaSThierry Reding struct device *dev = emc->dev; 6178209eefaSThierry Reding unsigned int i; 6188209eefaSThierry Reding int err; 6198209eefaSThierry Reding 6208209eefaSThierry Reding emc->debugfs.min_rate = ULONG_MAX; 6218209eefaSThierry Reding emc->debugfs.max_rate = 0; 6228209eefaSThierry Reding 6238209eefaSThierry Reding for (i = 0; i < emc->num_timings; i++) { 6248209eefaSThierry Reding if (emc->timings[i].rate < emc->debugfs.min_rate) 6258209eefaSThierry Reding emc->debugfs.min_rate = emc->timings[i].rate; 6268209eefaSThierry Reding 6278209eefaSThierry Reding if (emc->timings[i].rate > emc->debugfs.max_rate) 6288209eefaSThierry Reding emc->debugfs.max_rate = emc->timings[i].rate; 6298209eefaSThierry Reding } 6308209eefaSThierry Reding 6312243af41SDmitry Osipenko if (!emc->num_timings) { 6322243af41SDmitry Osipenko emc->debugfs.min_rate = clk_get_rate(emc->clk); 6332243af41SDmitry Osipenko emc->debugfs.max_rate = emc->debugfs.min_rate; 6342243af41SDmitry Osipenko } 6352243af41SDmitry Osipenko 6368209eefaSThierry Reding err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, 6378209eefaSThierry Reding emc->debugfs.max_rate); 6388209eefaSThierry Reding if (err < 0) { 6398209eefaSThierry Reding dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n", 6408209eefaSThierry Reding emc->debugfs.min_rate, emc->debugfs.max_rate, 6418209eefaSThierry Reding emc->clk); 6428209eefaSThierry Reding } 6438209eefaSThierry Reding 6448209eefaSThierry Reding emc->debugfs.root = debugfs_create_dir("emc", NULL); 6458209eefaSThierry Reding if (!emc->debugfs.root) { 6468209eefaSThierry Reding dev_err(emc->dev, "failed to create debugfs directory\n"); 6478209eefaSThierry Reding return; 6488209eefaSThierry Reding } 6498209eefaSThierry Reding 6506cc8823aSDmitry Osipenko debugfs_create_file("available_rates", 0444, emc->debugfs.root, 6518209eefaSThierry Reding emc, &tegra_emc_debug_available_rates_fops); 6526cc8823aSDmitry Osipenko debugfs_create_file("min_rate", 0644, emc->debugfs.root, 6538209eefaSThierry Reding emc, &tegra_emc_debug_min_rate_fops); 6546cc8823aSDmitry Osipenko debugfs_create_file("max_rate", 0644, emc->debugfs.root, 6558209eefaSThierry Reding emc, &tegra_emc_debug_max_rate_fops); 6568209eefaSThierry Reding } 6578209eefaSThierry Reding 65896e5da7cSDmitry Osipenko static int tegra_emc_probe(struct platform_device *pdev) 65996e5da7cSDmitry Osipenko { 66096e5da7cSDmitry Osipenko struct device_node *np; 66196e5da7cSDmitry Osipenko struct tegra_emc *emc; 66296e5da7cSDmitry Osipenko struct resource *res; 66396e5da7cSDmitry Osipenko int irq, err; 66496e5da7cSDmitry Osipenko 66596e5da7cSDmitry Osipenko /* driver has nothing to do in a case of memory timing absence */ 66696e5da7cSDmitry Osipenko if (of_get_child_count(pdev->dev.of_node) == 0) { 66796e5da7cSDmitry Osipenko dev_info(&pdev->dev, 66896e5da7cSDmitry Osipenko "EMC device tree node doesn't have memory timings\n"); 66996e5da7cSDmitry Osipenko return 0; 67096e5da7cSDmitry Osipenko } 67196e5da7cSDmitry Osipenko 67296e5da7cSDmitry Osipenko irq = platform_get_irq(pdev, 0); 67396e5da7cSDmitry Osipenko if (irq < 0) { 67496e5da7cSDmitry Osipenko dev_err(&pdev->dev, "interrupt not specified\n"); 67596e5da7cSDmitry Osipenko dev_err(&pdev->dev, "please update your device tree\n"); 67696e5da7cSDmitry Osipenko return irq; 67796e5da7cSDmitry Osipenko } 67896e5da7cSDmitry Osipenko 67996e5da7cSDmitry Osipenko np = tegra_emc_find_node_by_ram_code(&pdev->dev); 68096e5da7cSDmitry Osipenko if (!np) 68196e5da7cSDmitry Osipenko return -EINVAL; 68296e5da7cSDmitry Osipenko 68396e5da7cSDmitry Osipenko emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); 68496e5da7cSDmitry Osipenko if (!emc) { 68596e5da7cSDmitry Osipenko of_node_put(np); 68696e5da7cSDmitry Osipenko return -ENOMEM; 68796e5da7cSDmitry Osipenko } 68896e5da7cSDmitry Osipenko 68996e5da7cSDmitry Osipenko init_completion(&emc->clk_handshake_complete); 69096e5da7cSDmitry Osipenko emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; 69196e5da7cSDmitry Osipenko emc->dev = &pdev->dev; 69296e5da7cSDmitry Osipenko 69396e5da7cSDmitry Osipenko err = tegra_emc_load_timings_from_dt(emc, np); 69496e5da7cSDmitry Osipenko of_node_put(np); 69596e5da7cSDmitry Osipenko if (err) 69696e5da7cSDmitry Osipenko return err; 69796e5da7cSDmitry Osipenko 69896e5da7cSDmitry Osipenko res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 69996e5da7cSDmitry Osipenko emc->regs = devm_ioremap_resource(&pdev->dev, res); 70096e5da7cSDmitry Osipenko if (IS_ERR(emc->regs)) 70196e5da7cSDmitry Osipenko return PTR_ERR(emc->regs); 70296e5da7cSDmitry Osipenko 70396e5da7cSDmitry Osipenko err = emc_setup_hw(emc); 70496e5da7cSDmitry Osipenko if (err) 70596e5da7cSDmitry Osipenko return err; 70696e5da7cSDmitry Osipenko 70796e5da7cSDmitry Osipenko err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0, 70896e5da7cSDmitry Osipenko dev_name(&pdev->dev), emc); 70996e5da7cSDmitry Osipenko if (err) { 71096e5da7cSDmitry Osipenko dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err); 71196e5da7cSDmitry Osipenko return err; 71296e5da7cSDmitry Osipenko } 71396e5da7cSDmitry Osipenko 71477ab499dSDmitry Osipenko tegra20_clk_set_emc_round_callback(emc_round_rate, emc); 71577ab499dSDmitry Osipenko 71696e5da7cSDmitry Osipenko emc->clk = devm_clk_get(&pdev->dev, "emc"); 71796e5da7cSDmitry Osipenko if (IS_ERR(emc->clk)) { 71896e5da7cSDmitry Osipenko err = PTR_ERR(emc->clk); 71996e5da7cSDmitry Osipenko dev_err(&pdev->dev, "failed to get emc clock: %d\n", err); 72077ab499dSDmitry Osipenko goto unset_cb; 72196e5da7cSDmitry Osipenko } 72296e5da7cSDmitry Osipenko 72396e5da7cSDmitry Osipenko err = clk_notifier_register(emc->clk, &emc->clk_nb); 72496e5da7cSDmitry Osipenko if (err) { 72596e5da7cSDmitry Osipenko dev_err(&pdev->dev, "failed to register clk notifier: %d\n", 72696e5da7cSDmitry Osipenko err); 72777ab499dSDmitry Osipenko goto unset_cb; 72896e5da7cSDmitry Osipenko } 72996e5da7cSDmitry Osipenko 7308209eefaSThierry Reding platform_set_drvdata(pdev, emc); 7318209eefaSThierry Reding tegra_emc_debugfs_init(emc); 7328209eefaSThierry Reding 73396e5da7cSDmitry Osipenko return 0; 73477ab499dSDmitry Osipenko 73577ab499dSDmitry Osipenko unset_cb: 73677ab499dSDmitry Osipenko tegra20_clk_set_emc_round_callback(NULL, NULL); 73777ab499dSDmitry Osipenko 73877ab499dSDmitry Osipenko return err; 73996e5da7cSDmitry Osipenko } 74096e5da7cSDmitry Osipenko 74196e5da7cSDmitry Osipenko static const struct of_device_id tegra_emc_of_match[] = { 74296e5da7cSDmitry Osipenko { .compatible = "nvidia,tegra20-emc", }, 74396e5da7cSDmitry Osipenko {}, 74496e5da7cSDmitry Osipenko }; 74596e5da7cSDmitry Osipenko 74696e5da7cSDmitry Osipenko static struct platform_driver tegra_emc_driver = { 74796e5da7cSDmitry Osipenko .probe = tegra_emc_probe, 74896e5da7cSDmitry Osipenko .driver = { 74996e5da7cSDmitry Osipenko .name = "tegra20-emc", 75096e5da7cSDmitry Osipenko .of_match_table = tegra_emc_of_match, 75196e5da7cSDmitry Osipenko .suppress_bind_attrs = true, 75296e5da7cSDmitry Osipenko }, 75396e5da7cSDmitry Osipenko }; 75496e5da7cSDmitry Osipenko 75596e5da7cSDmitry Osipenko static int __init tegra_emc_init(void) 75696e5da7cSDmitry Osipenko { 75796e5da7cSDmitry Osipenko return platform_driver_register(&tegra_emc_driver); 75896e5da7cSDmitry Osipenko } 75996e5da7cSDmitry Osipenko subsys_initcall(tegra_emc_init); 760