xref: /openbmc/linux/drivers/memory/tegra/tegra186.c (revision 0022cec7) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2017-2021 NVIDIA CORPORATION.  All rights reserved.
4  */
5 
6 #include <linux/io.h>
7 #include <linux/iommu.h>
8 #include <linux/module.h>
9 #include <linux/mod_devicetable.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 
13 #include <soc/tegra/mc.h>
14 
15 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
16 #include <dt-bindings/memory/tegra186-mc.h>
17 #endif
18 
19 #include "mc.h"
20 
21 #define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0)
22 #define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16)
23 #define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8)
24 
25 static int tegra186_mc_probe(struct tegra_mc *mc)
26 {
27 	struct platform_device *pdev = to_platform_device(mc->dev);
28 	unsigned int i;
29 	char name[8];
30 	int err;
31 
32 	mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast");
33 	if (IS_ERR(mc->bcast_ch_regs)) {
34 		if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) {
35 			dev_warn(&pdev->dev,
36 				 "Broadcast channel is missing, please update your device-tree\n");
37 			mc->bcast_ch_regs = NULL;
38 			goto populate;
39 		}
40 
41 		return PTR_ERR(mc->bcast_ch_regs);
42 	}
43 
44 	mc->ch_regs = devm_kcalloc(mc->dev, mc->soc->num_channels, sizeof(*mc->ch_regs),
45 				   GFP_KERNEL);
46 	if (!mc->ch_regs)
47 		return -ENOMEM;
48 
49 	for (i = 0; i < mc->soc->num_channels; i++) {
50 		snprintf(name, sizeof(name), "ch%u", i);
51 
52 		mc->ch_regs[i] = devm_platform_ioremap_resource_byname(pdev, name);
53 		if (IS_ERR(mc->ch_regs[i]))
54 			return PTR_ERR(mc->ch_regs[i]);
55 	}
56 
57 populate:
58 	err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev);
59 	if (err < 0)
60 		return err;
61 
62 	return 0;
63 }
64 
65 static void tegra186_mc_remove(struct tegra_mc *mc)
66 {
67 	of_platform_depopulate(mc->dev);
68 }
69 
70 #if IS_ENABLED(CONFIG_IOMMU_API)
71 static void tegra186_mc_client_sid_override(struct tegra_mc *mc,
72 					    const struct tegra_mc_client *client,
73 					    unsigned int sid)
74 {
75 	u32 value, old;
76 
77 	value = readl(mc->regs + client->regs.sid.security);
78 	if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) {
79 		/*
80 		 * If the secure firmware has locked this down the override
81 		 * for this memory client, there's nothing we can do here.
82 		 */
83 		if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED)
84 			return;
85 
86 		/*
87 		 * Otherwise, try to set the override itself. Typically the
88 		 * secure firmware will never have set this configuration.
89 		 * Instead, it will either have disabled write access to
90 		 * this field, or it will already have set an explicit
91 		 * override itself.
92 		 */
93 		WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0);
94 
95 		value |= MC_SID_STREAMID_SECURITY_OVERRIDE;
96 		writel(value, mc->regs + client->regs.sid.security);
97 	}
98 
99 	value = readl(mc->regs + client->regs.sid.override);
100 	old = value & MC_SID_STREAMID_OVERRIDE_MASK;
101 
102 	if (old != sid) {
103 		dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old,
104 			client->name, sid);
105 		writel(sid, mc->regs + client->regs.sid.override);
106 	}
107 }
108 #endif
109 
110 static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
111 {
112 #if IS_ENABLED(CONFIG_IOMMU_API)
113 	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
114 	struct of_phandle_args args;
115 	unsigned int i, index = 0;
116 
117 	while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells",
118 					   index, &args)) {
119 		if (args.np == mc->dev->of_node && args.args_count != 0) {
120 			for (i = 0; i < mc->soc->num_clients; i++) {
121 				const struct tegra_mc_client *client = &mc->soc->clients[i];
122 
123 				if (client->id == args.args[0]) {
124 					u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK;
125 
126 					tegra186_mc_client_sid_override(mc, client, sid);
127 				}
128 			}
129 		}
130 
131 		index++;
132 	}
133 #endif
134 
135 	return 0;
136 }
137 
138 const struct tegra_mc_ops tegra186_mc_ops = {
139 	.probe = tegra186_mc_probe,
140 	.remove = tegra186_mc_remove,
141 	.probe_device = tegra186_mc_probe_device,
142 	.handle_irq = tegra30_mc_handle_irq,
143 };
144 
145 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
146 static const struct tegra_mc_client tegra186_mc_clients[] = {
147 	{
148 		.id = TEGRA186_MEMORY_CLIENT_PTCR,
149 		.name = "ptcr",
150 		.sid = TEGRA186_SID_PASSTHROUGH,
151 		.regs = {
152 			.sid = {
153 				.override = 0x000,
154 				.security = 0x004,
155 			},
156 		},
157 	}, {
158 		.id = TEGRA186_MEMORY_CLIENT_AFIR,
159 		.name = "afir",
160 		.sid = TEGRA186_SID_AFI,
161 		.regs = {
162 			.sid = {
163 				.override = 0x070,
164 				.security = 0x074,
165 			},
166 		},
167 	}, {
168 		.id = TEGRA186_MEMORY_CLIENT_HDAR,
169 		.name = "hdar",
170 		.sid = TEGRA186_SID_HDA,
171 		.regs = {
172 			.sid = {
173 				.override = 0x0a8,
174 				.security = 0x0ac,
175 			},
176 		},
177 	}, {
178 		.id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR,
179 		.name = "host1xdmar",
180 		.sid = TEGRA186_SID_HOST1X,
181 		.regs = {
182 			.sid = {
183 				.override = 0x0b0,
184 				.security = 0x0b4,
185 			},
186 		},
187 	}, {
188 		.id = TEGRA186_MEMORY_CLIENT_NVENCSRD,
189 		.name = "nvencsrd",
190 		.sid = TEGRA186_SID_NVENC,
191 		.regs = {
192 			.sid = {
193 				.override = 0x0e0,
194 				.security = 0x0e4,
195 			},
196 		},
197 	}, {
198 		.id = TEGRA186_MEMORY_CLIENT_SATAR,
199 		.name = "satar",
200 		.sid = TEGRA186_SID_SATA,
201 		.regs = {
202 			.sid = {
203 				.override = 0x0f8,
204 				.security = 0x0fc,
205 			},
206 		},
207 	}, {
208 		.id = TEGRA186_MEMORY_CLIENT_MPCORER,
209 		.name = "mpcorer",
210 		.sid = TEGRA186_SID_PASSTHROUGH,
211 		.regs = {
212 			.sid = {
213 				.override = 0x138,
214 				.security = 0x13c,
215 			},
216 		},
217 	}, {
218 		.id = TEGRA186_MEMORY_CLIENT_NVENCSWR,
219 		.name = "nvencswr",
220 		.sid = TEGRA186_SID_NVENC,
221 		.regs = {
222 			.sid = {
223 				.override = 0x158,
224 				.security = 0x15c,
225 			},
226 		},
227 	}, {
228 		.id = TEGRA186_MEMORY_CLIENT_AFIW,
229 		.name = "afiw",
230 		.sid = TEGRA186_SID_AFI,
231 		.regs = {
232 			.sid = {
233 				.override = 0x188,
234 				.security = 0x18c,
235 			},
236 		},
237 	}, {
238 		.id = TEGRA186_MEMORY_CLIENT_HDAW,
239 		.name = "hdaw",
240 		.sid = TEGRA186_SID_HDA,
241 		.regs = {
242 			.sid = {
243 				.override = 0x1a8,
244 				.security = 0x1ac,
245 			},
246 		},
247 	}, {
248 		.id = TEGRA186_MEMORY_CLIENT_MPCOREW,
249 		.name = "mpcorew",
250 		.sid = TEGRA186_SID_PASSTHROUGH,
251 		.regs = {
252 			.sid = {
253 				.override = 0x1c8,
254 				.security = 0x1cc,
255 			},
256 		},
257 	}, {
258 		.id = TEGRA186_MEMORY_CLIENT_SATAW,
259 		.name = "sataw",
260 		.sid = TEGRA186_SID_SATA,
261 		.regs = {
262 			.sid = {
263 				.override = 0x1e8,
264 				.security = 0x1ec,
265 			},
266 		},
267 	}, {
268 		.id = TEGRA186_MEMORY_CLIENT_ISPRA,
269 		.name = "ispra",
270 		.sid = TEGRA186_SID_ISP,
271 		.regs = {
272 			.sid = {
273 				.override = 0x220,
274 				.security = 0x224,
275 			},
276 		},
277 	}, {
278 		.id = TEGRA186_MEMORY_CLIENT_ISPWA,
279 		.name = "ispwa",
280 		.sid = TEGRA186_SID_ISP,
281 		.regs = {
282 			.sid = {
283 				.override = 0x230,
284 				.security = 0x234,
285 			},
286 		},
287 	}, {
288 		.id = TEGRA186_MEMORY_CLIENT_ISPWB,
289 		.name = "ispwb",
290 		.sid = TEGRA186_SID_ISP,
291 		.regs = {
292 			.sid = {
293 				.override = 0x238,
294 				.security = 0x23c,
295 			},
296 		},
297 	}, {
298 		.id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR,
299 		.name = "xusb_hostr",
300 		.sid = TEGRA186_SID_XUSB_HOST,
301 		.regs = {
302 			.sid = {
303 				.override = 0x250,
304 				.security = 0x254,
305 			},
306 		},
307 	}, {
308 		.id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW,
309 		.name = "xusb_hostw",
310 		.sid = TEGRA186_SID_XUSB_HOST,
311 		.regs = {
312 			.sid = {
313 				.override = 0x258,
314 				.security = 0x25c,
315 			},
316 		},
317 	}, {
318 		.id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR,
319 		.name = "xusb_devr",
320 		.sid = TEGRA186_SID_XUSB_DEV,
321 		.regs = {
322 			.sid = {
323 				.override = 0x260,
324 				.security = 0x264,
325 			},
326 		},
327 	}, {
328 		.id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW,
329 		.name = "xusb_devw",
330 		.sid = TEGRA186_SID_XUSB_DEV,
331 		.regs = {
332 			.sid = {
333 				.override = 0x268,
334 				.security = 0x26c,
335 			},
336 		},
337 	}, {
338 		.id = TEGRA186_MEMORY_CLIENT_TSECSRD,
339 		.name = "tsecsrd",
340 		.sid = TEGRA186_SID_TSEC,
341 		.regs = {
342 			.sid = {
343 				.override = 0x2a0,
344 				.security = 0x2a4,
345 			},
346 		},
347 	}, {
348 		.id = TEGRA186_MEMORY_CLIENT_TSECSWR,
349 		.name = "tsecswr",
350 		.sid = TEGRA186_SID_TSEC,
351 		.regs = {
352 			.sid = {
353 				.override = 0x2a8,
354 				.security = 0x2ac,
355 			},
356 		},
357 	}, {
358 		.id = TEGRA186_MEMORY_CLIENT_GPUSRD,
359 		.name = "gpusrd",
360 		.sid = TEGRA186_SID_GPU,
361 		.regs = {
362 			.sid = {
363 				.override = 0x2c0,
364 				.security = 0x2c4,
365 			},
366 		},
367 	}, {
368 		.id = TEGRA186_MEMORY_CLIENT_GPUSWR,
369 		.name = "gpuswr",
370 		.sid = TEGRA186_SID_GPU,
371 		.regs = {
372 			.sid = {
373 				.override = 0x2c8,
374 				.security = 0x2cc,
375 			},
376 		},
377 	}, {
378 		.id = TEGRA186_MEMORY_CLIENT_SDMMCRA,
379 		.name = "sdmmcra",
380 		.sid = TEGRA186_SID_SDMMC1,
381 		.regs = {
382 			.sid = {
383 				.override = 0x300,
384 				.security = 0x304,
385 			},
386 		},
387 	}, {
388 		.id = TEGRA186_MEMORY_CLIENT_SDMMCRAA,
389 		.name = "sdmmcraa",
390 		.sid = TEGRA186_SID_SDMMC2,
391 		.regs = {
392 			.sid = {
393 				.override = 0x308,
394 				.security = 0x30c,
395 			},
396 		},
397 	}, {
398 		.id = TEGRA186_MEMORY_CLIENT_SDMMCR,
399 		.name = "sdmmcr",
400 		.sid = TEGRA186_SID_SDMMC3,
401 		.regs = {
402 			.sid = {
403 				.override = 0x310,
404 				.security = 0x314,
405 			},
406 		},
407 	}, {
408 		.id = TEGRA186_MEMORY_CLIENT_SDMMCRAB,
409 		.name = "sdmmcrab",
410 		.sid = TEGRA186_SID_SDMMC4,
411 		.regs = {
412 			.sid = {
413 				.override = 0x318,
414 				.security = 0x31c,
415 			},
416 		},
417 	}, {
418 		.id = TEGRA186_MEMORY_CLIENT_SDMMCWA,
419 		.name = "sdmmcwa",
420 		.sid = TEGRA186_SID_SDMMC1,
421 		.regs = {
422 			.sid = {
423 				.override = 0x320,
424 				.security = 0x324,
425 			},
426 		},
427 	}, {
428 		.id = TEGRA186_MEMORY_CLIENT_SDMMCWAA,
429 		.name = "sdmmcwaa",
430 		.sid = TEGRA186_SID_SDMMC2,
431 		.regs = {
432 			.sid = {
433 				.override = 0x328,
434 				.security = 0x32c,
435 			},
436 		},
437 	}, {
438 		.id = TEGRA186_MEMORY_CLIENT_SDMMCW,
439 		.name = "sdmmcw",
440 		.sid = TEGRA186_SID_SDMMC3,
441 		.regs = {
442 			.sid = {
443 				.override = 0x330,
444 				.security = 0x334,
445 			},
446 		},
447 	}, {
448 		.id = TEGRA186_MEMORY_CLIENT_SDMMCWAB,
449 		.name = "sdmmcwab",
450 		.sid = TEGRA186_SID_SDMMC4,
451 		.regs = {
452 			.sid = {
453 				.override = 0x338,
454 				.security = 0x33c,
455 			},
456 		},
457 	}, {
458 		.id = TEGRA186_MEMORY_CLIENT_VICSRD,
459 		.name = "vicsrd",
460 		.sid = TEGRA186_SID_VIC,
461 		.regs = {
462 			.sid = {
463 				.override = 0x360,
464 				.security = 0x364,
465 			},
466 		},
467 	}, {
468 		.id = TEGRA186_MEMORY_CLIENT_VICSWR,
469 		.name = "vicswr",
470 		.sid = TEGRA186_SID_VIC,
471 		.regs = {
472 			.sid = {
473 				.override = 0x368,
474 				.security = 0x36c,
475 			},
476 		},
477 	}, {
478 		.id = TEGRA186_MEMORY_CLIENT_VIW,
479 		.name = "viw",
480 		.sid = TEGRA186_SID_VI,
481 		.regs = {
482 			.sid = {
483 				.override = 0x390,
484 				.security = 0x394,
485 			},
486 		},
487 	}, {
488 		.id = TEGRA186_MEMORY_CLIENT_NVDECSRD,
489 		.name = "nvdecsrd",
490 		.sid = TEGRA186_SID_NVDEC,
491 		.regs = {
492 			.sid = {
493 				.override = 0x3c0,
494 				.security = 0x3c4,
495 			},
496 		},
497 	}, {
498 		.id = TEGRA186_MEMORY_CLIENT_NVDECSWR,
499 		.name = "nvdecswr",
500 		.sid = TEGRA186_SID_NVDEC,
501 		.regs = {
502 			.sid = {
503 				.override = 0x3c8,
504 				.security = 0x3cc,
505 			},
506 		},
507 	}, {
508 		.id = TEGRA186_MEMORY_CLIENT_APER,
509 		.name = "aper",
510 		.sid = TEGRA186_SID_APE,
511 		.regs = {
512 			.sid = {
513 				.override = 0x3d0,
514 				.security = 0x3d4,
515 			},
516 		},
517 	}, {
518 		.id = TEGRA186_MEMORY_CLIENT_APEW,
519 		.name = "apew",
520 		.sid = TEGRA186_SID_APE,
521 		.regs = {
522 			.sid = {
523 				.override = 0x3d8,
524 				.security = 0x3dc,
525 			},
526 		},
527 	}, {
528 		.id = TEGRA186_MEMORY_CLIENT_NVJPGSRD,
529 		.name = "nvjpgsrd",
530 		.sid = TEGRA186_SID_NVJPG,
531 		.regs = {
532 			.sid = {
533 				.override = 0x3f0,
534 				.security = 0x3f4,
535 			},
536 		},
537 	}, {
538 		.id = TEGRA186_MEMORY_CLIENT_NVJPGSWR,
539 		.name = "nvjpgswr",
540 		.sid = TEGRA186_SID_NVJPG,
541 		.regs = {
542 			.sid = {
543 				.override = 0x3f8,
544 				.security = 0x3fc,
545 			},
546 		},
547 	}, {
548 		.id = TEGRA186_MEMORY_CLIENT_SESRD,
549 		.name = "sesrd",
550 		.sid = TEGRA186_SID_SE,
551 		.regs = {
552 			.sid = {
553 				.override = 0x400,
554 				.security = 0x404,
555 			},
556 		},
557 	}, {
558 		.id = TEGRA186_MEMORY_CLIENT_SESWR,
559 		.name = "seswr",
560 		.sid = TEGRA186_SID_SE,
561 		.regs = {
562 			.sid = {
563 				.override = 0x408,
564 				.security = 0x40c,
565 			},
566 		},
567 	}, {
568 		.id = TEGRA186_MEMORY_CLIENT_ETRR,
569 		.name = "etrr",
570 		.sid = TEGRA186_SID_ETR,
571 		.regs = {
572 			.sid = {
573 				.override = 0x420,
574 				.security = 0x424,
575 			},
576 		},
577 	}, {
578 		.id = TEGRA186_MEMORY_CLIENT_ETRW,
579 		.name = "etrw",
580 		.sid = TEGRA186_SID_ETR,
581 		.regs = {
582 			.sid = {
583 				.override = 0x428,
584 				.security = 0x42c,
585 			},
586 		},
587 	}, {
588 		.id = TEGRA186_MEMORY_CLIENT_TSECSRDB,
589 		.name = "tsecsrdb",
590 		.sid = TEGRA186_SID_TSECB,
591 		.regs = {
592 			.sid = {
593 				.override = 0x430,
594 				.security = 0x434,
595 			},
596 		},
597 	}, {
598 		.id = TEGRA186_MEMORY_CLIENT_TSECSWRB,
599 		.name = "tsecswrb",
600 		.sid = TEGRA186_SID_TSECB,
601 		.regs = {
602 			.sid = {
603 				.override = 0x438,
604 				.security = 0x43c,
605 			},
606 		},
607 	}, {
608 		.id = TEGRA186_MEMORY_CLIENT_GPUSRD2,
609 		.name = "gpusrd2",
610 		.sid = TEGRA186_SID_GPU,
611 		.regs = {
612 			.sid = {
613 				.override = 0x440,
614 				.security = 0x444,
615 			},
616 		},
617 	}, {
618 		.id = TEGRA186_MEMORY_CLIENT_GPUSWR2,
619 		.name = "gpuswr2",
620 		.sid = TEGRA186_SID_GPU,
621 		.regs = {
622 			.sid = {
623 				.override = 0x448,
624 				.security = 0x44c,
625 			},
626 		},
627 	}, {
628 		.id = TEGRA186_MEMORY_CLIENT_AXISR,
629 		.name = "axisr",
630 		.sid = TEGRA186_SID_GPCDMA_0,
631 		.regs = {
632 			.sid = {
633 				.override = 0x460,
634 				.security = 0x464,
635 			},
636 		},
637 	}, {
638 		.id = TEGRA186_MEMORY_CLIENT_AXISW,
639 		.name = "axisw",
640 		.sid = TEGRA186_SID_GPCDMA_0,
641 		.regs = {
642 			.sid = {
643 				.override = 0x468,
644 				.security = 0x46c,
645 			},
646 		},
647 	}, {
648 		.id = TEGRA186_MEMORY_CLIENT_EQOSR,
649 		.name = "eqosr",
650 		.sid = TEGRA186_SID_EQOS,
651 		.regs = {
652 			.sid = {
653 				.override = 0x470,
654 				.security = 0x474,
655 			},
656 		},
657 	}, {
658 		.id = TEGRA186_MEMORY_CLIENT_EQOSW,
659 		.name = "eqosw",
660 		.sid = TEGRA186_SID_EQOS,
661 		.regs = {
662 			.sid = {
663 				.override = 0x478,
664 				.security = 0x47c,
665 			},
666 		},
667 	}, {
668 		.id = TEGRA186_MEMORY_CLIENT_UFSHCR,
669 		.name = "ufshcr",
670 		.sid = TEGRA186_SID_UFSHC,
671 		.regs = {
672 			.sid = {
673 				.override = 0x480,
674 				.security = 0x484,
675 			},
676 		},
677 	}, {
678 		.id = TEGRA186_MEMORY_CLIENT_UFSHCW,
679 		.name = "ufshcw",
680 		.sid = TEGRA186_SID_UFSHC,
681 		.regs = {
682 			.sid = {
683 				.override = 0x488,
684 				.security = 0x48c,
685 			},
686 		},
687 	}, {
688 		.id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR,
689 		.name = "nvdisplayr",
690 		.sid = TEGRA186_SID_NVDISPLAY,
691 		.regs = {
692 			.sid = {
693 				.override = 0x490,
694 				.security = 0x494,
695 			},
696 		},
697 	}, {
698 		.id = TEGRA186_MEMORY_CLIENT_BPMPR,
699 		.name = "bpmpr",
700 		.sid = TEGRA186_SID_BPMP,
701 		.regs = {
702 			.sid = {
703 				.override = 0x498,
704 				.security = 0x49c,
705 			},
706 		},
707 	}, {
708 		.id = TEGRA186_MEMORY_CLIENT_BPMPW,
709 		.name = "bpmpw",
710 		.sid = TEGRA186_SID_BPMP,
711 		.regs = {
712 			.sid = {
713 				.override = 0x4a0,
714 				.security = 0x4a4,
715 			},
716 		},
717 	}, {
718 		.id = TEGRA186_MEMORY_CLIENT_BPMPDMAR,
719 		.name = "bpmpdmar",
720 		.sid = TEGRA186_SID_BPMP,
721 		.regs = {
722 			.sid = {
723 				.override = 0x4a8,
724 				.security = 0x4ac,
725 			},
726 		},
727 	}, {
728 		.id = TEGRA186_MEMORY_CLIENT_BPMPDMAW,
729 		.name = "bpmpdmaw",
730 		.sid = TEGRA186_SID_BPMP,
731 		.regs = {
732 			.sid = {
733 				.override = 0x4b0,
734 				.security = 0x4b4,
735 			},
736 		},
737 	}, {
738 		.id = TEGRA186_MEMORY_CLIENT_AONR,
739 		.name = "aonr",
740 		.sid = TEGRA186_SID_AON,
741 		.regs = {
742 			.sid = {
743 				.override = 0x4b8,
744 				.security = 0x4bc,
745 			},
746 		},
747 	}, {
748 		.id = TEGRA186_MEMORY_CLIENT_AONW,
749 		.name = "aonw",
750 		.sid = TEGRA186_SID_AON,
751 		.regs = {
752 			.sid = {
753 				.override = 0x4c0,
754 				.security = 0x4c4,
755 			},
756 		},
757 	}, {
758 		.id = TEGRA186_MEMORY_CLIENT_AONDMAR,
759 		.name = "aondmar",
760 		.sid = TEGRA186_SID_AON,
761 		.regs = {
762 			.sid = {
763 				.override = 0x4c8,
764 				.security = 0x4cc,
765 			},
766 		},
767 	}, {
768 		.id = TEGRA186_MEMORY_CLIENT_AONDMAW,
769 		.name = "aondmaw",
770 		.sid = TEGRA186_SID_AON,
771 		.regs = {
772 			.sid = {
773 				.override = 0x4d0,
774 				.security = 0x4d4,
775 			},
776 		},
777 	}, {
778 		.id = TEGRA186_MEMORY_CLIENT_SCER,
779 		.name = "scer",
780 		.sid = TEGRA186_SID_SCE,
781 		.regs = {
782 			.sid = {
783 				.override = 0x4d8,
784 				.security = 0x4dc,
785 			},
786 		},
787 	}, {
788 		.id = TEGRA186_MEMORY_CLIENT_SCEW,
789 		.name = "scew",
790 		.sid = TEGRA186_SID_SCE,
791 		.regs = {
792 			.sid = {
793 				.override = 0x4e0,
794 				.security = 0x4e4,
795 			},
796 		},
797 	}, {
798 		.id = TEGRA186_MEMORY_CLIENT_SCEDMAR,
799 		.name = "scedmar",
800 		.sid = TEGRA186_SID_SCE,
801 		.regs = {
802 			.sid = {
803 				.override = 0x4e8,
804 				.security = 0x4ec,
805 			},
806 		},
807 	}, {
808 		.id = TEGRA186_MEMORY_CLIENT_SCEDMAW,
809 		.name = "scedmaw",
810 		.sid = TEGRA186_SID_SCE,
811 		.regs = {
812 			.sid = {
813 				.override = 0x4f0,
814 				.security = 0x4f4,
815 			},
816 		},
817 	}, {
818 		.id = TEGRA186_MEMORY_CLIENT_APEDMAR,
819 		.name = "apedmar",
820 		.sid = TEGRA186_SID_APE,
821 		.regs = {
822 			.sid = {
823 				.override = 0x4f8,
824 				.security = 0x4fc,
825 			},
826 		},
827 	}, {
828 		.id = TEGRA186_MEMORY_CLIENT_APEDMAW,
829 		.name = "apedmaw",
830 		.sid = TEGRA186_SID_APE,
831 		.regs = {
832 			.sid = {
833 				.override = 0x500,
834 				.security = 0x504,
835 			},
836 		},
837 	}, {
838 		.id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1,
839 		.name = "nvdisplayr1",
840 		.sid = TEGRA186_SID_NVDISPLAY,
841 		.regs = {
842 			.sid = {
843 				.override = 0x508,
844 				.security = 0x50c,
845 			},
846 		},
847 	}, {
848 		.id = TEGRA186_MEMORY_CLIENT_VICSRD1,
849 		.name = "vicsrd1",
850 		.sid = TEGRA186_SID_VIC,
851 		.regs = {
852 			.sid = {
853 				.override = 0x510,
854 				.security = 0x514,
855 			},
856 		},
857 	}, {
858 		.id = TEGRA186_MEMORY_CLIENT_NVDECSRD1,
859 		.name = "nvdecsrd1",
860 		.sid = TEGRA186_SID_NVDEC,
861 		.regs = {
862 			.sid = {
863 				.override = 0x518,
864 				.security = 0x51c,
865 			},
866 		},
867 	},
868 };
869 
870 const struct tegra_mc_soc tegra186_mc_soc = {
871 	.num_clients = ARRAY_SIZE(tegra186_mc_clients),
872 	.clients = tegra186_mc_clients,
873 	.num_address_bits = 40,
874 	.num_channels = 4,
875 	.client_id_mask = 0xff,
876 	.intmask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
877 		   MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
878 		   MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
879 	.ops = &tegra186_mc_ops,
880 	.ch_intmask = 0x0000000f,
881 	.global_intstatus_channel_shift = 0,
882 };
883 #endif
884