1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2019 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/debugfs.h> 8 #include <linux/module.h> 9 #include <linux/mod_devicetable.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 13 #include <soc/tegra/bpmp.h> 14 #include "mc.h" 15 16 struct tegra186_emc_dvfs { 17 unsigned long latency; 18 unsigned long rate; 19 }; 20 21 struct tegra186_emc { 22 struct tegra_bpmp *bpmp; 23 struct device *dev; 24 struct clk *clk; 25 26 struct tegra186_emc_dvfs *dvfs; 27 unsigned int num_dvfs; 28 29 struct { 30 struct dentry *root; 31 unsigned long min_rate; 32 unsigned long max_rate; 33 } debugfs; 34 35 struct icc_provider provider; 36 }; 37 38 static inline struct tegra186_emc *to_tegra186_emc(struct icc_provider *provider) 39 { 40 return container_of(provider, struct tegra186_emc, provider); 41 } 42 43 /* 44 * debugfs interface 45 * 46 * The memory controller driver exposes some files in debugfs that can be used 47 * to control the EMC frequency. The top-level directory can be found here: 48 * 49 * /sys/kernel/debug/emc 50 * 51 * It contains the following files: 52 * 53 * - available_rates: This file contains a list of valid, space-separated 54 * EMC frequencies. 55 * 56 * - min_rate: Writing a value to this file sets the given frequency as the 57 * floor of the permitted range. If this is higher than the currently 58 * configured EMC frequency, this will cause the frequency to be 59 * increased so that it stays within the valid range. 60 * 61 * - max_rate: Similarily to the min_rate file, writing a value to this file 62 * sets the given frequency as the ceiling of the permitted range. If 63 * the value is lower than the currently configured EMC frequency, this 64 * will cause the frequency to be decreased so that it stays within the 65 * valid range. 66 */ 67 68 static bool tegra186_emc_validate_rate(struct tegra186_emc *emc, 69 unsigned long rate) 70 { 71 unsigned int i; 72 73 for (i = 0; i < emc->num_dvfs; i++) 74 if (rate == emc->dvfs[i].rate) 75 return true; 76 77 return false; 78 } 79 80 static int tegra186_emc_debug_available_rates_show(struct seq_file *s, 81 void *data) 82 { 83 struct tegra186_emc *emc = s->private; 84 const char *prefix = ""; 85 unsigned int i; 86 87 for (i = 0; i < emc->num_dvfs; i++) { 88 seq_printf(s, "%s%lu", prefix, emc->dvfs[i].rate); 89 prefix = " "; 90 } 91 92 seq_puts(s, "\n"); 93 94 return 0; 95 } 96 DEFINE_SHOW_ATTRIBUTE(tegra186_emc_debug_available_rates); 97 98 static int tegra186_emc_debug_min_rate_get(void *data, u64 *rate) 99 { 100 struct tegra186_emc *emc = data; 101 102 *rate = emc->debugfs.min_rate; 103 104 return 0; 105 } 106 107 static int tegra186_emc_debug_min_rate_set(void *data, u64 rate) 108 { 109 struct tegra186_emc *emc = data; 110 int err; 111 112 if (!tegra186_emc_validate_rate(emc, rate)) 113 return -EINVAL; 114 115 err = clk_set_min_rate(emc->clk, rate); 116 if (err < 0) 117 return err; 118 119 emc->debugfs.min_rate = rate; 120 121 return 0; 122 } 123 124 DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_min_rate_fops, 125 tegra186_emc_debug_min_rate_get, 126 tegra186_emc_debug_min_rate_set, "%llu\n"); 127 128 static int tegra186_emc_debug_max_rate_get(void *data, u64 *rate) 129 { 130 struct tegra186_emc *emc = data; 131 132 *rate = emc->debugfs.max_rate; 133 134 return 0; 135 } 136 137 static int tegra186_emc_debug_max_rate_set(void *data, u64 rate) 138 { 139 struct tegra186_emc *emc = data; 140 int err; 141 142 if (!tegra186_emc_validate_rate(emc, rate)) 143 return -EINVAL; 144 145 err = clk_set_max_rate(emc->clk, rate); 146 if (err < 0) 147 return err; 148 149 emc->debugfs.max_rate = rate; 150 151 return 0; 152 } 153 154 DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_max_rate_fops, 155 tegra186_emc_debug_max_rate_get, 156 tegra186_emc_debug_max_rate_set, "%llu\n"); 157 158 /* 159 * tegra_emc_icc_set_bw() - Set BW api for EMC provider 160 * @src: ICC node for External Memory Controller (EMC) 161 * @dst: ICC node for External Memory (DRAM) 162 * 163 * Do nothing here as info to BPMP-FW is now passed in the BW set function 164 * of the MC driver. BPMP-FW sets the final Freq based on the passed values. 165 */ 166 static int tegra_emc_icc_set_bw(struct icc_node *src, struct icc_node *dst) 167 { 168 return 0; 169 } 170 171 static struct icc_node * 172 tegra_emc_of_icc_xlate(struct of_phandle_args *spec, void *data) 173 { 174 struct icc_provider *provider = data; 175 struct icc_node *node; 176 177 /* External Memory is the only possible ICC route */ 178 list_for_each_entry(node, &provider->nodes, node_list) { 179 if (node->id != TEGRA_ICC_EMEM) 180 continue; 181 182 return node; 183 } 184 185 return ERR_PTR(-EPROBE_DEFER); 186 } 187 188 static int tegra_emc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak) 189 { 190 *avg = 0; 191 *peak = 0; 192 193 return 0; 194 } 195 196 static int tegra_emc_interconnect_init(struct tegra186_emc *emc) 197 { 198 struct tegra_mc *mc = dev_get_drvdata(emc->dev->parent); 199 const struct tegra_mc_soc *soc = mc->soc; 200 struct icc_node *node; 201 int err; 202 203 emc->provider.dev = emc->dev; 204 emc->provider.set = tegra_emc_icc_set_bw; 205 emc->provider.data = &emc->provider; 206 emc->provider.aggregate = soc->icc_ops->aggregate; 207 emc->provider.xlate = tegra_emc_of_icc_xlate; 208 emc->provider.get_bw = tegra_emc_icc_get_init_bw; 209 210 icc_provider_init(&emc->provider); 211 212 /* create External Memory Controller node */ 213 node = icc_node_create(TEGRA_ICC_EMC); 214 if (IS_ERR(node)) { 215 err = PTR_ERR(node); 216 goto err_msg; 217 } 218 219 node->name = "External Memory Controller"; 220 icc_node_add(node, &emc->provider); 221 222 /* link External Memory Controller to External Memory (DRAM) */ 223 err = icc_link_create(node, TEGRA_ICC_EMEM); 224 if (err) 225 goto remove_nodes; 226 227 /* create External Memory node */ 228 node = icc_node_create(TEGRA_ICC_EMEM); 229 if (IS_ERR(node)) { 230 err = PTR_ERR(node); 231 goto remove_nodes; 232 } 233 234 node->name = "External Memory (DRAM)"; 235 icc_node_add(node, &emc->provider); 236 237 err = icc_provider_register(&emc->provider); 238 if (err) 239 goto remove_nodes; 240 241 return 0; 242 243 remove_nodes: 244 icc_nodes_remove(&emc->provider); 245 err_msg: 246 dev_err(emc->dev, "failed to initialize ICC: %d\n", err); 247 248 return err; 249 } 250 251 static int tegra186_emc_probe(struct platform_device *pdev) 252 { 253 struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent); 254 struct mrq_emc_dvfs_latency_response response; 255 struct tegra_bpmp_message msg; 256 struct tegra186_emc *emc; 257 unsigned int i; 258 int err; 259 260 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); 261 if (!emc) 262 return -ENOMEM; 263 264 emc->bpmp = tegra_bpmp_get(&pdev->dev); 265 if (IS_ERR(emc->bpmp)) 266 return dev_err_probe(&pdev->dev, PTR_ERR(emc->bpmp), "failed to get BPMP\n"); 267 268 emc->clk = devm_clk_get(&pdev->dev, "emc"); 269 if (IS_ERR(emc->clk)) { 270 err = PTR_ERR(emc->clk); 271 dev_err(&pdev->dev, "failed to get EMC clock: %d\n", err); 272 goto put_bpmp; 273 } 274 275 platform_set_drvdata(pdev, emc); 276 emc->dev = &pdev->dev; 277 278 memset(&msg, 0, sizeof(msg)); 279 msg.mrq = MRQ_EMC_DVFS_LATENCY; 280 msg.tx.data = NULL; 281 msg.tx.size = 0; 282 msg.rx.data = &response; 283 msg.rx.size = sizeof(response); 284 285 err = tegra_bpmp_transfer(emc->bpmp, &msg); 286 if (err < 0) { 287 dev_err(&pdev->dev, "failed to EMC DVFS pairs: %d\n", err); 288 goto put_bpmp; 289 } 290 if (msg.rx.ret < 0) { 291 err = -EINVAL; 292 dev_err(&pdev->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret); 293 goto put_bpmp; 294 } 295 296 emc->debugfs.min_rate = ULONG_MAX; 297 emc->debugfs.max_rate = 0; 298 299 emc->num_dvfs = response.num_pairs; 300 301 emc->dvfs = devm_kmalloc_array(&pdev->dev, emc->num_dvfs, 302 sizeof(*emc->dvfs), GFP_KERNEL); 303 if (!emc->dvfs) { 304 err = -ENOMEM; 305 goto put_bpmp; 306 } 307 308 dev_dbg(&pdev->dev, "%u DVFS pairs:\n", emc->num_dvfs); 309 310 for (i = 0; i < emc->num_dvfs; i++) { 311 emc->dvfs[i].rate = response.pairs[i].freq * 1000; 312 emc->dvfs[i].latency = response.pairs[i].latency; 313 314 if (emc->dvfs[i].rate < emc->debugfs.min_rate) 315 emc->debugfs.min_rate = emc->dvfs[i].rate; 316 317 if (emc->dvfs[i].rate > emc->debugfs.max_rate) 318 emc->debugfs.max_rate = emc->dvfs[i].rate; 319 320 dev_dbg(&pdev->dev, " %2u: %lu Hz -> %lu us\n", i, 321 emc->dvfs[i].rate, emc->dvfs[i].latency); 322 } 323 324 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, 325 emc->debugfs.max_rate); 326 if (err < 0) { 327 dev_err(&pdev->dev, 328 "failed to set rate range [%lu-%lu] for %pC\n", 329 emc->debugfs.min_rate, emc->debugfs.max_rate, 330 emc->clk); 331 goto put_bpmp; 332 } 333 334 emc->debugfs.root = debugfs_create_dir("emc", NULL); 335 debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root, 336 emc, &tegra186_emc_debug_available_rates_fops); 337 debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, 338 emc, &tegra186_emc_debug_min_rate_fops); 339 debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, 340 emc, &tegra186_emc_debug_max_rate_fops); 341 342 if (mc && mc->soc->icc_ops) { 343 if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_BWMGR_INT)) { 344 mc->bwmgr_mrq_supported = true; 345 346 /* 347 * MC driver probe can't get BPMP reference as it gets probed 348 * earlier than BPMP. So, save the BPMP ref got from the EMC 349 * DT node in the mc->bpmp and use it in MC's icc_set hook. 350 */ 351 mc->bpmp = emc->bpmp; 352 barrier(); 353 } 354 355 /* 356 * Initialize the ICC even if BPMP-FW doesn't support 'MRQ_BWMGR_INT'. 357 * Use the flag 'mc->bwmgr_mrq_supported' within MC driver and return 358 * EINVAL instead of passing the request to BPMP-FW later when the BW 359 * request is made by client with 'icc_set_bw()' call. 360 */ 361 err = tegra_emc_interconnect_init(emc); 362 if (err) { 363 mc->bpmp = NULL; 364 goto put_bpmp; 365 } 366 } 367 368 return 0; 369 370 put_bpmp: 371 tegra_bpmp_put(emc->bpmp); 372 return err; 373 } 374 375 static int tegra186_emc_remove(struct platform_device *pdev) 376 { 377 struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent); 378 struct tegra186_emc *emc = platform_get_drvdata(pdev); 379 380 debugfs_remove_recursive(emc->debugfs.root); 381 382 mc->bpmp = NULL; 383 tegra_bpmp_put(emc->bpmp); 384 385 return 0; 386 } 387 388 static const struct of_device_id tegra186_emc_of_match[] = { 389 #if defined(CONFIG_ARCH_TEGRA_186_SOC) 390 { .compatible = "nvidia,tegra186-emc" }, 391 #endif 392 #if defined(CONFIG_ARCH_TEGRA_194_SOC) 393 { .compatible = "nvidia,tegra194-emc" }, 394 #endif 395 #if defined(CONFIG_ARCH_TEGRA_234_SOC) 396 { .compatible = "nvidia,tegra234-emc" }, 397 #endif 398 { /* sentinel */ } 399 }; 400 MODULE_DEVICE_TABLE(of, tegra186_emc_of_match); 401 402 static struct platform_driver tegra186_emc_driver = { 403 .driver = { 404 .name = "tegra186-emc", 405 .of_match_table = tegra186_emc_of_match, 406 .suppress_bind_attrs = true, 407 .sync_state = icc_sync_state, 408 }, 409 .probe = tegra186_emc_probe, 410 .remove = tegra186_emc_remove, 411 }; 412 module_platform_driver(tegra186_emc_driver); 413 414 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 415 MODULE_DESCRIPTION("NVIDIA Tegra186 External Memory Controller driver"); 416