xref: /openbmc/linux/drivers/memory/tegra/tegra124.c (revision e2f1cf25) 
1 /*
2  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 
9 #include <linux/of.h>
10 #include <linux/mm.h>
11 
12 #include <asm/cacheflush.h>
13 
14 #include <dt-bindings/memory/tegra124-mc.h>
15 
16 #include "mc.h"
17 
18 #define MC_EMEM_ARB_CFG				0x90
19 #define MC_EMEM_ARB_OUTSTANDING_REQ		0x94
20 #define MC_EMEM_ARB_TIMING_RCD			0x98
21 #define MC_EMEM_ARB_TIMING_RP			0x9c
22 #define MC_EMEM_ARB_TIMING_RC			0xa0
23 #define MC_EMEM_ARB_TIMING_RAS			0xa4
24 #define MC_EMEM_ARB_TIMING_FAW			0xa8
25 #define MC_EMEM_ARB_TIMING_RRD			0xac
26 #define MC_EMEM_ARB_TIMING_RAP2PRE		0xb0
27 #define MC_EMEM_ARB_TIMING_WAP2PRE		0xb4
28 #define MC_EMEM_ARB_TIMING_R2R			0xb8
29 #define MC_EMEM_ARB_TIMING_W2W			0xbc
30 #define MC_EMEM_ARB_TIMING_R2W			0xc0
31 #define MC_EMEM_ARB_TIMING_W2R			0xc4
32 #define MC_EMEM_ARB_DA_TURNS			0xd0
33 #define MC_EMEM_ARB_DA_COVERS			0xd4
34 #define MC_EMEM_ARB_MISC0			0xd8
35 #define MC_EMEM_ARB_MISC1			0xdc
36 #define MC_EMEM_ARB_RING1_THROTTLE		0xe0
37 
38 static const unsigned long tegra124_mc_emem_regs[] = {
39 	MC_EMEM_ARB_CFG,
40 	MC_EMEM_ARB_OUTSTANDING_REQ,
41 	MC_EMEM_ARB_TIMING_RCD,
42 	MC_EMEM_ARB_TIMING_RP,
43 	MC_EMEM_ARB_TIMING_RC,
44 	MC_EMEM_ARB_TIMING_RAS,
45 	MC_EMEM_ARB_TIMING_FAW,
46 	MC_EMEM_ARB_TIMING_RRD,
47 	MC_EMEM_ARB_TIMING_RAP2PRE,
48 	MC_EMEM_ARB_TIMING_WAP2PRE,
49 	MC_EMEM_ARB_TIMING_R2R,
50 	MC_EMEM_ARB_TIMING_W2W,
51 	MC_EMEM_ARB_TIMING_R2W,
52 	MC_EMEM_ARB_TIMING_W2R,
53 	MC_EMEM_ARB_DA_TURNS,
54 	MC_EMEM_ARB_DA_COVERS,
55 	MC_EMEM_ARB_MISC0,
56 	MC_EMEM_ARB_MISC1,
57 	MC_EMEM_ARB_RING1_THROTTLE
58 };
59 
60 static const struct tegra_mc_client tegra124_mc_clients[] = {
61 	{
62 		.id = 0x00,
63 		.name = "ptcr",
64 		.swgroup = TEGRA_SWGROUP_PTC,
65 	}, {
66 		.id = 0x01,
67 		.name = "display0a",
68 		.swgroup = TEGRA_SWGROUP_DC,
69 		.smmu = {
70 			.reg = 0x228,
71 			.bit = 1,
72 		},
73 		.la = {
74 			.reg = 0x2e8,
75 			.shift = 0,
76 			.mask = 0xff,
77 			.def = 0xc2,
78 		},
79 	}, {
80 		.id = 0x02,
81 		.name = "display0ab",
82 		.swgroup = TEGRA_SWGROUP_DCB,
83 		.smmu = {
84 			.reg = 0x228,
85 			.bit = 2,
86 		},
87 		.la = {
88 			.reg = 0x2f4,
89 			.shift = 0,
90 			.mask = 0xff,
91 			.def = 0xc6,
92 		},
93 	}, {
94 		.id = 0x03,
95 		.name = "display0b",
96 		.swgroup = TEGRA_SWGROUP_DC,
97 		.smmu = {
98 			.reg = 0x228,
99 			.bit = 3,
100 		},
101 		.la = {
102 			.reg = 0x2e8,
103 			.shift = 16,
104 			.mask = 0xff,
105 			.def = 0x50,
106 		},
107 	}, {
108 		.id = 0x04,
109 		.name = "display0bb",
110 		.swgroup = TEGRA_SWGROUP_DCB,
111 		.smmu = {
112 			.reg = 0x228,
113 			.bit = 4,
114 		},
115 		.la = {
116 			.reg = 0x2f4,
117 			.shift = 16,
118 			.mask = 0xff,
119 			.def = 0x50,
120 		},
121 	}, {
122 		.id = 0x05,
123 		.name = "display0c",
124 		.swgroup = TEGRA_SWGROUP_DC,
125 		.smmu = {
126 			.reg = 0x228,
127 			.bit = 5,
128 		},
129 		.la = {
130 			.reg = 0x2ec,
131 			.shift = 0,
132 			.mask = 0xff,
133 			.def = 0x50,
134 		},
135 	}, {
136 		.id = 0x06,
137 		.name = "display0cb",
138 		.swgroup = TEGRA_SWGROUP_DCB,
139 		.smmu = {
140 			.reg = 0x228,
141 			.bit = 6,
142 		},
143 		.la = {
144 			.reg = 0x2f8,
145 			.shift = 0,
146 			.mask = 0xff,
147 			.def = 0x50,
148 		},
149 	}, {
150 		.id = 0x0e,
151 		.name = "afir",
152 		.swgroup = TEGRA_SWGROUP_AFI,
153 		.smmu = {
154 			.reg = 0x228,
155 			.bit = 14,
156 		},
157 		.la = {
158 			.reg = 0x2e0,
159 			.shift = 0,
160 			.mask = 0xff,
161 			.def = 0x13,
162 		},
163 	}, {
164 		.id = 0x0f,
165 		.name = "avpcarm7r",
166 		.swgroup = TEGRA_SWGROUP_AVPC,
167 		.smmu = {
168 			.reg = 0x228,
169 			.bit = 15,
170 		},
171 		.la = {
172 			.reg = 0x2e4,
173 			.shift = 0,
174 			.mask = 0xff,
175 			.def = 0x04,
176 		},
177 	}, {
178 		.id = 0x10,
179 		.name = "displayhc",
180 		.swgroup = TEGRA_SWGROUP_DC,
181 		.smmu = {
182 			.reg = 0x228,
183 			.bit = 16,
184 		},
185 		.la = {
186 			.reg = 0x2f0,
187 			.shift = 0,
188 			.mask = 0xff,
189 			.def = 0x50,
190 		},
191 	}, {
192 		.id = 0x11,
193 		.name = "displayhcb",
194 		.swgroup = TEGRA_SWGROUP_DCB,
195 		.smmu = {
196 			.reg = 0x228,
197 			.bit = 17,
198 		},
199 		.la = {
200 			.reg = 0x2fc,
201 			.shift = 0,
202 			.mask = 0xff,
203 			.def = 0x50,
204 		},
205 	}, {
206 		.id = 0x15,
207 		.name = "hdar",
208 		.swgroup = TEGRA_SWGROUP_HDA,
209 		.smmu = {
210 			.reg = 0x228,
211 			.bit = 21,
212 		},
213 		.la = {
214 			.reg = 0x318,
215 			.shift = 0,
216 			.mask = 0xff,
217 			.def = 0x24,
218 		},
219 	}, {
220 		.id = 0x16,
221 		.name = "host1xdmar",
222 		.swgroup = TEGRA_SWGROUP_HC,
223 		.smmu = {
224 			.reg = 0x228,
225 			.bit = 22,
226 		},
227 		.la = {
228 			.reg = 0x310,
229 			.shift = 0,
230 			.mask = 0xff,
231 			.def = 0x1e,
232 		},
233 	}, {
234 		.id = 0x17,
235 		.name = "host1xr",
236 		.swgroup = TEGRA_SWGROUP_HC,
237 		.smmu = {
238 			.reg = 0x228,
239 			.bit = 23,
240 		},
241 		.la = {
242 			.reg = 0x310,
243 			.shift = 16,
244 			.mask = 0xff,
245 			.def = 0x50,
246 		},
247 	}, {
248 		.id = 0x1c,
249 		.name = "msencsrd",
250 		.swgroup = TEGRA_SWGROUP_MSENC,
251 		.smmu = {
252 			.reg = 0x228,
253 			.bit = 28,
254 		},
255 		.la = {
256 			.reg = 0x328,
257 			.shift = 0,
258 			.mask = 0xff,
259 			.def = 0x23,
260 		},
261 	}, {
262 		.id = 0x1d,
263 		.name = "ppcsahbdmar",
264 		.swgroup = TEGRA_SWGROUP_PPCS,
265 		.smmu = {
266 			.reg = 0x228,
267 			.bit = 29,
268 		},
269 		.la = {
270 			.reg = 0x344,
271 			.shift = 0,
272 			.mask = 0xff,
273 			.def = 0x49,
274 		},
275 	}, {
276 		.id = 0x1e,
277 		.name = "ppcsahbslvr",
278 		.swgroup = TEGRA_SWGROUP_PPCS,
279 		.smmu = {
280 			.reg = 0x228,
281 			.bit = 30,
282 		},
283 		.la = {
284 			.reg = 0x344,
285 			.shift = 16,
286 			.mask = 0xff,
287 			.def = 0x1a,
288 		},
289 	}, {
290 		.id = 0x1f,
291 		.name = "satar",
292 		.swgroup = TEGRA_SWGROUP_SATA,
293 		.smmu = {
294 			.reg = 0x228,
295 			.bit = 31,
296 		},
297 		.la = {
298 			.reg = 0x350,
299 			.shift = 0,
300 			.mask = 0xff,
301 			.def = 0x65,
302 		},
303 	}, {
304 		.id = 0x22,
305 		.name = "vdebsevr",
306 		.swgroup = TEGRA_SWGROUP_VDE,
307 		.smmu = {
308 			.reg = 0x22c,
309 			.bit = 2,
310 		},
311 		.la = {
312 			.reg = 0x354,
313 			.shift = 0,
314 			.mask = 0xff,
315 			.def = 0x4f,
316 		},
317 	}, {
318 		.id = 0x23,
319 		.name = "vdember",
320 		.swgroup = TEGRA_SWGROUP_VDE,
321 		.smmu = {
322 			.reg = 0x22c,
323 			.bit = 3,
324 		},
325 		.la = {
326 			.reg = 0x354,
327 			.shift = 16,
328 			.mask = 0xff,
329 			.def = 0x3d,
330 		},
331 	}, {
332 		.id = 0x24,
333 		.name = "vdemcer",
334 		.swgroup = TEGRA_SWGROUP_VDE,
335 		.smmu = {
336 			.reg = 0x22c,
337 			.bit = 4,
338 		},
339 		.la = {
340 			.reg = 0x358,
341 			.shift = 0,
342 			.mask = 0xff,
343 			.def = 0x66,
344 		},
345 	}, {
346 		.id = 0x25,
347 		.name = "vdetper",
348 		.swgroup = TEGRA_SWGROUP_VDE,
349 		.smmu = {
350 			.reg = 0x22c,
351 			.bit = 5,
352 		},
353 		.la = {
354 			.reg = 0x358,
355 			.shift = 16,
356 			.mask = 0xff,
357 			.def = 0xa5,
358 		},
359 	}, {
360 		.id = 0x26,
361 		.name = "mpcorelpr",
362 		.swgroup = TEGRA_SWGROUP_MPCORELP,
363 		.la = {
364 			.reg = 0x324,
365 			.shift = 0,
366 			.mask = 0xff,
367 			.def = 0x04,
368 		},
369 	}, {
370 		.id = 0x27,
371 		.name = "mpcorer",
372 		.swgroup = TEGRA_SWGROUP_MPCORE,
373 		.la = {
374 			.reg = 0x320,
375 			.shift = 0,
376 			.mask = 0xff,
377 			.def = 0x04,
378 		},
379 	}, {
380 		.id = 0x2b,
381 		.name = "msencswr",
382 		.swgroup = TEGRA_SWGROUP_MSENC,
383 		.smmu = {
384 			.reg = 0x22c,
385 			.bit = 11,
386 		},
387 		.la = {
388 			.reg = 0x328,
389 			.shift = 16,
390 			.mask = 0xff,
391 			.def = 0x80,
392 		},
393 	}, {
394 		.id = 0x31,
395 		.name = "afiw",
396 		.swgroup = TEGRA_SWGROUP_AFI,
397 		.smmu = {
398 			.reg = 0x22c,
399 			.bit = 17,
400 		},
401 		.la = {
402 			.reg = 0x2e0,
403 			.shift = 16,
404 			.mask = 0xff,
405 			.def = 0x80,
406 		},
407 	}, {
408 		.id = 0x32,
409 		.name = "avpcarm7w",
410 		.swgroup = TEGRA_SWGROUP_AVPC,
411 		.smmu = {
412 			.reg = 0x22c,
413 			.bit = 18,
414 		},
415 		.la = {
416 			.reg = 0x2e4,
417 			.shift = 16,
418 			.mask = 0xff,
419 			.def = 0x80,
420 		},
421 	}, {
422 		.id = 0x35,
423 		.name = "hdaw",
424 		.swgroup = TEGRA_SWGROUP_HDA,
425 		.smmu = {
426 			.reg = 0x22c,
427 			.bit = 21,
428 		},
429 		.la = {
430 			.reg = 0x318,
431 			.shift = 16,
432 			.mask = 0xff,
433 			.def = 0x80,
434 		},
435 	}, {
436 		.id = 0x36,
437 		.name = "host1xw",
438 		.swgroup = TEGRA_SWGROUP_HC,
439 		.smmu = {
440 			.reg = 0x22c,
441 			.bit = 22,
442 		},
443 		.la = {
444 			.reg = 0x314,
445 			.shift = 0,
446 			.mask = 0xff,
447 			.def = 0x80,
448 		},
449 	}, {
450 		.id = 0x38,
451 		.name = "mpcorelpw",
452 		.swgroup = TEGRA_SWGROUP_MPCORELP,
453 		.la = {
454 			.reg = 0x324,
455 			.shift = 16,
456 			.mask = 0xff,
457 			.def = 0x80,
458 		},
459 	}, {
460 		.id = 0x39,
461 		.name = "mpcorew",
462 		.swgroup = TEGRA_SWGROUP_MPCORE,
463 		.la = {
464 			.reg = 0x320,
465 			.shift = 16,
466 			.mask = 0xff,
467 			.def = 0x80,
468 		},
469 	}, {
470 		.id = 0x3b,
471 		.name = "ppcsahbdmaw",
472 		.swgroup = TEGRA_SWGROUP_PPCS,
473 		.smmu = {
474 			.reg = 0x22c,
475 			.bit = 27,
476 		},
477 		.la = {
478 			.reg = 0x348,
479 			.shift = 0,
480 			.mask = 0xff,
481 			.def = 0x80,
482 		},
483 	}, {
484 		.id = 0x3c,
485 		.name = "ppcsahbslvw",
486 		.swgroup = TEGRA_SWGROUP_PPCS,
487 		.smmu = {
488 			.reg = 0x22c,
489 			.bit = 28,
490 		},
491 		.la = {
492 			.reg = 0x348,
493 			.shift = 16,
494 			.mask = 0xff,
495 			.def = 0x80,
496 		},
497 	}, {
498 		.id = 0x3d,
499 		.name = "sataw",
500 		.swgroup = TEGRA_SWGROUP_SATA,
501 		.smmu = {
502 			.reg = 0x22c,
503 			.bit = 29,
504 		},
505 		.la = {
506 			.reg = 0x350,
507 			.shift = 16,
508 			.mask = 0xff,
509 			.def = 0x65,
510 		},
511 	}, {
512 		.id = 0x3e,
513 		.name = "vdebsevw",
514 		.swgroup = TEGRA_SWGROUP_VDE,
515 		.smmu = {
516 			.reg = 0x22c,
517 			.bit = 30,
518 		},
519 		.la = {
520 			.reg = 0x35c,
521 			.shift = 0,
522 			.mask = 0xff,
523 			.def = 0x80,
524 		},
525 	}, {
526 		.id = 0x3f,
527 		.name = "vdedbgw",
528 		.swgroup = TEGRA_SWGROUP_VDE,
529 		.smmu = {
530 			.reg = 0x22c,
531 			.bit = 31,
532 		},
533 		.la = {
534 			.reg = 0x35c,
535 			.shift = 16,
536 			.mask = 0xff,
537 			.def = 0x80,
538 		},
539 	}, {
540 		.id = 0x40,
541 		.name = "vdembew",
542 		.swgroup = TEGRA_SWGROUP_VDE,
543 		.smmu = {
544 			.reg = 0x230,
545 			.bit = 0,
546 		},
547 		.la = {
548 			.reg = 0x360,
549 			.shift = 0,
550 			.mask = 0xff,
551 			.def = 0x80,
552 		},
553 	}, {
554 		.id = 0x41,
555 		.name = "vdetpmw",
556 		.swgroup = TEGRA_SWGROUP_VDE,
557 		.smmu = {
558 			.reg = 0x230,
559 			.bit = 1,
560 		},
561 		.la = {
562 			.reg = 0x360,
563 			.shift = 16,
564 			.mask = 0xff,
565 			.def = 0x80,
566 		},
567 	}, {
568 		.id = 0x44,
569 		.name = "ispra",
570 		.swgroup = TEGRA_SWGROUP_ISP2,
571 		.smmu = {
572 			.reg = 0x230,
573 			.bit = 4,
574 		},
575 		.la = {
576 			.reg = 0x370,
577 			.shift = 0,
578 			.mask = 0xff,
579 			.def = 0x18,
580 		},
581 	}, {
582 		.id = 0x46,
583 		.name = "ispwa",
584 		.swgroup = TEGRA_SWGROUP_ISP2,
585 		.smmu = {
586 			.reg = 0x230,
587 			.bit = 6,
588 		},
589 		.la = {
590 			.reg = 0x374,
591 			.shift = 0,
592 			.mask = 0xff,
593 			.def = 0x80,
594 		},
595 	}, {
596 		.id = 0x47,
597 		.name = "ispwb",
598 		.swgroup = TEGRA_SWGROUP_ISP2,
599 		.smmu = {
600 			.reg = 0x230,
601 			.bit = 7,
602 		},
603 		.la = {
604 			.reg = 0x374,
605 			.shift = 16,
606 			.mask = 0xff,
607 			.def = 0x80,
608 		},
609 	}, {
610 		.id = 0x4a,
611 		.name = "xusb_hostr",
612 		.swgroup = TEGRA_SWGROUP_XUSB_HOST,
613 		.smmu = {
614 			.reg = 0x230,
615 			.bit = 10,
616 		},
617 		.la = {
618 			.reg = 0x37c,
619 			.shift = 0,
620 			.mask = 0xff,
621 			.def = 0x39,
622 		},
623 	}, {
624 		.id = 0x4b,
625 		.name = "xusb_hostw",
626 		.swgroup = TEGRA_SWGROUP_XUSB_HOST,
627 		.smmu = {
628 			.reg = 0x230,
629 			.bit = 11,
630 		},
631 		.la = {
632 			.reg = 0x37c,
633 			.shift = 16,
634 			.mask = 0xff,
635 			.def = 0x80,
636 		},
637 	}, {
638 		.id = 0x4c,
639 		.name = "xusb_devr",
640 		.swgroup = TEGRA_SWGROUP_XUSB_DEV,
641 		.smmu = {
642 			.reg = 0x230,
643 			.bit = 12,
644 		},
645 		.la = {
646 			.reg = 0x380,
647 			.shift = 0,
648 			.mask = 0xff,
649 			.def = 0x39,
650 		},
651 	}, {
652 		.id = 0x4d,
653 		.name = "xusb_devw",
654 		.swgroup = TEGRA_SWGROUP_XUSB_DEV,
655 		.smmu = {
656 			.reg = 0x230,
657 			.bit = 13,
658 		},
659 		.la = {
660 			.reg = 0x380,
661 			.shift = 16,
662 			.mask = 0xff,
663 			.def = 0x80,
664 		},
665 	}, {
666 		.id = 0x4e,
667 		.name = "isprab",
668 		.swgroup = TEGRA_SWGROUP_ISP2B,
669 		.smmu = {
670 			.reg = 0x230,
671 			.bit = 14,
672 		},
673 		.la = {
674 			.reg = 0x384,
675 			.shift = 0,
676 			.mask = 0xff,
677 			.def = 0x18,
678 		},
679 	}, {
680 		.id = 0x50,
681 		.name = "ispwab",
682 		.swgroup = TEGRA_SWGROUP_ISP2B,
683 		.smmu = {
684 			.reg = 0x230,
685 			.bit = 16,
686 		},
687 		.la = {
688 			.reg = 0x388,
689 			.shift = 0,
690 			.mask = 0xff,
691 			.def = 0x80,
692 		},
693 	}, {
694 		.id = 0x51,
695 		.name = "ispwbb",
696 		.swgroup = TEGRA_SWGROUP_ISP2B,
697 		.smmu = {
698 			.reg = 0x230,
699 			.bit = 17,
700 		},
701 		.la = {
702 			.reg = 0x388,
703 			.shift = 16,
704 			.mask = 0xff,
705 			.def = 0x80,
706 		},
707 	}, {
708 		.id = 0x54,
709 		.name = "tsecsrd",
710 		.swgroup = TEGRA_SWGROUP_TSEC,
711 		.smmu = {
712 			.reg = 0x230,
713 			.bit = 20,
714 		},
715 		.la = {
716 			.reg = 0x390,
717 			.shift = 0,
718 			.mask = 0xff,
719 			.def = 0x9b,
720 		},
721 	}, {
722 		.id = 0x55,
723 		.name = "tsecswr",
724 		.swgroup = TEGRA_SWGROUP_TSEC,
725 		.smmu = {
726 			.reg = 0x230,
727 			.bit = 21,
728 		},
729 		.la = {
730 			.reg = 0x390,
731 			.shift = 16,
732 			.mask = 0xff,
733 			.def = 0x80,
734 		},
735 	}, {
736 		.id = 0x56,
737 		.name = "a9avpscr",
738 		.swgroup = TEGRA_SWGROUP_A9AVP,
739 		.smmu = {
740 			.reg = 0x230,
741 			.bit = 22,
742 		},
743 		.la = {
744 			.reg = 0x3a4,
745 			.shift = 0,
746 			.mask = 0xff,
747 			.def = 0x04,
748 		},
749 	}, {
750 		.id = 0x57,
751 		.name = "a9avpscw",
752 		.swgroup = TEGRA_SWGROUP_A9AVP,
753 		.smmu = {
754 			.reg = 0x230,
755 			.bit = 23,
756 		},
757 		.la = {
758 			.reg = 0x3a4,
759 			.shift = 16,
760 			.mask = 0xff,
761 			.def = 0x80,
762 		},
763 	}, {
764 		.id = 0x58,
765 		.name = "gpusrd",
766 		.swgroup = TEGRA_SWGROUP_GPU,
767 		.smmu = {
768 			/* read-only */
769 			.reg = 0x230,
770 			.bit = 24,
771 		},
772 		.la = {
773 			.reg = 0x3c8,
774 			.shift = 0,
775 			.mask = 0xff,
776 			.def = 0x1a,
777 		},
778 	}, {
779 		.id = 0x59,
780 		.name = "gpuswr",
781 		.swgroup = TEGRA_SWGROUP_GPU,
782 		.smmu = {
783 			/* read-only */
784 			.reg = 0x230,
785 			.bit = 25,
786 		},
787 		.la = {
788 			.reg = 0x3c8,
789 			.shift = 16,
790 			.mask = 0xff,
791 			.def = 0x80,
792 		},
793 	}, {
794 		.id = 0x5a,
795 		.name = "displayt",
796 		.swgroup = TEGRA_SWGROUP_DC,
797 		.smmu = {
798 			.reg = 0x230,
799 			.bit = 26,
800 		},
801 		.la = {
802 			.reg = 0x2f0,
803 			.shift = 16,
804 			.mask = 0xff,
805 			.def = 0x50,
806 		},
807 	}, {
808 		.id = 0x60,
809 		.name = "sdmmcra",
810 		.swgroup = TEGRA_SWGROUP_SDMMC1A,
811 		.smmu = {
812 			.reg = 0x234,
813 			.bit = 0,
814 		},
815 		.la = {
816 			.reg = 0x3b8,
817 			.shift = 0,
818 			.mask = 0xff,
819 			.def = 0x49,
820 		},
821 	}, {
822 		.id = 0x61,
823 		.name = "sdmmcraa",
824 		.swgroup = TEGRA_SWGROUP_SDMMC2A,
825 		.smmu = {
826 			.reg = 0x234,
827 			.bit = 1,
828 		},
829 		.la = {
830 			.reg = 0x3bc,
831 			.shift = 0,
832 			.mask = 0xff,
833 			.def = 0x49,
834 		},
835 	}, {
836 		.id = 0x62,
837 		.name = "sdmmcr",
838 		.swgroup = TEGRA_SWGROUP_SDMMC3A,
839 		.smmu = {
840 			.reg = 0x234,
841 			.bit = 2,
842 		},
843 		.la = {
844 			.reg = 0x3c0,
845 			.shift = 0,
846 			.mask = 0xff,
847 			.def = 0x49,
848 		},
849 	}, {
850 		.id = 0x63,
851 		.swgroup = TEGRA_SWGROUP_SDMMC4A,
852 		.name = "sdmmcrab",
853 		.smmu = {
854 			.reg = 0x234,
855 			.bit = 3,
856 		},
857 		.la = {
858 			.reg = 0x3c4,
859 			.shift = 0,
860 			.mask = 0xff,
861 			.def = 0x49,
862 		},
863 	}, {
864 		.id = 0x64,
865 		.name = "sdmmcwa",
866 		.swgroup = TEGRA_SWGROUP_SDMMC1A,
867 		.smmu = {
868 			.reg = 0x234,
869 			.bit = 4,
870 		},
871 		.la = {
872 			.reg = 0x3b8,
873 			.shift = 16,
874 			.mask = 0xff,
875 			.def = 0x80,
876 		},
877 	}, {
878 		.id = 0x65,
879 		.name = "sdmmcwaa",
880 		.swgroup = TEGRA_SWGROUP_SDMMC2A,
881 		.smmu = {
882 			.reg = 0x234,
883 			.bit = 5,
884 		},
885 		.la = {
886 			.reg = 0x3bc,
887 			.shift = 16,
888 			.mask = 0xff,
889 			.def = 0x80,
890 		},
891 	}, {
892 		.id = 0x66,
893 		.name = "sdmmcw",
894 		.swgroup = TEGRA_SWGROUP_SDMMC3A,
895 		.smmu = {
896 			.reg = 0x234,
897 			.bit = 6,
898 		},
899 		.la = {
900 			.reg = 0x3c0,
901 			.shift = 16,
902 			.mask = 0xff,
903 			.def = 0x80,
904 		},
905 	}, {
906 		.id = 0x67,
907 		.name = "sdmmcwab",
908 		.swgroup = TEGRA_SWGROUP_SDMMC4A,
909 		.smmu = {
910 			.reg = 0x234,
911 			.bit = 7,
912 		},
913 		.la = {
914 			.reg = 0x3c4,
915 			.shift = 16,
916 			.mask = 0xff,
917 			.def = 0x80,
918 		},
919 	}, {
920 		.id = 0x6c,
921 		.name = "vicsrd",
922 		.swgroup = TEGRA_SWGROUP_VIC,
923 		.smmu = {
924 			.reg = 0x234,
925 			.bit = 12,
926 		},
927 		.la = {
928 			.reg = 0x394,
929 			.shift = 0,
930 			.mask = 0xff,
931 			.def = 0x1a,
932 		},
933 	}, {
934 		.id = 0x6d,
935 		.name = "vicswr",
936 		.swgroup = TEGRA_SWGROUP_VIC,
937 		.smmu = {
938 			.reg = 0x234,
939 			.bit = 13,
940 		},
941 		.la = {
942 			.reg = 0x394,
943 			.shift = 16,
944 			.mask = 0xff,
945 			.def = 0x80,
946 		},
947 	}, {
948 		.id = 0x72,
949 		.name = "viw",
950 		.swgroup = TEGRA_SWGROUP_VI,
951 		.smmu = {
952 			.reg = 0x234,
953 			.bit = 18,
954 		},
955 		.la = {
956 			.reg = 0x398,
957 			.shift = 0,
958 			.mask = 0xff,
959 			.def = 0x80,
960 		},
961 	}, {
962 		.id = 0x73,
963 		.name = "displayd",
964 		.swgroup = TEGRA_SWGROUP_DC,
965 		.smmu = {
966 			.reg = 0x234,
967 			.bit = 19,
968 		},
969 		.la = {
970 			.reg = 0x3c8,
971 			.shift = 0,
972 			.mask = 0xff,
973 			.def = 0x50,
974 		},
975 	},
976 };
977 
978 static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
979 	{ .name = "dc",        .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },
980 	{ .name = "dcb",       .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },
981 	{ .name = "afi",       .swgroup = TEGRA_SWGROUP_AFI,       .reg = 0x238 },
982 	{ .name = "avpc",      .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },
983 	{ .name = "hda",       .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },
984 	{ .name = "hc",        .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },
985 	{ .name = "msenc",     .swgroup = TEGRA_SWGROUP_MSENC,     .reg = 0x264 },
986 	{ .name = "ppcs",      .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },
987 	{ .name = "sata",      .swgroup = TEGRA_SWGROUP_SATA,      .reg = 0x274 },
988 	{ .name = "vde",       .swgroup = TEGRA_SWGROUP_VDE,       .reg = 0x27c },
989 	{ .name = "isp2",      .swgroup = TEGRA_SWGROUP_ISP2,      .reg = 0x258 },
990 	{ .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
991 	{ .name = "xusb_dev",  .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },
992 	{ .name = "isp2b",     .swgroup = TEGRA_SWGROUP_ISP2B,     .reg = 0xaa4 },
993 	{ .name = "tsec",      .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },
994 	{ .name = "a9avp",     .swgroup = TEGRA_SWGROUP_A9AVP,     .reg = 0x290 },
995 	{ .name = "gpu",       .swgroup = TEGRA_SWGROUP_GPU,       .reg = 0xaac },
996 	{ .name = "sdmmc1a",   .swgroup = TEGRA_SWGROUP_SDMMC1A,   .reg = 0xa94 },
997 	{ .name = "sdmmc2a",   .swgroup = TEGRA_SWGROUP_SDMMC2A,   .reg = 0xa98 },
998 	{ .name = "sdmmc3a",   .swgroup = TEGRA_SWGROUP_SDMMC3A,   .reg = 0xa9c },
999 	{ .name = "sdmmc4a",   .swgroup = TEGRA_SWGROUP_SDMMC4A,   .reg = 0xaa0 },
1000 	{ .name = "vic",       .swgroup = TEGRA_SWGROUP_VIC,       .reg = 0x284 },
1001 	{ .name = "vi",        .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },
1002 };
1003 
1004 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1005 static void tegra124_flush_dcache(struct page *page, unsigned long offset,
1006 				  size_t size)
1007 {
1008 	phys_addr_t phys = page_to_phys(page) + offset;
1009 	void *virt = page_address(page) + offset;
1010 
1011 	__cpuc_flush_dcache_area(virt, size);
1012 	outer_flush_range(phys, phys + size);
1013 }
1014 
1015 static const struct tegra_smmu_ops tegra124_smmu_ops = {
1016 	.flush_dcache = tegra124_flush_dcache,
1017 };
1018 
1019 static const struct tegra_smmu_soc tegra124_smmu_soc = {
1020 	.clients = tegra124_mc_clients,
1021 	.num_clients = ARRAY_SIZE(tegra124_mc_clients),
1022 	.swgroups = tegra124_swgroups,
1023 	.num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1024 	.supports_round_robin_arbitration = true,
1025 	.supports_request_limit = true,
1026 	.num_asids = 128,
1027 	.ops = &tegra124_smmu_ops,
1028 };
1029 
1030 const struct tegra_mc_soc tegra124_mc_soc = {
1031 	.clients = tegra124_mc_clients,
1032 	.num_clients = ARRAY_SIZE(tegra124_mc_clients),
1033 	.num_address_bits = 34,
1034 	.atom_size = 32,
1035 	.smmu = &tegra124_smmu_soc,
1036 	.emem_regs = tegra124_mc_emem_regs,
1037 	.num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1038 };
1039 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
1040 
1041 #ifdef CONFIG_ARCH_TEGRA_132_SOC
1042 static void tegra132_flush_dcache(struct page *page, unsigned long offset,
1043 				  size_t size)
1044 {
1045 	void *virt = page_address(page) + offset;
1046 
1047 	__flush_dcache_area(virt, size);
1048 }
1049 
1050 static const struct tegra_smmu_ops tegra132_smmu_ops = {
1051 	.flush_dcache = tegra132_flush_dcache,
1052 };
1053 
1054 static const struct tegra_smmu_soc tegra132_smmu_soc = {
1055 	.clients = tegra124_mc_clients,
1056 	.num_clients = ARRAY_SIZE(tegra124_mc_clients),
1057 	.swgroups = tegra124_swgroups,
1058 	.num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1059 	.supports_round_robin_arbitration = true,
1060 	.supports_request_limit = true,
1061 	.num_asids = 128,
1062 	.ops = &tegra132_smmu_ops,
1063 };
1064 
1065 const struct tegra_mc_soc tegra132_mc_soc = {
1066 	.clients = tegra124_mc_clients,
1067 	.num_clients = ARRAY_SIZE(tegra124_mc_clients),
1068 	.num_address_bits = 34,
1069 	.atom_size = 32,
1070 	.smmu = &tegra132_smmu_soc,
1071 };
1072 #endif /* CONFIG_ARCH_TEGRA_132_SOC */
1073