1 /*
2  * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * Author:
5  *	Mikko Perttunen <mperttunen@nvidia.com>
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17 
18 #include <linux/clk-provider.h>
19 #include <linux/clk.h>
20 #include <linux/clkdev.h>
21 #include <linux/debugfs.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/of_address.h>
25 #include <linux/of_platform.h>
26 #include <linux/platform_device.h>
27 #include <linux/sort.h>
28 #include <linux/string.h>
29 
30 #include <soc/tegra/emc.h>
31 #include <soc/tegra/fuse.h>
32 #include <soc/tegra/mc.h>
33 
34 #define EMC_FBIO_CFG5				0x104
35 #define	EMC_FBIO_CFG5_DRAM_TYPE_MASK		0x3
36 #define	EMC_FBIO_CFG5_DRAM_TYPE_SHIFT		0
37 
38 #define EMC_INTSTATUS				0x0
39 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE	BIT(4)
40 
41 #define EMC_CFG					0xc
42 #define EMC_CFG_DRAM_CLKSTOP_PD			BIT(31)
43 #define EMC_CFG_DRAM_CLKSTOP_SR			BIT(30)
44 #define EMC_CFG_DRAM_ACPD			BIT(29)
45 #define EMC_CFG_DYN_SREF			BIT(28)
46 #define EMC_CFG_PWR_MASK			((0xF << 28) | BIT(18))
47 #define EMC_CFG_DSR_VTTGEN_DRV_EN		BIT(18)
48 
49 #define EMC_REFCTRL				0x20
50 #define EMC_REFCTRL_DEV_SEL_SHIFT		0
51 #define EMC_REFCTRL_ENABLE			BIT(31)
52 
53 #define EMC_TIMING_CONTROL			0x28
54 #define EMC_RC					0x2c
55 #define EMC_RFC					0x30
56 #define EMC_RAS					0x34
57 #define EMC_RP					0x38
58 #define EMC_R2W					0x3c
59 #define EMC_W2R					0x40
60 #define EMC_R2P					0x44
61 #define EMC_W2P					0x48
62 #define EMC_RD_RCD				0x4c
63 #define EMC_WR_RCD				0x50
64 #define EMC_RRD					0x54
65 #define EMC_REXT				0x58
66 #define EMC_WDV					0x5c
67 #define EMC_QUSE				0x60
68 #define EMC_QRST				0x64
69 #define EMC_QSAFE				0x68
70 #define EMC_RDV					0x6c
71 #define EMC_REFRESH				0x70
72 #define EMC_BURST_REFRESH_NUM			0x74
73 #define EMC_PDEX2WR				0x78
74 #define EMC_PDEX2RD				0x7c
75 #define EMC_PCHG2PDEN				0x80
76 #define EMC_ACT2PDEN				0x84
77 #define EMC_AR2PDEN				0x88
78 #define EMC_RW2PDEN				0x8c
79 #define EMC_TXSR				0x90
80 #define EMC_TCKE				0x94
81 #define EMC_TFAW				0x98
82 #define EMC_TRPAB				0x9c
83 #define EMC_TCLKSTABLE				0xa0
84 #define EMC_TCLKSTOP				0xa4
85 #define EMC_TREFBW				0xa8
86 #define EMC_ODT_WRITE				0xb0
87 #define EMC_ODT_READ				0xb4
88 #define EMC_WEXT				0xb8
89 #define EMC_CTT					0xbc
90 #define EMC_RFC_SLR				0xc0
91 #define EMC_MRS_WAIT_CNT2			0xc4
92 
93 #define EMC_MRS_WAIT_CNT			0xc8
94 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT	0
95 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK	\
96 	(0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
97 #define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT	16
98 #define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK		\
99 	(0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
100 
101 #define EMC_MRS					0xcc
102 #define EMC_MODE_SET_DLL_RESET			BIT(8)
103 #define EMC_MODE_SET_LONG_CNT			BIT(26)
104 #define EMC_EMRS				0xd0
105 #define EMC_REF					0xd4
106 #define EMC_PRE					0xd8
107 
108 #define EMC_SELF_REF				0xe0
109 #define EMC_SELF_REF_CMD_ENABLED		BIT(0)
110 #define EMC_SELF_REF_DEV_SEL_SHIFT		30
111 
112 #define EMC_MRW					0xe8
113 
114 #define EMC_MRR					0xec
115 #define EMC_MRR_MA_SHIFT			16
116 #define LPDDR2_MR4_TEMP_SHIFT			0
117 
118 #define EMC_XM2DQSPADCTRL3			0xf8
119 #define EMC_FBIO_SPARE				0x100
120 
121 #define EMC_FBIO_CFG6				0x114
122 #define EMC_EMRS2				0x12c
123 #define EMC_MRW2				0x134
124 #define EMC_MRW4				0x13c
125 #define EMC_EINPUT				0x14c
126 #define EMC_EINPUT_DURATION			0x150
127 #define EMC_PUTERM_EXTRA			0x154
128 #define EMC_TCKESR				0x158
129 #define EMC_TPD					0x15c
130 
131 #define EMC_AUTO_CAL_CONFIG			0x2a4
132 #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START	BIT(31)
133 #define EMC_AUTO_CAL_INTERVAL			0x2a8
134 #define EMC_AUTO_CAL_STATUS			0x2ac
135 #define EMC_AUTO_CAL_STATUS_ACTIVE		BIT(31)
136 #define EMC_STATUS				0x2b4
137 #define EMC_STATUS_TIMING_UPDATE_STALLED	BIT(23)
138 
139 #define EMC_CFG_2				0x2b8
140 #define EMC_CFG_2_MODE_SHIFT			0
141 #define EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR	BIT(6)
142 
143 #define EMC_CFG_DIG_DLL				0x2bc
144 #define EMC_CFG_DIG_DLL_PERIOD			0x2c0
145 #define EMC_RDV_MASK				0x2cc
146 #define EMC_WDV_MASK				0x2d0
147 #define EMC_CTT_DURATION			0x2d8
148 #define EMC_CTT_TERM_CTRL			0x2dc
149 #define EMC_ZCAL_INTERVAL			0x2e0
150 #define EMC_ZCAL_WAIT_CNT			0x2e4
151 
152 #define EMC_ZQ_CAL				0x2ec
153 #define EMC_ZQ_CAL_CMD				BIT(0)
154 #define EMC_ZQ_CAL_LONG				BIT(4)
155 #define EMC_ZQ_CAL_LONG_CMD_DEV0		\
156 	(DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
157 #define EMC_ZQ_CAL_LONG_CMD_DEV1		\
158 	(DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
159 
160 #define EMC_XM2CMDPADCTRL			0x2f0
161 #define EMC_XM2DQSPADCTRL			0x2f8
162 #define EMC_XM2DQSPADCTRL2			0x2fc
163 #define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE	BIT(0)
164 #define EMC_XM2DQSPADCTRL2_VREF_ENABLE		BIT(5)
165 #define EMC_XM2DQPADCTRL			0x300
166 #define EMC_XM2DQPADCTRL2			0x304
167 #define EMC_XM2CLKPADCTRL			0x308
168 #define EMC_XM2COMPPADCTRL			0x30c
169 #define EMC_XM2VTTGENPADCTRL			0x310
170 #define EMC_XM2VTTGENPADCTRL2			0x314
171 #define EMC_XM2VTTGENPADCTRL3			0x318
172 #define EMC_XM2DQSPADCTRL4			0x320
173 #define EMC_DLL_XFORM_DQS0			0x328
174 #define EMC_DLL_XFORM_DQS1			0x32c
175 #define EMC_DLL_XFORM_DQS2			0x330
176 #define EMC_DLL_XFORM_DQS3			0x334
177 #define EMC_DLL_XFORM_DQS4			0x338
178 #define EMC_DLL_XFORM_DQS5			0x33c
179 #define EMC_DLL_XFORM_DQS6			0x340
180 #define EMC_DLL_XFORM_DQS7			0x344
181 #define EMC_DLL_XFORM_QUSE0			0x348
182 #define EMC_DLL_XFORM_QUSE1			0x34c
183 #define EMC_DLL_XFORM_QUSE2			0x350
184 #define EMC_DLL_XFORM_QUSE3			0x354
185 #define EMC_DLL_XFORM_QUSE4			0x358
186 #define EMC_DLL_XFORM_QUSE5			0x35c
187 #define EMC_DLL_XFORM_QUSE6			0x360
188 #define EMC_DLL_XFORM_QUSE7			0x364
189 #define EMC_DLL_XFORM_DQ0			0x368
190 #define EMC_DLL_XFORM_DQ1			0x36c
191 #define EMC_DLL_XFORM_DQ2			0x370
192 #define EMC_DLL_XFORM_DQ3			0x374
193 #define EMC_DLI_TRIM_TXDQS0			0x3a8
194 #define EMC_DLI_TRIM_TXDQS1			0x3ac
195 #define EMC_DLI_TRIM_TXDQS2			0x3b0
196 #define EMC_DLI_TRIM_TXDQS3			0x3b4
197 #define EMC_DLI_TRIM_TXDQS4			0x3b8
198 #define EMC_DLI_TRIM_TXDQS5			0x3bc
199 #define EMC_DLI_TRIM_TXDQS6			0x3c0
200 #define EMC_DLI_TRIM_TXDQS7			0x3c4
201 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE	0x3cc
202 #define EMC_SEL_DPD_CTRL			0x3d8
203 #define EMC_SEL_DPD_CTRL_DATA_SEL_DPD		BIT(8)
204 #define EMC_SEL_DPD_CTRL_ODT_SEL_DPD		BIT(5)
205 #define EMC_SEL_DPD_CTRL_RESET_SEL_DPD		BIT(4)
206 #define EMC_SEL_DPD_CTRL_CA_SEL_DPD		BIT(3)
207 #define EMC_SEL_DPD_CTRL_CLK_SEL_DPD		BIT(2)
208 #define EMC_SEL_DPD_CTRL_DDR3_MASK	\
209 	((0xf << 2) | BIT(8))
210 #define EMC_SEL_DPD_CTRL_MASK \
211 	((0x3 << 2) | BIT(5) | BIT(8))
212 #define EMC_PRE_REFRESH_REQ_CNT			0x3dc
213 #define EMC_DYN_SELF_REF_CONTROL		0x3e0
214 #define EMC_TXSRDLL				0x3e4
215 #define EMC_CCFIFO_ADDR				0x3e8
216 #define EMC_CCFIFO_DATA				0x3ec
217 #define EMC_CCFIFO_STATUS			0x3f0
218 #define EMC_CDB_CNTL_1				0x3f4
219 #define EMC_CDB_CNTL_2				0x3f8
220 #define EMC_XM2CLKPADCTRL2			0x3fc
221 #define EMC_AUTO_CAL_CONFIG2			0x458
222 #define EMC_AUTO_CAL_CONFIG3			0x45c
223 #define EMC_IBDLY				0x468
224 #define EMC_DLL_XFORM_ADDR0			0x46c
225 #define EMC_DLL_XFORM_ADDR1			0x470
226 #define EMC_DLL_XFORM_ADDR2			0x474
227 #define EMC_DSR_VTTGEN_DRV			0x47c
228 #define EMC_TXDSRVTTGEN				0x480
229 #define EMC_XM2CMDPADCTRL4			0x484
230 #define EMC_XM2CMDPADCTRL5			0x488
231 #define EMC_DLL_XFORM_DQS8			0x4a0
232 #define EMC_DLL_XFORM_DQS9			0x4a4
233 #define EMC_DLL_XFORM_DQS10			0x4a8
234 #define EMC_DLL_XFORM_DQS11			0x4ac
235 #define EMC_DLL_XFORM_DQS12			0x4b0
236 #define EMC_DLL_XFORM_DQS13			0x4b4
237 #define EMC_DLL_XFORM_DQS14			0x4b8
238 #define EMC_DLL_XFORM_DQS15			0x4bc
239 #define EMC_DLL_XFORM_QUSE8			0x4c0
240 #define EMC_DLL_XFORM_QUSE9			0x4c4
241 #define EMC_DLL_XFORM_QUSE10			0x4c8
242 #define EMC_DLL_XFORM_QUSE11			0x4cc
243 #define EMC_DLL_XFORM_QUSE12			0x4d0
244 #define EMC_DLL_XFORM_QUSE13			0x4d4
245 #define EMC_DLL_XFORM_QUSE14			0x4d8
246 #define EMC_DLL_XFORM_QUSE15			0x4dc
247 #define EMC_DLL_XFORM_DQ4			0x4e0
248 #define EMC_DLL_XFORM_DQ5			0x4e4
249 #define EMC_DLL_XFORM_DQ6			0x4e8
250 #define EMC_DLL_XFORM_DQ7			0x4ec
251 #define EMC_DLI_TRIM_TXDQS8			0x520
252 #define EMC_DLI_TRIM_TXDQS9			0x524
253 #define EMC_DLI_TRIM_TXDQS10			0x528
254 #define EMC_DLI_TRIM_TXDQS11			0x52c
255 #define EMC_DLI_TRIM_TXDQS12			0x530
256 #define EMC_DLI_TRIM_TXDQS13			0x534
257 #define EMC_DLI_TRIM_TXDQS14			0x538
258 #define EMC_DLI_TRIM_TXDQS15			0x53c
259 #define EMC_CDB_CNTL_3				0x540
260 #define EMC_XM2DQSPADCTRL5			0x544
261 #define EMC_XM2DQSPADCTRL6			0x548
262 #define EMC_XM2DQPADCTRL3			0x54c
263 #define EMC_DLL_XFORM_ADDR3			0x550
264 #define EMC_DLL_XFORM_ADDR4			0x554
265 #define EMC_DLL_XFORM_ADDR5			0x558
266 #define EMC_CFG_PIPE				0x560
267 #define EMC_QPOP				0x564
268 #define EMC_QUSE_WIDTH				0x568
269 #define EMC_PUTERM_WIDTH			0x56c
270 #define EMC_BGBIAS_CTL0				0x570
271 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX BIT(3)
272 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN BIT(2)
273 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD	BIT(1)
274 #define EMC_PUTERM_ADJ				0x574
275 
276 #define DRAM_DEV_SEL_ALL			0
277 #define DRAM_DEV_SEL_0				(2 << 30)
278 #define DRAM_DEV_SEL_1				(1 << 30)
279 
280 #define EMC_CFG_POWER_FEATURES_MASK		\
281 	(EMC_CFG_DYN_SREF | EMC_CFG_DRAM_ACPD | EMC_CFG_DRAM_CLKSTOP_SR | \
282 	EMC_CFG_DRAM_CLKSTOP_PD | EMC_CFG_DSR_VTTGEN_DRV_EN)
283 #define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
284 #define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
285 
286 /* Maximum amount of time in us. to wait for changes to become effective */
287 #define EMC_STATUS_UPDATE_TIMEOUT		1000
288 
289 enum emc_dram_type {
290 	DRAM_TYPE_DDR3 = 0,
291 	DRAM_TYPE_DDR1 = 1,
292 	DRAM_TYPE_LPDDR3 = 2,
293 	DRAM_TYPE_DDR2 = 3
294 };
295 
296 enum emc_dll_change {
297 	DLL_CHANGE_NONE,
298 	DLL_CHANGE_ON,
299 	DLL_CHANGE_OFF
300 };
301 
302 static const unsigned long emc_burst_regs[] = {
303 	EMC_RC,
304 	EMC_RFC,
305 	EMC_RFC_SLR,
306 	EMC_RAS,
307 	EMC_RP,
308 	EMC_R2W,
309 	EMC_W2R,
310 	EMC_R2P,
311 	EMC_W2P,
312 	EMC_RD_RCD,
313 	EMC_WR_RCD,
314 	EMC_RRD,
315 	EMC_REXT,
316 	EMC_WEXT,
317 	EMC_WDV,
318 	EMC_WDV_MASK,
319 	EMC_QUSE,
320 	EMC_QUSE_WIDTH,
321 	EMC_IBDLY,
322 	EMC_EINPUT,
323 	EMC_EINPUT_DURATION,
324 	EMC_PUTERM_EXTRA,
325 	EMC_PUTERM_WIDTH,
326 	EMC_PUTERM_ADJ,
327 	EMC_CDB_CNTL_1,
328 	EMC_CDB_CNTL_2,
329 	EMC_CDB_CNTL_3,
330 	EMC_QRST,
331 	EMC_QSAFE,
332 	EMC_RDV,
333 	EMC_RDV_MASK,
334 	EMC_REFRESH,
335 	EMC_BURST_REFRESH_NUM,
336 	EMC_PRE_REFRESH_REQ_CNT,
337 	EMC_PDEX2WR,
338 	EMC_PDEX2RD,
339 	EMC_PCHG2PDEN,
340 	EMC_ACT2PDEN,
341 	EMC_AR2PDEN,
342 	EMC_RW2PDEN,
343 	EMC_TXSR,
344 	EMC_TXSRDLL,
345 	EMC_TCKE,
346 	EMC_TCKESR,
347 	EMC_TPD,
348 	EMC_TFAW,
349 	EMC_TRPAB,
350 	EMC_TCLKSTABLE,
351 	EMC_TCLKSTOP,
352 	EMC_TREFBW,
353 	EMC_FBIO_CFG6,
354 	EMC_ODT_WRITE,
355 	EMC_ODT_READ,
356 	EMC_FBIO_CFG5,
357 	EMC_CFG_DIG_DLL,
358 	EMC_CFG_DIG_DLL_PERIOD,
359 	EMC_DLL_XFORM_DQS0,
360 	EMC_DLL_XFORM_DQS1,
361 	EMC_DLL_XFORM_DQS2,
362 	EMC_DLL_XFORM_DQS3,
363 	EMC_DLL_XFORM_DQS4,
364 	EMC_DLL_XFORM_DQS5,
365 	EMC_DLL_XFORM_DQS6,
366 	EMC_DLL_XFORM_DQS7,
367 	EMC_DLL_XFORM_DQS8,
368 	EMC_DLL_XFORM_DQS9,
369 	EMC_DLL_XFORM_DQS10,
370 	EMC_DLL_XFORM_DQS11,
371 	EMC_DLL_XFORM_DQS12,
372 	EMC_DLL_XFORM_DQS13,
373 	EMC_DLL_XFORM_DQS14,
374 	EMC_DLL_XFORM_DQS15,
375 	EMC_DLL_XFORM_QUSE0,
376 	EMC_DLL_XFORM_QUSE1,
377 	EMC_DLL_XFORM_QUSE2,
378 	EMC_DLL_XFORM_QUSE3,
379 	EMC_DLL_XFORM_QUSE4,
380 	EMC_DLL_XFORM_QUSE5,
381 	EMC_DLL_XFORM_QUSE6,
382 	EMC_DLL_XFORM_QUSE7,
383 	EMC_DLL_XFORM_ADDR0,
384 	EMC_DLL_XFORM_ADDR1,
385 	EMC_DLL_XFORM_ADDR2,
386 	EMC_DLL_XFORM_ADDR3,
387 	EMC_DLL_XFORM_ADDR4,
388 	EMC_DLL_XFORM_ADDR5,
389 	EMC_DLL_XFORM_QUSE8,
390 	EMC_DLL_XFORM_QUSE9,
391 	EMC_DLL_XFORM_QUSE10,
392 	EMC_DLL_XFORM_QUSE11,
393 	EMC_DLL_XFORM_QUSE12,
394 	EMC_DLL_XFORM_QUSE13,
395 	EMC_DLL_XFORM_QUSE14,
396 	EMC_DLL_XFORM_QUSE15,
397 	EMC_DLI_TRIM_TXDQS0,
398 	EMC_DLI_TRIM_TXDQS1,
399 	EMC_DLI_TRIM_TXDQS2,
400 	EMC_DLI_TRIM_TXDQS3,
401 	EMC_DLI_TRIM_TXDQS4,
402 	EMC_DLI_TRIM_TXDQS5,
403 	EMC_DLI_TRIM_TXDQS6,
404 	EMC_DLI_TRIM_TXDQS7,
405 	EMC_DLI_TRIM_TXDQS8,
406 	EMC_DLI_TRIM_TXDQS9,
407 	EMC_DLI_TRIM_TXDQS10,
408 	EMC_DLI_TRIM_TXDQS11,
409 	EMC_DLI_TRIM_TXDQS12,
410 	EMC_DLI_TRIM_TXDQS13,
411 	EMC_DLI_TRIM_TXDQS14,
412 	EMC_DLI_TRIM_TXDQS15,
413 	EMC_DLL_XFORM_DQ0,
414 	EMC_DLL_XFORM_DQ1,
415 	EMC_DLL_XFORM_DQ2,
416 	EMC_DLL_XFORM_DQ3,
417 	EMC_DLL_XFORM_DQ4,
418 	EMC_DLL_XFORM_DQ5,
419 	EMC_DLL_XFORM_DQ6,
420 	EMC_DLL_XFORM_DQ7,
421 	EMC_XM2CMDPADCTRL,
422 	EMC_XM2CMDPADCTRL4,
423 	EMC_XM2CMDPADCTRL5,
424 	EMC_XM2DQPADCTRL2,
425 	EMC_XM2DQPADCTRL3,
426 	EMC_XM2CLKPADCTRL,
427 	EMC_XM2CLKPADCTRL2,
428 	EMC_XM2COMPPADCTRL,
429 	EMC_XM2VTTGENPADCTRL,
430 	EMC_XM2VTTGENPADCTRL2,
431 	EMC_XM2VTTGENPADCTRL3,
432 	EMC_XM2DQSPADCTRL3,
433 	EMC_XM2DQSPADCTRL4,
434 	EMC_XM2DQSPADCTRL5,
435 	EMC_XM2DQSPADCTRL6,
436 	EMC_DSR_VTTGEN_DRV,
437 	EMC_TXDSRVTTGEN,
438 	EMC_FBIO_SPARE,
439 	EMC_ZCAL_WAIT_CNT,
440 	EMC_MRS_WAIT_CNT2,
441 	EMC_CTT,
442 	EMC_CTT_DURATION,
443 	EMC_CFG_PIPE,
444 	EMC_DYN_SELF_REF_CONTROL,
445 	EMC_QPOP
446 };
447 
448 struct emc_timing {
449 	unsigned long rate;
450 
451 	u32 emc_burst_data[ARRAY_SIZE(emc_burst_regs)];
452 
453 	u32 emc_auto_cal_config;
454 	u32 emc_auto_cal_config2;
455 	u32 emc_auto_cal_config3;
456 	u32 emc_auto_cal_interval;
457 	u32 emc_bgbias_ctl0;
458 	u32 emc_cfg;
459 	u32 emc_cfg_2;
460 	u32 emc_ctt_term_ctrl;
461 	u32 emc_mode_1;
462 	u32 emc_mode_2;
463 	u32 emc_mode_4;
464 	u32 emc_mode_reset;
465 	u32 emc_mrs_wait_cnt;
466 	u32 emc_sel_dpd_ctrl;
467 	u32 emc_xm2dqspadctrl2;
468 	u32 emc_zcal_cnt_long;
469 	u32 emc_zcal_interval;
470 };
471 
472 struct tegra_emc {
473 	struct device *dev;
474 
475 	struct tegra_mc *mc;
476 
477 	void __iomem *regs;
478 
479 	enum emc_dram_type dram_type;
480 	unsigned int dram_num;
481 
482 	struct emc_timing last_timing;
483 	struct emc_timing *timings;
484 	unsigned int num_timings;
485 };
486 
487 /* Timing change sequence functions */
488 
489 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value,
490 			      unsigned long offset)
491 {
492 	writel(value, emc->regs + EMC_CCFIFO_DATA);
493 	writel(offset, emc->regs + EMC_CCFIFO_ADDR);
494 }
495 
496 static void emc_seq_update_timing(struct tegra_emc *emc)
497 {
498 	unsigned int i;
499 	u32 value;
500 
501 	writel(1, emc->regs + EMC_TIMING_CONTROL);
502 
503 	for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
504 		value = readl(emc->regs + EMC_STATUS);
505 		if ((value & EMC_STATUS_TIMING_UPDATE_STALLED) == 0)
506 			return;
507 		udelay(1);
508 	}
509 
510 	dev_err(emc->dev, "timing update timed out\n");
511 }
512 
513 static void emc_seq_disable_auto_cal(struct tegra_emc *emc)
514 {
515 	unsigned int i;
516 	u32 value;
517 
518 	writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
519 
520 	for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
521 		value = readl(emc->regs + EMC_AUTO_CAL_STATUS);
522 		if ((value & EMC_AUTO_CAL_STATUS_ACTIVE) == 0)
523 			return;
524 		udelay(1);
525 	}
526 
527 	dev_err(emc->dev, "auto cal disable timed out\n");
528 }
529 
530 static void emc_seq_wait_clkchange(struct tegra_emc *emc)
531 {
532 	unsigned int i;
533 	u32 value;
534 
535 	for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
536 		value = readl(emc->regs + EMC_INTSTATUS);
537 		if (value & EMC_INTSTATUS_CLKCHANGE_COMPLETE)
538 			return;
539 		udelay(1);
540 	}
541 
542 	dev_err(emc->dev, "clock change timed out\n");
543 }
544 
545 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
546 						unsigned long rate)
547 {
548 	struct emc_timing *timing = NULL;
549 	unsigned int i;
550 
551 	for (i = 0; i < emc->num_timings; i++) {
552 		if (emc->timings[i].rate == rate) {
553 			timing = &emc->timings[i];
554 			break;
555 		}
556 	}
557 
558 	if (!timing) {
559 		dev_err(emc->dev, "no timing for rate %lu\n", rate);
560 		return NULL;
561 	}
562 
563 	return timing;
564 }
565 
566 int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
567 				    unsigned long rate)
568 {
569 	struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
570 	struct emc_timing *last = &emc->last_timing;
571 	enum emc_dll_change dll_change;
572 	unsigned int pre_wait = 0;
573 	u32 val, val2, mask;
574 	bool update = false;
575 	unsigned int i;
576 
577 	if (!timing)
578 		return -ENOENT;
579 
580 	if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1))
581 		dll_change = DLL_CHANGE_NONE;
582 	else if (timing->emc_mode_1 & 0x1)
583 		dll_change = DLL_CHANGE_ON;
584 	else
585 		dll_change = DLL_CHANGE_OFF;
586 
587 	/* Clear CLKCHANGE_COMPLETE interrupts */
588 	writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS);
589 
590 	/* Disable dynamic self-refresh */
591 	val = readl(emc->regs + EMC_CFG);
592 	if (val & EMC_CFG_PWR_MASK) {
593 		val &= ~EMC_CFG_POWER_FEATURES_MASK;
594 		writel(val, emc->regs + EMC_CFG);
595 
596 		pre_wait = 5;
597 	}
598 
599 	/* Disable SEL_DPD_CTRL for clock change */
600 	if (emc->dram_type == DRAM_TYPE_DDR3)
601 		mask = EMC_SEL_DPD_CTRL_DDR3_MASK;
602 	else
603 		mask = EMC_SEL_DPD_CTRL_MASK;
604 
605 	val = readl(emc->regs + EMC_SEL_DPD_CTRL);
606 	if (val & mask) {
607 		val &= ~mask;
608 		writel(val, emc->regs + EMC_SEL_DPD_CTRL);
609 	}
610 
611 	/* Prepare DQ/DQS for clock change */
612 	val = readl(emc->regs + EMC_BGBIAS_CTL0);
613 	val2 = last->emc_bgbias_ctl0;
614 	if (!(timing->emc_bgbias_ctl0 &
615 	      EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) &&
616 	    (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX)) {
617 		val2 &= ~EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX;
618 		update = true;
619 	}
620 
621 	if ((val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD) ||
622 	    (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN)) {
623 		update = true;
624 	}
625 
626 	if (update) {
627 		writel(val2, emc->regs + EMC_BGBIAS_CTL0);
628 		if (pre_wait < 5)
629 			pre_wait = 5;
630 	}
631 
632 	update = false;
633 	val = readl(emc->regs + EMC_XM2DQSPADCTRL2);
634 	if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE &&
635 	    !(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) {
636 		val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE;
637 		update = true;
638 	}
639 
640 	if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE &&
641 	    !(val & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE)) {
642 		val |= EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE;
643 		update = true;
644 	}
645 
646 	if (update) {
647 		writel(val, emc->regs + EMC_XM2DQSPADCTRL2);
648 		if (pre_wait < 30)
649 			pre_wait = 30;
650 	}
651 
652 	/* Wait to settle */
653 	if (pre_wait) {
654 		emc_seq_update_timing(emc);
655 		udelay(pre_wait);
656 	}
657 
658 	/* Program CTT_TERM control */
659 	if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) {
660 		emc_seq_disable_auto_cal(emc);
661 		writel(timing->emc_ctt_term_ctrl,
662 		       emc->regs + EMC_CTT_TERM_CTRL);
663 		emc_seq_update_timing(emc);
664 	}
665 
666 	/* Program burst shadow registers */
667 	for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i)
668 		writel(timing->emc_burst_data[i],
669 		       emc->regs + emc_burst_regs[i]);
670 
671 	writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2);
672 	writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL);
673 
674 	tegra_mc_write_emem_configuration(emc->mc, timing->rate);
675 
676 	val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK;
677 	emc_ccfifo_writel(emc, val, EMC_CFG);
678 
679 	/* Program AUTO_CAL_CONFIG */
680 	if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2)
681 		emc_ccfifo_writel(emc, timing->emc_auto_cal_config2,
682 				  EMC_AUTO_CAL_CONFIG2);
683 
684 	if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3)
685 		emc_ccfifo_writel(emc, timing->emc_auto_cal_config3,
686 				  EMC_AUTO_CAL_CONFIG3);
687 
688 	if (timing->emc_auto_cal_config != last->emc_auto_cal_config) {
689 		val = timing->emc_auto_cal_config;
690 		val &= EMC_AUTO_CAL_CONFIG_AUTO_CAL_START;
691 		emc_ccfifo_writel(emc, val, EMC_AUTO_CAL_CONFIG);
692 	}
693 
694 	/* DDR3: predict MRS long wait count */
695 	if (emc->dram_type == DRAM_TYPE_DDR3 &&
696 	    dll_change == DLL_CHANGE_ON) {
697 		u32 cnt = 512;
698 
699 		if (timing->emc_zcal_interval != 0 &&
700 		    last->emc_zcal_interval == 0)
701 			cnt -= emc->dram_num * 256;
702 
703 		val = (timing->emc_mrs_wait_cnt
704 			& EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK)
705 			>> EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT;
706 		if (cnt < val)
707 			cnt = val;
708 
709 		val = timing->emc_mrs_wait_cnt
710 			& ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
711 		val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
712 			& EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
713 
714 		writel(val, emc->regs + EMC_MRS_WAIT_CNT);
715 	}
716 
717 	val = timing->emc_cfg_2;
718 	val &= ~EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR;
719 	emc_ccfifo_writel(emc, val, EMC_CFG_2);
720 
721 	/* DDR3: Turn off DLL and enter self-refresh */
722 	if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF)
723 		emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
724 
725 	/* Disable refresh controller */
726 	emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num),
727 			  EMC_REFCTRL);
728 	if (emc->dram_type == DRAM_TYPE_DDR3)
729 		emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num) |
730 				       EMC_SELF_REF_CMD_ENABLED,
731 				  EMC_SELF_REF);
732 
733 	/* Flow control marker */
734 	emc_ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
735 
736 	/* DDR3: Exit self-refresh */
737 	if (emc->dram_type == DRAM_TYPE_DDR3)
738 		emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num),
739 				  EMC_SELF_REF);
740 	emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num) |
741 			       EMC_REFCTRL_ENABLE,
742 			  EMC_REFCTRL);
743 
744 	/* Set DRAM mode registers */
745 	if (emc->dram_type == DRAM_TYPE_DDR3) {
746 		if (timing->emc_mode_1 != last->emc_mode_1)
747 			emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
748 		if (timing->emc_mode_2 != last->emc_mode_2)
749 			emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2);
750 
751 		if ((timing->emc_mode_reset != last->emc_mode_reset) ||
752 		    dll_change == DLL_CHANGE_ON) {
753 			val = timing->emc_mode_reset;
754 			if (dll_change == DLL_CHANGE_ON) {
755 				val |= EMC_MODE_SET_DLL_RESET;
756 				val |= EMC_MODE_SET_LONG_CNT;
757 			} else {
758 				val &= ~EMC_MODE_SET_DLL_RESET;
759 			}
760 			emc_ccfifo_writel(emc, val, EMC_MRS);
761 		}
762 	} else {
763 		if (timing->emc_mode_2 != last->emc_mode_2)
764 			emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2);
765 		if (timing->emc_mode_1 != last->emc_mode_1)
766 			emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW);
767 		if (timing->emc_mode_4 != last->emc_mode_4)
768 			emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4);
769 	}
770 
771 	/*  Issue ZCAL command if turning ZCAL on */
772 	if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) {
773 		emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL);
774 		if (emc->dram_num > 1)
775 			emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV1,
776 					  EMC_ZQ_CAL);
777 	}
778 
779 	/*  Write to RO register to remove stall after change */
780 	emc_ccfifo_writel(emc, 0, EMC_CCFIFO_STATUS);
781 
782 	if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR)
783 		emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2);
784 
785 	/* Disable AUTO_CAL for clock change */
786 	emc_seq_disable_auto_cal(emc);
787 
788 	/* Read register to wait until programming has settled */
789 	readl(emc->regs + EMC_INTSTATUS);
790 
791 	return 0;
792 }
793 
794 void tegra_emc_complete_timing_change(struct tegra_emc *emc,
795 				      unsigned long rate)
796 {
797 	struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
798 	struct emc_timing *last = &emc->last_timing;
799 	u32 val;
800 
801 	if (!timing)
802 		return;
803 
804 	/* Wait until the state machine has settled */
805 	emc_seq_wait_clkchange(emc);
806 
807 	/* Restore AUTO_CAL */
808 	if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl)
809 		writel(timing->emc_auto_cal_interval,
810 		       emc->regs + EMC_AUTO_CAL_INTERVAL);
811 
812 	/* Restore dynamic self-refresh */
813 	if (timing->emc_cfg & EMC_CFG_PWR_MASK)
814 		writel(timing->emc_cfg, emc->regs + EMC_CFG);
815 
816 	/* Set ZCAL wait count */
817 	writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT);
818 
819 	/* LPDDR3: Turn off BGBIAS if low frequency */
820 	if (emc->dram_type == DRAM_TYPE_LPDDR3 &&
821 	    timing->emc_bgbias_ctl0 &
822 	      EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) {
823 		val = timing->emc_bgbias_ctl0;
824 		val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN;
825 		val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD;
826 		writel(val, emc->regs + EMC_BGBIAS_CTL0);
827 	} else {
828 		if (emc->dram_type == DRAM_TYPE_DDR3 &&
829 		    readl(emc->regs + EMC_BGBIAS_CTL0) !=
830 		      timing->emc_bgbias_ctl0) {
831 			writel(timing->emc_bgbias_ctl0,
832 			       emc->regs + EMC_BGBIAS_CTL0);
833 		}
834 
835 		writel(timing->emc_auto_cal_interval,
836 		       emc->regs + EMC_AUTO_CAL_INTERVAL);
837 	}
838 
839 	/* Wait for timing to settle */
840 	udelay(2);
841 
842 	/* Reprogram SEL_DPD_CTRL */
843 	writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL);
844 	emc_seq_update_timing(emc);
845 
846 	emc->last_timing = *timing;
847 }
848 
849 /* Initialization and deinitialization */
850 
851 static void emc_read_current_timing(struct tegra_emc *emc,
852 				    struct emc_timing *timing)
853 {
854 	unsigned int i;
855 
856 	for (i = 0; i < ARRAY_SIZE(emc_burst_regs); ++i)
857 		timing->emc_burst_data[i] =
858 			readl(emc->regs + emc_burst_regs[i]);
859 
860 	timing->emc_cfg = readl(emc->regs + EMC_CFG);
861 
862 	timing->emc_auto_cal_interval = 0;
863 	timing->emc_zcal_cnt_long = 0;
864 	timing->emc_mode_1 = 0;
865 	timing->emc_mode_2 = 0;
866 	timing->emc_mode_4 = 0;
867 	timing->emc_mode_reset = 0;
868 }
869 
870 static int emc_init(struct tegra_emc *emc)
871 {
872 	emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5);
873 	emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK;
874 	emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT;
875 
876 	emc->dram_num = tegra_mc_get_emem_device_count(emc->mc);
877 
878 	emc_read_current_timing(emc, &emc->last_timing);
879 
880 	return 0;
881 }
882 
883 static int load_one_timing_from_dt(struct tegra_emc *emc,
884 				   struct emc_timing *timing,
885 				   struct device_node *node)
886 {
887 	u32 value;
888 	int err;
889 
890 	err = of_property_read_u32(node, "clock-frequency", &value);
891 	if (err) {
892 		dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n",
893 			node, err);
894 		return err;
895 	}
896 
897 	timing->rate = value;
898 
899 	err = of_property_read_u32_array(node, "nvidia,emc-configuration",
900 					 timing->emc_burst_data,
901 					 ARRAY_SIZE(timing->emc_burst_data));
902 	if (err) {
903 		dev_err(emc->dev,
904 			"timing %pOFn: failed to read emc burst data: %d\n",
905 			node, err);
906 		return err;
907 	}
908 
909 #define EMC_READ_PROP(prop, dtprop) { \
910 	err = of_property_read_u32(node, dtprop, &timing->prop); \
911 	if (err) { \
912 		dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \
913 			node, err); \
914 		return err; \
915 	} \
916 }
917 
918 	EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config")
919 	EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2")
920 	EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3")
921 	EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
922 	EMC_READ_PROP(emc_bgbias_ctl0, "nvidia,emc-bgbias-ctl0")
923 	EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg")
924 	EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2")
925 	EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl")
926 	EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1")
927 	EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2")
928 	EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4")
929 	EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset")
930 	EMC_READ_PROP(emc_mrs_wait_cnt, "nvidia,emc-mrs-wait-cnt")
931 	EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl")
932 	EMC_READ_PROP(emc_xm2dqspadctrl2, "nvidia,emc-xm2dqspadctrl2")
933 	EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
934 	EMC_READ_PROP(emc_zcal_interval, "nvidia,emc-zcal-interval")
935 
936 #undef EMC_READ_PROP
937 
938 	return 0;
939 }
940 
941 static int cmp_timings(const void *_a, const void *_b)
942 {
943 	const struct emc_timing *a = _a;
944 	const struct emc_timing *b = _b;
945 
946 	if (a->rate < b->rate)
947 		return -1;
948 	else if (a->rate == b->rate)
949 		return 0;
950 	else
951 		return 1;
952 }
953 
954 static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
955 					  struct device_node *node)
956 {
957 	int child_count = of_get_child_count(node);
958 	struct device_node *child;
959 	struct emc_timing *timing;
960 	unsigned int i = 0;
961 	int err;
962 
963 	emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
964 				    GFP_KERNEL);
965 	if (!emc->timings)
966 		return -ENOMEM;
967 
968 	emc->num_timings = child_count;
969 
970 	for_each_child_of_node(node, child) {
971 		timing = &emc->timings[i++];
972 
973 		err = load_one_timing_from_dt(emc, timing, child);
974 		if (err) {
975 			of_node_put(child);
976 			return err;
977 		}
978 	}
979 
980 	sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
981 	     NULL);
982 
983 	return 0;
984 }
985 
986 static const struct of_device_id tegra_emc_of_match[] = {
987 	{ .compatible = "nvidia,tegra124-emc" },
988 	{}
989 };
990 
991 static struct device_node *
992 tegra_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code)
993 {
994 	struct device_node *np;
995 	int err;
996 
997 	for_each_child_of_node(node, np) {
998 		u32 value;
999 
1000 		err = of_property_read_u32(np, "nvidia,ram-code", &value);
1001 		if (err || (value != ram_code))
1002 			continue;
1003 
1004 		return np;
1005 	}
1006 
1007 	return NULL;
1008 }
1009 
1010 /* Debugfs entry */
1011 
1012 static int emc_debug_rate_get(void *data, u64 *rate)
1013 {
1014 	struct clk *c = data;
1015 
1016 	*rate = clk_get_rate(c);
1017 
1018 	return 0;
1019 }
1020 
1021 static int emc_debug_rate_set(void *data, u64 rate)
1022 {
1023 	struct clk *c = data;
1024 
1025 	return clk_set_rate(c, rate);
1026 }
1027 
1028 DEFINE_SIMPLE_ATTRIBUTE(emc_debug_rate_fops, emc_debug_rate_get,
1029 			emc_debug_rate_set, "%lld\n");
1030 
1031 static int emc_debug_supported_rates_show(struct seq_file *s, void *data)
1032 {
1033 	struct tegra_emc *emc = s->private;
1034 	const char *prefix = "";
1035 	unsigned int i;
1036 
1037 	for (i = 0; i < emc->num_timings; i++) {
1038 		struct emc_timing *timing = &emc->timings[i];
1039 
1040 		seq_printf(s, "%s%lu", prefix, timing->rate);
1041 
1042 		prefix = " ";
1043 	}
1044 
1045 	seq_puts(s, "\n");
1046 
1047 	return 0;
1048 }
1049 
1050 static int emc_debug_supported_rates_open(struct inode *inode,
1051 					  struct file *file)
1052 {
1053 	return single_open(file, emc_debug_supported_rates_show,
1054 			   inode->i_private);
1055 }
1056 
1057 static const struct file_operations emc_debug_supported_rates_fops = {
1058 	.open = emc_debug_supported_rates_open,
1059 	.read = seq_read,
1060 	.llseek = seq_lseek,
1061 	.release = single_release,
1062 };
1063 
1064 static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc)
1065 {
1066 	struct dentry *root, *file;
1067 	struct clk *clk;
1068 
1069 	root = debugfs_create_dir("emc", NULL);
1070 	if (!root) {
1071 		dev_err(dev, "failed to create debugfs directory\n");
1072 		return;
1073 	}
1074 
1075 	clk = clk_get_sys("tegra-clk-debug", "emc");
1076 	if (IS_ERR(clk)) {
1077 		dev_err(dev, "failed to get debug clock: %ld\n", PTR_ERR(clk));
1078 		return;
1079 	}
1080 
1081 	file = debugfs_create_file("rate", S_IRUGO | S_IWUSR, root, clk,
1082 				   &emc_debug_rate_fops);
1083 	if (!file)
1084 		dev_err(dev, "failed to create debugfs entry\n");
1085 
1086 	file = debugfs_create_file("supported_rates", S_IRUGO, root, emc,
1087 				   &emc_debug_supported_rates_fops);
1088 	if (!file)
1089 		dev_err(dev, "failed to create debugfs entry\n");
1090 }
1091 
1092 static int tegra_emc_probe(struct platform_device *pdev)
1093 {
1094 	struct platform_device *mc;
1095 	struct device_node *np;
1096 	struct tegra_emc *emc;
1097 	struct resource *res;
1098 	u32 ram_code;
1099 	int err;
1100 
1101 	emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
1102 	if (!emc)
1103 		return -ENOMEM;
1104 
1105 	emc->dev = &pdev->dev;
1106 
1107 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1108 	emc->regs = devm_ioremap_resource(&pdev->dev, res);
1109 	if (IS_ERR(emc->regs))
1110 		return PTR_ERR(emc->regs);
1111 
1112 	np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0);
1113 	if (!np) {
1114 		dev_err(&pdev->dev, "could not get memory controller\n");
1115 		return -ENOENT;
1116 	}
1117 
1118 	mc = of_find_device_by_node(np);
1119 	of_node_put(np);
1120 	if (!mc)
1121 		return -ENOENT;
1122 
1123 	emc->mc = platform_get_drvdata(mc);
1124 	if (!emc->mc)
1125 		return -EPROBE_DEFER;
1126 
1127 	ram_code = tegra_read_ram_code();
1128 
1129 	np = tegra_emc_find_node_by_ram_code(pdev->dev.of_node, ram_code);
1130 	if (!np) {
1131 		dev_err(&pdev->dev,
1132 			"no memory timings for RAM code %u found in DT\n",
1133 			ram_code);
1134 		return -ENOENT;
1135 	}
1136 
1137 	err = tegra_emc_load_timings_from_dt(emc, np);
1138 	of_node_put(np);
1139 	if (err)
1140 		return err;
1141 
1142 	if (emc->num_timings == 0) {
1143 		dev_err(&pdev->dev,
1144 			"no memory timings for RAM code %u registered\n",
1145 			ram_code);
1146 		return -ENOENT;
1147 	}
1148 
1149 	err = emc_init(emc);
1150 	if (err) {
1151 		dev_err(&pdev->dev, "EMC initialization failed: %d\n", err);
1152 		return err;
1153 	}
1154 
1155 	platform_set_drvdata(pdev, emc);
1156 
1157 	if (IS_ENABLED(CONFIG_DEBUG_FS))
1158 		emc_debugfs_init(&pdev->dev, emc);
1159 
1160 	return 0;
1161 };
1162 
1163 static struct platform_driver tegra_emc_driver = {
1164 	.probe = tegra_emc_probe,
1165 	.driver = {
1166 		.name = "tegra-emc",
1167 		.of_match_table = tegra_emc_of_match,
1168 		.suppress_bind_attrs = true,
1169 	},
1170 };
1171 
1172 static int tegra_emc_init(void)
1173 {
1174 	return platform_driver_register(&tegra_emc_driver);
1175 }
1176 subsys_initcall(tegra_emc_init);
1177