1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/export.h> 10 #include <linux/interrupt.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 #include <linux/sort.h> 18 19 #include <soc/tegra/fuse.h> 20 21 #include "mc.h" 22 23 static const struct of_device_id tegra_mc_of_match[] = { 24 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 25 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc }, 26 #endif 27 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 28 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc }, 29 #endif 30 #ifdef CONFIG_ARCH_TEGRA_114_SOC 31 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc }, 32 #endif 33 #ifdef CONFIG_ARCH_TEGRA_124_SOC 34 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc }, 35 #endif 36 #ifdef CONFIG_ARCH_TEGRA_132_SOC 37 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc }, 38 #endif 39 #ifdef CONFIG_ARCH_TEGRA_210_SOC 40 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc }, 41 #endif 42 { } 43 }; 44 MODULE_DEVICE_TABLE(of, tegra_mc_of_match); 45 46 static void tegra_mc_devm_action_put_device(void *data) 47 { 48 struct tegra_mc *mc = data; 49 50 put_device(mc->dev); 51 } 52 53 /** 54 * devm_tegra_memory_controller_get() - get Tegra Memory Controller handle 55 * @dev: device pointer for the consumer device 56 * 57 * This function will search for the Memory Controller node in a device-tree 58 * and retrieve the Memory Controller handle. 59 * 60 * Return: ERR_PTR() on error or a valid pointer to a struct tegra_mc. 61 */ 62 struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev) 63 { 64 struct platform_device *pdev; 65 struct device_node *np; 66 struct tegra_mc *mc; 67 int err; 68 69 np = of_parse_phandle(dev->of_node, "nvidia,memory-controller", 0); 70 if (!np) 71 return ERR_PTR(-ENOENT); 72 73 pdev = of_find_device_by_node(np); 74 of_node_put(np); 75 if (!pdev) 76 return ERR_PTR(-ENODEV); 77 78 mc = platform_get_drvdata(pdev); 79 if (!mc) { 80 put_device(&pdev->dev); 81 return ERR_PTR(-EPROBE_DEFER); 82 } 83 84 err = devm_add_action(dev, tegra_mc_devm_action_put_device, mc); 85 if (err) { 86 put_device(mc->dev); 87 return ERR_PTR(err); 88 } 89 90 return mc; 91 } 92 EXPORT_SYMBOL_GPL(devm_tegra_memory_controller_get); 93 94 static int tegra_mc_block_dma_common(struct tegra_mc *mc, 95 const struct tegra_mc_reset *rst) 96 { 97 unsigned long flags; 98 u32 value; 99 100 spin_lock_irqsave(&mc->lock, flags); 101 102 value = mc_readl(mc, rst->control) | BIT(rst->bit); 103 mc_writel(mc, value, rst->control); 104 105 spin_unlock_irqrestore(&mc->lock, flags); 106 107 return 0; 108 } 109 110 static bool tegra_mc_dma_idling_common(struct tegra_mc *mc, 111 const struct tegra_mc_reset *rst) 112 { 113 return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; 114 } 115 116 static int tegra_mc_unblock_dma_common(struct tegra_mc *mc, 117 const struct tegra_mc_reset *rst) 118 { 119 unsigned long flags; 120 u32 value; 121 122 spin_lock_irqsave(&mc->lock, flags); 123 124 value = mc_readl(mc, rst->control) & ~BIT(rst->bit); 125 mc_writel(mc, value, rst->control); 126 127 spin_unlock_irqrestore(&mc->lock, flags); 128 129 return 0; 130 } 131 132 static int tegra_mc_reset_status_common(struct tegra_mc *mc, 133 const struct tegra_mc_reset *rst) 134 { 135 return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; 136 } 137 138 const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = { 139 .block_dma = tegra_mc_block_dma_common, 140 .dma_idling = tegra_mc_dma_idling_common, 141 .unblock_dma = tegra_mc_unblock_dma_common, 142 .reset_status = tegra_mc_reset_status_common, 143 }; 144 145 static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev) 146 { 147 return container_of(rcdev, struct tegra_mc, reset); 148 } 149 150 static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc, 151 unsigned long id) 152 { 153 unsigned int i; 154 155 for (i = 0; i < mc->soc->num_resets; i++) 156 if (mc->soc->resets[i].id == id) 157 return &mc->soc->resets[i]; 158 159 return NULL; 160 } 161 162 static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev, 163 unsigned long id) 164 { 165 struct tegra_mc *mc = reset_to_mc(rcdev); 166 const struct tegra_mc_reset_ops *rst_ops; 167 const struct tegra_mc_reset *rst; 168 int retries = 500; 169 int err; 170 171 rst = tegra_mc_reset_find(mc, id); 172 if (!rst) 173 return -ENODEV; 174 175 rst_ops = mc->soc->reset_ops; 176 if (!rst_ops) 177 return -ENODEV; 178 179 /* DMA flushing will fail if reset is already asserted */ 180 if (rst_ops->reset_status) { 181 /* check whether reset is asserted */ 182 if (rst_ops->reset_status(mc, rst)) 183 return 0; 184 } 185 186 if (rst_ops->block_dma) { 187 /* block clients DMA requests */ 188 err = rst_ops->block_dma(mc, rst); 189 if (err) { 190 dev_err(mc->dev, "failed to block %s DMA: %d\n", 191 rst->name, err); 192 return err; 193 } 194 } 195 196 if (rst_ops->dma_idling) { 197 /* wait for completion of the outstanding DMA requests */ 198 while (!rst_ops->dma_idling(mc, rst)) { 199 if (!retries--) { 200 dev_err(mc->dev, "failed to flush %s DMA\n", 201 rst->name); 202 return -EBUSY; 203 } 204 205 usleep_range(10, 100); 206 } 207 } 208 209 if (rst_ops->hotreset_assert) { 210 /* clear clients DMA requests sitting before arbitration */ 211 err = rst_ops->hotreset_assert(mc, rst); 212 if (err) { 213 dev_err(mc->dev, "failed to hot reset %s: %d\n", 214 rst->name, err); 215 return err; 216 } 217 } 218 219 return 0; 220 } 221 222 static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev, 223 unsigned long id) 224 { 225 struct tegra_mc *mc = reset_to_mc(rcdev); 226 const struct tegra_mc_reset_ops *rst_ops; 227 const struct tegra_mc_reset *rst; 228 int err; 229 230 rst = tegra_mc_reset_find(mc, id); 231 if (!rst) 232 return -ENODEV; 233 234 rst_ops = mc->soc->reset_ops; 235 if (!rst_ops) 236 return -ENODEV; 237 238 if (rst_ops->hotreset_deassert) { 239 /* take out client from hot reset */ 240 err = rst_ops->hotreset_deassert(mc, rst); 241 if (err) { 242 dev_err(mc->dev, "failed to deassert hot reset %s: %d\n", 243 rst->name, err); 244 return err; 245 } 246 } 247 248 if (rst_ops->unblock_dma) { 249 /* allow new DMA requests to proceed to arbitration */ 250 err = rst_ops->unblock_dma(mc, rst); 251 if (err) { 252 dev_err(mc->dev, "failed to unblock %s DMA : %d\n", 253 rst->name, err); 254 return err; 255 } 256 } 257 258 return 0; 259 } 260 261 static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev, 262 unsigned long id) 263 { 264 struct tegra_mc *mc = reset_to_mc(rcdev); 265 const struct tegra_mc_reset_ops *rst_ops; 266 const struct tegra_mc_reset *rst; 267 268 rst = tegra_mc_reset_find(mc, id); 269 if (!rst) 270 return -ENODEV; 271 272 rst_ops = mc->soc->reset_ops; 273 if (!rst_ops) 274 return -ENODEV; 275 276 return rst_ops->reset_status(mc, rst); 277 } 278 279 static const struct reset_control_ops tegra_mc_reset_ops = { 280 .assert = tegra_mc_hotreset_assert, 281 .deassert = tegra_mc_hotreset_deassert, 282 .status = tegra_mc_hotreset_status, 283 }; 284 285 static int tegra_mc_reset_setup(struct tegra_mc *mc) 286 { 287 int err; 288 289 mc->reset.ops = &tegra_mc_reset_ops; 290 mc->reset.owner = THIS_MODULE; 291 mc->reset.of_node = mc->dev->of_node; 292 mc->reset.of_reset_n_cells = 1; 293 mc->reset.nr_resets = mc->soc->num_resets; 294 295 err = reset_controller_register(&mc->reset); 296 if (err < 0) 297 return err; 298 299 return 0; 300 } 301 302 int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) 303 { 304 unsigned int i; 305 struct tegra_mc_timing *timing = NULL; 306 307 for (i = 0; i < mc->num_timings; i++) { 308 if (mc->timings[i].rate == rate) { 309 timing = &mc->timings[i]; 310 break; 311 } 312 } 313 314 if (!timing) { 315 dev_err(mc->dev, "no memory timing registered for rate %lu\n", 316 rate); 317 return -EINVAL; 318 } 319 320 for (i = 0; i < mc->soc->num_emem_regs; ++i) 321 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); 322 323 return 0; 324 } 325 EXPORT_SYMBOL_GPL(tegra_mc_write_emem_configuration); 326 327 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) 328 { 329 u8 dram_count; 330 331 dram_count = mc_readl(mc, MC_EMEM_ADR_CFG); 332 dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV; 333 dram_count++; 334 335 return dram_count; 336 } 337 EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count); 338 339 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ 340 defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 341 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 342 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 343 defined(CONFIG_ARCH_TEGRA_210_SOC) 344 static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) 345 { 346 unsigned long long tick; 347 unsigned int i; 348 u32 value; 349 350 /* compute the number of MC clock cycles per tick */ 351 tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk); 352 do_div(tick, NSEC_PER_SEC); 353 354 value = mc_readl(mc, MC_EMEM_ARB_CFG); 355 value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK; 356 value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick); 357 mc_writel(mc, value, MC_EMEM_ARB_CFG); 358 359 /* write latency allowance defaults */ 360 for (i = 0; i < mc->soc->num_clients; i++) { 361 const struct tegra_mc_client *client = &mc->soc->clients[i]; 362 u32 value; 363 364 value = mc_readl(mc, client->regs.la.reg); 365 value &= ~(client->regs.la.mask << client->regs.la.shift); 366 value |= (client->regs.la.def & client->regs.la.mask) << client->regs.la.shift; 367 mc_writel(mc, value, client->regs.la.reg); 368 } 369 370 /* latch new values */ 371 mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); 372 373 return 0; 374 } 375 376 static int load_one_timing(struct tegra_mc *mc, 377 struct tegra_mc_timing *timing, 378 struct device_node *node) 379 { 380 int err; 381 u32 tmp; 382 383 err = of_property_read_u32(node, "clock-frequency", &tmp); 384 if (err) { 385 dev_err(mc->dev, 386 "timing %pOFn: failed to read rate\n", node); 387 return err; 388 } 389 390 timing->rate = tmp; 391 timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, 392 sizeof(u32), GFP_KERNEL); 393 if (!timing->emem_data) 394 return -ENOMEM; 395 396 err = of_property_read_u32_array(node, "nvidia,emem-configuration", 397 timing->emem_data, 398 mc->soc->num_emem_regs); 399 if (err) { 400 dev_err(mc->dev, 401 "timing %pOFn: failed to read EMEM configuration\n", 402 node); 403 return err; 404 } 405 406 return 0; 407 } 408 409 static int load_timings(struct tegra_mc *mc, struct device_node *node) 410 { 411 struct device_node *child; 412 struct tegra_mc_timing *timing; 413 int child_count = of_get_child_count(node); 414 int i = 0, err; 415 416 mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing), 417 GFP_KERNEL); 418 if (!mc->timings) 419 return -ENOMEM; 420 421 mc->num_timings = child_count; 422 423 for_each_child_of_node(node, child) { 424 timing = &mc->timings[i++]; 425 426 err = load_one_timing(mc, timing, child); 427 if (err) { 428 of_node_put(child); 429 return err; 430 } 431 } 432 433 return 0; 434 } 435 436 static int tegra_mc_setup_timings(struct tegra_mc *mc) 437 { 438 struct device_node *node; 439 u32 ram_code, node_ram_code; 440 int err; 441 442 ram_code = tegra_read_ram_code(); 443 444 mc->num_timings = 0; 445 446 for_each_child_of_node(mc->dev->of_node, node) { 447 err = of_property_read_u32(node, "nvidia,ram-code", 448 &node_ram_code); 449 if (err || (node_ram_code != ram_code)) 450 continue; 451 452 err = load_timings(mc, node); 453 of_node_put(node); 454 if (err) 455 return err; 456 break; 457 } 458 459 if (mc->num_timings == 0) 460 dev_warn(mc->dev, 461 "no memory timings for RAM code %u registered\n", 462 ram_code); 463 464 return 0; 465 } 466 467 int tegra30_mc_probe(struct tegra_mc *mc) 468 { 469 int err; 470 471 mc->clk = devm_clk_get_optional(mc->dev, "mc"); 472 if (IS_ERR(mc->clk)) { 473 dev_err(mc->dev, "failed to get MC clock: %ld\n", PTR_ERR(mc->clk)); 474 return PTR_ERR(mc->clk); 475 } 476 477 /* ensure that debug features are disabled */ 478 mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG); 479 480 err = tegra_mc_setup_latency_allowance(mc); 481 if (err < 0) { 482 dev_err(mc->dev, "failed to setup latency allowance: %d\n", err); 483 return err; 484 } 485 486 err = tegra_mc_setup_timings(mc); 487 if (err < 0) { 488 dev_err(mc->dev, "failed to setup timings: %d\n", err); 489 return err; 490 } 491 492 return 0; 493 } 494 495 static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) 496 { 497 struct tegra_mc *mc = data; 498 unsigned long status; 499 unsigned int bit; 500 501 /* mask all interrupts to avoid flooding */ 502 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; 503 if (!status) 504 return IRQ_NONE; 505 506 for_each_set_bit(bit, &status, 32) { 507 const char *error = tegra_mc_status_names[bit] ?: "unknown"; 508 const char *client = "unknown", *desc; 509 const char *direction, *secure; 510 phys_addr_t addr = 0; 511 unsigned int i; 512 char perm[7]; 513 u8 id, type; 514 u32 value; 515 516 value = mc_readl(mc, MC_ERR_STATUS); 517 518 #ifdef CONFIG_PHYS_ADDR_T_64BIT 519 if (mc->soc->num_address_bits > 32) { 520 addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & 521 MC_ERR_STATUS_ADR_HI_MASK); 522 addr <<= 32; 523 } 524 #endif 525 526 if (value & MC_ERR_STATUS_RW) 527 direction = "write"; 528 else 529 direction = "read"; 530 531 if (value & MC_ERR_STATUS_SECURITY) 532 secure = "secure "; 533 else 534 secure = ""; 535 536 id = value & mc->soc->client_id_mask; 537 538 for (i = 0; i < mc->soc->num_clients; i++) { 539 if (mc->soc->clients[i].id == id) { 540 client = mc->soc->clients[i].name; 541 break; 542 } 543 } 544 545 type = (value & MC_ERR_STATUS_TYPE_MASK) >> 546 MC_ERR_STATUS_TYPE_SHIFT; 547 desc = tegra_mc_error_names[type]; 548 549 switch (value & MC_ERR_STATUS_TYPE_MASK) { 550 case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE: 551 perm[0] = ' '; 552 perm[1] = '['; 553 554 if (value & MC_ERR_STATUS_READABLE) 555 perm[2] = 'R'; 556 else 557 perm[2] = '-'; 558 559 if (value & MC_ERR_STATUS_WRITABLE) 560 perm[3] = 'W'; 561 else 562 perm[3] = '-'; 563 564 if (value & MC_ERR_STATUS_NONSECURE) 565 perm[4] = '-'; 566 else 567 perm[4] = 'S'; 568 569 perm[5] = ']'; 570 perm[6] = '\0'; 571 break; 572 573 default: 574 perm[0] = '\0'; 575 break; 576 } 577 578 value = mc_readl(mc, MC_ERR_ADR); 579 addr |= value; 580 581 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", 582 client, secure, direction, &addr, error, 583 desc, perm); 584 } 585 586 /* clear interrupts */ 587 mc_writel(mc, status, MC_INTSTATUS); 588 589 return IRQ_HANDLED; 590 } 591 592 const struct tegra_mc_ops tegra30_mc_ops = { 593 .probe = tegra30_mc_probe, 594 .handle_irq = tegra30_mc_handle_irq, 595 }; 596 #endif 597 598 const char *const tegra_mc_status_names[32] = { 599 [ 1] = "External interrupt", 600 [ 6] = "EMEM address decode error", 601 [ 7] = "GART page fault", 602 [ 8] = "Security violation", 603 [ 9] = "EMEM arbitration error", 604 [10] = "Page fault", 605 [11] = "Invalid APB ASID update", 606 [12] = "VPR violation", 607 [13] = "Secure carveout violation", 608 [16] = "MTS carveout violation", 609 }; 610 611 const char *const tegra_mc_error_names[8] = { 612 [2] = "EMEM decode error", 613 [3] = "TrustZone violation", 614 [4] = "Carveout violation", 615 [6] = "SMMU translation error", 616 }; 617 618 /* 619 * Memory Controller (MC) has few Memory Clients that are issuing memory 620 * bandwidth allocation requests to the MC interconnect provider. The MC 621 * provider aggregates the requests and then sends the aggregated request 622 * up to the External Memory Controller (EMC) interconnect provider which 623 * re-configures hardware interface to External Memory (EMEM) in accordance 624 * to the required bandwidth. Each MC interconnect node represents an 625 * individual Memory Client. 626 * 627 * Memory interconnect topology: 628 * 629 * +----+ 630 * +--------+ | | 631 * | TEXSRD +--->+ | 632 * +--------+ | | 633 * | | +-----+ +------+ 634 * ... | MC +--->+ EMC +--->+ EMEM | 635 * | | +-----+ +------+ 636 * +--------+ | | 637 * | DISP.. +--->+ | 638 * +--------+ | | 639 * +----+ 640 */ 641 static int tegra_mc_interconnect_setup(struct tegra_mc *mc) 642 { 643 struct icc_node *node; 644 unsigned int i; 645 int err; 646 647 /* older device-trees don't have interconnect properties */ 648 if (!device_property_present(mc->dev, "#interconnect-cells") || 649 !mc->soc->icc_ops) 650 return 0; 651 652 mc->provider.dev = mc->dev; 653 mc->provider.data = &mc->provider; 654 mc->provider.set = mc->soc->icc_ops->set; 655 mc->provider.aggregate = mc->soc->icc_ops->aggregate; 656 mc->provider.xlate_extended = mc->soc->icc_ops->xlate_extended; 657 658 err = icc_provider_add(&mc->provider); 659 if (err) 660 return err; 661 662 /* create Memory Controller node */ 663 node = icc_node_create(TEGRA_ICC_MC); 664 if (IS_ERR(node)) { 665 err = PTR_ERR(node); 666 goto del_provider; 667 } 668 669 node->name = "Memory Controller"; 670 icc_node_add(node, &mc->provider); 671 672 /* link Memory Controller to External Memory Controller */ 673 err = icc_link_create(node, TEGRA_ICC_EMC); 674 if (err) 675 goto remove_nodes; 676 677 for (i = 0; i < mc->soc->num_clients; i++) { 678 /* create MC client node */ 679 node = icc_node_create(mc->soc->clients[i].id); 680 if (IS_ERR(node)) { 681 err = PTR_ERR(node); 682 goto remove_nodes; 683 } 684 685 node->name = mc->soc->clients[i].name; 686 icc_node_add(node, &mc->provider); 687 688 /* link Memory Client to Memory Controller */ 689 err = icc_link_create(node, TEGRA_ICC_MC); 690 if (err) 691 goto remove_nodes; 692 } 693 694 /* 695 * MC driver is registered too early, so early that generic driver 696 * syncing doesn't work for the MC. But it doesn't really matter 697 * since syncing works for the EMC drivers, hence we can sync the 698 * MC driver by ourselves and then EMC will complete syncing of 699 * the whole ICC state. 700 */ 701 icc_sync_state(mc->dev); 702 703 return 0; 704 705 remove_nodes: 706 icc_nodes_remove(&mc->provider); 707 del_provider: 708 icc_provider_del(&mc->provider); 709 710 return err; 711 } 712 713 static int tegra_mc_probe(struct platform_device *pdev) 714 { 715 struct resource *res; 716 struct tegra_mc *mc; 717 u64 mask; 718 int err; 719 720 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); 721 if (!mc) 722 return -ENOMEM; 723 724 platform_set_drvdata(pdev, mc); 725 spin_lock_init(&mc->lock); 726 mc->soc = of_device_get_match_data(&pdev->dev); 727 mc->dev = &pdev->dev; 728 729 mask = DMA_BIT_MASK(mc->soc->num_address_bits); 730 731 err = dma_coerce_mask_and_coherent(&pdev->dev, mask); 732 if (err < 0) { 733 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 734 return err; 735 } 736 737 /* length of MC tick in nanoseconds */ 738 mc->tick = 30; 739 740 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 741 mc->regs = devm_ioremap_resource(&pdev->dev, res); 742 if (IS_ERR(mc->regs)) 743 return PTR_ERR(mc->regs); 744 745 mc->debugfs.root = debugfs_create_dir("mc", NULL); 746 747 if (mc->soc->ops && mc->soc->ops->probe) { 748 err = mc->soc->ops->probe(mc); 749 if (err < 0) 750 return err; 751 } 752 753 if (mc->soc->ops && mc->soc->ops->handle_irq) { 754 mc->irq = platform_get_irq(pdev, 0); 755 if (mc->irq < 0) 756 return mc->irq; 757 758 WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); 759 760 mc_writel(mc, mc->soc->intmask, MC_INTMASK); 761 762 err = devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, 0, 763 dev_name(&pdev->dev), mc); 764 if (err < 0) { 765 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, 766 err); 767 return err; 768 } 769 } 770 771 err = tegra_mc_reset_setup(mc); 772 if (err < 0) 773 dev_err(&pdev->dev, "failed to register reset controller: %d\n", 774 err); 775 776 err = tegra_mc_interconnect_setup(mc); 777 if (err < 0) 778 dev_err(&pdev->dev, "failed to initialize interconnect: %d\n", 779 err); 780 781 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) { 782 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); 783 if (IS_ERR(mc->smmu)) { 784 dev_err(&pdev->dev, "failed to probe SMMU: %ld\n", 785 PTR_ERR(mc->smmu)); 786 mc->smmu = NULL; 787 } 788 } 789 790 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && !mc->soc->smmu) { 791 mc->gart = tegra_gart_probe(&pdev->dev, mc); 792 if (IS_ERR(mc->gart)) { 793 dev_err(&pdev->dev, "failed to probe GART: %ld\n", 794 PTR_ERR(mc->gart)); 795 mc->gart = NULL; 796 } 797 } 798 799 return 0; 800 } 801 802 static int __maybe_unused tegra_mc_suspend(struct device *dev) 803 { 804 struct tegra_mc *mc = dev_get_drvdata(dev); 805 806 if (mc->soc->ops && mc->soc->ops->suspend) 807 return mc->soc->ops->suspend(mc); 808 809 return 0; 810 } 811 812 static int __maybe_unused tegra_mc_resume(struct device *dev) 813 { 814 struct tegra_mc *mc = dev_get_drvdata(dev); 815 816 if (mc->soc->ops && mc->soc->ops->resume) 817 return mc->soc->ops->resume(mc); 818 819 return 0; 820 } 821 822 static const struct dev_pm_ops tegra_mc_pm_ops = { 823 SET_SYSTEM_SLEEP_PM_OPS(tegra_mc_suspend, tegra_mc_resume) 824 }; 825 826 static struct platform_driver tegra_mc_driver = { 827 .driver = { 828 .name = "tegra-mc", 829 .of_match_table = tegra_mc_of_match, 830 .pm = &tegra_mc_pm_ops, 831 .suppress_bind_attrs = true, 832 }, 833 .prevent_deferred_probe = true, 834 .probe = tegra_mc_probe, 835 }; 836 837 static int tegra_mc_init(void) 838 { 839 return platform_driver_register(&tegra_mc_driver); 840 } 841 arch_initcall(tegra_mc_init); 842 843 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 844 MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver"); 845 MODULE_LICENSE("GPL v2"); 846