1 /* 2 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/interrupt.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/slab.h> 16 #include <linux/sort.h> 17 18 #include <soc/tegra/fuse.h> 19 20 #include "mc.h" 21 22 #define MC_INTSTATUS 0x000 23 #define MC_INT_DECERR_MTS (1 << 16) 24 #define MC_INT_SECERR_SEC (1 << 13) 25 #define MC_INT_DECERR_VPR (1 << 12) 26 #define MC_INT_INVALID_APB_ASID_UPDATE (1 << 11) 27 #define MC_INT_INVALID_SMMU_PAGE (1 << 10) 28 #define MC_INT_ARBITRATION_EMEM (1 << 9) 29 #define MC_INT_SECURITY_VIOLATION (1 << 8) 30 #define MC_INT_DECERR_EMEM (1 << 6) 31 32 #define MC_INTMASK 0x004 33 34 #define MC_ERR_STATUS 0x08 35 #define MC_ERR_STATUS_TYPE_SHIFT 28 36 #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT) 37 #define MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT) 38 #define MC_ERR_STATUS_READABLE (1 << 27) 39 #define MC_ERR_STATUS_WRITABLE (1 << 26) 40 #define MC_ERR_STATUS_NONSECURE (1 << 25) 41 #define MC_ERR_STATUS_ADR_HI_SHIFT 20 42 #define MC_ERR_STATUS_ADR_HI_MASK 0x3 43 #define MC_ERR_STATUS_SECURITY (1 << 17) 44 #define MC_ERR_STATUS_RW (1 << 16) 45 #define MC_ERR_STATUS_CLIENT_MASK 0x7f 46 47 #define MC_ERR_ADR 0x0c 48 49 #define MC_EMEM_ARB_CFG 0x90 50 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0) 51 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff 52 #define MC_EMEM_ARB_MISC0 0xd8 53 54 #define MC_EMEM_ADR_CFG 0x54 55 #define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0) 56 57 static const struct of_device_id tegra_mc_of_match[] = { 58 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 59 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc }, 60 #endif 61 #ifdef CONFIG_ARCH_TEGRA_114_SOC 62 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc }, 63 #endif 64 #ifdef CONFIG_ARCH_TEGRA_124_SOC 65 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc }, 66 #endif 67 #ifdef CONFIG_ARCH_TEGRA_132_SOC 68 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc }, 69 #endif 70 { } 71 }; 72 MODULE_DEVICE_TABLE(of, tegra_mc_of_match); 73 74 static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) 75 { 76 unsigned long long tick; 77 unsigned int i; 78 u32 value; 79 80 /* compute the number of MC clock cycles per tick */ 81 tick = mc->tick * clk_get_rate(mc->clk); 82 do_div(tick, NSEC_PER_SEC); 83 84 value = readl(mc->regs + MC_EMEM_ARB_CFG); 85 value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK; 86 value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick); 87 writel(value, mc->regs + MC_EMEM_ARB_CFG); 88 89 /* write latency allowance defaults */ 90 for (i = 0; i < mc->soc->num_clients; i++) { 91 const struct tegra_mc_la *la = &mc->soc->clients[i].la; 92 u32 value; 93 94 value = readl(mc->regs + la->reg); 95 value &= ~(la->mask << la->shift); 96 value |= (la->def & la->mask) << la->shift; 97 writel(value, mc->regs + la->reg); 98 } 99 100 return 0; 101 } 102 103 void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) 104 { 105 unsigned int i; 106 struct tegra_mc_timing *timing = NULL; 107 108 for (i = 0; i < mc->num_timings; i++) { 109 if (mc->timings[i].rate == rate) { 110 timing = &mc->timings[i]; 111 break; 112 } 113 } 114 115 if (!timing) { 116 dev_err(mc->dev, "no memory timing registered for rate %lu\n", 117 rate); 118 return; 119 } 120 121 for (i = 0; i < mc->soc->num_emem_regs; ++i) 122 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); 123 } 124 125 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) 126 { 127 u8 dram_count; 128 129 dram_count = mc_readl(mc, MC_EMEM_ADR_CFG); 130 dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV; 131 dram_count++; 132 133 return dram_count; 134 } 135 136 static int load_one_timing(struct tegra_mc *mc, 137 struct tegra_mc_timing *timing, 138 struct device_node *node) 139 { 140 int err; 141 u32 tmp; 142 143 err = of_property_read_u32(node, "clock-frequency", &tmp); 144 if (err) { 145 dev_err(mc->dev, 146 "timing %s: failed to read rate\n", node->name); 147 return err; 148 } 149 150 timing->rate = tmp; 151 timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, 152 sizeof(u32), GFP_KERNEL); 153 if (!timing->emem_data) 154 return -ENOMEM; 155 156 err = of_property_read_u32_array(node, "nvidia,emem-configuration", 157 timing->emem_data, 158 mc->soc->num_emem_regs); 159 if (err) { 160 dev_err(mc->dev, 161 "timing %s: failed to read EMEM configuration\n", 162 node->name); 163 return err; 164 } 165 166 return 0; 167 } 168 169 static int load_timings(struct tegra_mc *mc, struct device_node *node) 170 { 171 struct device_node *child; 172 struct tegra_mc_timing *timing; 173 int child_count = of_get_child_count(node); 174 int i = 0, err; 175 176 mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing), 177 GFP_KERNEL); 178 if (!mc->timings) 179 return -ENOMEM; 180 181 mc->num_timings = child_count; 182 183 for_each_child_of_node(node, child) { 184 timing = &mc->timings[i++]; 185 186 err = load_one_timing(mc, timing, child); 187 if (err) 188 return err; 189 } 190 191 return 0; 192 } 193 194 static int tegra_mc_setup_timings(struct tegra_mc *mc) 195 { 196 struct device_node *node; 197 u32 ram_code, node_ram_code; 198 int err; 199 200 ram_code = tegra_read_ram_code(); 201 202 mc->num_timings = 0; 203 204 for_each_child_of_node(mc->dev->of_node, node) { 205 err = of_property_read_u32(node, "nvidia,ram-code", 206 &node_ram_code); 207 if (err || (node_ram_code != ram_code)) { 208 of_node_put(node); 209 continue; 210 } 211 212 err = load_timings(mc, node); 213 if (err) 214 return err; 215 of_node_put(node); 216 break; 217 } 218 219 if (mc->num_timings == 0) 220 dev_warn(mc->dev, 221 "no memory timings for RAM code %u registered\n", 222 ram_code); 223 224 return 0; 225 } 226 227 static const char *const status_names[32] = { 228 [ 1] = "External interrupt", 229 [ 6] = "EMEM address decode error", 230 [ 8] = "Security violation", 231 [ 9] = "EMEM arbitration error", 232 [10] = "Page fault", 233 [11] = "Invalid APB ASID update", 234 [12] = "VPR violation", 235 [13] = "Secure carveout violation", 236 [16] = "MTS carveout violation", 237 }; 238 239 static const char *const error_names[8] = { 240 [2] = "EMEM decode error", 241 [3] = "TrustZone violation", 242 [4] = "Carveout violation", 243 [6] = "SMMU translation error", 244 }; 245 246 static irqreturn_t tegra_mc_irq(int irq, void *data) 247 { 248 struct tegra_mc *mc = data; 249 unsigned long status, mask; 250 unsigned int bit; 251 252 /* mask all interrupts to avoid flooding */ 253 status = mc_readl(mc, MC_INTSTATUS); 254 mask = mc_readl(mc, MC_INTMASK); 255 256 for_each_set_bit(bit, &status, 32) { 257 const char *error = status_names[bit] ?: "unknown"; 258 const char *client = "unknown", *desc; 259 const char *direction, *secure; 260 phys_addr_t addr = 0; 261 unsigned int i; 262 char perm[7]; 263 u8 id, type; 264 u32 value; 265 266 value = mc_readl(mc, MC_ERR_STATUS); 267 268 #ifdef CONFIG_PHYS_ADDR_T_64BIT 269 if (mc->soc->num_address_bits > 32) { 270 addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & 271 MC_ERR_STATUS_ADR_HI_MASK); 272 addr <<= 32; 273 } 274 #endif 275 276 if (value & MC_ERR_STATUS_RW) 277 direction = "write"; 278 else 279 direction = "read"; 280 281 if (value & MC_ERR_STATUS_SECURITY) 282 secure = "secure "; 283 else 284 secure = ""; 285 286 id = value & MC_ERR_STATUS_CLIENT_MASK; 287 288 for (i = 0; i < mc->soc->num_clients; i++) { 289 if (mc->soc->clients[i].id == id) { 290 client = mc->soc->clients[i].name; 291 break; 292 } 293 } 294 295 type = (value & MC_ERR_STATUS_TYPE_MASK) >> 296 MC_ERR_STATUS_TYPE_SHIFT; 297 desc = error_names[type]; 298 299 switch (value & MC_ERR_STATUS_TYPE_MASK) { 300 case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE: 301 perm[0] = ' '; 302 perm[1] = '['; 303 304 if (value & MC_ERR_STATUS_READABLE) 305 perm[2] = 'R'; 306 else 307 perm[2] = '-'; 308 309 if (value & MC_ERR_STATUS_WRITABLE) 310 perm[3] = 'W'; 311 else 312 perm[3] = '-'; 313 314 if (value & MC_ERR_STATUS_NONSECURE) 315 perm[4] = '-'; 316 else 317 perm[4] = 'S'; 318 319 perm[5] = ']'; 320 perm[6] = '\0'; 321 break; 322 323 default: 324 perm[0] = '\0'; 325 break; 326 } 327 328 value = mc_readl(mc, MC_ERR_ADR); 329 addr |= value; 330 331 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", 332 client, secure, direction, &addr, error, 333 desc, perm); 334 } 335 336 /* clear interrupts */ 337 mc_writel(mc, status, MC_INTSTATUS); 338 339 return IRQ_HANDLED; 340 } 341 342 static int tegra_mc_probe(struct platform_device *pdev) 343 { 344 const struct of_device_id *match; 345 struct resource *res; 346 struct tegra_mc *mc; 347 u32 value; 348 int err; 349 350 match = of_match_node(tegra_mc_of_match, pdev->dev.of_node); 351 if (!match) 352 return -ENODEV; 353 354 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); 355 if (!mc) 356 return -ENOMEM; 357 358 platform_set_drvdata(pdev, mc); 359 mc->soc = match->data; 360 mc->dev = &pdev->dev; 361 362 /* length of MC tick in nanoseconds */ 363 mc->tick = 30; 364 365 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 366 mc->regs = devm_ioremap_resource(&pdev->dev, res); 367 if (IS_ERR(mc->regs)) 368 return PTR_ERR(mc->regs); 369 370 mc->clk = devm_clk_get(&pdev->dev, "mc"); 371 if (IS_ERR(mc->clk)) { 372 dev_err(&pdev->dev, "failed to get MC clock: %ld\n", 373 PTR_ERR(mc->clk)); 374 return PTR_ERR(mc->clk); 375 } 376 377 err = tegra_mc_setup_latency_allowance(mc); 378 if (err < 0) { 379 dev_err(&pdev->dev, "failed to setup latency allowance: %d\n", 380 err); 381 return err; 382 } 383 384 err = tegra_mc_setup_timings(mc); 385 if (err < 0) { 386 dev_err(&pdev->dev, "failed to setup timings: %d\n", err); 387 return err; 388 } 389 390 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) { 391 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); 392 if (IS_ERR(mc->smmu)) { 393 dev_err(&pdev->dev, "failed to probe SMMU: %ld\n", 394 PTR_ERR(mc->smmu)); 395 return PTR_ERR(mc->smmu); 396 } 397 } 398 399 mc->irq = platform_get_irq(pdev, 0); 400 if (mc->irq < 0) { 401 dev_err(&pdev->dev, "interrupt not specified\n"); 402 return mc->irq; 403 } 404 405 err = devm_request_irq(&pdev->dev, mc->irq, tegra_mc_irq, IRQF_SHARED, 406 dev_name(&pdev->dev), mc); 407 if (err < 0) { 408 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, 409 err); 410 return err; 411 } 412 413 value = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | 414 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE | 415 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM; 416 417 mc_writel(mc, value, MC_INTMASK); 418 419 return 0; 420 } 421 422 static struct platform_driver tegra_mc_driver = { 423 .driver = { 424 .name = "tegra-mc", 425 .of_match_table = tegra_mc_of_match, 426 .suppress_bind_attrs = true, 427 }, 428 .prevent_deferred_probe = true, 429 .probe = tegra_mc_probe, 430 }; 431 432 static int tegra_mc_init(void) 433 { 434 return platform_driver_register(&tegra_mc_driver); 435 } 436 arch_initcall(tegra_mc_init); 437 438 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 439 MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver"); 440 MODULE_LICENSE("GPL v2"); 441