1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/export.h> 10 #include <linux/interrupt.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 #include <linux/sort.h> 18 19 #include <soc/tegra/fuse.h> 20 21 #include "mc.h" 22 23 static const struct of_device_id tegra_mc_of_match[] = { 24 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 25 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc }, 26 #endif 27 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 28 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc }, 29 #endif 30 #ifdef CONFIG_ARCH_TEGRA_114_SOC 31 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc }, 32 #endif 33 #ifdef CONFIG_ARCH_TEGRA_124_SOC 34 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc }, 35 #endif 36 #ifdef CONFIG_ARCH_TEGRA_132_SOC 37 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc }, 38 #endif 39 #ifdef CONFIG_ARCH_TEGRA_210_SOC 40 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc }, 41 #endif 42 #ifdef CONFIG_ARCH_TEGRA_186_SOC 43 { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc }, 44 #endif 45 #ifdef CONFIG_ARCH_TEGRA_194_SOC 46 { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc }, 47 #endif 48 { /* sentinel */ } 49 }; 50 MODULE_DEVICE_TABLE(of, tegra_mc_of_match); 51 52 static void tegra_mc_devm_action_put_device(void *data) 53 { 54 struct tegra_mc *mc = data; 55 56 put_device(mc->dev); 57 } 58 59 /** 60 * devm_tegra_memory_controller_get() - get Tegra Memory Controller handle 61 * @dev: device pointer for the consumer device 62 * 63 * This function will search for the Memory Controller node in a device-tree 64 * and retrieve the Memory Controller handle. 65 * 66 * Return: ERR_PTR() on error or a valid pointer to a struct tegra_mc. 67 */ 68 struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev) 69 { 70 struct platform_device *pdev; 71 struct device_node *np; 72 struct tegra_mc *mc; 73 int err; 74 75 np = of_parse_phandle(dev->of_node, "nvidia,memory-controller", 0); 76 if (!np) 77 return ERR_PTR(-ENOENT); 78 79 pdev = of_find_device_by_node(np); 80 of_node_put(np); 81 if (!pdev) 82 return ERR_PTR(-ENODEV); 83 84 mc = platform_get_drvdata(pdev); 85 if (!mc) { 86 put_device(&pdev->dev); 87 return ERR_PTR(-EPROBE_DEFER); 88 } 89 90 err = devm_add_action_or_reset(dev, tegra_mc_devm_action_put_device, mc); 91 if (err) 92 return ERR_PTR(err); 93 94 return mc; 95 } 96 EXPORT_SYMBOL_GPL(devm_tegra_memory_controller_get); 97 98 int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev) 99 { 100 if (mc->soc->ops && mc->soc->ops->probe_device) 101 return mc->soc->ops->probe_device(mc, dev); 102 103 return 0; 104 } 105 EXPORT_SYMBOL_GPL(tegra_mc_probe_device); 106 107 static int tegra_mc_block_dma_common(struct tegra_mc *mc, 108 const struct tegra_mc_reset *rst) 109 { 110 unsigned long flags; 111 u32 value; 112 113 spin_lock_irqsave(&mc->lock, flags); 114 115 value = mc_readl(mc, rst->control) | BIT(rst->bit); 116 mc_writel(mc, value, rst->control); 117 118 spin_unlock_irqrestore(&mc->lock, flags); 119 120 return 0; 121 } 122 123 static bool tegra_mc_dma_idling_common(struct tegra_mc *mc, 124 const struct tegra_mc_reset *rst) 125 { 126 return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; 127 } 128 129 static int tegra_mc_unblock_dma_common(struct tegra_mc *mc, 130 const struct tegra_mc_reset *rst) 131 { 132 unsigned long flags; 133 u32 value; 134 135 spin_lock_irqsave(&mc->lock, flags); 136 137 value = mc_readl(mc, rst->control) & ~BIT(rst->bit); 138 mc_writel(mc, value, rst->control); 139 140 spin_unlock_irqrestore(&mc->lock, flags); 141 142 return 0; 143 } 144 145 static int tegra_mc_reset_status_common(struct tegra_mc *mc, 146 const struct tegra_mc_reset *rst) 147 { 148 return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; 149 } 150 151 const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = { 152 .block_dma = tegra_mc_block_dma_common, 153 .dma_idling = tegra_mc_dma_idling_common, 154 .unblock_dma = tegra_mc_unblock_dma_common, 155 .reset_status = tegra_mc_reset_status_common, 156 }; 157 158 static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev) 159 { 160 return container_of(rcdev, struct tegra_mc, reset); 161 } 162 163 static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc, 164 unsigned long id) 165 { 166 unsigned int i; 167 168 for (i = 0; i < mc->soc->num_resets; i++) 169 if (mc->soc->resets[i].id == id) 170 return &mc->soc->resets[i]; 171 172 return NULL; 173 } 174 175 static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev, 176 unsigned long id) 177 { 178 struct tegra_mc *mc = reset_to_mc(rcdev); 179 const struct tegra_mc_reset_ops *rst_ops; 180 const struct tegra_mc_reset *rst; 181 int retries = 500; 182 int err; 183 184 rst = tegra_mc_reset_find(mc, id); 185 if (!rst) 186 return -ENODEV; 187 188 rst_ops = mc->soc->reset_ops; 189 if (!rst_ops) 190 return -ENODEV; 191 192 /* DMA flushing will fail if reset is already asserted */ 193 if (rst_ops->reset_status) { 194 /* check whether reset is asserted */ 195 if (rst_ops->reset_status(mc, rst)) 196 return 0; 197 } 198 199 if (rst_ops->block_dma) { 200 /* block clients DMA requests */ 201 err = rst_ops->block_dma(mc, rst); 202 if (err) { 203 dev_err(mc->dev, "failed to block %s DMA: %d\n", 204 rst->name, err); 205 return err; 206 } 207 } 208 209 if (rst_ops->dma_idling) { 210 /* wait for completion of the outstanding DMA requests */ 211 while (!rst_ops->dma_idling(mc, rst)) { 212 if (!retries--) { 213 dev_err(mc->dev, "failed to flush %s DMA\n", 214 rst->name); 215 return -EBUSY; 216 } 217 218 usleep_range(10, 100); 219 } 220 } 221 222 if (rst_ops->hotreset_assert) { 223 /* clear clients DMA requests sitting before arbitration */ 224 err = rst_ops->hotreset_assert(mc, rst); 225 if (err) { 226 dev_err(mc->dev, "failed to hot reset %s: %d\n", 227 rst->name, err); 228 return err; 229 } 230 } 231 232 return 0; 233 } 234 235 static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev, 236 unsigned long id) 237 { 238 struct tegra_mc *mc = reset_to_mc(rcdev); 239 const struct tegra_mc_reset_ops *rst_ops; 240 const struct tegra_mc_reset *rst; 241 int err; 242 243 rst = tegra_mc_reset_find(mc, id); 244 if (!rst) 245 return -ENODEV; 246 247 rst_ops = mc->soc->reset_ops; 248 if (!rst_ops) 249 return -ENODEV; 250 251 if (rst_ops->hotreset_deassert) { 252 /* take out client from hot reset */ 253 err = rst_ops->hotreset_deassert(mc, rst); 254 if (err) { 255 dev_err(mc->dev, "failed to deassert hot reset %s: %d\n", 256 rst->name, err); 257 return err; 258 } 259 } 260 261 if (rst_ops->unblock_dma) { 262 /* allow new DMA requests to proceed to arbitration */ 263 err = rst_ops->unblock_dma(mc, rst); 264 if (err) { 265 dev_err(mc->dev, "failed to unblock %s DMA : %d\n", 266 rst->name, err); 267 return err; 268 } 269 } 270 271 return 0; 272 } 273 274 static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev, 275 unsigned long id) 276 { 277 struct tegra_mc *mc = reset_to_mc(rcdev); 278 const struct tegra_mc_reset_ops *rst_ops; 279 const struct tegra_mc_reset *rst; 280 281 rst = tegra_mc_reset_find(mc, id); 282 if (!rst) 283 return -ENODEV; 284 285 rst_ops = mc->soc->reset_ops; 286 if (!rst_ops) 287 return -ENODEV; 288 289 return rst_ops->reset_status(mc, rst); 290 } 291 292 static const struct reset_control_ops tegra_mc_reset_ops = { 293 .assert = tegra_mc_hotreset_assert, 294 .deassert = tegra_mc_hotreset_deassert, 295 .status = tegra_mc_hotreset_status, 296 }; 297 298 static int tegra_mc_reset_setup(struct tegra_mc *mc) 299 { 300 int err; 301 302 mc->reset.ops = &tegra_mc_reset_ops; 303 mc->reset.owner = THIS_MODULE; 304 mc->reset.of_node = mc->dev->of_node; 305 mc->reset.of_reset_n_cells = 1; 306 mc->reset.nr_resets = mc->soc->num_resets; 307 308 err = reset_controller_register(&mc->reset); 309 if (err < 0) 310 return err; 311 312 return 0; 313 } 314 315 int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) 316 { 317 unsigned int i; 318 struct tegra_mc_timing *timing = NULL; 319 320 for (i = 0; i < mc->num_timings; i++) { 321 if (mc->timings[i].rate == rate) { 322 timing = &mc->timings[i]; 323 break; 324 } 325 } 326 327 if (!timing) { 328 dev_err(mc->dev, "no memory timing registered for rate %lu\n", 329 rate); 330 return -EINVAL; 331 } 332 333 for (i = 0; i < mc->soc->num_emem_regs; ++i) 334 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); 335 336 return 0; 337 } 338 EXPORT_SYMBOL_GPL(tegra_mc_write_emem_configuration); 339 340 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) 341 { 342 u8 dram_count; 343 344 dram_count = mc_readl(mc, MC_EMEM_ADR_CFG); 345 dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV; 346 dram_count++; 347 348 return dram_count; 349 } 350 EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count); 351 352 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ 353 defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 354 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 355 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 356 defined(CONFIG_ARCH_TEGRA_210_SOC) 357 static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) 358 { 359 unsigned long long tick; 360 unsigned int i; 361 u32 value; 362 363 /* compute the number of MC clock cycles per tick */ 364 tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk); 365 do_div(tick, NSEC_PER_SEC); 366 367 value = mc_readl(mc, MC_EMEM_ARB_CFG); 368 value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK; 369 value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick); 370 mc_writel(mc, value, MC_EMEM_ARB_CFG); 371 372 /* write latency allowance defaults */ 373 for (i = 0; i < mc->soc->num_clients; i++) { 374 const struct tegra_mc_client *client = &mc->soc->clients[i]; 375 u32 value; 376 377 value = mc_readl(mc, client->regs.la.reg); 378 value &= ~(client->regs.la.mask << client->regs.la.shift); 379 value |= (client->regs.la.def & client->regs.la.mask) << client->regs.la.shift; 380 mc_writel(mc, value, client->regs.la.reg); 381 } 382 383 /* latch new values */ 384 mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); 385 386 return 0; 387 } 388 389 static int load_one_timing(struct tegra_mc *mc, 390 struct tegra_mc_timing *timing, 391 struct device_node *node) 392 { 393 int err; 394 u32 tmp; 395 396 err = of_property_read_u32(node, "clock-frequency", &tmp); 397 if (err) { 398 dev_err(mc->dev, 399 "timing %pOFn: failed to read rate\n", node); 400 return err; 401 } 402 403 timing->rate = tmp; 404 timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, 405 sizeof(u32), GFP_KERNEL); 406 if (!timing->emem_data) 407 return -ENOMEM; 408 409 err = of_property_read_u32_array(node, "nvidia,emem-configuration", 410 timing->emem_data, 411 mc->soc->num_emem_regs); 412 if (err) { 413 dev_err(mc->dev, 414 "timing %pOFn: failed to read EMEM configuration\n", 415 node); 416 return err; 417 } 418 419 return 0; 420 } 421 422 static int load_timings(struct tegra_mc *mc, struct device_node *node) 423 { 424 struct device_node *child; 425 struct tegra_mc_timing *timing; 426 int child_count = of_get_child_count(node); 427 int i = 0, err; 428 429 mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing), 430 GFP_KERNEL); 431 if (!mc->timings) 432 return -ENOMEM; 433 434 mc->num_timings = child_count; 435 436 for_each_child_of_node(node, child) { 437 timing = &mc->timings[i++]; 438 439 err = load_one_timing(mc, timing, child); 440 if (err) { 441 of_node_put(child); 442 return err; 443 } 444 } 445 446 return 0; 447 } 448 449 static int tegra_mc_setup_timings(struct tegra_mc *mc) 450 { 451 struct device_node *node; 452 u32 ram_code, node_ram_code; 453 int err; 454 455 ram_code = tegra_read_ram_code(); 456 457 mc->num_timings = 0; 458 459 for_each_child_of_node(mc->dev->of_node, node) { 460 err = of_property_read_u32(node, "nvidia,ram-code", 461 &node_ram_code); 462 if (err || (node_ram_code != ram_code)) 463 continue; 464 465 err = load_timings(mc, node); 466 of_node_put(node); 467 if (err) 468 return err; 469 break; 470 } 471 472 if (mc->num_timings == 0) 473 dev_warn(mc->dev, 474 "no memory timings for RAM code %u registered\n", 475 ram_code); 476 477 return 0; 478 } 479 480 int tegra30_mc_probe(struct tegra_mc *mc) 481 { 482 int err; 483 484 mc->clk = devm_clk_get_optional(mc->dev, "mc"); 485 if (IS_ERR(mc->clk)) { 486 dev_err(mc->dev, "failed to get MC clock: %ld\n", PTR_ERR(mc->clk)); 487 return PTR_ERR(mc->clk); 488 } 489 490 /* ensure that debug features are disabled */ 491 mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG); 492 493 err = tegra_mc_setup_latency_allowance(mc); 494 if (err < 0) { 495 dev_err(mc->dev, "failed to setup latency allowance: %d\n", err); 496 return err; 497 } 498 499 err = tegra_mc_setup_timings(mc); 500 if (err < 0) { 501 dev_err(mc->dev, "failed to setup timings: %d\n", err); 502 return err; 503 } 504 505 return 0; 506 } 507 508 static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) 509 { 510 struct tegra_mc *mc = data; 511 unsigned long status; 512 unsigned int bit; 513 514 /* mask all interrupts to avoid flooding */ 515 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; 516 if (!status) 517 return IRQ_NONE; 518 519 for_each_set_bit(bit, &status, 32) { 520 const char *error = tegra_mc_status_names[bit] ?: "unknown"; 521 const char *client = "unknown", *desc; 522 const char *direction, *secure; 523 phys_addr_t addr = 0; 524 unsigned int i; 525 char perm[7]; 526 u8 id, type; 527 u32 value; 528 529 value = mc_readl(mc, MC_ERR_STATUS); 530 531 #ifdef CONFIG_PHYS_ADDR_T_64BIT 532 if (mc->soc->num_address_bits > 32) { 533 addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & 534 MC_ERR_STATUS_ADR_HI_MASK); 535 addr <<= 32; 536 } 537 #endif 538 539 if (value & MC_ERR_STATUS_RW) 540 direction = "write"; 541 else 542 direction = "read"; 543 544 if (value & MC_ERR_STATUS_SECURITY) 545 secure = "secure "; 546 else 547 secure = ""; 548 549 id = value & mc->soc->client_id_mask; 550 551 for (i = 0; i < mc->soc->num_clients; i++) { 552 if (mc->soc->clients[i].id == id) { 553 client = mc->soc->clients[i].name; 554 break; 555 } 556 } 557 558 type = (value & MC_ERR_STATUS_TYPE_MASK) >> 559 MC_ERR_STATUS_TYPE_SHIFT; 560 desc = tegra_mc_error_names[type]; 561 562 switch (value & MC_ERR_STATUS_TYPE_MASK) { 563 case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE: 564 perm[0] = ' '; 565 perm[1] = '['; 566 567 if (value & MC_ERR_STATUS_READABLE) 568 perm[2] = 'R'; 569 else 570 perm[2] = '-'; 571 572 if (value & MC_ERR_STATUS_WRITABLE) 573 perm[3] = 'W'; 574 else 575 perm[3] = '-'; 576 577 if (value & MC_ERR_STATUS_NONSECURE) 578 perm[4] = '-'; 579 else 580 perm[4] = 'S'; 581 582 perm[5] = ']'; 583 perm[6] = '\0'; 584 break; 585 586 default: 587 perm[0] = '\0'; 588 break; 589 } 590 591 value = mc_readl(mc, MC_ERR_ADR); 592 addr |= value; 593 594 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", 595 client, secure, direction, &addr, error, 596 desc, perm); 597 } 598 599 /* clear interrupts */ 600 mc_writel(mc, status, MC_INTSTATUS); 601 602 return IRQ_HANDLED; 603 } 604 605 const struct tegra_mc_ops tegra30_mc_ops = { 606 .probe = tegra30_mc_probe, 607 .handle_irq = tegra30_mc_handle_irq, 608 }; 609 #endif 610 611 const char *const tegra_mc_status_names[32] = { 612 [ 1] = "External interrupt", 613 [ 6] = "EMEM address decode error", 614 [ 7] = "GART page fault", 615 [ 8] = "Security violation", 616 [ 9] = "EMEM arbitration error", 617 [10] = "Page fault", 618 [11] = "Invalid APB ASID update", 619 [12] = "VPR violation", 620 [13] = "Secure carveout violation", 621 [16] = "MTS carveout violation", 622 }; 623 624 const char *const tegra_mc_error_names[8] = { 625 [2] = "EMEM decode error", 626 [3] = "TrustZone violation", 627 [4] = "Carveout violation", 628 [6] = "SMMU translation error", 629 }; 630 631 /* 632 * Memory Controller (MC) has few Memory Clients that are issuing memory 633 * bandwidth allocation requests to the MC interconnect provider. The MC 634 * provider aggregates the requests and then sends the aggregated request 635 * up to the External Memory Controller (EMC) interconnect provider which 636 * re-configures hardware interface to External Memory (EMEM) in accordance 637 * to the required bandwidth. Each MC interconnect node represents an 638 * individual Memory Client. 639 * 640 * Memory interconnect topology: 641 * 642 * +----+ 643 * +--------+ | | 644 * | TEXSRD +--->+ | 645 * +--------+ | | 646 * | | +-----+ +------+ 647 * ... | MC +--->+ EMC +--->+ EMEM | 648 * | | +-----+ +------+ 649 * +--------+ | | 650 * | DISP.. +--->+ | 651 * +--------+ | | 652 * +----+ 653 */ 654 static int tegra_mc_interconnect_setup(struct tegra_mc *mc) 655 { 656 struct icc_node *node; 657 unsigned int i; 658 int err; 659 660 /* older device-trees don't have interconnect properties */ 661 if (!device_property_present(mc->dev, "#interconnect-cells") || 662 !mc->soc->icc_ops) 663 return 0; 664 665 mc->provider.dev = mc->dev; 666 mc->provider.data = &mc->provider; 667 mc->provider.set = mc->soc->icc_ops->set; 668 mc->provider.aggregate = mc->soc->icc_ops->aggregate; 669 mc->provider.xlate_extended = mc->soc->icc_ops->xlate_extended; 670 671 err = icc_provider_add(&mc->provider); 672 if (err) 673 return err; 674 675 /* create Memory Controller node */ 676 node = icc_node_create(TEGRA_ICC_MC); 677 if (IS_ERR(node)) { 678 err = PTR_ERR(node); 679 goto del_provider; 680 } 681 682 node->name = "Memory Controller"; 683 icc_node_add(node, &mc->provider); 684 685 /* link Memory Controller to External Memory Controller */ 686 err = icc_link_create(node, TEGRA_ICC_EMC); 687 if (err) 688 goto remove_nodes; 689 690 for (i = 0; i < mc->soc->num_clients; i++) { 691 /* create MC client node */ 692 node = icc_node_create(mc->soc->clients[i].id); 693 if (IS_ERR(node)) { 694 err = PTR_ERR(node); 695 goto remove_nodes; 696 } 697 698 node->name = mc->soc->clients[i].name; 699 icc_node_add(node, &mc->provider); 700 701 /* link Memory Client to Memory Controller */ 702 err = icc_link_create(node, TEGRA_ICC_MC); 703 if (err) 704 goto remove_nodes; 705 } 706 707 return 0; 708 709 remove_nodes: 710 icc_nodes_remove(&mc->provider); 711 del_provider: 712 icc_provider_del(&mc->provider); 713 714 return err; 715 } 716 717 static int tegra_mc_probe(struct platform_device *pdev) 718 { 719 struct resource *res; 720 struct tegra_mc *mc; 721 u64 mask; 722 int err; 723 724 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); 725 if (!mc) 726 return -ENOMEM; 727 728 platform_set_drvdata(pdev, mc); 729 spin_lock_init(&mc->lock); 730 mc->soc = of_device_get_match_data(&pdev->dev); 731 mc->dev = &pdev->dev; 732 733 mask = DMA_BIT_MASK(mc->soc->num_address_bits); 734 735 err = dma_coerce_mask_and_coherent(&pdev->dev, mask); 736 if (err < 0) { 737 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 738 return err; 739 } 740 741 /* length of MC tick in nanoseconds */ 742 mc->tick = 30; 743 744 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 745 mc->regs = devm_ioremap_resource(&pdev->dev, res); 746 if (IS_ERR(mc->regs)) 747 return PTR_ERR(mc->regs); 748 749 mc->debugfs.root = debugfs_create_dir("mc", NULL); 750 751 if (mc->soc->ops && mc->soc->ops->probe) { 752 err = mc->soc->ops->probe(mc); 753 if (err < 0) 754 return err; 755 } 756 757 if (mc->soc->ops && mc->soc->ops->handle_irq) { 758 mc->irq = platform_get_irq(pdev, 0); 759 if (mc->irq < 0) 760 return mc->irq; 761 762 WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); 763 764 mc_writel(mc, mc->soc->intmask, MC_INTMASK); 765 766 err = devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, 0, 767 dev_name(&pdev->dev), mc); 768 if (err < 0) { 769 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, 770 err); 771 return err; 772 } 773 } 774 775 if (mc->soc->reset_ops) { 776 err = tegra_mc_reset_setup(mc); 777 if (err < 0) 778 dev_err(&pdev->dev, "failed to register reset controller: %d\n", err); 779 } 780 781 err = tegra_mc_interconnect_setup(mc); 782 if (err < 0) 783 dev_err(&pdev->dev, "failed to initialize interconnect: %d\n", 784 err); 785 786 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) { 787 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); 788 if (IS_ERR(mc->smmu)) { 789 dev_err(&pdev->dev, "failed to probe SMMU: %ld\n", 790 PTR_ERR(mc->smmu)); 791 mc->smmu = NULL; 792 } 793 } 794 795 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && !mc->soc->smmu) { 796 mc->gart = tegra_gart_probe(&pdev->dev, mc); 797 if (IS_ERR(mc->gart)) { 798 dev_err(&pdev->dev, "failed to probe GART: %ld\n", 799 PTR_ERR(mc->gart)); 800 mc->gart = NULL; 801 } 802 } 803 804 return 0; 805 } 806 807 static int __maybe_unused tegra_mc_suspend(struct device *dev) 808 { 809 struct tegra_mc *mc = dev_get_drvdata(dev); 810 811 if (mc->soc->ops && mc->soc->ops->suspend) 812 return mc->soc->ops->suspend(mc); 813 814 return 0; 815 } 816 817 static int __maybe_unused tegra_mc_resume(struct device *dev) 818 { 819 struct tegra_mc *mc = dev_get_drvdata(dev); 820 821 if (mc->soc->ops && mc->soc->ops->resume) 822 return mc->soc->ops->resume(mc); 823 824 return 0; 825 } 826 827 static void tegra_mc_sync_state(struct device *dev) 828 { 829 struct tegra_mc *mc = dev_get_drvdata(dev); 830 831 /* check whether ICC provider is registered */ 832 if (mc->provider.dev == dev) 833 icc_sync_state(dev); 834 } 835 836 static const struct dev_pm_ops tegra_mc_pm_ops = { 837 SET_SYSTEM_SLEEP_PM_OPS(tegra_mc_suspend, tegra_mc_resume) 838 }; 839 840 static struct platform_driver tegra_mc_driver = { 841 .driver = { 842 .name = "tegra-mc", 843 .of_match_table = tegra_mc_of_match, 844 .pm = &tegra_mc_pm_ops, 845 .suppress_bind_attrs = true, 846 .sync_state = tegra_mc_sync_state, 847 }, 848 .prevent_deferred_probe = true, 849 .probe = tegra_mc_probe, 850 }; 851 852 static int tegra_mc_init(void) 853 { 854 return platform_driver_register(&tegra_mc_driver); 855 } 856 arch_initcall(tegra_mc_init); 857 858 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 859 MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver"); 860 MODULE_LICENSE("GPL v2"); 861