189184651SThierry Reding /* 289184651SThierry Reding * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. 389184651SThierry Reding * 489184651SThierry Reding * This program is free software; you can redistribute it and/or modify 589184651SThierry Reding * it under the terms of the GNU General Public License version 2 as 689184651SThierry Reding * published by the Free Software Foundation. 789184651SThierry Reding */ 889184651SThierry Reding 989184651SThierry Reding #include <linux/clk.h> 1089184651SThierry Reding #include <linux/interrupt.h> 1189184651SThierry Reding #include <linux/kernel.h> 1289184651SThierry Reding #include <linux/module.h> 1389184651SThierry Reding #include <linux/of.h> 1489184651SThierry Reding #include <linux/platform_device.h> 1589184651SThierry Reding #include <linux/slab.h> 163d9dd6fdSMikko Perttunen #include <linux/sort.h> 173d9dd6fdSMikko Perttunen 183d9dd6fdSMikko Perttunen #include <soc/tegra/fuse.h> 1989184651SThierry Reding 2089184651SThierry Reding #include "mc.h" 2189184651SThierry Reding 2289184651SThierry Reding #define MC_INTSTATUS 0x000 2389184651SThierry Reding #define MC_INT_DECERR_MTS (1 << 16) 2489184651SThierry Reding #define MC_INT_SECERR_SEC (1 << 13) 2589184651SThierry Reding #define MC_INT_DECERR_VPR (1 << 12) 2689184651SThierry Reding #define MC_INT_INVALID_APB_ASID_UPDATE (1 << 11) 2789184651SThierry Reding #define MC_INT_INVALID_SMMU_PAGE (1 << 10) 2889184651SThierry Reding #define MC_INT_ARBITRATION_EMEM (1 << 9) 2989184651SThierry Reding #define MC_INT_SECURITY_VIOLATION (1 << 8) 3089184651SThierry Reding #define MC_INT_DECERR_EMEM (1 << 6) 3189184651SThierry Reding 3289184651SThierry Reding #define MC_INTMASK 0x004 3389184651SThierry Reding 3489184651SThierry Reding #define MC_ERR_STATUS 0x08 3589184651SThierry Reding #define MC_ERR_STATUS_TYPE_SHIFT 28 3689184651SThierry Reding #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT) 3789184651SThierry Reding #define MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT) 3889184651SThierry Reding #define MC_ERR_STATUS_READABLE (1 << 27) 3989184651SThierry Reding #define MC_ERR_STATUS_WRITABLE (1 << 26) 4089184651SThierry Reding #define MC_ERR_STATUS_NONSECURE (1 << 25) 4189184651SThierry Reding #define MC_ERR_STATUS_ADR_HI_SHIFT 20 4289184651SThierry Reding #define MC_ERR_STATUS_ADR_HI_MASK 0x3 4389184651SThierry Reding #define MC_ERR_STATUS_SECURITY (1 << 17) 4489184651SThierry Reding #define MC_ERR_STATUS_RW (1 << 16) 4589184651SThierry Reding 4689184651SThierry Reding #define MC_ERR_ADR 0x0c 4789184651SThierry Reding 4889184651SThierry Reding #define MC_EMEM_ARB_CFG 0x90 4989184651SThierry Reding #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0) 5089184651SThierry Reding #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff 5189184651SThierry Reding #define MC_EMEM_ARB_MISC0 0xd8 5289184651SThierry Reding 533d9dd6fdSMikko Perttunen #define MC_EMEM_ADR_CFG 0x54 543d9dd6fdSMikko Perttunen #define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0) 553d9dd6fdSMikko Perttunen 5689184651SThierry Reding static const struct of_device_id tegra_mc_of_match[] = { 5789184651SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 5889184651SThierry Reding { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc }, 5989184651SThierry Reding #endif 6089184651SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 6189184651SThierry Reding { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc }, 6289184651SThierry Reding #endif 6389184651SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 6489184651SThierry Reding { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc }, 6589184651SThierry Reding #endif 66242b1d71SThierry Reding #ifdef CONFIG_ARCH_TEGRA_132_SOC 67242b1d71SThierry Reding { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc }, 68242b1d71SThierry Reding #endif 69588c43a7SThierry Reding #ifdef CONFIG_ARCH_TEGRA_210_SOC 70588c43a7SThierry Reding { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc }, 71588c43a7SThierry Reding #endif 7289184651SThierry Reding { } 7389184651SThierry Reding }; 7489184651SThierry Reding MODULE_DEVICE_TABLE(of, tegra_mc_of_match); 7589184651SThierry Reding 7689184651SThierry Reding static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) 7789184651SThierry Reding { 7889184651SThierry Reding unsigned long long tick; 7989184651SThierry Reding unsigned int i; 8089184651SThierry Reding u32 value; 8189184651SThierry Reding 8289184651SThierry Reding /* compute the number of MC clock cycles per tick */ 8389184651SThierry Reding tick = mc->tick * clk_get_rate(mc->clk); 8489184651SThierry Reding do_div(tick, NSEC_PER_SEC); 8589184651SThierry Reding 8689184651SThierry Reding value = readl(mc->regs + MC_EMEM_ARB_CFG); 8789184651SThierry Reding value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK; 8889184651SThierry Reding value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick); 8989184651SThierry Reding writel(value, mc->regs + MC_EMEM_ARB_CFG); 9089184651SThierry Reding 9189184651SThierry Reding /* write latency allowance defaults */ 9289184651SThierry Reding for (i = 0; i < mc->soc->num_clients; i++) { 9389184651SThierry Reding const struct tegra_mc_la *la = &mc->soc->clients[i].la; 9489184651SThierry Reding u32 value; 9589184651SThierry Reding 9689184651SThierry Reding value = readl(mc->regs + la->reg); 9789184651SThierry Reding value &= ~(la->mask << la->shift); 9889184651SThierry Reding value |= (la->def & la->mask) << la->shift; 9989184651SThierry Reding writel(value, mc->regs + la->reg); 10089184651SThierry Reding } 10189184651SThierry Reding 10289184651SThierry Reding return 0; 10389184651SThierry Reding } 10489184651SThierry Reding 1053d9dd6fdSMikko Perttunen void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) 1063d9dd6fdSMikko Perttunen { 1073d9dd6fdSMikko Perttunen unsigned int i; 1083d9dd6fdSMikko Perttunen struct tegra_mc_timing *timing = NULL; 1093d9dd6fdSMikko Perttunen 1103d9dd6fdSMikko Perttunen for (i = 0; i < mc->num_timings; i++) { 1113d9dd6fdSMikko Perttunen if (mc->timings[i].rate == rate) { 1123d9dd6fdSMikko Perttunen timing = &mc->timings[i]; 1133d9dd6fdSMikko Perttunen break; 1143d9dd6fdSMikko Perttunen } 1153d9dd6fdSMikko Perttunen } 1163d9dd6fdSMikko Perttunen 1173d9dd6fdSMikko Perttunen if (!timing) { 1183d9dd6fdSMikko Perttunen dev_err(mc->dev, "no memory timing registered for rate %lu\n", 1193d9dd6fdSMikko Perttunen rate); 1203d9dd6fdSMikko Perttunen return; 1213d9dd6fdSMikko Perttunen } 1223d9dd6fdSMikko Perttunen 1233d9dd6fdSMikko Perttunen for (i = 0; i < mc->soc->num_emem_regs; ++i) 1243d9dd6fdSMikko Perttunen mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); 1253d9dd6fdSMikko Perttunen } 1263d9dd6fdSMikko Perttunen 1273d9dd6fdSMikko Perttunen unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) 1283d9dd6fdSMikko Perttunen { 1293d9dd6fdSMikko Perttunen u8 dram_count; 1303d9dd6fdSMikko Perttunen 1313d9dd6fdSMikko Perttunen dram_count = mc_readl(mc, MC_EMEM_ADR_CFG); 1323d9dd6fdSMikko Perttunen dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV; 1333d9dd6fdSMikko Perttunen dram_count++; 1343d9dd6fdSMikko Perttunen 1353d9dd6fdSMikko Perttunen return dram_count; 1363d9dd6fdSMikko Perttunen } 1373d9dd6fdSMikko Perttunen 1383d9dd6fdSMikko Perttunen static int load_one_timing(struct tegra_mc *mc, 1393d9dd6fdSMikko Perttunen struct tegra_mc_timing *timing, 1403d9dd6fdSMikko Perttunen struct device_node *node) 1413d9dd6fdSMikko Perttunen { 1423d9dd6fdSMikko Perttunen int err; 1433d9dd6fdSMikko Perttunen u32 tmp; 1443d9dd6fdSMikko Perttunen 1453d9dd6fdSMikko Perttunen err = of_property_read_u32(node, "clock-frequency", &tmp); 1463d9dd6fdSMikko Perttunen if (err) { 1473d9dd6fdSMikko Perttunen dev_err(mc->dev, 1483d9dd6fdSMikko Perttunen "timing %s: failed to read rate\n", node->name); 1493d9dd6fdSMikko Perttunen return err; 1503d9dd6fdSMikko Perttunen } 1513d9dd6fdSMikko Perttunen 1523d9dd6fdSMikko Perttunen timing->rate = tmp; 1533d9dd6fdSMikko Perttunen timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, 1543d9dd6fdSMikko Perttunen sizeof(u32), GFP_KERNEL); 1553d9dd6fdSMikko Perttunen if (!timing->emem_data) 1563d9dd6fdSMikko Perttunen return -ENOMEM; 1573d9dd6fdSMikko Perttunen 1583d9dd6fdSMikko Perttunen err = of_property_read_u32_array(node, "nvidia,emem-configuration", 1593d9dd6fdSMikko Perttunen timing->emem_data, 1603d9dd6fdSMikko Perttunen mc->soc->num_emem_regs); 1613d9dd6fdSMikko Perttunen if (err) { 1623d9dd6fdSMikko Perttunen dev_err(mc->dev, 1633d9dd6fdSMikko Perttunen "timing %s: failed to read EMEM configuration\n", 1643d9dd6fdSMikko Perttunen node->name); 1653d9dd6fdSMikko Perttunen return err; 1663d9dd6fdSMikko Perttunen } 1673d9dd6fdSMikko Perttunen 1683d9dd6fdSMikko Perttunen return 0; 1693d9dd6fdSMikko Perttunen } 1703d9dd6fdSMikko Perttunen 1713d9dd6fdSMikko Perttunen static int load_timings(struct tegra_mc *mc, struct device_node *node) 1723d9dd6fdSMikko Perttunen { 1733d9dd6fdSMikko Perttunen struct device_node *child; 1743d9dd6fdSMikko Perttunen struct tegra_mc_timing *timing; 1753d9dd6fdSMikko Perttunen int child_count = of_get_child_count(node); 1763d9dd6fdSMikko Perttunen int i = 0, err; 1773d9dd6fdSMikko Perttunen 1783d9dd6fdSMikko Perttunen mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing), 1793d9dd6fdSMikko Perttunen GFP_KERNEL); 1803d9dd6fdSMikko Perttunen if (!mc->timings) 1813d9dd6fdSMikko Perttunen return -ENOMEM; 1823d9dd6fdSMikko Perttunen 1833d9dd6fdSMikko Perttunen mc->num_timings = child_count; 1843d9dd6fdSMikko Perttunen 1853d9dd6fdSMikko Perttunen for_each_child_of_node(node, child) { 1863d9dd6fdSMikko Perttunen timing = &mc->timings[i++]; 1873d9dd6fdSMikko Perttunen 1883d9dd6fdSMikko Perttunen err = load_one_timing(mc, timing, child); 18955bb1d83SAmitoj Kaur Chawla if (err) { 19055bb1d83SAmitoj Kaur Chawla of_node_put(child); 1913d9dd6fdSMikko Perttunen return err; 1923d9dd6fdSMikko Perttunen } 19355bb1d83SAmitoj Kaur Chawla } 1943d9dd6fdSMikko Perttunen 1953d9dd6fdSMikko Perttunen return 0; 1963d9dd6fdSMikko Perttunen } 1973d9dd6fdSMikko Perttunen 1983d9dd6fdSMikko Perttunen static int tegra_mc_setup_timings(struct tegra_mc *mc) 1993d9dd6fdSMikko Perttunen { 2003d9dd6fdSMikko Perttunen struct device_node *node; 2013d9dd6fdSMikko Perttunen u32 ram_code, node_ram_code; 2023d9dd6fdSMikko Perttunen int err; 2033d9dd6fdSMikko Perttunen 2043d9dd6fdSMikko Perttunen ram_code = tegra_read_ram_code(); 2053d9dd6fdSMikko Perttunen 2063d9dd6fdSMikko Perttunen mc->num_timings = 0; 2073d9dd6fdSMikko Perttunen 2083d9dd6fdSMikko Perttunen for_each_child_of_node(mc->dev->of_node, node) { 2093d9dd6fdSMikko Perttunen err = of_property_read_u32(node, "nvidia,ram-code", 2103d9dd6fdSMikko Perttunen &node_ram_code); 211d1122e4bSJulia Lawall if (err || (node_ram_code != ram_code)) 2123d9dd6fdSMikko Perttunen continue; 2133d9dd6fdSMikko Perttunen 2143d9dd6fdSMikko Perttunen err = load_timings(mc, node); 21555bb1d83SAmitoj Kaur Chawla of_node_put(node); 2163d9dd6fdSMikko Perttunen if (err) 2173d9dd6fdSMikko Perttunen return err; 2183d9dd6fdSMikko Perttunen break; 2193d9dd6fdSMikko Perttunen } 2203d9dd6fdSMikko Perttunen 2213d9dd6fdSMikko Perttunen if (mc->num_timings == 0) 2223d9dd6fdSMikko Perttunen dev_warn(mc->dev, 2233d9dd6fdSMikko Perttunen "no memory timings for RAM code %u registered\n", 2243d9dd6fdSMikko Perttunen ram_code); 2253d9dd6fdSMikko Perttunen 2263d9dd6fdSMikko Perttunen return 0; 2273d9dd6fdSMikko Perttunen } 2283d9dd6fdSMikko Perttunen 22989184651SThierry Reding static const char *const status_names[32] = { 23089184651SThierry Reding [ 1] = "External interrupt", 23189184651SThierry Reding [ 6] = "EMEM address decode error", 23289184651SThierry Reding [ 8] = "Security violation", 23389184651SThierry Reding [ 9] = "EMEM arbitration error", 23489184651SThierry Reding [10] = "Page fault", 23589184651SThierry Reding [11] = "Invalid APB ASID update", 23689184651SThierry Reding [12] = "VPR violation", 23789184651SThierry Reding [13] = "Secure carveout violation", 23889184651SThierry Reding [16] = "MTS carveout violation", 23989184651SThierry Reding }; 24089184651SThierry Reding 24189184651SThierry Reding static const char *const error_names[8] = { 24289184651SThierry Reding [2] = "EMEM decode error", 24389184651SThierry Reding [3] = "TrustZone violation", 24489184651SThierry Reding [4] = "Carveout violation", 24589184651SThierry Reding [6] = "SMMU translation error", 24689184651SThierry Reding }; 24789184651SThierry Reding 24889184651SThierry Reding static irqreturn_t tegra_mc_irq(int irq, void *data) 24989184651SThierry Reding { 25089184651SThierry Reding struct tegra_mc *mc = data; 25189184651SThierry Reding unsigned long status, mask; 25289184651SThierry Reding unsigned int bit; 25389184651SThierry Reding 25489184651SThierry Reding /* mask all interrupts to avoid flooding */ 25589184651SThierry Reding mask = mc_readl(mc, MC_INTMASK); 256bf3fbdfbSDmitry Osipenko status = mc_readl(mc, MC_INTSTATUS) & mask; 257bf3fbdfbSDmitry Osipenko 258bf3fbdfbSDmitry Osipenko if (!status) 259bf3fbdfbSDmitry Osipenko return IRQ_NONE; 26089184651SThierry Reding 26189184651SThierry Reding for_each_set_bit(bit, &status, 32) { 26289184651SThierry Reding const char *error = status_names[bit] ?: "unknown"; 26389184651SThierry Reding const char *client = "unknown", *desc; 26489184651SThierry Reding const char *direction, *secure; 26589184651SThierry Reding phys_addr_t addr = 0; 26689184651SThierry Reding unsigned int i; 26789184651SThierry Reding char perm[7]; 26889184651SThierry Reding u8 id, type; 26989184651SThierry Reding u32 value; 27089184651SThierry Reding 27189184651SThierry Reding value = mc_readl(mc, MC_ERR_STATUS); 27289184651SThierry Reding 27389184651SThierry Reding #ifdef CONFIG_PHYS_ADDR_T_64BIT 27489184651SThierry Reding if (mc->soc->num_address_bits > 32) { 27589184651SThierry Reding addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & 27689184651SThierry Reding MC_ERR_STATUS_ADR_HI_MASK); 27789184651SThierry Reding addr <<= 32; 27889184651SThierry Reding } 27989184651SThierry Reding #endif 28089184651SThierry Reding 28189184651SThierry Reding if (value & MC_ERR_STATUS_RW) 28289184651SThierry Reding direction = "write"; 28389184651SThierry Reding else 28489184651SThierry Reding direction = "read"; 28589184651SThierry Reding 28689184651SThierry Reding if (value & MC_ERR_STATUS_SECURITY) 28789184651SThierry Reding secure = "secure "; 28889184651SThierry Reding else 28989184651SThierry Reding secure = ""; 29089184651SThierry Reding 2913c01cf3bSPaul Walmsley id = value & mc->soc->client_id_mask; 29289184651SThierry Reding 29389184651SThierry Reding for (i = 0; i < mc->soc->num_clients; i++) { 29489184651SThierry Reding if (mc->soc->clients[i].id == id) { 29589184651SThierry Reding client = mc->soc->clients[i].name; 29689184651SThierry Reding break; 29789184651SThierry Reding } 29889184651SThierry Reding } 29989184651SThierry Reding 30089184651SThierry Reding type = (value & MC_ERR_STATUS_TYPE_MASK) >> 30189184651SThierry Reding MC_ERR_STATUS_TYPE_SHIFT; 30289184651SThierry Reding desc = error_names[type]; 30389184651SThierry Reding 30489184651SThierry Reding switch (value & MC_ERR_STATUS_TYPE_MASK) { 30589184651SThierry Reding case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE: 30689184651SThierry Reding perm[0] = ' '; 30789184651SThierry Reding perm[1] = '['; 30889184651SThierry Reding 30989184651SThierry Reding if (value & MC_ERR_STATUS_READABLE) 31089184651SThierry Reding perm[2] = 'R'; 31189184651SThierry Reding else 31289184651SThierry Reding perm[2] = '-'; 31389184651SThierry Reding 31489184651SThierry Reding if (value & MC_ERR_STATUS_WRITABLE) 31589184651SThierry Reding perm[3] = 'W'; 31689184651SThierry Reding else 31789184651SThierry Reding perm[3] = '-'; 31889184651SThierry Reding 31989184651SThierry Reding if (value & MC_ERR_STATUS_NONSECURE) 32089184651SThierry Reding perm[4] = '-'; 32189184651SThierry Reding else 32289184651SThierry Reding perm[4] = 'S'; 32389184651SThierry Reding 32489184651SThierry Reding perm[5] = ']'; 32589184651SThierry Reding perm[6] = '\0'; 32689184651SThierry Reding break; 32789184651SThierry Reding 32889184651SThierry Reding default: 32989184651SThierry Reding perm[0] = '\0'; 33089184651SThierry Reding break; 33189184651SThierry Reding } 33289184651SThierry Reding 33389184651SThierry Reding value = mc_readl(mc, MC_ERR_ADR); 33489184651SThierry Reding addr |= value; 33589184651SThierry Reding 33689184651SThierry Reding dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", 33789184651SThierry Reding client, secure, direction, &addr, error, 33889184651SThierry Reding desc, perm); 33989184651SThierry Reding } 34089184651SThierry Reding 34189184651SThierry Reding /* clear interrupts */ 34289184651SThierry Reding mc_writel(mc, status, MC_INTSTATUS); 34389184651SThierry Reding 34489184651SThierry Reding return IRQ_HANDLED; 34589184651SThierry Reding } 34689184651SThierry Reding 34789184651SThierry Reding static int tegra_mc_probe(struct platform_device *pdev) 34889184651SThierry Reding { 34989184651SThierry Reding const struct of_device_id *match; 35089184651SThierry Reding struct resource *res; 35189184651SThierry Reding struct tegra_mc *mc; 35289184651SThierry Reding u32 value; 35389184651SThierry Reding int err; 35489184651SThierry Reding 35589184651SThierry Reding match = of_match_node(tegra_mc_of_match, pdev->dev.of_node); 35689184651SThierry Reding if (!match) 35789184651SThierry Reding return -ENODEV; 35889184651SThierry Reding 35989184651SThierry Reding mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); 36089184651SThierry Reding if (!mc) 36189184651SThierry Reding return -ENOMEM; 36289184651SThierry Reding 36389184651SThierry Reding platform_set_drvdata(pdev, mc); 36489184651SThierry Reding mc->soc = match->data; 36589184651SThierry Reding mc->dev = &pdev->dev; 36689184651SThierry Reding 36789184651SThierry Reding /* length of MC tick in nanoseconds */ 36889184651SThierry Reding mc->tick = 30; 36989184651SThierry Reding 37089184651SThierry Reding res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 37189184651SThierry Reding mc->regs = devm_ioremap_resource(&pdev->dev, res); 37289184651SThierry Reding if (IS_ERR(mc->regs)) 37389184651SThierry Reding return PTR_ERR(mc->regs); 37489184651SThierry Reding 37589184651SThierry Reding mc->clk = devm_clk_get(&pdev->dev, "mc"); 37689184651SThierry Reding if (IS_ERR(mc->clk)) { 37789184651SThierry Reding dev_err(&pdev->dev, "failed to get MC clock: %ld\n", 37889184651SThierry Reding PTR_ERR(mc->clk)); 37989184651SThierry Reding return PTR_ERR(mc->clk); 38089184651SThierry Reding } 38189184651SThierry Reding 38289184651SThierry Reding err = tegra_mc_setup_latency_allowance(mc); 38389184651SThierry Reding if (err < 0) { 38489184651SThierry Reding dev_err(&pdev->dev, "failed to setup latency allowance: %d\n", 38589184651SThierry Reding err); 38689184651SThierry Reding return err; 38789184651SThierry Reding } 38889184651SThierry Reding 3893d9dd6fdSMikko Perttunen err = tegra_mc_setup_timings(mc); 3903d9dd6fdSMikko Perttunen if (err < 0) { 3913d9dd6fdSMikko Perttunen dev_err(&pdev->dev, "failed to setup timings: %d\n", err); 3923d9dd6fdSMikko Perttunen return err; 3933d9dd6fdSMikko Perttunen } 3943d9dd6fdSMikko Perttunen 39589184651SThierry Reding if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) { 39689184651SThierry Reding mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); 39789184651SThierry Reding if (IS_ERR(mc->smmu)) { 39889184651SThierry Reding dev_err(&pdev->dev, "failed to probe SMMU: %ld\n", 39989184651SThierry Reding PTR_ERR(mc->smmu)); 40089184651SThierry Reding return PTR_ERR(mc->smmu); 40189184651SThierry Reding } 40289184651SThierry Reding } 40389184651SThierry Reding 40489184651SThierry Reding mc->irq = platform_get_irq(pdev, 0); 40589184651SThierry Reding if (mc->irq < 0) { 40689184651SThierry Reding dev_err(&pdev->dev, "interrupt not specified\n"); 40789184651SThierry Reding return mc->irq; 40889184651SThierry Reding } 40989184651SThierry Reding 41089184651SThierry Reding err = devm_request_irq(&pdev->dev, mc->irq, tegra_mc_irq, IRQF_SHARED, 41189184651SThierry Reding dev_name(&pdev->dev), mc); 41289184651SThierry Reding if (err < 0) { 41389184651SThierry Reding dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, 41489184651SThierry Reding err); 41589184651SThierry Reding return err; 41689184651SThierry Reding } 41789184651SThierry Reding 4183c01cf3bSPaul Walmsley WARN(!mc->soc->client_id_mask, "Missing client ID mask for this SoC\n"); 4193c01cf3bSPaul Walmsley 42089184651SThierry Reding value = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | 42189184651SThierry Reding MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE | 4226f0a4d0cSTomeu Vizoso MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM; 4236f0a4d0cSTomeu Vizoso 42489184651SThierry Reding mc_writel(mc, value, MC_INTMASK); 42589184651SThierry Reding 42689184651SThierry Reding return 0; 42789184651SThierry Reding } 42889184651SThierry Reding 42989184651SThierry Reding static struct platform_driver tegra_mc_driver = { 43089184651SThierry Reding .driver = { 43189184651SThierry Reding .name = "tegra-mc", 43289184651SThierry Reding .of_match_table = tegra_mc_of_match, 43389184651SThierry Reding .suppress_bind_attrs = true, 43489184651SThierry Reding }, 43589184651SThierry Reding .prevent_deferred_probe = true, 43689184651SThierry Reding .probe = tegra_mc_probe, 43789184651SThierry Reding }; 43889184651SThierry Reding 43989184651SThierry Reding static int tegra_mc_init(void) 44089184651SThierry Reding { 44189184651SThierry Reding return platform_driver_register(&tegra_mc_driver); 44289184651SThierry Reding } 44389184651SThierry Reding arch_initcall(tegra_mc_init); 44489184651SThierry Reding 44589184651SThierry Reding MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 44689184651SThierry Reding MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver"); 44789184651SThierry Reding MODULE_LICENSE("GPL v2"); 448