189184651SThierry Reding /* 289184651SThierry Reding * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. 389184651SThierry Reding * 489184651SThierry Reding * This program is free software; you can redistribute it and/or modify 589184651SThierry Reding * it under the terms of the GNU General Public License version 2 as 689184651SThierry Reding * published by the Free Software Foundation. 789184651SThierry Reding */ 889184651SThierry Reding 989184651SThierry Reding #include <linux/clk.h> 1089184651SThierry Reding #include <linux/interrupt.h> 1189184651SThierry Reding #include <linux/kernel.h> 1289184651SThierry Reding #include <linux/module.h> 1389184651SThierry Reding #include <linux/of.h> 1489184651SThierry Reding #include <linux/platform_device.h> 1589184651SThierry Reding #include <linux/slab.h> 1689184651SThierry Reding 1789184651SThierry Reding #include "mc.h" 1889184651SThierry Reding 1989184651SThierry Reding #define MC_INTSTATUS 0x000 2089184651SThierry Reding #define MC_INT_DECERR_MTS (1 << 16) 2189184651SThierry Reding #define MC_INT_SECERR_SEC (1 << 13) 2289184651SThierry Reding #define MC_INT_DECERR_VPR (1 << 12) 2389184651SThierry Reding #define MC_INT_INVALID_APB_ASID_UPDATE (1 << 11) 2489184651SThierry Reding #define MC_INT_INVALID_SMMU_PAGE (1 << 10) 2589184651SThierry Reding #define MC_INT_ARBITRATION_EMEM (1 << 9) 2689184651SThierry Reding #define MC_INT_SECURITY_VIOLATION (1 << 8) 2789184651SThierry Reding #define MC_INT_DECERR_EMEM (1 << 6) 2889184651SThierry Reding 2989184651SThierry Reding #define MC_INTMASK 0x004 3089184651SThierry Reding 3189184651SThierry Reding #define MC_ERR_STATUS 0x08 3289184651SThierry Reding #define MC_ERR_STATUS_TYPE_SHIFT 28 3389184651SThierry Reding #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT) 3489184651SThierry Reding #define MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT) 3589184651SThierry Reding #define MC_ERR_STATUS_READABLE (1 << 27) 3689184651SThierry Reding #define MC_ERR_STATUS_WRITABLE (1 << 26) 3789184651SThierry Reding #define MC_ERR_STATUS_NONSECURE (1 << 25) 3889184651SThierry Reding #define MC_ERR_STATUS_ADR_HI_SHIFT 20 3989184651SThierry Reding #define MC_ERR_STATUS_ADR_HI_MASK 0x3 4089184651SThierry Reding #define MC_ERR_STATUS_SECURITY (1 << 17) 4189184651SThierry Reding #define MC_ERR_STATUS_RW (1 << 16) 4289184651SThierry Reding #define MC_ERR_STATUS_CLIENT_MASK 0x7f 4389184651SThierry Reding 4489184651SThierry Reding #define MC_ERR_ADR 0x0c 4589184651SThierry Reding 4689184651SThierry Reding #define MC_EMEM_ARB_CFG 0x90 4789184651SThierry Reding #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0) 4889184651SThierry Reding #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff 4989184651SThierry Reding #define MC_EMEM_ARB_MISC0 0xd8 5089184651SThierry Reding 5189184651SThierry Reding static const struct of_device_id tegra_mc_of_match[] = { 5289184651SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 5389184651SThierry Reding { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc }, 5489184651SThierry Reding #endif 5589184651SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 5689184651SThierry Reding { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc }, 5789184651SThierry Reding #endif 5889184651SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 5989184651SThierry Reding { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc }, 6089184651SThierry Reding #endif 61242b1d71SThierry Reding #ifdef CONFIG_ARCH_TEGRA_132_SOC 62242b1d71SThierry Reding { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc }, 63242b1d71SThierry Reding #endif 6489184651SThierry Reding { } 6589184651SThierry Reding }; 6689184651SThierry Reding MODULE_DEVICE_TABLE(of, tegra_mc_of_match); 6789184651SThierry Reding 6889184651SThierry Reding static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) 6989184651SThierry Reding { 7089184651SThierry Reding unsigned long long tick; 7189184651SThierry Reding unsigned int i; 7289184651SThierry Reding u32 value; 7389184651SThierry Reding 7489184651SThierry Reding /* compute the number of MC clock cycles per tick */ 7589184651SThierry Reding tick = mc->tick * clk_get_rate(mc->clk); 7689184651SThierry Reding do_div(tick, NSEC_PER_SEC); 7789184651SThierry Reding 7889184651SThierry Reding value = readl(mc->regs + MC_EMEM_ARB_CFG); 7989184651SThierry Reding value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK; 8089184651SThierry Reding value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick); 8189184651SThierry Reding writel(value, mc->regs + MC_EMEM_ARB_CFG); 8289184651SThierry Reding 8389184651SThierry Reding /* write latency allowance defaults */ 8489184651SThierry Reding for (i = 0; i < mc->soc->num_clients; i++) { 8589184651SThierry Reding const struct tegra_mc_la *la = &mc->soc->clients[i].la; 8689184651SThierry Reding u32 value; 8789184651SThierry Reding 8889184651SThierry Reding value = readl(mc->regs + la->reg); 8989184651SThierry Reding value &= ~(la->mask << la->shift); 9089184651SThierry Reding value |= (la->def & la->mask) << la->shift; 9189184651SThierry Reding writel(value, mc->regs + la->reg); 9289184651SThierry Reding } 9389184651SThierry Reding 9489184651SThierry Reding return 0; 9589184651SThierry Reding } 9689184651SThierry Reding 9789184651SThierry Reding static const char *const status_names[32] = { 9889184651SThierry Reding [ 1] = "External interrupt", 9989184651SThierry Reding [ 6] = "EMEM address decode error", 10089184651SThierry Reding [ 8] = "Security violation", 10189184651SThierry Reding [ 9] = "EMEM arbitration error", 10289184651SThierry Reding [10] = "Page fault", 10389184651SThierry Reding [11] = "Invalid APB ASID update", 10489184651SThierry Reding [12] = "VPR violation", 10589184651SThierry Reding [13] = "Secure carveout violation", 10689184651SThierry Reding [16] = "MTS carveout violation", 10789184651SThierry Reding }; 10889184651SThierry Reding 10989184651SThierry Reding static const char *const error_names[8] = { 11089184651SThierry Reding [2] = "EMEM decode error", 11189184651SThierry Reding [3] = "TrustZone violation", 11289184651SThierry Reding [4] = "Carveout violation", 11389184651SThierry Reding [6] = "SMMU translation error", 11489184651SThierry Reding }; 11589184651SThierry Reding 11689184651SThierry Reding static irqreturn_t tegra_mc_irq(int irq, void *data) 11789184651SThierry Reding { 11889184651SThierry Reding struct tegra_mc *mc = data; 11989184651SThierry Reding unsigned long status, mask; 12089184651SThierry Reding unsigned int bit; 12189184651SThierry Reding 12289184651SThierry Reding /* mask all interrupts to avoid flooding */ 12389184651SThierry Reding status = mc_readl(mc, MC_INTSTATUS); 12489184651SThierry Reding mask = mc_readl(mc, MC_INTMASK); 12589184651SThierry Reding 12689184651SThierry Reding for_each_set_bit(bit, &status, 32) { 12789184651SThierry Reding const char *error = status_names[bit] ?: "unknown"; 12889184651SThierry Reding const char *client = "unknown", *desc; 12989184651SThierry Reding const char *direction, *secure; 13089184651SThierry Reding phys_addr_t addr = 0; 13189184651SThierry Reding unsigned int i; 13289184651SThierry Reding char perm[7]; 13389184651SThierry Reding u8 id, type; 13489184651SThierry Reding u32 value; 13589184651SThierry Reding 13689184651SThierry Reding value = mc_readl(mc, MC_ERR_STATUS); 13789184651SThierry Reding 13889184651SThierry Reding #ifdef CONFIG_PHYS_ADDR_T_64BIT 13989184651SThierry Reding if (mc->soc->num_address_bits > 32) { 14089184651SThierry Reding addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & 14189184651SThierry Reding MC_ERR_STATUS_ADR_HI_MASK); 14289184651SThierry Reding addr <<= 32; 14389184651SThierry Reding } 14489184651SThierry Reding #endif 14589184651SThierry Reding 14689184651SThierry Reding if (value & MC_ERR_STATUS_RW) 14789184651SThierry Reding direction = "write"; 14889184651SThierry Reding else 14989184651SThierry Reding direction = "read"; 15089184651SThierry Reding 15189184651SThierry Reding if (value & MC_ERR_STATUS_SECURITY) 15289184651SThierry Reding secure = "secure "; 15389184651SThierry Reding else 15489184651SThierry Reding secure = ""; 15589184651SThierry Reding 15689184651SThierry Reding id = value & MC_ERR_STATUS_CLIENT_MASK; 15789184651SThierry Reding 15889184651SThierry Reding for (i = 0; i < mc->soc->num_clients; i++) { 15989184651SThierry Reding if (mc->soc->clients[i].id == id) { 16089184651SThierry Reding client = mc->soc->clients[i].name; 16189184651SThierry Reding break; 16289184651SThierry Reding } 16389184651SThierry Reding } 16489184651SThierry Reding 16589184651SThierry Reding type = (value & MC_ERR_STATUS_TYPE_MASK) >> 16689184651SThierry Reding MC_ERR_STATUS_TYPE_SHIFT; 16789184651SThierry Reding desc = error_names[type]; 16889184651SThierry Reding 16989184651SThierry Reding switch (value & MC_ERR_STATUS_TYPE_MASK) { 17089184651SThierry Reding case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE: 17189184651SThierry Reding perm[0] = ' '; 17289184651SThierry Reding perm[1] = '['; 17389184651SThierry Reding 17489184651SThierry Reding if (value & MC_ERR_STATUS_READABLE) 17589184651SThierry Reding perm[2] = 'R'; 17689184651SThierry Reding else 17789184651SThierry Reding perm[2] = '-'; 17889184651SThierry Reding 17989184651SThierry Reding if (value & MC_ERR_STATUS_WRITABLE) 18089184651SThierry Reding perm[3] = 'W'; 18189184651SThierry Reding else 18289184651SThierry Reding perm[3] = '-'; 18389184651SThierry Reding 18489184651SThierry Reding if (value & MC_ERR_STATUS_NONSECURE) 18589184651SThierry Reding perm[4] = '-'; 18689184651SThierry Reding else 18789184651SThierry Reding perm[4] = 'S'; 18889184651SThierry Reding 18989184651SThierry Reding perm[5] = ']'; 19089184651SThierry Reding perm[6] = '\0'; 19189184651SThierry Reding break; 19289184651SThierry Reding 19389184651SThierry Reding default: 19489184651SThierry Reding perm[0] = '\0'; 19589184651SThierry Reding break; 19689184651SThierry Reding } 19789184651SThierry Reding 19889184651SThierry Reding value = mc_readl(mc, MC_ERR_ADR); 19989184651SThierry Reding addr |= value; 20089184651SThierry Reding 20189184651SThierry Reding dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", 20289184651SThierry Reding client, secure, direction, &addr, error, 20389184651SThierry Reding desc, perm); 20489184651SThierry Reding } 20589184651SThierry Reding 20689184651SThierry Reding /* clear interrupts */ 20789184651SThierry Reding mc_writel(mc, status, MC_INTSTATUS); 20889184651SThierry Reding 20989184651SThierry Reding return IRQ_HANDLED; 21089184651SThierry Reding } 21189184651SThierry Reding 21289184651SThierry Reding static int tegra_mc_probe(struct platform_device *pdev) 21389184651SThierry Reding { 21489184651SThierry Reding const struct of_device_id *match; 21589184651SThierry Reding struct resource *res; 21689184651SThierry Reding struct tegra_mc *mc; 21789184651SThierry Reding u32 value; 21889184651SThierry Reding int err; 21989184651SThierry Reding 22089184651SThierry Reding match = of_match_node(tegra_mc_of_match, pdev->dev.of_node); 22189184651SThierry Reding if (!match) 22289184651SThierry Reding return -ENODEV; 22389184651SThierry Reding 22489184651SThierry Reding mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); 22589184651SThierry Reding if (!mc) 22689184651SThierry Reding return -ENOMEM; 22789184651SThierry Reding 22889184651SThierry Reding platform_set_drvdata(pdev, mc); 22989184651SThierry Reding mc->soc = match->data; 23089184651SThierry Reding mc->dev = &pdev->dev; 23189184651SThierry Reding 23289184651SThierry Reding /* length of MC tick in nanoseconds */ 23389184651SThierry Reding mc->tick = 30; 23489184651SThierry Reding 23589184651SThierry Reding res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 23689184651SThierry Reding mc->regs = devm_ioremap_resource(&pdev->dev, res); 23789184651SThierry Reding if (IS_ERR(mc->regs)) 23889184651SThierry Reding return PTR_ERR(mc->regs); 23989184651SThierry Reding 24089184651SThierry Reding mc->clk = devm_clk_get(&pdev->dev, "mc"); 24189184651SThierry Reding if (IS_ERR(mc->clk)) { 24289184651SThierry Reding dev_err(&pdev->dev, "failed to get MC clock: %ld\n", 24389184651SThierry Reding PTR_ERR(mc->clk)); 24489184651SThierry Reding return PTR_ERR(mc->clk); 24589184651SThierry Reding } 24689184651SThierry Reding 24789184651SThierry Reding err = tegra_mc_setup_latency_allowance(mc); 24889184651SThierry Reding if (err < 0) { 24989184651SThierry Reding dev_err(&pdev->dev, "failed to setup latency allowance: %d\n", 25089184651SThierry Reding err); 25189184651SThierry Reding return err; 25289184651SThierry Reding } 25389184651SThierry Reding 25489184651SThierry Reding if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) { 25589184651SThierry Reding mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); 25689184651SThierry Reding if (IS_ERR(mc->smmu)) { 25789184651SThierry Reding dev_err(&pdev->dev, "failed to probe SMMU: %ld\n", 25889184651SThierry Reding PTR_ERR(mc->smmu)); 25989184651SThierry Reding return PTR_ERR(mc->smmu); 26089184651SThierry Reding } 26189184651SThierry Reding } 26289184651SThierry Reding 26389184651SThierry Reding mc->irq = platform_get_irq(pdev, 0); 26489184651SThierry Reding if (mc->irq < 0) { 26589184651SThierry Reding dev_err(&pdev->dev, "interrupt not specified\n"); 26689184651SThierry Reding return mc->irq; 26789184651SThierry Reding } 26889184651SThierry Reding 26989184651SThierry Reding err = devm_request_irq(&pdev->dev, mc->irq, tegra_mc_irq, IRQF_SHARED, 27089184651SThierry Reding dev_name(&pdev->dev), mc); 27189184651SThierry Reding if (err < 0) { 27289184651SThierry Reding dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, 27389184651SThierry Reding err); 27489184651SThierry Reding return err; 27589184651SThierry Reding } 27689184651SThierry Reding 27789184651SThierry Reding value = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | 27889184651SThierry Reding MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE | 2796f0a4d0cSTomeu Vizoso MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM; 2806f0a4d0cSTomeu Vizoso 28189184651SThierry Reding mc_writel(mc, value, MC_INTMASK); 28289184651SThierry Reding 28389184651SThierry Reding return 0; 28489184651SThierry Reding } 28589184651SThierry Reding 28689184651SThierry Reding static struct platform_driver tegra_mc_driver = { 28789184651SThierry Reding .driver = { 28889184651SThierry Reding .name = "tegra-mc", 28989184651SThierry Reding .of_match_table = tegra_mc_of_match, 29089184651SThierry Reding .suppress_bind_attrs = true, 29189184651SThierry Reding }, 29289184651SThierry Reding .prevent_deferred_probe = true, 29389184651SThierry Reding .probe = tegra_mc_probe, 29489184651SThierry Reding }; 29589184651SThierry Reding 29689184651SThierry Reding static int tegra_mc_init(void) 29789184651SThierry Reding { 29889184651SThierry Reding return platform_driver_register(&tegra_mc_driver); 29989184651SThierry Reding } 30089184651SThierry Reding arch_initcall(tegra_mc_init); 30189184651SThierry Reding 30289184651SThierry Reding MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 30389184651SThierry Reding MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver"); 30489184651SThierry Reding MODULE_LICENSE("GPL v2"); 305