189184651SThierry Reding /* 289184651SThierry Reding * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. 389184651SThierry Reding * 489184651SThierry Reding * This program is free software; you can redistribute it and/or modify 589184651SThierry Reding * it under the terms of the GNU General Public License version 2 as 689184651SThierry Reding * published by the Free Software Foundation. 789184651SThierry Reding */ 889184651SThierry Reding 989184651SThierry Reding #include <linux/clk.h> 1020e92462SDmitry Osipenko #include <linux/delay.h> 1189184651SThierry Reding #include <linux/interrupt.h> 1289184651SThierry Reding #include <linux/kernel.h> 1389184651SThierry Reding #include <linux/module.h> 1489184651SThierry Reding #include <linux/of.h> 1559cd046fSDmitry Osipenko #include <linux/of_device.h> 1689184651SThierry Reding #include <linux/platform_device.h> 1789184651SThierry Reding #include <linux/slab.h> 183d9dd6fdSMikko Perttunen #include <linux/sort.h> 193d9dd6fdSMikko Perttunen 203d9dd6fdSMikko Perttunen #include <soc/tegra/fuse.h> 2189184651SThierry Reding 2289184651SThierry Reding #include "mc.h" 2389184651SThierry Reding 2489184651SThierry Reding #define MC_INTSTATUS 0x000 2589184651SThierry Reding 2689184651SThierry Reding #define MC_INTMASK 0x004 2789184651SThierry Reding 2889184651SThierry Reding #define MC_ERR_STATUS 0x08 2989184651SThierry Reding #define MC_ERR_STATUS_TYPE_SHIFT 28 3089184651SThierry Reding #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT) 3189184651SThierry Reding #define MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT) 3289184651SThierry Reding #define MC_ERR_STATUS_READABLE (1 << 27) 3389184651SThierry Reding #define MC_ERR_STATUS_WRITABLE (1 << 26) 3489184651SThierry Reding #define MC_ERR_STATUS_NONSECURE (1 << 25) 3589184651SThierry Reding #define MC_ERR_STATUS_ADR_HI_SHIFT 20 3689184651SThierry Reding #define MC_ERR_STATUS_ADR_HI_MASK 0x3 3789184651SThierry Reding #define MC_ERR_STATUS_SECURITY (1 << 17) 3889184651SThierry Reding #define MC_ERR_STATUS_RW (1 << 16) 3989184651SThierry Reding 4089184651SThierry Reding #define MC_ERR_ADR 0x0c 4189184651SThierry Reding 42b3bb6b85SDmitry Osipenko #define MC_GART_ERROR_REQ 0x30 43a8d502fdSDmitry Osipenko #define MC_DECERR_EMEM_OTHERS_STATUS 0x58 44a8d502fdSDmitry Osipenko #define MC_SECURITY_VIOLATION_STATUS 0x74 45a8d502fdSDmitry Osipenko 4689184651SThierry Reding #define MC_EMEM_ARB_CFG 0x90 4789184651SThierry Reding #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0) 4889184651SThierry Reding #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff 4989184651SThierry Reding #define MC_EMEM_ARB_MISC0 0xd8 5089184651SThierry Reding 513d9dd6fdSMikko Perttunen #define MC_EMEM_ADR_CFG 0x54 523d9dd6fdSMikko Perttunen #define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0) 533d9dd6fdSMikko Perttunen 5489184651SThierry Reding static const struct of_device_id tegra_mc_of_match[] = { 55a8d502fdSDmitry Osipenko #ifdef CONFIG_ARCH_TEGRA_2x_SOC 5696efa118SDmitry Osipenko { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc }, 57a8d502fdSDmitry Osipenko #endif 5889184651SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 5989184651SThierry Reding { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc }, 6089184651SThierry Reding #endif 6189184651SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 6289184651SThierry Reding { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc }, 6389184651SThierry Reding #endif 6489184651SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 6589184651SThierry Reding { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc }, 6689184651SThierry Reding #endif 67242b1d71SThierry Reding #ifdef CONFIG_ARCH_TEGRA_132_SOC 68242b1d71SThierry Reding { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc }, 69242b1d71SThierry Reding #endif 70588c43a7SThierry Reding #ifdef CONFIG_ARCH_TEGRA_210_SOC 71588c43a7SThierry Reding { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc }, 72588c43a7SThierry Reding #endif 7389184651SThierry Reding { } 7489184651SThierry Reding }; 7589184651SThierry Reding MODULE_DEVICE_TABLE(of, tegra_mc_of_match); 7689184651SThierry Reding 7720e92462SDmitry Osipenko static int terga_mc_block_dma_common(struct tegra_mc *mc, 7820e92462SDmitry Osipenko const struct tegra_mc_reset *rst) 7920e92462SDmitry Osipenko { 8020e92462SDmitry Osipenko unsigned long flags; 8120e92462SDmitry Osipenko u32 value; 8220e92462SDmitry Osipenko 8320e92462SDmitry Osipenko spin_lock_irqsave(&mc->lock, flags); 8420e92462SDmitry Osipenko 8520e92462SDmitry Osipenko value = mc_readl(mc, rst->control) | BIT(rst->bit); 8620e92462SDmitry Osipenko mc_writel(mc, value, rst->control); 8720e92462SDmitry Osipenko 8820e92462SDmitry Osipenko spin_unlock_irqrestore(&mc->lock, flags); 8920e92462SDmitry Osipenko 9020e92462SDmitry Osipenko return 0; 9120e92462SDmitry Osipenko } 9220e92462SDmitry Osipenko 9320e92462SDmitry Osipenko static bool terga_mc_dma_idling_common(struct tegra_mc *mc, 9420e92462SDmitry Osipenko const struct tegra_mc_reset *rst) 9520e92462SDmitry Osipenko { 9620e92462SDmitry Osipenko return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; 9720e92462SDmitry Osipenko } 9820e92462SDmitry Osipenko 9920e92462SDmitry Osipenko static int terga_mc_unblock_dma_common(struct tegra_mc *mc, 10020e92462SDmitry Osipenko const struct tegra_mc_reset *rst) 10120e92462SDmitry Osipenko { 10220e92462SDmitry Osipenko unsigned long flags; 10320e92462SDmitry Osipenko u32 value; 10420e92462SDmitry Osipenko 10520e92462SDmitry Osipenko spin_lock_irqsave(&mc->lock, flags); 10620e92462SDmitry Osipenko 10720e92462SDmitry Osipenko value = mc_readl(mc, rst->control) & ~BIT(rst->bit); 10820e92462SDmitry Osipenko mc_writel(mc, value, rst->control); 10920e92462SDmitry Osipenko 11020e92462SDmitry Osipenko spin_unlock_irqrestore(&mc->lock, flags); 11120e92462SDmitry Osipenko 11220e92462SDmitry Osipenko return 0; 11320e92462SDmitry Osipenko } 11420e92462SDmitry Osipenko 11520e92462SDmitry Osipenko static int terga_mc_reset_status_common(struct tegra_mc *mc, 11620e92462SDmitry Osipenko const struct tegra_mc_reset *rst) 11720e92462SDmitry Osipenko { 11820e92462SDmitry Osipenko return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; 11920e92462SDmitry Osipenko } 12020e92462SDmitry Osipenko 12120e92462SDmitry Osipenko const struct tegra_mc_reset_ops terga_mc_reset_ops_common = { 12220e92462SDmitry Osipenko .block_dma = terga_mc_block_dma_common, 12320e92462SDmitry Osipenko .dma_idling = terga_mc_dma_idling_common, 12420e92462SDmitry Osipenko .unblock_dma = terga_mc_unblock_dma_common, 12520e92462SDmitry Osipenko .reset_status = terga_mc_reset_status_common, 12620e92462SDmitry Osipenko }; 12720e92462SDmitry Osipenko 12820e92462SDmitry Osipenko static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev) 12920e92462SDmitry Osipenko { 13020e92462SDmitry Osipenko return container_of(rcdev, struct tegra_mc, reset); 13120e92462SDmitry Osipenko } 13220e92462SDmitry Osipenko 13320e92462SDmitry Osipenko static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc, 13420e92462SDmitry Osipenko unsigned long id) 13520e92462SDmitry Osipenko { 13620e92462SDmitry Osipenko unsigned int i; 13720e92462SDmitry Osipenko 13820e92462SDmitry Osipenko for (i = 0; i < mc->soc->num_resets; i++) 13920e92462SDmitry Osipenko if (mc->soc->resets[i].id == id) 14020e92462SDmitry Osipenko return &mc->soc->resets[i]; 14120e92462SDmitry Osipenko 14220e92462SDmitry Osipenko return NULL; 14320e92462SDmitry Osipenko } 14420e92462SDmitry Osipenko 14520e92462SDmitry Osipenko static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev, 14620e92462SDmitry Osipenko unsigned long id) 14720e92462SDmitry Osipenko { 14820e92462SDmitry Osipenko struct tegra_mc *mc = reset_to_mc(rcdev); 14920e92462SDmitry Osipenko const struct tegra_mc_reset_ops *rst_ops; 15020e92462SDmitry Osipenko const struct tegra_mc_reset *rst; 15120e92462SDmitry Osipenko int retries = 500; 15220e92462SDmitry Osipenko int err; 15320e92462SDmitry Osipenko 15420e92462SDmitry Osipenko rst = tegra_mc_reset_find(mc, id); 15520e92462SDmitry Osipenko if (!rst) 15620e92462SDmitry Osipenko return -ENODEV; 15720e92462SDmitry Osipenko 15820e92462SDmitry Osipenko rst_ops = mc->soc->reset_ops; 15920e92462SDmitry Osipenko if (!rst_ops) 16020e92462SDmitry Osipenko return -ENODEV; 16120e92462SDmitry Osipenko 16220e92462SDmitry Osipenko if (rst_ops->block_dma) { 16320e92462SDmitry Osipenko /* block clients DMA requests */ 16420e92462SDmitry Osipenko err = rst_ops->block_dma(mc, rst); 16520e92462SDmitry Osipenko if (err) { 16620e92462SDmitry Osipenko dev_err(mc->dev, "Failed to block %s DMA: %d\n", 16720e92462SDmitry Osipenko rst->name, err); 16820e92462SDmitry Osipenko return err; 16920e92462SDmitry Osipenko } 17020e92462SDmitry Osipenko } 17120e92462SDmitry Osipenko 17220e92462SDmitry Osipenko if (rst_ops->dma_idling) { 17320e92462SDmitry Osipenko /* wait for completion of the outstanding DMA requests */ 17420e92462SDmitry Osipenko while (!rst_ops->dma_idling(mc, rst)) { 17520e92462SDmitry Osipenko if (!retries--) { 17620e92462SDmitry Osipenko dev_err(mc->dev, "Failed to flush %s DMA\n", 17720e92462SDmitry Osipenko rst->name); 17820e92462SDmitry Osipenko return -EBUSY; 17920e92462SDmitry Osipenko } 18020e92462SDmitry Osipenko 18120e92462SDmitry Osipenko usleep_range(10, 100); 18220e92462SDmitry Osipenko } 18320e92462SDmitry Osipenko } 18420e92462SDmitry Osipenko 18520e92462SDmitry Osipenko if (rst_ops->hotreset_assert) { 18620e92462SDmitry Osipenko /* clear clients DMA requests sitting before arbitration */ 18720e92462SDmitry Osipenko err = rst_ops->hotreset_assert(mc, rst); 18820e92462SDmitry Osipenko if (err) { 18920e92462SDmitry Osipenko dev_err(mc->dev, "Failed to hot reset %s: %d\n", 19020e92462SDmitry Osipenko rst->name, err); 19120e92462SDmitry Osipenko return err; 19220e92462SDmitry Osipenko } 19320e92462SDmitry Osipenko } 19420e92462SDmitry Osipenko 19520e92462SDmitry Osipenko return 0; 19620e92462SDmitry Osipenko } 19720e92462SDmitry Osipenko 19820e92462SDmitry Osipenko static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev, 19920e92462SDmitry Osipenko unsigned long id) 20020e92462SDmitry Osipenko { 20120e92462SDmitry Osipenko struct tegra_mc *mc = reset_to_mc(rcdev); 20220e92462SDmitry Osipenko const struct tegra_mc_reset_ops *rst_ops; 20320e92462SDmitry Osipenko const struct tegra_mc_reset *rst; 20420e92462SDmitry Osipenko int err; 20520e92462SDmitry Osipenko 20620e92462SDmitry Osipenko rst = tegra_mc_reset_find(mc, id); 20720e92462SDmitry Osipenko if (!rst) 20820e92462SDmitry Osipenko return -ENODEV; 20920e92462SDmitry Osipenko 21020e92462SDmitry Osipenko rst_ops = mc->soc->reset_ops; 21120e92462SDmitry Osipenko if (!rst_ops) 21220e92462SDmitry Osipenko return -ENODEV; 21320e92462SDmitry Osipenko 21420e92462SDmitry Osipenko if (rst_ops->hotreset_deassert) { 21520e92462SDmitry Osipenko /* take out client from hot reset */ 21620e92462SDmitry Osipenko err = rst_ops->hotreset_deassert(mc, rst); 21720e92462SDmitry Osipenko if (err) { 21820e92462SDmitry Osipenko dev_err(mc->dev, "Failed to deassert hot reset %s: %d\n", 21920e92462SDmitry Osipenko rst->name, err); 22020e92462SDmitry Osipenko return err; 22120e92462SDmitry Osipenko } 22220e92462SDmitry Osipenko } 22320e92462SDmitry Osipenko 22420e92462SDmitry Osipenko if (rst_ops->unblock_dma) { 22520e92462SDmitry Osipenko /* allow new DMA requests to proceed to arbitration */ 22620e92462SDmitry Osipenko err = rst_ops->unblock_dma(mc, rst); 22720e92462SDmitry Osipenko if (err) { 22820e92462SDmitry Osipenko dev_err(mc->dev, "Failed to unblock %s DMA : %d\n", 22920e92462SDmitry Osipenko rst->name, err); 23020e92462SDmitry Osipenko return err; 23120e92462SDmitry Osipenko } 23220e92462SDmitry Osipenko } 23320e92462SDmitry Osipenko 23420e92462SDmitry Osipenko return 0; 23520e92462SDmitry Osipenko } 23620e92462SDmitry Osipenko 23720e92462SDmitry Osipenko static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev, 23820e92462SDmitry Osipenko unsigned long id) 23920e92462SDmitry Osipenko { 24020e92462SDmitry Osipenko struct tegra_mc *mc = reset_to_mc(rcdev); 24120e92462SDmitry Osipenko const struct tegra_mc_reset_ops *rst_ops; 24220e92462SDmitry Osipenko const struct tegra_mc_reset *rst; 24320e92462SDmitry Osipenko 24420e92462SDmitry Osipenko rst = tegra_mc_reset_find(mc, id); 24520e92462SDmitry Osipenko if (!rst) 24620e92462SDmitry Osipenko return -ENODEV; 24720e92462SDmitry Osipenko 24820e92462SDmitry Osipenko rst_ops = mc->soc->reset_ops; 24920e92462SDmitry Osipenko if (!rst_ops) 25020e92462SDmitry Osipenko return -ENODEV; 25120e92462SDmitry Osipenko 25220e92462SDmitry Osipenko return rst_ops->reset_status(mc, rst); 25320e92462SDmitry Osipenko } 25420e92462SDmitry Osipenko 25520e92462SDmitry Osipenko static const struct reset_control_ops tegra_mc_reset_ops = { 25620e92462SDmitry Osipenko .assert = tegra_mc_hotreset_assert, 25720e92462SDmitry Osipenko .deassert = tegra_mc_hotreset_deassert, 25820e92462SDmitry Osipenko .status = tegra_mc_hotreset_status, 25920e92462SDmitry Osipenko }; 26020e92462SDmitry Osipenko 26120e92462SDmitry Osipenko static int tegra_mc_reset_setup(struct tegra_mc *mc) 26220e92462SDmitry Osipenko { 26320e92462SDmitry Osipenko int err; 26420e92462SDmitry Osipenko 26520e92462SDmitry Osipenko mc->reset.ops = &tegra_mc_reset_ops; 26620e92462SDmitry Osipenko mc->reset.owner = THIS_MODULE; 26720e92462SDmitry Osipenko mc->reset.of_node = mc->dev->of_node; 26820e92462SDmitry Osipenko mc->reset.of_reset_n_cells = 1; 26920e92462SDmitry Osipenko mc->reset.nr_resets = mc->soc->num_resets; 27020e92462SDmitry Osipenko 27120e92462SDmitry Osipenko err = reset_controller_register(&mc->reset); 27220e92462SDmitry Osipenko if (err < 0) 27320e92462SDmitry Osipenko return err; 27420e92462SDmitry Osipenko 27520e92462SDmitry Osipenko return 0; 27620e92462SDmitry Osipenko } 27720e92462SDmitry Osipenko 27889184651SThierry Reding static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) 27989184651SThierry Reding { 28089184651SThierry Reding unsigned long long tick; 28189184651SThierry Reding unsigned int i; 28289184651SThierry Reding u32 value; 28389184651SThierry Reding 28489184651SThierry Reding /* compute the number of MC clock cycles per tick */ 28589184651SThierry Reding tick = mc->tick * clk_get_rate(mc->clk); 28689184651SThierry Reding do_div(tick, NSEC_PER_SEC); 28789184651SThierry Reding 28889184651SThierry Reding value = readl(mc->regs + MC_EMEM_ARB_CFG); 28989184651SThierry Reding value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK; 29089184651SThierry Reding value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick); 29189184651SThierry Reding writel(value, mc->regs + MC_EMEM_ARB_CFG); 29289184651SThierry Reding 29389184651SThierry Reding /* write latency allowance defaults */ 29489184651SThierry Reding for (i = 0; i < mc->soc->num_clients; i++) { 29589184651SThierry Reding const struct tegra_mc_la *la = &mc->soc->clients[i].la; 29689184651SThierry Reding u32 value; 29789184651SThierry Reding 29889184651SThierry Reding value = readl(mc->regs + la->reg); 29989184651SThierry Reding value &= ~(la->mask << la->shift); 30089184651SThierry Reding value |= (la->def & la->mask) << la->shift; 30189184651SThierry Reding writel(value, mc->regs + la->reg); 30289184651SThierry Reding } 30389184651SThierry Reding 30489184651SThierry Reding return 0; 30589184651SThierry Reding } 30689184651SThierry Reding 3073d9dd6fdSMikko Perttunen void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) 3083d9dd6fdSMikko Perttunen { 3093d9dd6fdSMikko Perttunen unsigned int i; 3103d9dd6fdSMikko Perttunen struct tegra_mc_timing *timing = NULL; 3113d9dd6fdSMikko Perttunen 3123d9dd6fdSMikko Perttunen for (i = 0; i < mc->num_timings; i++) { 3133d9dd6fdSMikko Perttunen if (mc->timings[i].rate == rate) { 3143d9dd6fdSMikko Perttunen timing = &mc->timings[i]; 3153d9dd6fdSMikko Perttunen break; 3163d9dd6fdSMikko Perttunen } 3173d9dd6fdSMikko Perttunen } 3183d9dd6fdSMikko Perttunen 3193d9dd6fdSMikko Perttunen if (!timing) { 3203d9dd6fdSMikko Perttunen dev_err(mc->dev, "no memory timing registered for rate %lu\n", 3213d9dd6fdSMikko Perttunen rate); 3223d9dd6fdSMikko Perttunen return; 3233d9dd6fdSMikko Perttunen } 3243d9dd6fdSMikko Perttunen 3253d9dd6fdSMikko Perttunen for (i = 0; i < mc->soc->num_emem_regs; ++i) 3263d9dd6fdSMikko Perttunen mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); 3273d9dd6fdSMikko Perttunen } 3283d9dd6fdSMikko Perttunen 3293d9dd6fdSMikko Perttunen unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) 3303d9dd6fdSMikko Perttunen { 3313d9dd6fdSMikko Perttunen u8 dram_count; 3323d9dd6fdSMikko Perttunen 3333d9dd6fdSMikko Perttunen dram_count = mc_readl(mc, MC_EMEM_ADR_CFG); 3343d9dd6fdSMikko Perttunen dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV; 3353d9dd6fdSMikko Perttunen dram_count++; 3363d9dd6fdSMikko Perttunen 3373d9dd6fdSMikko Perttunen return dram_count; 3383d9dd6fdSMikko Perttunen } 3393d9dd6fdSMikko Perttunen 3403d9dd6fdSMikko Perttunen static int load_one_timing(struct tegra_mc *mc, 3413d9dd6fdSMikko Perttunen struct tegra_mc_timing *timing, 3423d9dd6fdSMikko Perttunen struct device_node *node) 3433d9dd6fdSMikko Perttunen { 3443d9dd6fdSMikko Perttunen int err; 3453d9dd6fdSMikko Perttunen u32 tmp; 3463d9dd6fdSMikko Perttunen 3473d9dd6fdSMikko Perttunen err = of_property_read_u32(node, "clock-frequency", &tmp); 3483d9dd6fdSMikko Perttunen if (err) { 3493d9dd6fdSMikko Perttunen dev_err(mc->dev, 350c86f9854SRob Herring "timing %pOFn: failed to read rate\n", node); 3513d9dd6fdSMikko Perttunen return err; 3523d9dd6fdSMikko Perttunen } 3533d9dd6fdSMikko Perttunen 3543d9dd6fdSMikko Perttunen timing->rate = tmp; 3553d9dd6fdSMikko Perttunen timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, 3563d9dd6fdSMikko Perttunen sizeof(u32), GFP_KERNEL); 3573d9dd6fdSMikko Perttunen if (!timing->emem_data) 3583d9dd6fdSMikko Perttunen return -ENOMEM; 3593d9dd6fdSMikko Perttunen 3603d9dd6fdSMikko Perttunen err = of_property_read_u32_array(node, "nvidia,emem-configuration", 3613d9dd6fdSMikko Perttunen timing->emem_data, 3623d9dd6fdSMikko Perttunen mc->soc->num_emem_regs); 3633d9dd6fdSMikko Perttunen if (err) { 3643d9dd6fdSMikko Perttunen dev_err(mc->dev, 365c86f9854SRob Herring "timing %pOFn: failed to read EMEM configuration\n", 366c86f9854SRob Herring node); 3673d9dd6fdSMikko Perttunen return err; 3683d9dd6fdSMikko Perttunen } 3693d9dd6fdSMikko Perttunen 3703d9dd6fdSMikko Perttunen return 0; 3713d9dd6fdSMikko Perttunen } 3723d9dd6fdSMikko Perttunen 3733d9dd6fdSMikko Perttunen static int load_timings(struct tegra_mc *mc, struct device_node *node) 3743d9dd6fdSMikko Perttunen { 3753d9dd6fdSMikko Perttunen struct device_node *child; 3763d9dd6fdSMikko Perttunen struct tegra_mc_timing *timing; 3773d9dd6fdSMikko Perttunen int child_count = of_get_child_count(node); 3783d9dd6fdSMikko Perttunen int i = 0, err; 3793d9dd6fdSMikko Perttunen 3803d9dd6fdSMikko Perttunen mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing), 3813d9dd6fdSMikko Perttunen GFP_KERNEL); 3823d9dd6fdSMikko Perttunen if (!mc->timings) 3833d9dd6fdSMikko Perttunen return -ENOMEM; 3843d9dd6fdSMikko Perttunen 3853d9dd6fdSMikko Perttunen mc->num_timings = child_count; 3863d9dd6fdSMikko Perttunen 3873d9dd6fdSMikko Perttunen for_each_child_of_node(node, child) { 3883d9dd6fdSMikko Perttunen timing = &mc->timings[i++]; 3893d9dd6fdSMikko Perttunen 3903d9dd6fdSMikko Perttunen err = load_one_timing(mc, timing, child); 39155bb1d83SAmitoj Kaur Chawla if (err) { 39255bb1d83SAmitoj Kaur Chawla of_node_put(child); 3933d9dd6fdSMikko Perttunen return err; 3943d9dd6fdSMikko Perttunen } 39555bb1d83SAmitoj Kaur Chawla } 3963d9dd6fdSMikko Perttunen 3973d9dd6fdSMikko Perttunen return 0; 3983d9dd6fdSMikko Perttunen } 3993d9dd6fdSMikko Perttunen 4003d9dd6fdSMikko Perttunen static int tegra_mc_setup_timings(struct tegra_mc *mc) 4013d9dd6fdSMikko Perttunen { 4023d9dd6fdSMikko Perttunen struct device_node *node; 4033d9dd6fdSMikko Perttunen u32 ram_code, node_ram_code; 4043d9dd6fdSMikko Perttunen int err; 4053d9dd6fdSMikko Perttunen 4063d9dd6fdSMikko Perttunen ram_code = tegra_read_ram_code(); 4073d9dd6fdSMikko Perttunen 4083d9dd6fdSMikko Perttunen mc->num_timings = 0; 4093d9dd6fdSMikko Perttunen 4103d9dd6fdSMikko Perttunen for_each_child_of_node(mc->dev->of_node, node) { 4113d9dd6fdSMikko Perttunen err = of_property_read_u32(node, "nvidia,ram-code", 4123d9dd6fdSMikko Perttunen &node_ram_code); 413d1122e4bSJulia Lawall if (err || (node_ram_code != ram_code)) 4143d9dd6fdSMikko Perttunen continue; 4153d9dd6fdSMikko Perttunen 4163d9dd6fdSMikko Perttunen err = load_timings(mc, node); 41755bb1d83SAmitoj Kaur Chawla of_node_put(node); 4183d9dd6fdSMikko Perttunen if (err) 4193d9dd6fdSMikko Perttunen return err; 4203d9dd6fdSMikko Perttunen break; 4213d9dd6fdSMikko Perttunen } 4223d9dd6fdSMikko Perttunen 4233d9dd6fdSMikko Perttunen if (mc->num_timings == 0) 4243d9dd6fdSMikko Perttunen dev_warn(mc->dev, 4253d9dd6fdSMikko Perttunen "no memory timings for RAM code %u registered\n", 4263d9dd6fdSMikko Perttunen ram_code); 4273d9dd6fdSMikko Perttunen 4283d9dd6fdSMikko Perttunen return 0; 4293d9dd6fdSMikko Perttunen } 4303d9dd6fdSMikko Perttunen 43189184651SThierry Reding static const char *const status_names[32] = { 43289184651SThierry Reding [ 1] = "External interrupt", 43389184651SThierry Reding [ 6] = "EMEM address decode error", 434a8d502fdSDmitry Osipenko [ 7] = "GART page fault", 43589184651SThierry Reding [ 8] = "Security violation", 43689184651SThierry Reding [ 9] = "EMEM arbitration error", 43789184651SThierry Reding [10] = "Page fault", 43889184651SThierry Reding [11] = "Invalid APB ASID update", 43989184651SThierry Reding [12] = "VPR violation", 44089184651SThierry Reding [13] = "Secure carveout violation", 44189184651SThierry Reding [16] = "MTS carveout violation", 44289184651SThierry Reding }; 44389184651SThierry Reding 44489184651SThierry Reding static const char *const error_names[8] = { 44589184651SThierry Reding [2] = "EMEM decode error", 44689184651SThierry Reding [3] = "TrustZone violation", 44789184651SThierry Reding [4] = "Carveout violation", 44889184651SThierry Reding [6] = "SMMU translation error", 44989184651SThierry Reding }; 45089184651SThierry Reding 45189184651SThierry Reding static irqreturn_t tegra_mc_irq(int irq, void *data) 45289184651SThierry Reding { 45389184651SThierry Reding struct tegra_mc *mc = data; 4541c74d5c0SDmitry Osipenko unsigned long status; 45589184651SThierry Reding unsigned int bit; 45689184651SThierry Reding 45789184651SThierry Reding /* mask all interrupts to avoid flooding */ 4581c74d5c0SDmitry Osipenko status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; 459bf3fbdfbSDmitry Osipenko if (!status) 460bf3fbdfbSDmitry Osipenko return IRQ_NONE; 46189184651SThierry Reding 46289184651SThierry Reding for_each_set_bit(bit, &status, 32) { 46389184651SThierry Reding const char *error = status_names[bit] ?: "unknown"; 46489184651SThierry Reding const char *client = "unknown", *desc; 46589184651SThierry Reding const char *direction, *secure; 46689184651SThierry Reding phys_addr_t addr = 0; 46789184651SThierry Reding unsigned int i; 46889184651SThierry Reding char perm[7]; 46989184651SThierry Reding u8 id, type; 47089184651SThierry Reding u32 value; 47189184651SThierry Reding 47289184651SThierry Reding value = mc_readl(mc, MC_ERR_STATUS); 47389184651SThierry Reding 47489184651SThierry Reding #ifdef CONFIG_PHYS_ADDR_T_64BIT 47589184651SThierry Reding if (mc->soc->num_address_bits > 32) { 47689184651SThierry Reding addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & 47789184651SThierry Reding MC_ERR_STATUS_ADR_HI_MASK); 47889184651SThierry Reding addr <<= 32; 47989184651SThierry Reding } 48089184651SThierry Reding #endif 48189184651SThierry Reding 48289184651SThierry Reding if (value & MC_ERR_STATUS_RW) 48389184651SThierry Reding direction = "write"; 48489184651SThierry Reding else 48589184651SThierry Reding direction = "read"; 48689184651SThierry Reding 48789184651SThierry Reding if (value & MC_ERR_STATUS_SECURITY) 48889184651SThierry Reding secure = "secure "; 48989184651SThierry Reding else 49089184651SThierry Reding secure = ""; 49189184651SThierry Reding 4923c01cf3bSPaul Walmsley id = value & mc->soc->client_id_mask; 49389184651SThierry Reding 49489184651SThierry Reding for (i = 0; i < mc->soc->num_clients; i++) { 49589184651SThierry Reding if (mc->soc->clients[i].id == id) { 49689184651SThierry Reding client = mc->soc->clients[i].name; 49789184651SThierry Reding break; 49889184651SThierry Reding } 49989184651SThierry Reding } 50089184651SThierry Reding 50189184651SThierry Reding type = (value & MC_ERR_STATUS_TYPE_MASK) >> 50289184651SThierry Reding MC_ERR_STATUS_TYPE_SHIFT; 50389184651SThierry Reding desc = error_names[type]; 50489184651SThierry Reding 50589184651SThierry Reding switch (value & MC_ERR_STATUS_TYPE_MASK) { 50689184651SThierry Reding case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE: 50789184651SThierry Reding perm[0] = ' '; 50889184651SThierry Reding perm[1] = '['; 50989184651SThierry Reding 51089184651SThierry Reding if (value & MC_ERR_STATUS_READABLE) 51189184651SThierry Reding perm[2] = 'R'; 51289184651SThierry Reding else 51389184651SThierry Reding perm[2] = '-'; 51489184651SThierry Reding 51589184651SThierry Reding if (value & MC_ERR_STATUS_WRITABLE) 51689184651SThierry Reding perm[3] = 'W'; 51789184651SThierry Reding else 51889184651SThierry Reding perm[3] = '-'; 51989184651SThierry Reding 52089184651SThierry Reding if (value & MC_ERR_STATUS_NONSECURE) 52189184651SThierry Reding perm[4] = '-'; 52289184651SThierry Reding else 52389184651SThierry Reding perm[4] = 'S'; 52489184651SThierry Reding 52589184651SThierry Reding perm[5] = ']'; 52689184651SThierry Reding perm[6] = '\0'; 52789184651SThierry Reding break; 52889184651SThierry Reding 52989184651SThierry Reding default: 53089184651SThierry Reding perm[0] = '\0'; 53189184651SThierry Reding break; 53289184651SThierry Reding } 53389184651SThierry Reding 53489184651SThierry Reding value = mc_readl(mc, MC_ERR_ADR); 53589184651SThierry Reding addr |= value; 53689184651SThierry Reding 53789184651SThierry Reding dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", 53889184651SThierry Reding client, secure, direction, &addr, error, 53989184651SThierry Reding desc, perm); 54089184651SThierry Reding } 54189184651SThierry Reding 54289184651SThierry Reding /* clear interrupts */ 54389184651SThierry Reding mc_writel(mc, status, MC_INTSTATUS); 54489184651SThierry Reding 54589184651SThierry Reding return IRQ_HANDLED; 54689184651SThierry Reding } 54789184651SThierry Reding 548a8d502fdSDmitry Osipenko static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data) 549a8d502fdSDmitry Osipenko { 550a8d502fdSDmitry Osipenko struct tegra_mc *mc = data; 551a8d502fdSDmitry Osipenko unsigned long status; 552a8d502fdSDmitry Osipenko unsigned int bit; 553a8d502fdSDmitry Osipenko 554a8d502fdSDmitry Osipenko /* mask all interrupts to avoid flooding */ 555a8d502fdSDmitry Osipenko status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; 556a8d502fdSDmitry Osipenko if (!status) 557a8d502fdSDmitry Osipenko return IRQ_NONE; 558a8d502fdSDmitry Osipenko 559a8d502fdSDmitry Osipenko for_each_set_bit(bit, &status, 32) { 560a8d502fdSDmitry Osipenko const char *direction = "read", *secure = ""; 561a8d502fdSDmitry Osipenko const char *error = status_names[bit]; 562a8d502fdSDmitry Osipenko const char *client, *desc; 563a8d502fdSDmitry Osipenko phys_addr_t addr; 564a8d502fdSDmitry Osipenko u32 value, reg; 565a8d502fdSDmitry Osipenko u8 id, type; 566a8d502fdSDmitry Osipenko 567a8d502fdSDmitry Osipenko switch (BIT(bit)) { 568a8d502fdSDmitry Osipenko case MC_INT_DECERR_EMEM: 569a8d502fdSDmitry Osipenko reg = MC_DECERR_EMEM_OTHERS_STATUS; 570a8d502fdSDmitry Osipenko value = mc_readl(mc, reg); 571a8d502fdSDmitry Osipenko 572a8d502fdSDmitry Osipenko id = value & mc->soc->client_id_mask; 573a8d502fdSDmitry Osipenko desc = error_names[2]; 574a8d502fdSDmitry Osipenko 575a8d502fdSDmitry Osipenko if (value & BIT(31)) 576a8d502fdSDmitry Osipenko direction = "write"; 577a8d502fdSDmitry Osipenko break; 578a8d502fdSDmitry Osipenko 579a8d502fdSDmitry Osipenko case MC_INT_INVALID_GART_PAGE: 580b3bb6b85SDmitry Osipenko reg = MC_GART_ERROR_REQ; 581b3bb6b85SDmitry Osipenko value = mc_readl(mc, reg); 582b3bb6b85SDmitry Osipenko 583b3bb6b85SDmitry Osipenko id = (value >> 1) & mc->soc->client_id_mask; 584b3bb6b85SDmitry Osipenko desc = error_names[2]; 585b3bb6b85SDmitry Osipenko 586b3bb6b85SDmitry Osipenko if (value & BIT(0)) 587b3bb6b85SDmitry Osipenko direction = "write"; 588b3bb6b85SDmitry Osipenko break; 589a8d502fdSDmitry Osipenko 590a8d502fdSDmitry Osipenko case MC_INT_SECURITY_VIOLATION: 591a8d502fdSDmitry Osipenko reg = MC_SECURITY_VIOLATION_STATUS; 592a8d502fdSDmitry Osipenko value = mc_readl(mc, reg); 593a8d502fdSDmitry Osipenko 594a8d502fdSDmitry Osipenko id = value & mc->soc->client_id_mask; 595a8d502fdSDmitry Osipenko type = (value & BIT(30)) ? 4 : 3; 596a8d502fdSDmitry Osipenko desc = error_names[type]; 597a8d502fdSDmitry Osipenko secure = "secure "; 598a8d502fdSDmitry Osipenko 599a8d502fdSDmitry Osipenko if (value & BIT(31)) 600a8d502fdSDmitry Osipenko direction = "write"; 601a8d502fdSDmitry Osipenko break; 602a8d502fdSDmitry Osipenko 603a8d502fdSDmitry Osipenko default: 604a8d502fdSDmitry Osipenko continue; 605a8d502fdSDmitry Osipenko } 606a8d502fdSDmitry Osipenko 607a8d502fdSDmitry Osipenko client = mc->soc->clients[id].name; 608a8d502fdSDmitry Osipenko addr = mc_readl(mc, reg + sizeof(u32)); 609a8d502fdSDmitry Osipenko 610a8d502fdSDmitry Osipenko dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n", 611a8d502fdSDmitry Osipenko client, secure, direction, &addr, error, 612a8d502fdSDmitry Osipenko desc); 613a8d502fdSDmitry Osipenko } 614a8d502fdSDmitry Osipenko 615a8d502fdSDmitry Osipenko /* clear interrupts */ 616a8d502fdSDmitry Osipenko mc_writel(mc, status, MC_INTSTATUS); 617a8d502fdSDmitry Osipenko 618a8d502fdSDmitry Osipenko return IRQ_HANDLED; 619a8d502fdSDmitry Osipenko } 620a8d502fdSDmitry Osipenko 62189184651SThierry Reding static int tegra_mc_probe(struct platform_device *pdev) 62289184651SThierry Reding { 62389184651SThierry Reding struct resource *res; 62489184651SThierry Reding struct tegra_mc *mc; 625a8d502fdSDmitry Osipenko void *isr; 62689184651SThierry Reding int err; 62789184651SThierry Reding 62889184651SThierry Reding mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); 62989184651SThierry Reding if (!mc) 63089184651SThierry Reding return -ENOMEM; 63189184651SThierry Reding 63289184651SThierry Reding platform_set_drvdata(pdev, mc); 63320e92462SDmitry Osipenko spin_lock_init(&mc->lock); 63459cd046fSDmitry Osipenko mc->soc = of_device_get_match_data(&pdev->dev); 63589184651SThierry Reding mc->dev = &pdev->dev; 63689184651SThierry Reding 63789184651SThierry Reding /* length of MC tick in nanoseconds */ 63889184651SThierry Reding mc->tick = 30; 63989184651SThierry Reding 64089184651SThierry Reding res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 64189184651SThierry Reding mc->regs = devm_ioremap_resource(&pdev->dev, res); 64289184651SThierry Reding if (IS_ERR(mc->regs)) 64389184651SThierry Reding return PTR_ERR(mc->regs); 64489184651SThierry Reding 64589184651SThierry Reding mc->clk = devm_clk_get(&pdev->dev, "mc"); 64689184651SThierry Reding if (IS_ERR(mc->clk)) { 64789184651SThierry Reding dev_err(&pdev->dev, "failed to get MC clock: %ld\n", 64889184651SThierry Reding PTR_ERR(mc->clk)); 64989184651SThierry Reding return PTR_ERR(mc->clk); 65089184651SThierry Reding } 65189184651SThierry Reding 65296efa118SDmitry Osipenko #ifdef CONFIG_ARCH_TEGRA_2x_SOC 65396efa118SDmitry Osipenko if (mc->soc == &tegra20_mc_soc) { 65496efa118SDmitry Osipenko isr = tegra20_mc_irq; 65596efa118SDmitry Osipenko } else 65696efa118SDmitry Osipenko #endif 65796efa118SDmitry Osipenko { 65889184651SThierry Reding err = tegra_mc_setup_latency_allowance(mc); 65989184651SThierry Reding if (err < 0) { 66089184651SThierry Reding dev_err(&pdev->dev, "failed to setup latency allowance: %d\n", 66189184651SThierry Reding err); 66289184651SThierry Reding return err; 66389184651SThierry Reding } 66489184651SThierry Reding 665a8d502fdSDmitry Osipenko isr = tegra_mc_irq; 666a8d502fdSDmitry Osipenko 6673d9dd6fdSMikko Perttunen err = tegra_mc_setup_timings(mc); 6683d9dd6fdSMikko Perttunen if (err < 0) { 669be4dbdecSDmitry Osipenko dev_err(&pdev->dev, "failed to setup timings: %d\n", 670be4dbdecSDmitry Osipenko err); 6713d9dd6fdSMikko Perttunen return err; 6723d9dd6fdSMikko Perttunen } 673be4dbdecSDmitry Osipenko } 6743d9dd6fdSMikko Perttunen 67589184651SThierry Reding mc->irq = platform_get_irq(pdev, 0); 67689184651SThierry Reding if (mc->irq < 0) { 67789184651SThierry Reding dev_err(&pdev->dev, "interrupt not specified\n"); 67889184651SThierry Reding return mc->irq; 67989184651SThierry Reding } 68089184651SThierry Reding 6813c01cf3bSPaul Walmsley WARN(!mc->soc->client_id_mask, "Missing client ID mask for this SoC\n"); 6823c01cf3bSPaul Walmsley 6831c74d5c0SDmitry Osipenko mc_writel(mc, mc->soc->intmask, MC_INTMASK); 68489184651SThierry Reding 68533ea002aSDmitry Osipenko err = devm_request_irq(&pdev->dev, mc->irq, isr, 0, 686db4a9c19SDmitry Osipenko dev_name(&pdev->dev), mc); 687db4a9c19SDmitry Osipenko if (err < 0) { 688db4a9c19SDmitry Osipenko dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, 689db4a9c19SDmitry Osipenko err); 690db4a9c19SDmitry Osipenko return err; 691db4a9c19SDmitry Osipenko } 692db4a9c19SDmitry Osipenko 6931662dd64SDmitry Osipenko err = tegra_mc_reset_setup(mc); 6941662dd64SDmitry Osipenko if (err < 0) 6951662dd64SDmitry Osipenko dev_err(&pdev->dev, "failed to register reset controller: %d\n", 6961662dd64SDmitry Osipenko err); 6971662dd64SDmitry Osipenko 698568ece5bSDmitry Osipenko if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) { 69945a81df0SDmitry Osipenko mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); 700568ece5bSDmitry Osipenko if (IS_ERR(mc->smmu)) { 70145a81df0SDmitry Osipenko dev_err(&pdev->dev, "failed to probe SMMU: %ld\n", 70245a81df0SDmitry Osipenko PTR_ERR(mc->smmu)); 703568ece5bSDmitry Osipenko mc->smmu = NULL; 704568ece5bSDmitry Osipenko } 70545a81df0SDmitry Osipenko } 70645a81df0SDmitry Osipenko 707ce2785a7SDmitry Osipenko if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && !mc->soc->smmu) { 708ce2785a7SDmitry Osipenko mc->gart = tegra_gart_probe(&pdev->dev, mc); 709ce2785a7SDmitry Osipenko if (IS_ERR(mc->gart)) { 710ce2785a7SDmitry Osipenko dev_err(&pdev->dev, "failed to probe GART: %ld\n", 711ce2785a7SDmitry Osipenko PTR_ERR(mc->gart)); 712ce2785a7SDmitry Osipenko mc->gart = NULL; 713ce2785a7SDmitry Osipenko } 714ce2785a7SDmitry Osipenko } 715ce2785a7SDmitry Osipenko 71689184651SThierry Reding return 0; 71789184651SThierry Reding } 71889184651SThierry Reding 719ce2785a7SDmitry Osipenko static int tegra_mc_suspend(struct device *dev) 720ce2785a7SDmitry Osipenko { 721ce2785a7SDmitry Osipenko struct tegra_mc *mc = dev_get_drvdata(dev); 722ce2785a7SDmitry Osipenko int err; 723ce2785a7SDmitry Osipenko 724ce2785a7SDmitry Osipenko if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { 725ce2785a7SDmitry Osipenko err = tegra_gart_suspend(mc->gart); 726ce2785a7SDmitry Osipenko if (err) 727ce2785a7SDmitry Osipenko return err; 728ce2785a7SDmitry Osipenko } 729ce2785a7SDmitry Osipenko 730ce2785a7SDmitry Osipenko return 0; 731ce2785a7SDmitry Osipenko } 732ce2785a7SDmitry Osipenko 733ce2785a7SDmitry Osipenko static int tegra_mc_resume(struct device *dev) 734ce2785a7SDmitry Osipenko { 735ce2785a7SDmitry Osipenko struct tegra_mc *mc = dev_get_drvdata(dev); 736ce2785a7SDmitry Osipenko int err; 737ce2785a7SDmitry Osipenko 738ce2785a7SDmitry Osipenko if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { 739ce2785a7SDmitry Osipenko err = tegra_gart_resume(mc->gart); 740ce2785a7SDmitry Osipenko if (err) 741ce2785a7SDmitry Osipenko return err; 742ce2785a7SDmitry Osipenko } 743ce2785a7SDmitry Osipenko 744ce2785a7SDmitry Osipenko return 0; 745ce2785a7SDmitry Osipenko } 746ce2785a7SDmitry Osipenko 747ce2785a7SDmitry Osipenko static const struct dev_pm_ops tegra_mc_pm_ops = { 748ce2785a7SDmitry Osipenko .suspend = tegra_mc_suspend, 749ce2785a7SDmitry Osipenko .resume = tegra_mc_resume, 750ce2785a7SDmitry Osipenko }; 751ce2785a7SDmitry Osipenko 75289184651SThierry Reding static struct platform_driver tegra_mc_driver = { 75389184651SThierry Reding .driver = { 75489184651SThierry Reding .name = "tegra-mc", 75589184651SThierry Reding .of_match_table = tegra_mc_of_match, 756ce2785a7SDmitry Osipenko .pm = &tegra_mc_pm_ops, 75789184651SThierry Reding .suppress_bind_attrs = true, 75889184651SThierry Reding }, 75989184651SThierry Reding .prevent_deferred_probe = true, 76089184651SThierry Reding .probe = tegra_mc_probe, 76189184651SThierry Reding }; 76289184651SThierry Reding 76389184651SThierry Reding static int tegra_mc_init(void) 76489184651SThierry Reding { 76589184651SThierry Reding return platform_driver_register(&tegra_mc_driver); 76689184651SThierry Reding } 76789184651SThierry Reding arch_initcall(tegra_mc_init); 76889184651SThierry Reding 76989184651SThierry Reding MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 77089184651SThierry Reding MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver"); 77189184651SThierry Reding MODULE_LICENSE("GPL v2"); 772