189184651SThierry Reding /* 289184651SThierry Reding * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. 389184651SThierry Reding * 489184651SThierry Reding * This program is free software; you can redistribute it and/or modify 589184651SThierry Reding * it under the terms of the GNU General Public License version 2 as 689184651SThierry Reding * published by the Free Software Foundation. 789184651SThierry Reding */ 889184651SThierry Reding 989184651SThierry Reding #include <linux/clk.h> 1089184651SThierry Reding #include <linux/interrupt.h> 1189184651SThierry Reding #include <linux/kernel.h> 1289184651SThierry Reding #include <linux/module.h> 1389184651SThierry Reding #include <linux/of.h> 1489184651SThierry Reding #include <linux/platform_device.h> 1589184651SThierry Reding #include <linux/slab.h> 163d9dd6fdSMikko Perttunen #include <linux/sort.h> 173d9dd6fdSMikko Perttunen 183d9dd6fdSMikko Perttunen #include <soc/tegra/fuse.h> 1989184651SThierry Reding 2089184651SThierry Reding #include "mc.h" 2189184651SThierry Reding 2289184651SThierry Reding #define MC_INTSTATUS 0x000 2389184651SThierry Reding 2489184651SThierry Reding #define MC_INTMASK 0x004 2589184651SThierry Reding 2689184651SThierry Reding #define MC_ERR_STATUS 0x08 2789184651SThierry Reding #define MC_ERR_STATUS_TYPE_SHIFT 28 2889184651SThierry Reding #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT) 2989184651SThierry Reding #define MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT) 3089184651SThierry Reding #define MC_ERR_STATUS_READABLE (1 << 27) 3189184651SThierry Reding #define MC_ERR_STATUS_WRITABLE (1 << 26) 3289184651SThierry Reding #define MC_ERR_STATUS_NONSECURE (1 << 25) 3389184651SThierry Reding #define MC_ERR_STATUS_ADR_HI_SHIFT 20 3489184651SThierry Reding #define MC_ERR_STATUS_ADR_HI_MASK 0x3 3589184651SThierry Reding #define MC_ERR_STATUS_SECURITY (1 << 17) 3689184651SThierry Reding #define MC_ERR_STATUS_RW (1 << 16) 3789184651SThierry Reding 3889184651SThierry Reding #define MC_ERR_ADR 0x0c 3989184651SThierry Reding 4089184651SThierry Reding #define MC_EMEM_ARB_CFG 0x90 4189184651SThierry Reding #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0) 4289184651SThierry Reding #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff 4389184651SThierry Reding #define MC_EMEM_ARB_MISC0 0xd8 4489184651SThierry Reding 453d9dd6fdSMikko Perttunen #define MC_EMEM_ADR_CFG 0x54 463d9dd6fdSMikko Perttunen #define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0) 473d9dd6fdSMikko Perttunen 4889184651SThierry Reding static const struct of_device_id tegra_mc_of_match[] = { 4989184651SThierry Reding #ifdef CONFIG_ARCH_TEGRA_3x_SOC 5089184651SThierry Reding { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc }, 5189184651SThierry Reding #endif 5289184651SThierry Reding #ifdef CONFIG_ARCH_TEGRA_114_SOC 5389184651SThierry Reding { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc }, 5489184651SThierry Reding #endif 5589184651SThierry Reding #ifdef CONFIG_ARCH_TEGRA_124_SOC 5689184651SThierry Reding { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc }, 5789184651SThierry Reding #endif 58242b1d71SThierry Reding #ifdef CONFIG_ARCH_TEGRA_132_SOC 59242b1d71SThierry Reding { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc }, 60242b1d71SThierry Reding #endif 61588c43a7SThierry Reding #ifdef CONFIG_ARCH_TEGRA_210_SOC 62588c43a7SThierry Reding { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc }, 63588c43a7SThierry Reding #endif 6489184651SThierry Reding { } 6589184651SThierry Reding }; 6689184651SThierry Reding MODULE_DEVICE_TABLE(of, tegra_mc_of_match); 6789184651SThierry Reding 6889184651SThierry Reding static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) 6989184651SThierry Reding { 7089184651SThierry Reding unsigned long long tick; 7189184651SThierry Reding unsigned int i; 7289184651SThierry Reding u32 value; 7389184651SThierry Reding 7489184651SThierry Reding /* compute the number of MC clock cycles per tick */ 7589184651SThierry Reding tick = mc->tick * clk_get_rate(mc->clk); 7689184651SThierry Reding do_div(tick, NSEC_PER_SEC); 7789184651SThierry Reding 7889184651SThierry Reding value = readl(mc->regs + MC_EMEM_ARB_CFG); 7989184651SThierry Reding value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK; 8089184651SThierry Reding value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick); 8189184651SThierry Reding writel(value, mc->regs + MC_EMEM_ARB_CFG); 8289184651SThierry Reding 8389184651SThierry Reding /* write latency allowance defaults */ 8489184651SThierry Reding for (i = 0; i < mc->soc->num_clients; i++) { 8589184651SThierry Reding const struct tegra_mc_la *la = &mc->soc->clients[i].la; 8689184651SThierry Reding u32 value; 8789184651SThierry Reding 8889184651SThierry Reding value = readl(mc->regs + la->reg); 8989184651SThierry Reding value &= ~(la->mask << la->shift); 9089184651SThierry Reding value |= (la->def & la->mask) << la->shift; 9189184651SThierry Reding writel(value, mc->regs + la->reg); 9289184651SThierry Reding } 9389184651SThierry Reding 9489184651SThierry Reding return 0; 9589184651SThierry Reding } 9689184651SThierry Reding 973d9dd6fdSMikko Perttunen void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) 983d9dd6fdSMikko Perttunen { 993d9dd6fdSMikko Perttunen unsigned int i; 1003d9dd6fdSMikko Perttunen struct tegra_mc_timing *timing = NULL; 1013d9dd6fdSMikko Perttunen 1023d9dd6fdSMikko Perttunen for (i = 0; i < mc->num_timings; i++) { 1033d9dd6fdSMikko Perttunen if (mc->timings[i].rate == rate) { 1043d9dd6fdSMikko Perttunen timing = &mc->timings[i]; 1053d9dd6fdSMikko Perttunen break; 1063d9dd6fdSMikko Perttunen } 1073d9dd6fdSMikko Perttunen } 1083d9dd6fdSMikko Perttunen 1093d9dd6fdSMikko Perttunen if (!timing) { 1103d9dd6fdSMikko Perttunen dev_err(mc->dev, "no memory timing registered for rate %lu\n", 1113d9dd6fdSMikko Perttunen rate); 1123d9dd6fdSMikko Perttunen return; 1133d9dd6fdSMikko Perttunen } 1143d9dd6fdSMikko Perttunen 1153d9dd6fdSMikko Perttunen for (i = 0; i < mc->soc->num_emem_regs; ++i) 1163d9dd6fdSMikko Perttunen mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); 1173d9dd6fdSMikko Perttunen } 1183d9dd6fdSMikko Perttunen 1193d9dd6fdSMikko Perttunen unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) 1203d9dd6fdSMikko Perttunen { 1213d9dd6fdSMikko Perttunen u8 dram_count; 1223d9dd6fdSMikko Perttunen 1233d9dd6fdSMikko Perttunen dram_count = mc_readl(mc, MC_EMEM_ADR_CFG); 1243d9dd6fdSMikko Perttunen dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV; 1253d9dd6fdSMikko Perttunen dram_count++; 1263d9dd6fdSMikko Perttunen 1273d9dd6fdSMikko Perttunen return dram_count; 1283d9dd6fdSMikko Perttunen } 1293d9dd6fdSMikko Perttunen 1303d9dd6fdSMikko Perttunen static int load_one_timing(struct tegra_mc *mc, 1313d9dd6fdSMikko Perttunen struct tegra_mc_timing *timing, 1323d9dd6fdSMikko Perttunen struct device_node *node) 1333d9dd6fdSMikko Perttunen { 1343d9dd6fdSMikko Perttunen int err; 1353d9dd6fdSMikko Perttunen u32 tmp; 1363d9dd6fdSMikko Perttunen 1373d9dd6fdSMikko Perttunen err = of_property_read_u32(node, "clock-frequency", &tmp); 1383d9dd6fdSMikko Perttunen if (err) { 1393d9dd6fdSMikko Perttunen dev_err(mc->dev, 1403d9dd6fdSMikko Perttunen "timing %s: failed to read rate\n", node->name); 1413d9dd6fdSMikko Perttunen return err; 1423d9dd6fdSMikko Perttunen } 1433d9dd6fdSMikko Perttunen 1443d9dd6fdSMikko Perttunen timing->rate = tmp; 1453d9dd6fdSMikko Perttunen timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, 1463d9dd6fdSMikko Perttunen sizeof(u32), GFP_KERNEL); 1473d9dd6fdSMikko Perttunen if (!timing->emem_data) 1483d9dd6fdSMikko Perttunen return -ENOMEM; 1493d9dd6fdSMikko Perttunen 1503d9dd6fdSMikko Perttunen err = of_property_read_u32_array(node, "nvidia,emem-configuration", 1513d9dd6fdSMikko Perttunen timing->emem_data, 1523d9dd6fdSMikko Perttunen mc->soc->num_emem_regs); 1533d9dd6fdSMikko Perttunen if (err) { 1543d9dd6fdSMikko Perttunen dev_err(mc->dev, 1553d9dd6fdSMikko Perttunen "timing %s: failed to read EMEM configuration\n", 1563d9dd6fdSMikko Perttunen node->name); 1573d9dd6fdSMikko Perttunen return err; 1583d9dd6fdSMikko Perttunen } 1593d9dd6fdSMikko Perttunen 1603d9dd6fdSMikko Perttunen return 0; 1613d9dd6fdSMikko Perttunen } 1623d9dd6fdSMikko Perttunen 1633d9dd6fdSMikko Perttunen static int load_timings(struct tegra_mc *mc, struct device_node *node) 1643d9dd6fdSMikko Perttunen { 1653d9dd6fdSMikko Perttunen struct device_node *child; 1663d9dd6fdSMikko Perttunen struct tegra_mc_timing *timing; 1673d9dd6fdSMikko Perttunen int child_count = of_get_child_count(node); 1683d9dd6fdSMikko Perttunen int i = 0, err; 1693d9dd6fdSMikko Perttunen 1703d9dd6fdSMikko Perttunen mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing), 1713d9dd6fdSMikko Perttunen GFP_KERNEL); 1723d9dd6fdSMikko Perttunen if (!mc->timings) 1733d9dd6fdSMikko Perttunen return -ENOMEM; 1743d9dd6fdSMikko Perttunen 1753d9dd6fdSMikko Perttunen mc->num_timings = child_count; 1763d9dd6fdSMikko Perttunen 1773d9dd6fdSMikko Perttunen for_each_child_of_node(node, child) { 1783d9dd6fdSMikko Perttunen timing = &mc->timings[i++]; 1793d9dd6fdSMikko Perttunen 1803d9dd6fdSMikko Perttunen err = load_one_timing(mc, timing, child); 18155bb1d83SAmitoj Kaur Chawla if (err) { 18255bb1d83SAmitoj Kaur Chawla of_node_put(child); 1833d9dd6fdSMikko Perttunen return err; 1843d9dd6fdSMikko Perttunen } 18555bb1d83SAmitoj Kaur Chawla } 1863d9dd6fdSMikko Perttunen 1873d9dd6fdSMikko Perttunen return 0; 1883d9dd6fdSMikko Perttunen } 1893d9dd6fdSMikko Perttunen 1903d9dd6fdSMikko Perttunen static int tegra_mc_setup_timings(struct tegra_mc *mc) 1913d9dd6fdSMikko Perttunen { 1923d9dd6fdSMikko Perttunen struct device_node *node; 1933d9dd6fdSMikko Perttunen u32 ram_code, node_ram_code; 1943d9dd6fdSMikko Perttunen int err; 1953d9dd6fdSMikko Perttunen 1963d9dd6fdSMikko Perttunen ram_code = tegra_read_ram_code(); 1973d9dd6fdSMikko Perttunen 1983d9dd6fdSMikko Perttunen mc->num_timings = 0; 1993d9dd6fdSMikko Perttunen 2003d9dd6fdSMikko Perttunen for_each_child_of_node(mc->dev->of_node, node) { 2013d9dd6fdSMikko Perttunen err = of_property_read_u32(node, "nvidia,ram-code", 2023d9dd6fdSMikko Perttunen &node_ram_code); 203d1122e4bSJulia Lawall if (err || (node_ram_code != ram_code)) 2043d9dd6fdSMikko Perttunen continue; 2053d9dd6fdSMikko Perttunen 2063d9dd6fdSMikko Perttunen err = load_timings(mc, node); 20755bb1d83SAmitoj Kaur Chawla of_node_put(node); 2083d9dd6fdSMikko Perttunen if (err) 2093d9dd6fdSMikko Perttunen return err; 2103d9dd6fdSMikko Perttunen break; 2113d9dd6fdSMikko Perttunen } 2123d9dd6fdSMikko Perttunen 2133d9dd6fdSMikko Perttunen if (mc->num_timings == 0) 2143d9dd6fdSMikko Perttunen dev_warn(mc->dev, 2153d9dd6fdSMikko Perttunen "no memory timings for RAM code %u registered\n", 2163d9dd6fdSMikko Perttunen ram_code); 2173d9dd6fdSMikko Perttunen 2183d9dd6fdSMikko Perttunen return 0; 2193d9dd6fdSMikko Perttunen } 2203d9dd6fdSMikko Perttunen 22189184651SThierry Reding static const char *const status_names[32] = { 22289184651SThierry Reding [ 1] = "External interrupt", 22389184651SThierry Reding [ 6] = "EMEM address decode error", 22489184651SThierry Reding [ 8] = "Security violation", 22589184651SThierry Reding [ 9] = "EMEM arbitration error", 22689184651SThierry Reding [10] = "Page fault", 22789184651SThierry Reding [11] = "Invalid APB ASID update", 22889184651SThierry Reding [12] = "VPR violation", 22989184651SThierry Reding [13] = "Secure carveout violation", 23089184651SThierry Reding [16] = "MTS carveout violation", 23189184651SThierry Reding }; 23289184651SThierry Reding 23389184651SThierry Reding static const char *const error_names[8] = { 23489184651SThierry Reding [2] = "EMEM decode error", 23589184651SThierry Reding [3] = "TrustZone violation", 23689184651SThierry Reding [4] = "Carveout violation", 23789184651SThierry Reding [6] = "SMMU translation error", 23889184651SThierry Reding }; 23989184651SThierry Reding 24089184651SThierry Reding static irqreturn_t tegra_mc_irq(int irq, void *data) 24189184651SThierry Reding { 24289184651SThierry Reding struct tegra_mc *mc = data; 2431c74d5c0SDmitry Osipenko unsigned long status; 24489184651SThierry Reding unsigned int bit; 24589184651SThierry Reding 24689184651SThierry Reding /* mask all interrupts to avoid flooding */ 2471c74d5c0SDmitry Osipenko status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; 248bf3fbdfbSDmitry Osipenko if (!status) 249bf3fbdfbSDmitry Osipenko return IRQ_NONE; 25089184651SThierry Reding 25189184651SThierry Reding for_each_set_bit(bit, &status, 32) { 25289184651SThierry Reding const char *error = status_names[bit] ?: "unknown"; 25389184651SThierry Reding const char *client = "unknown", *desc; 25489184651SThierry Reding const char *direction, *secure; 25589184651SThierry Reding phys_addr_t addr = 0; 25689184651SThierry Reding unsigned int i; 25789184651SThierry Reding char perm[7]; 25889184651SThierry Reding u8 id, type; 25989184651SThierry Reding u32 value; 26089184651SThierry Reding 26189184651SThierry Reding value = mc_readl(mc, MC_ERR_STATUS); 26289184651SThierry Reding 26389184651SThierry Reding #ifdef CONFIG_PHYS_ADDR_T_64BIT 26489184651SThierry Reding if (mc->soc->num_address_bits > 32) { 26589184651SThierry Reding addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & 26689184651SThierry Reding MC_ERR_STATUS_ADR_HI_MASK); 26789184651SThierry Reding addr <<= 32; 26889184651SThierry Reding } 26989184651SThierry Reding #endif 27089184651SThierry Reding 27189184651SThierry Reding if (value & MC_ERR_STATUS_RW) 27289184651SThierry Reding direction = "write"; 27389184651SThierry Reding else 27489184651SThierry Reding direction = "read"; 27589184651SThierry Reding 27689184651SThierry Reding if (value & MC_ERR_STATUS_SECURITY) 27789184651SThierry Reding secure = "secure "; 27889184651SThierry Reding else 27989184651SThierry Reding secure = ""; 28089184651SThierry Reding 2813c01cf3bSPaul Walmsley id = value & mc->soc->client_id_mask; 28289184651SThierry Reding 28389184651SThierry Reding for (i = 0; i < mc->soc->num_clients; i++) { 28489184651SThierry Reding if (mc->soc->clients[i].id == id) { 28589184651SThierry Reding client = mc->soc->clients[i].name; 28689184651SThierry Reding break; 28789184651SThierry Reding } 28889184651SThierry Reding } 28989184651SThierry Reding 29089184651SThierry Reding type = (value & MC_ERR_STATUS_TYPE_MASK) >> 29189184651SThierry Reding MC_ERR_STATUS_TYPE_SHIFT; 29289184651SThierry Reding desc = error_names[type]; 29389184651SThierry Reding 29489184651SThierry Reding switch (value & MC_ERR_STATUS_TYPE_MASK) { 29589184651SThierry Reding case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE: 29689184651SThierry Reding perm[0] = ' '; 29789184651SThierry Reding perm[1] = '['; 29889184651SThierry Reding 29989184651SThierry Reding if (value & MC_ERR_STATUS_READABLE) 30089184651SThierry Reding perm[2] = 'R'; 30189184651SThierry Reding else 30289184651SThierry Reding perm[2] = '-'; 30389184651SThierry Reding 30489184651SThierry Reding if (value & MC_ERR_STATUS_WRITABLE) 30589184651SThierry Reding perm[3] = 'W'; 30689184651SThierry Reding else 30789184651SThierry Reding perm[3] = '-'; 30889184651SThierry Reding 30989184651SThierry Reding if (value & MC_ERR_STATUS_NONSECURE) 31089184651SThierry Reding perm[4] = '-'; 31189184651SThierry Reding else 31289184651SThierry Reding perm[4] = 'S'; 31389184651SThierry Reding 31489184651SThierry Reding perm[5] = ']'; 31589184651SThierry Reding perm[6] = '\0'; 31689184651SThierry Reding break; 31789184651SThierry Reding 31889184651SThierry Reding default: 31989184651SThierry Reding perm[0] = '\0'; 32089184651SThierry Reding break; 32189184651SThierry Reding } 32289184651SThierry Reding 32389184651SThierry Reding value = mc_readl(mc, MC_ERR_ADR); 32489184651SThierry Reding addr |= value; 32589184651SThierry Reding 32689184651SThierry Reding dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", 32789184651SThierry Reding client, secure, direction, &addr, error, 32889184651SThierry Reding desc, perm); 32989184651SThierry Reding } 33089184651SThierry Reding 33189184651SThierry Reding /* clear interrupts */ 33289184651SThierry Reding mc_writel(mc, status, MC_INTSTATUS); 33389184651SThierry Reding 33489184651SThierry Reding return IRQ_HANDLED; 33589184651SThierry Reding } 33689184651SThierry Reding 33789184651SThierry Reding static int tegra_mc_probe(struct platform_device *pdev) 33889184651SThierry Reding { 33989184651SThierry Reding const struct of_device_id *match; 34089184651SThierry Reding struct resource *res; 34189184651SThierry Reding struct tegra_mc *mc; 34289184651SThierry Reding int err; 34389184651SThierry Reding 34489184651SThierry Reding match = of_match_node(tegra_mc_of_match, pdev->dev.of_node); 34589184651SThierry Reding if (!match) 34689184651SThierry Reding return -ENODEV; 34789184651SThierry Reding 34889184651SThierry Reding mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); 34989184651SThierry Reding if (!mc) 35089184651SThierry Reding return -ENOMEM; 35189184651SThierry Reding 35289184651SThierry Reding platform_set_drvdata(pdev, mc); 35389184651SThierry Reding mc->soc = match->data; 35489184651SThierry Reding mc->dev = &pdev->dev; 35589184651SThierry Reding 35689184651SThierry Reding /* length of MC tick in nanoseconds */ 35789184651SThierry Reding mc->tick = 30; 35889184651SThierry Reding 35989184651SThierry Reding res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 36089184651SThierry Reding mc->regs = devm_ioremap_resource(&pdev->dev, res); 36189184651SThierry Reding if (IS_ERR(mc->regs)) 36289184651SThierry Reding return PTR_ERR(mc->regs); 36389184651SThierry Reding 36489184651SThierry Reding mc->clk = devm_clk_get(&pdev->dev, "mc"); 36589184651SThierry Reding if (IS_ERR(mc->clk)) { 36689184651SThierry Reding dev_err(&pdev->dev, "failed to get MC clock: %ld\n", 36789184651SThierry Reding PTR_ERR(mc->clk)); 36889184651SThierry Reding return PTR_ERR(mc->clk); 36989184651SThierry Reding } 37089184651SThierry Reding 37189184651SThierry Reding err = tegra_mc_setup_latency_allowance(mc); 37289184651SThierry Reding if (err < 0) { 37389184651SThierry Reding dev_err(&pdev->dev, "failed to setup latency allowance: %d\n", 37489184651SThierry Reding err); 37589184651SThierry Reding return err; 37689184651SThierry Reding } 37789184651SThierry Reding 3783d9dd6fdSMikko Perttunen err = tegra_mc_setup_timings(mc); 3793d9dd6fdSMikko Perttunen if (err < 0) { 3803d9dd6fdSMikko Perttunen dev_err(&pdev->dev, "failed to setup timings: %d\n", err); 3813d9dd6fdSMikko Perttunen return err; 3823d9dd6fdSMikko Perttunen } 3833d9dd6fdSMikko Perttunen 38489184651SThierry Reding if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) { 38589184651SThierry Reding mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); 38689184651SThierry Reding if (IS_ERR(mc->smmu)) { 38789184651SThierry Reding dev_err(&pdev->dev, "failed to probe SMMU: %ld\n", 38889184651SThierry Reding PTR_ERR(mc->smmu)); 38989184651SThierry Reding return PTR_ERR(mc->smmu); 39089184651SThierry Reding } 39189184651SThierry Reding } 39289184651SThierry Reding 39389184651SThierry Reding mc->irq = platform_get_irq(pdev, 0); 39489184651SThierry Reding if (mc->irq < 0) { 39589184651SThierry Reding dev_err(&pdev->dev, "interrupt not specified\n"); 39689184651SThierry Reding return mc->irq; 39789184651SThierry Reding } 39889184651SThierry Reding 3993c01cf3bSPaul Walmsley WARN(!mc->soc->client_id_mask, "Missing client ID mask for this SoC\n"); 4003c01cf3bSPaul Walmsley 4011c74d5c0SDmitry Osipenko mc_writel(mc, mc->soc->intmask, MC_INTMASK); 40289184651SThierry Reding 403db4a9c19SDmitry Osipenko err = devm_request_irq(&pdev->dev, mc->irq, tegra_mc_irq, IRQF_SHARED, 404db4a9c19SDmitry Osipenko dev_name(&pdev->dev), mc); 405db4a9c19SDmitry Osipenko if (err < 0) { 406db4a9c19SDmitry Osipenko dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, 407db4a9c19SDmitry Osipenko err); 408db4a9c19SDmitry Osipenko return err; 409db4a9c19SDmitry Osipenko } 410db4a9c19SDmitry Osipenko 41189184651SThierry Reding return 0; 41289184651SThierry Reding } 41389184651SThierry Reding 41489184651SThierry Reding static struct platform_driver tegra_mc_driver = { 41589184651SThierry Reding .driver = { 41689184651SThierry Reding .name = "tegra-mc", 41789184651SThierry Reding .of_match_table = tegra_mc_of_match, 41889184651SThierry Reding .suppress_bind_attrs = true, 41989184651SThierry Reding }, 42089184651SThierry Reding .prevent_deferred_probe = true, 42189184651SThierry Reding .probe = tegra_mc_probe, 42289184651SThierry Reding }; 42389184651SThierry Reding 42489184651SThierry Reding static int tegra_mc_init(void) 42589184651SThierry Reding { 42689184651SThierry Reding return platform_driver_register(&tegra_mc_driver); 42789184651SThierry Reding } 42889184651SThierry Reding arch_initcall(tegra_mc_init); 42989184651SThierry Reding 43089184651SThierry Reding MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 43189184651SThierry Reding MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver"); 43289184651SThierry Reding MODULE_LICENSE("GPL v2"); 433