1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics 2020 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/mfd/syscon.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_platform.h> 12 #include <linux/pinctrl/consumer.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 #include <linux/reset.h> 16 17 /* FMC2 Controller Registers */ 18 #define FMC2_BCR1 0x0 19 #define FMC2_BTR1 0x4 20 #define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1) 21 #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1) 22 #define FMC2_PCSCNTR 0x20 23 #define FMC2_BWTR1 0x104 24 #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1) 25 26 /* Register: FMC2_BCR1 */ 27 #define FMC2_BCR1_CCLKEN BIT(20) 28 #define FMC2_BCR1_FMC2EN BIT(31) 29 30 /* Register: FMC2_BCRx */ 31 #define FMC2_BCR_MBKEN BIT(0) 32 #define FMC2_BCR_MUXEN BIT(1) 33 #define FMC2_BCR_MTYP GENMASK(3, 2) 34 #define FMC2_BCR_MWID GENMASK(5, 4) 35 #define FMC2_BCR_FACCEN BIT(6) 36 #define FMC2_BCR_BURSTEN BIT(8) 37 #define FMC2_BCR_WAITPOL BIT(9) 38 #define FMC2_BCR_WAITCFG BIT(11) 39 #define FMC2_BCR_WREN BIT(12) 40 #define FMC2_BCR_WAITEN BIT(13) 41 #define FMC2_BCR_EXTMOD BIT(14) 42 #define FMC2_BCR_ASYNCWAIT BIT(15) 43 #define FMC2_BCR_CPSIZE GENMASK(18, 16) 44 #define FMC2_BCR_CBURSTRW BIT(19) 45 #define FMC2_BCR_NBLSET GENMASK(23, 22) 46 47 /* Register: FMC2_BTRx/FMC2_BWTRx */ 48 #define FMC2_BXTR_ADDSET GENMASK(3, 0) 49 #define FMC2_BXTR_ADDHLD GENMASK(7, 4) 50 #define FMC2_BXTR_DATAST GENMASK(15, 8) 51 #define FMC2_BXTR_BUSTURN GENMASK(19, 16) 52 #define FMC2_BTR_CLKDIV GENMASK(23, 20) 53 #define FMC2_BTR_DATLAT GENMASK(27, 24) 54 #define FMC2_BXTR_ACCMOD GENMASK(29, 28) 55 #define FMC2_BXTR_DATAHLD GENMASK(31, 30) 56 57 /* Register: FMC2_PCSCNTR */ 58 #define FMC2_PCSCNTR_CSCOUNT GENMASK(15, 0) 59 #define FMC2_PCSCNTR_CNTBEN(x) BIT((x) + 16) 60 61 #define FMC2_MAX_EBI_CE 4 62 #define FMC2_MAX_BANKS 5 63 64 #define FMC2_BCR_CPSIZE_0 0x0 65 #define FMC2_BCR_CPSIZE_128 0x1 66 #define FMC2_BCR_CPSIZE_256 0x2 67 #define FMC2_BCR_CPSIZE_512 0x3 68 #define FMC2_BCR_CPSIZE_1024 0x4 69 70 #define FMC2_BCR_MWID_8 0x0 71 #define FMC2_BCR_MWID_16 0x1 72 73 #define FMC2_BCR_MTYP_SRAM 0x0 74 #define FMC2_BCR_MTYP_PSRAM 0x1 75 #define FMC2_BCR_MTYP_NOR 0x2 76 77 #define FMC2_BXTR_EXTMOD_A 0x0 78 #define FMC2_BXTR_EXTMOD_B 0x1 79 #define FMC2_BXTR_EXTMOD_C 0x2 80 #define FMC2_BXTR_EXTMOD_D 0x3 81 82 #define FMC2_BCR_NBLSET_MAX 0x3 83 #define FMC2_BXTR_ADDSET_MAX 0xf 84 #define FMC2_BXTR_ADDHLD_MAX 0xf 85 #define FMC2_BXTR_DATAST_MAX 0xff 86 #define FMC2_BXTR_BUSTURN_MAX 0xf 87 #define FMC2_BXTR_DATAHLD_MAX 0x3 88 #define FMC2_BTR_CLKDIV_MAX 0xf 89 #define FMC2_BTR_DATLAT_MAX 0xf 90 #define FMC2_PCSCNTR_CSCOUNT_MAX 0xff 91 92 enum stm32_fmc2_ebi_bank { 93 FMC2_EBI1 = 0, 94 FMC2_EBI2, 95 FMC2_EBI3, 96 FMC2_EBI4, 97 FMC2_NAND 98 }; 99 100 enum stm32_fmc2_ebi_register_type { 101 FMC2_REG_BCR = 1, 102 FMC2_REG_BTR, 103 FMC2_REG_BWTR, 104 FMC2_REG_PCSCNTR 105 }; 106 107 enum stm32_fmc2_ebi_transaction_type { 108 FMC2_ASYNC_MODE_1_SRAM = 0, 109 FMC2_ASYNC_MODE_1_PSRAM, 110 FMC2_ASYNC_MODE_A_SRAM, 111 FMC2_ASYNC_MODE_A_PSRAM, 112 FMC2_ASYNC_MODE_2_NOR, 113 FMC2_ASYNC_MODE_B_NOR, 114 FMC2_ASYNC_MODE_C_NOR, 115 FMC2_ASYNC_MODE_D_NOR, 116 FMC2_SYNC_READ_SYNC_WRITE_PSRAM, 117 FMC2_SYNC_READ_ASYNC_WRITE_PSRAM, 118 FMC2_SYNC_READ_SYNC_WRITE_NOR, 119 FMC2_SYNC_READ_ASYNC_WRITE_NOR 120 }; 121 122 enum stm32_fmc2_ebi_buswidth { 123 FMC2_BUSWIDTH_8 = 8, 124 FMC2_BUSWIDTH_16 = 16 125 }; 126 127 enum stm32_fmc2_ebi_cpsize { 128 FMC2_CPSIZE_0 = 0, 129 FMC2_CPSIZE_128 = 128, 130 FMC2_CPSIZE_256 = 256, 131 FMC2_CPSIZE_512 = 512, 132 FMC2_CPSIZE_1024 = 1024 133 }; 134 135 struct stm32_fmc2_ebi { 136 struct device *dev; 137 struct clk *clk; 138 struct regmap *regmap; 139 u8 bank_assigned; 140 141 u32 bcr[FMC2_MAX_EBI_CE]; 142 u32 btr[FMC2_MAX_EBI_CE]; 143 u32 bwtr[FMC2_MAX_EBI_CE]; 144 u32 pcscntr; 145 }; 146 147 /* 148 * struct stm32_fmc2_prop - STM32 FMC2 EBI property 149 * @name: the device tree binding name of the property 150 * @bprop: indicate that it is a boolean property 151 * @mprop: indicate that it is a mandatory property 152 * @reg_type: the register that have to be modified 153 * @reg_mask: the bit that have to be modified in the selected register 154 * in case of it is a boolean property 155 * @reset_val: the default value that have to be set in case the property 156 * has not been defined in the device tree 157 * @check: this callback ckecks that the property is compliant with the 158 * transaction type selected 159 * @calculate: this callback is called to calculate for exemple a timing 160 * set in nanoseconds in the device tree in clock cycles or in 161 * clock period 162 * @set: this callback applies the values in the registers 163 */ 164 struct stm32_fmc2_prop { 165 const char *name; 166 bool bprop; 167 bool mprop; 168 int reg_type; 169 u32 reg_mask; 170 u32 reset_val; 171 int (*check)(struct stm32_fmc2_ebi *ebi, 172 const struct stm32_fmc2_prop *prop, int cs); 173 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup); 174 int (*set)(struct stm32_fmc2_ebi *ebi, 175 const struct stm32_fmc2_prop *prop, 176 int cs, u32 setup); 177 }; 178 179 static int stm32_fmc2_ebi_check_mux(struct stm32_fmc2_ebi *ebi, 180 const struct stm32_fmc2_prop *prop, 181 int cs) 182 { 183 u32 bcr; 184 int ret; 185 186 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 187 if (ret) 188 return ret; 189 190 if (bcr & FMC2_BCR_MTYP) 191 return 0; 192 193 return -EINVAL; 194 } 195 196 static int stm32_fmc2_ebi_check_waitcfg(struct stm32_fmc2_ebi *ebi, 197 const struct stm32_fmc2_prop *prop, 198 int cs) 199 { 200 u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 201 int ret; 202 203 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 204 if (ret) 205 return ret; 206 207 if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN) 208 return 0; 209 210 return -EINVAL; 211 } 212 213 static int stm32_fmc2_ebi_check_sync_trans(struct stm32_fmc2_ebi *ebi, 214 const struct stm32_fmc2_prop *prop, 215 int cs) 216 { 217 u32 bcr; 218 int ret; 219 220 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 221 if (ret) 222 return ret; 223 224 if (bcr & FMC2_BCR_BURSTEN) 225 return 0; 226 227 return -EINVAL; 228 } 229 230 static int stm32_fmc2_ebi_check_async_trans(struct stm32_fmc2_ebi *ebi, 231 const struct stm32_fmc2_prop *prop, 232 int cs) 233 { 234 u32 bcr; 235 int ret; 236 237 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 238 if (ret) 239 return ret; 240 241 if (!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) 242 return 0; 243 244 return -EINVAL; 245 } 246 247 static int stm32_fmc2_ebi_check_cpsize(struct stm32_fmc2_ebi *ebi, 248 const struct stm32_fmc2_prop *prop, 249 int cs) 250 { 251 u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); 252 int ret; 253 254 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 255 if (ret) 256 return ret; 257 258 if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN) 259 return 0; 260 261 return -EINVAL; 262 } 263 264 static int stm32_fmc2_ebi_check_address_hold(struct stm32_fmc2_ebi *ebi, 265 const struct stm32_fmc2_prop *prop, 266 int cs) 267 { 268 u32 bcr, bxtr, val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D); 269 int ret; 270 271 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 272 if (ret) 273 return ret; 274 275 if (prop->reg_type == FMC2_REG_BWTR) 276 ret = regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr); 277 else 278 ret = regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr); 279 if (ret) 280 return ret; 281 282 if ((!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) && 283 ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN)) 284 return 0; 285 286 return -EINVAL; 287 } 288 289 static int stm32_fmc2_ebi_check_clk_period(struct stm32_fmc2_ebi *ebi, 290 const struct stm32_fmc2_prop *prop, 291 int cs) 292 { 293 u32 bcr, bcr1; 294 int ret; 295 296 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 297 if (ret) 298 return ret; 299 300 if (cs) { 301 ret = regmap_read(ebi->regmap, FMC2_BCR1, &bcr1); 302 if (ret) 303 return ret; 304 } else { 305 bcr1 = bcr; 306 } 307 308 if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN))) 309 return 0; 310 311 return -EINVAL; 312 } 313 314 static int stm32_fmc2_ebi_check_cclk(struct stm32_fmc2_ebi *ebi, 315 const struct stm32_fmc2_prop *prop, 316 int cs) 317 { 318 if (cs) 319 return -EINVAL; 320 321 return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs); 322 } 323 324 static u32 stm32_fmc2_ebi_ns_to_clock_cycles(struct stm32_fmc2_ebi *ebi, 325 int cs, u32 setup) 326 { 327 unsigned long hclk = clk_get_rate(ebi->clk); 328 unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000); 329 330 return DIV_ROUND_UP(setup * 1000, hclkp); 331 } 332 333 static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm32_fmc2_ebi *ebi, 334 int cs, u32 setup) 335 { 336 u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup); 337 u32 bcr, btr, clk_period; 338 int ret; 339 340 ret = regmap_read(ebi->regmap, FMC2_BCR1, &bcr); 341 if (ret) 342 return ret; 343 344 if (bcr & FMC2_BCR1_CCLKEN || !cs) 345 ret = regmap_read(ebi->regmap, FMC2_BTR1, &btr); 346 else 347 ret = regmap_read(ebi->regmap, FMC2_BTR(cs), &btr); 348 if (ret) 349 return ret; 350 351 clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1; 352 353 return DIV_ROUND_UP(nb_clk_cycles, clk_period); 354 } 355 356 static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg) 357 { 358 switch (reg_type) { 359 case FMC2_REG_BCR: 360 *reg = FMC2_BCR(cs); 361 break; 362 case FMC2_REG_BTR: 363 *reg = FMC2_BTR(cs); 364 break; 365 case FMC2_REG_BWTR: 366 *reg = FMC2_BWTR(cs); 367 break; 368 case FMC2_REG_PCSCNTR: 369 *reg = FMC2_PCSCNTR; 370 break; 371 default: 372 return -EINVAL; 373 } 374 375 return 0; 376 } 377 378 static int stm32_fmc2_ebi_set_bit_field(struct stm32_fmc2_ebi *ebi, 379 const struct stm32_fmc2_prop *prop, 380 int cs, u32 setup) 381 { 382 u32 reg; 383 int ret; 384 385 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 386 if (ret) 387 return ret; 388 389 regmap_update_bits(ebi->regmap, reg, prop->reg_mask, 390 setup ? prop->reg_mask : 0); 391 392 return 0; 393 } 394 395 static int stm32_fmc2_ebi_set_trans_type(struct stm32_fmc2_ebi *ebi, 396 const struct stm32_fmc2_prop *prop, 397 int cs, u32 setup) 398 { 399 u32 bcr_mask, bcr = FMC2_BCR_WREN; 400 u32 btr_mask, btr = 0; 401 u32 bwtr_mask, bwtr = 0; 402 403 bwtr_mask = FMC2_BXTR_ACCMOD; 404 btr_mask = FMC2_BXTR_ACCMOD; 405 bcr_mask = FMC2_BCR_MUXEN | FMC2_BCR_MTYP | FMC2_BCR_FACCEN | 406 FMC2_BCR_WREN | FMC2_BCR_WAITEN | FMC2_BCR_BURSTEN | 407 FMC2_BCR_EXTMOD | FMC2_BCR_CBURSTRW; 408 409 switch (setup) { 410 case FMC2_ASYNC_MODE_1_SRAM: 411 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM); 412 /* 413 * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0, 414 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 415 */ 416 break; 417 case FMC2_ASYNC_MODE_1_PSRAM: 418 /* 419 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0, 420 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 421 */ 422 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); 423 break; 424 case FMC2_ASYNC_MODE_A_SRAM: 425 /* 426 * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0, 427 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0 428 */ 429 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM); 430 bcr |= FMC2_BCR_EXTMOD; 431 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A); 432 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A); 433 break; 434 case FMC2_ASYNC_MODE_A_PSRAM: 435 /* 436 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0, 437 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0 438 */ 439 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); 440 bcr |= FMC2_BCR_EXTMOD; 441 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A); 442 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A); 443 break; 444 case FMC2_ASYNC_MODE_2_NOR: 445 /* 446 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0, 447 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 448 */ 449 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 450 bcr |= FMC2_BCR_FACCEN; 451 break; 452 case FMC2_ASYNC_MODE_B_NOR: 453 /* 454 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0, 455 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 1 456 */ 457 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 458 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD; 459 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B); 460 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B); 461 break; 462 case FMC2_ASYNC_MODE_C_NOR: 463 /* 464 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0, 465 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 2 466 */ 467 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 468 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD; 469 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C); 470 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C); 471 break; 472 case FMC2_ASYNC_MODE_D_NOR: 473 /* 474 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0, 475 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 3 476 */ 477 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 478 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD; 479 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D); 480 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D); 481 break; 482 case FMC2_SYNC_READ_SYNC_WRITE_PSRAM: 483 /* 484 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0, 485 * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0 486 */ 487 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); 488 bcr |= FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW; 489 break; 490 case FMC2_SYNC_READ_ASYNC_WRITE_PSRAM: 491 /* 492 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0, 493 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 494 */ 495 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); 496 bcr |= FMC2_BCR_BURSTEN; 497 break; 498 case FMC2_SYNC_READ_SYNC_WRITE_NOR: 499 /* 500 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0, 501 * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0 502 */ 503 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 504 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW; 505 break; 506 case FMC2_SYNC_READ_ASYNC_WRITE_NOR: 507 /* 508 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0, 509 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 510 */ 511 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 512 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN; 513 break; 514 default: 515 /* Type of transaction not supported */ 516 return -EINVAL; 517 } 518 519 if (bcr & FMC2_BCR_EXTMOD) 520 regmap_update_bits(ebi->regmap, FMC2_BWTR(cs), 521 bwtr_mask, bwtr); 522 regmap_update_bits(ebi->regmap, FMC2_BTR(cs), btr_mask, btr); 523 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), bcr_mask, bcr); 524 525 return 0; 526 } 527 528 static int stm32_fmc2_ebi_set_buswidth(struct stm32_fmc2_ebi *ebi, 529 const struct stm32_fmc2_prop *prop, 530 int cs, u32 setup) 531 { 532 u32 val; 533 534 switch (setup) { 535 case FMC2_BUSWIDTH_8: 536 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_8); 537 break; 538 case FMC2_BUSWIDTH_16: 539 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_16); 540 break; 541 default: 542 /* Buswidth not supported */ 543 return -EINVAL; 544 } 545 546 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MWID, val); 547 548 return 0; 549 } 550 551 static int stm32_fmc2_ebi_set_cpsize(struct stm32_fmc2_ebi *ebi, 552 const struct stm32_fmc2_prop *prop, 553 int cs, u32 setup) 554 { 555 u32 val; 556 557 switch (setup) { 558 case FMC2_CPSIZE_0: 559 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_0); 560 break; 561 case FMC2_CPSIZE_128: 562 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_128); 563 break; 564 case FMC2_CPSIZE_256: 565 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_256); 566 break; 567 case FMC2_CPSIZE_512: 568 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_512); 569 break; 570 case FMC2_CPSIZE_1024: 571 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_1024); 572 break; 573 default: 574 /* Cpsize not supported */ 575 return -EINVAL; 576 } 577 578 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_CPSIZE, val); 579 580 return 0; 581 } 582 583 static int stm32_fmc2_ebi_set_bl_setup(struct stm32_fmc2_ebi *ebi, 584 const struct stm32_fmc2_prop *prop, 585 int cs, u32 setup) 586 { 587 u32 val; 588 589 val = min_t(u32, setup, FMC2_BCR_NBLSET_MAX); 590 val = FIELD_PREP(FMC2_BCR_NBLSET, val); 591 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_NBLSET, val); 592 593 return 0; 594 } 595 596 static int stm32_fmc2_ebi_set_address_setup(struct stm32_fmc2_ebi *ebi, 597 const struct stm32_fmc2_prop *prop, 598 int cs, u32 setup) 599 { 600 u32 bcr, bxtr, reg; 601 u32 val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D); 602 int ret; 603 604 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 605 if (ret) 606 return ret; 607 608 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 609 if (ret) 610 return ret; 611 612 if (prop->reg_type == FMC2_REG_BWTR) 613 ret = regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr); 614 else 615 ret = regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr); 616 if (ret) 617 return ret; 618 619 if ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN) 620 val = clamp_val(setup, 1, FMC2_BXTR_ADDSET_MAX); 621 else 622 val = min_t(u32, setup, FMC2_BXTR_ADDSET_MAX); 623 val = FIELD_PREP(FMC2_BXTR_ADDSET, val); 624 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDSET, val); 625 626 return 0; 627 } 628 629 static int stm32_fmc2_ebi_set_address_hold(struct stm32_fmc2_ebi *ebi, 630 const struct stm32_fmc2_prop *prop, 631 int cs, u32 setup) 632 { 633 u32 val, reg; 634 int ret; 635 636 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 637 if (ret) 638 return ret; 639 640 val = clamp_val(setup, 1, FMC2_BXTR_ADDHLD_MAX); 641 val = FIELD_PREP(FMC2_BXTR_ADDHLD, val); 642 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDHLD, val); 643 644 return 0; 645 } 646 647 static int stm32_fmc2_ebi_set_data_setup(struct stm32_fmc2_ebi *ebi, 648 const struct stm32_fmc2_prop *prop, 649 int cs, u32 setup) 650 { 651 u32 val, reg; 652 int ret; 653 654 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 655 if (ret) 656 return ret; 657 658 val = clamp_val(setup, 1, FMC2_BXTR_DATAST_MAX); 659 val = FIELD_PREP(FMC2_BXTR_DATAST, val); 660 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAST, val); 661 662 return 0; 663 } 664 665 static int stm32_fmc2_ebi_set_bus_turnaround(struct stm32_fmc2_ebi *ebi, 666 const struct stm32_fmc2_prop *prop, 667 int cs, u32 setup) 668 { 669 u32 val, reg; 670 int ret; 671 672 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 673 if (ret) 674 return ret; 675 676 val = setup ? min_t(u32, setup - 1, FMC2_BXTR_BUSTURN_MAX) : 0; 677 val = FIELD_PREP(FMC2_BXTR_BUSTURN, val); 678 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_BUSTURN, val); 679 680 return 0; 681 } 682 683 static int stm32_fmc2_ebi_set_data_hold(struct stm32_fmc2_ebi *ebi, 684 const struct stm32_fmc2_prop *prop, 685 int cs, u32 setup) 686 { 687 u32 val, reg; 688 int ret; 689 690 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 691 if (ret) 692 return ret; 693 694 if (prop->reg_type == FMC2_REG_BWTR) 695 val = setup ? min_t(u32, setup - 1, FMC2_BXTR_DATAHLD_MAX) : 0; 696 else 697 val = min_t(u32, setup, FMC2_BXTR_DATAHLD_MAX); 698 val = FIELD_PREP(FMC2_BXTR_DATAHLD, val); 699 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAHLD, val); 700 701 return 0; 702 } 703 704 static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi, 705 const struct stm32_fmc2_prop *prop, 706 int cs, u32 setup) 707 { 708 u32 val; 709 710 val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1; 711 val = FIELD_PREP(FMC2_BTR_CLKDIV, val); 712 regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_CLKDIV, val); 713 714 return 0; 715 } 716 717 static int stm32_fmc2_ebi_set_data_latency(struct stm32_fmc2_ebi *ebi, 718 const struct stm32_fmc2_prop *prop, 719 int cs, u32 setup) 720 { 721 u32 val; 722 723 val = setup > 1 ? min_t(u32, setup - 2, FMC2_BTR_DATLAT_MAX) : 0; 724 val = FIELD_PREP(FMC2_BTR_DATLAT, val); 725 regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_DATLAT, val); 726 727 return 0; 728 } 729 730 static int stm32_fmc2_ebi_set_max_low_pulse(struct stm32_fmc2_ebi *ebi, 731 const struct stm32_fmc2_prop *prop, 732 int cs, u32 setup) 733 { 734 u32 old_val, new_val, pcscntr; 735 int ret; 736 737 if (setup < 1) 738 return 0; 739 740 ret = regmap_read(ebi->regmap, FMC2_PCSCNTR, &pcscntr); 741 if (ret) 742 return ret; 743 744 /* Enable counter for the bank */ 745 regmap_update_bits(ebi->regmap, FMC2_PCSCNTR, 746 FMC2_PCSCNTR_CNTBEN(cs), 747 FMC2_PCSCNTR_CNTBEN(cs)); 748 749 new_val = min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX); 750 old_val = FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr); 751 if (old_val && new_val > old_val) 752 /* Keep current counter value */ 753 return 0; 754 755 new_val = FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, new_val); 756 regmap_update_bits(ebi->regmap, FMC2_PCSCNTR, 757 FMC2_PCSCNTR_CSCOUNT, new_val); 758 759 return 0; 760 } 761 762 static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = { 763 /* st,fmc2-ebi-cs-trans-type must be the first property */ 764 { 765 .name = "st,fmc2-ebi-cs-transaction-type", 766 .mprop = true, 767 .set = stm32_fmc2_ebi_set_trans_type, 768 }, 769 { 770 .name = "st,fmc2-ebi-cs-cclk-enable", 771 .bprop = true, 772 .reg_type = FMC2_REG_BCR, 773 .reg_mask = FMC2_BCR1_CCLKEN, 774 .check = stm32_fmc2_ebi_check_cclk, 775 .set = stm32_fmc2_ebi_set_bit_field, 776 }, 777 { 778 .name = "st,fmc2-ebi-cs-mux-enable", 779 .bprop = true, 780 .reg_type = FMC2_REG_BCR, 781 .reg_mask = FMC2_BCR_MUXEN, 782 .check = stm32_fmc2_ebi_check_mux, 783 .set = stm32_fmc2_ebi_set_bit_field, 784 }, 785 { 786 .name = "st,fmc2-ebi-cs-buswidth", 787 .reset_val = FMC2_BUSWIDTH_16, 788 .set = stm32_fmc2_ebi_set_buswidth, 789 }, 790 { 791 .name = "st,fmc2-ebi-cs-waitpol-high", 792 .bprop = true, 793 .reg_type = FMC2_REG_BCR, 794 .reg_mask = FMC2_BCR_WAITPOL, 795 .set = stm32_fmc2_ebi_set_bit_field, 796 }, 797 { 798 .name = "st,fmc2-ebi-cs-waitcfg-enable", 799 .bprop = true, 800 .reg_type = FMC2_REG_BCR, 801 .reg_mask = FMC2_BCR_WAITCFG, 802 .check = stm32_fmc2_ebi_check_waitcfg, 803 .set = stm32_fmc2_ebi_set_bit_field, 804 }, 805 { 806 .name = "st,fmc2-ebi-cs-wait-enable", 807 .bprop = true, 808 .reg_type = FMC2_REG_BCR, 809 .reg_mask = FMC2_BCR_WAITEN, 810 .check = stm32_fmc2_ebi_check_sync_trans, 811 .set = stm32_fmc2_ebi_set_bit_field, 812 }, 813 { 814 .name = "st,fmc2-ebi-cs-asyncwait-enable", 815 .bprop = true, 816 .reg_type = FMC2_REG_BCR, 817 .reg_mask = FMC2_BCR_ASYNCWAIT, 818 .check = stm32_fmc2_ebi_check_async_trans, 819 .set = stm32_fmc2_ebi_set_bit_field, 820 }, 821 { 822 .name = "st,fmc2-ebi-cs-cpsize", 823 .check = stm32_fmc2_ebi_check_cpsize, 824 .set = stm32_fmc2_ebi_set_cpsize, 825 }, 826 { 827 .name = "st,fmc2-ebi-cs-byte-lane-setup-ns", 828 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 829 .set = stm32_fmc2_ebi_set_bl_setup, 830 }, 831 { 832 .name = "st,fmc2-ebi-cs-address-setup-ns", 833 .reg_type = FMC2_REG_BTR, 834 .reset_val = FMC2_BXTR_ADDSET_MAX, 835 .check = stm32_fmc2_ebi_check_async_trans, 836 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 837 .set = stm32_fmc2_ebi_set_address_setup, 838 }, 839 { 840 .name = "st,fmc2-ebi-cs-address-hold-ns", 841 .reg_type = FMC2_REG_BTR, 842 .reset_val = FMC2_BXTR_ADDHLD_MAX, 843 .check = stm32_fmc2_ebi_check_address_hold, 844 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 845 .set = stm32_fmc2_ebi_set_address_hold, 846 }, 847 { 848 .name = "st,fmc2-ebi-cs-data-setup-ns", 849 .reg_type = FMC2_REG_BTR, 850 .reset_val = FMC2_BXTR_DATAST_MAX, 851 .check = stm32_fmc2_ebi_check_async_trans, 852 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 853 .set = stm32_fmc2_ebi_set_data_setup, 854 }, 855 { 856 .name = "st,fmc2-ebi-cs-bus-turnaround-ns", 857 .reg_type = FMC2_REG_BTR, 858 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1, 859 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 860 .set = stm32_fmc2_ebi_set_bus_turnaround, 861 }, 862 { 863 .name = "st,fmc2-ebi-cs-data-hold-ns", 864 .reg_type = FMC2_REG_BTR, 865 .check = stm32_fmc2_ebi_check_async_trans, 866 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 867 .set = stm32_fmc2_ebi_set_data_hold, 868 }, 869 { 870 .name = "st,fmc2-ebi-cs-clk-period-ns", 871 .reset_val = FMC2_BTR_CLKDIV_MAX + 1, 872 .check = stm32_fmc2_ebi_check_clk_period, 873 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 874 .set = stm32_fmc2_ebi_set_clk_period, 875 }, 876 { 877 .name = "st,fmc2-ebi-cs-data-latency-ns", 878 .check = stm32_fmc2_ebi_check_sync_trans, 879 .calculate = stm32_fmc2_ebi_ns_to_clk_period, 880 .set = stm32_fmc2_ebi_set_data_latency, 881 }, 882 { 883 .name = "st,fmc2-ebi-cs-write-address-setup-ns", 884 .reg_type = FMC2_REG_BWTR, 885 .reset_val = FMC2_BXTR_ADDSET_MAX, 886 .check = stm32_fmc2_ebi_check_async_trans, 887 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 888 .set = stm32_fmc2_ebi_set_address_setup, 889 }, 890 { 891 .name = "st,fmc2-ebi-cs-write-address-hold-ns", 892 .reg_type = FMC2_REG_BWTR, 893 .reset_val = FMC2_BXTR_ADDHLD_MAX, 894 .check = stm32_fmc2_ebi_check_address_hold, 895 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 896 .set = stm32_fmc2_ebi_set_address_hold, 897 }, 898 { 899 .name = "st,fmc2-ebi-cs-write-data-setup-ns", 900 .reg_type = FMC2_REG_BWTR, 901 .reset_val = FMC2_BXTR_DATAST_MAX, 902 .check = stm32_fmc2_ebi_check_async_trans, 903 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 904 .set = stm32_fmc2_ebi_set_data_setup, 905 }, 906 { 907 .name = "st,fmc2-ebi-cs-write-bus-turnaround-ns", 908 .reg_type = FMC2_REG_BWTR, 909 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1, 910 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 911 .set = stm32_fmc2_ebi_set_bus_turnaround, 912 }, 913 { 914 .name = "st,fmc2-ebi-cs-write-data-hold-ns", 915 .reg_type = FMC2_REG_BWTR, 916 .check = stm32_fmc2_ebi_check_async_trans, 917 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 918 .set = stm32_fmc2_ebi_set_data_hold, 919 }, 920 { 921 .name = "st,fmc2-ebi-cs-max-low-pulse-ns", 922 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 923 .set = stm32_fmc2_ebi_set_max_low_pulse, 924 }, 925 }; 926 927 static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi, 928 struct device_node *dev_node, 929 const struct stm32_fmc2_prop *prop, 930 int cs) 931 { 932 struct device *dev = ebi->dev; 933 u32 setup = 0; 934 935 if (!prop->set) { 936 dev_err(dev, "property %s is not well defined\n", prop->name); 937 return -EINVAL; 938 } 939 940 if (prop->check && prop->check(ebi, prop, cs)) 941 /* Skeep this property */ 942 return 0; 943 944 if (prop->bprop) { 945 bool bprop; 946 947 bprop = of_property_read_bool(dev_node, prop->name); 948 if (prop->mprop && !bprop) { 949 dev_err(dev, "mandatory property %s not defined in the device tree\n", 950 prop->name); 951 return -EINVAL; 952 } 953 954 if (bprop) 955 setup = 1; 956 } else { 957 u32 val; 958 int ret; 959 960 ret = of_property_read_u32(dev_node, prop->name, &val); 961 if (prop->mprop && ret) { 962 dev_err(dev, "mandatory property %s not defined in the device tree\n", 963 prop->name); 964 return ret; 965 } 966 967 if (ret) 968 setup = prop->reset_val; 969 else if (prop->calculate) 970 setup = prop->calculate(ebi, cs, val); 971 else 972 setup = val; 973 } 974 975 return prop->set(ebi, prop, cs, setup); 976 } 977 978 static void stm32_fmc2_ebi_enable_bank(struct stm32_fmc2_ebi *ebi, int cs) 979 { 980 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), 981 FMC2_BCR_MBKEN, FMC2_BCR_MBKEN); 982 } 983 984 static void stm32_fmc2_ebi_disable_bank(struct stm32_fmc2_ebi *ebi, int cs) 985 { 986 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MBKEN, 0); 987 } 988 989 static int stm32_fmc2_ebi_save_setup(struct stm32_fmc2_ebi *ebi) 990 { 991 unsigned int cs; 992 int ret; 993 994 for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) { 995 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &ebi->bcr[cs]); 996 ret |= regmap_read(ebi->regmap, FMC2_BTR(cs), &ebi->btr[cs]); 997 ret |= regmap_read(ebi->regmap, FMC2_BWTR(cs), &ebi->bwtr[cs]); 998 if (ret) 999 return ret; 1000 } 1001 1002 return regmap_read(ebi->regmap, FMC2_PCSCNTR, &ebi->pcscntr); 1003 } 1004 1005 static void stm32_fmc2_ebi_set_setup(struct stm32_fmc2_ebi *ebi) 1006 { 1007 unsigned int cs; 1008 1009 for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) { 1010 regmap_write(ebi->regmap, FMC2_BCR(cs), ebi->bcr[cs]); 1011 regmap_write(ebi->regmap, FMC2_BTR(cs), ebi->btr[cs]); 1012 regmap_write(ebi->regmap, FMC2_BWTR(cs), ebi->bwtr[cs]); 1013 } 1014 1015 regmap_write(ebi->regmap, FMC2_PCSCNTR, ebi->pcscntr); 1016 } 1017 1018 static void stm32_fmc2_ebi_disable_banks(struct stm32_fmc2_ebi *ebi) 1019 { 1020 unsigned int cs; 1021 1022 for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) { 1023 if (!(ebi->bank_assigned & BIT(cs))) 1024 continue; 1025 1026 stm32_fmc2_ebi_disable_bank(ebi, cs); 1027 } 1028 } 1029 1030 /* NWAIT signal can not be connected to EBI controller and NAND controller */ 1031 static int stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi) 1032 { 1033 struct device *dev = ebi->dev; 1034 unsigned int cs; 1035 u32 bcr; 1036 int ret; 1037 1038 for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) { 1039 if (!(ebi->bank_assigned & BIT(cs))) 1040 continue; 1041 1042 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 1043 if (ret) 1044 return ret; 1045 1046 if ((bcr & FMC2_BCR_WAITEN || bcr & FMC2_BCR_ASYNCWAIT) && 1047 ebi->bank_assigned & BIT(FMC2_NAND)) { 1048 dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n"); 1049 return -EINVAL; 1050 } 1051 } 1052 1053 return 0; 1054 } 1055 1056 static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi) 1057 { 1058 regmap_update_bits(ebi->regmap, FMC2_BCR1, 1059 FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN); 1060 } 1061 1062 static void stm32_fmc2_ebi_disable(struct stm32_fmc2_ebi *ebi) 1063 { 1064 regmap_update_bits(ebi->regmap, FMC2_BCR1, FMC2_BCR1_FMC2EN, 0); 1065 } 1066 1067 static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi, 1068 struct device_node *dev_node, 1069 u32 cs) 1070 { 1071 unsigned int i; 1072 int ret; 1073 1074 stm32_fmc2_ebi_disable_bank(ebi, cs); 1075 1076 for (i = 0; i < ARRAY_SIZE(stm32_fmc2_child_props); i++) { 1077 const struct stm32_fmc2_prop *p = &stm32_fmc2_child_props[i]; 1078 1079 ret = stm32_fmc2_ebi_parse_prop(ebi, dev_node, p, cs); 1080 if (ret) { 1081 dev_err(ebi->dev, "property %s could not be set: %d\n", 1082 p->name, ret); 1083 return ret; 1084 } 1085 } 1086 1087 stm32_fmc2_ebi_enable_bank(ebi, cs); 1088 1089 return 0; 1090 } 1091 1092 static int stm32_fmc2_ebi_parse_dt(struct stm32_fmc2_ebi *ebi) 1093 { 1094 struct device *dev = ebi->dev; 1095 struct device_node *child; 1096 bool child_found = false; 1097 u32 bank; 1098 int ret; 1099 1100 for_each_available_child_of_node(dev->of_node, child) { 1101 ret = of_property_read_u32(child, "reg", &bank); 1102 if (ret) { 1103 dev_err(dev, "could not retrieve reg property: %d\n", 1104 ret); 1105 of_node_put(child); 1106 return ret; 1107 } 1108 1109 if (bank >= FMC2_MAX_BANKS) { 1110 dev_err(dev, "invalid reg value: %d\n", bank); 1111 of_node_put(child); 1112 return -EINVAL; 1113 } 1114 1115 if (ebi->bank_assigned & BIT(bank)) { 1116 dev_err(dev, "bank already assigned: %d\n", bank); 1117 of_node_put(child); 1118 return -EINVAL; 1119 } 1120 1121 if (bank < FMC2_MAX_EBI_CE) { 1122 ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank); 1123 if (ret) { 1124 dev_err(dev, "setup chip select %d failed: %d\n", 1125 bank, ret); 1126 of_node_put(child); 1127 return ret; 1128 } 1129 } 1130 1131 ebi->bank_assigned |= BIT(bank); 1132 child_found = true; 1133 } 1134 1135 if (!child_found) { 1136 dev_warn(dev, "no subnodes found, disable the driver.\n"); 1137 return -ENODEV; 1138 } 1139 1140 ret = stm32_fmc2_ebi_nwait_used_by_ctrls(ebi); 1141 if (ret) 1142 return ret; 1143 1144 stm32_fmc2_ebi_enable(ebi); 1145 1146 return of_platform_populate(dev->of_node, NULL, NULL, dev); 1147 } 1148 1149 static int stm32_fmc2_ebi_probe(struct platform_device *pdev) 1150 { 1151 struct device *dev = &pdev->dev; 1152 struct stm32_fmc2_ebi *ebi; 1153 struct reset_control *rstc; 1154 int ret; 1155 1156 ebi = devm_kzalloc(&pdev->dev, sizeof(*ebi), GFP_KERNEL); 1157 if (!ebi) 1158 return -ENOMEM; 1159 1160 ebi->dev = dev; 1161 1162 ebi->regmap = device_node_to_regmap(dev->of_node); 1163 if (IS_ERR(ebi->regmap)) 1164 return PTR_ERR(ebi->regmap); 1165 1166 ebi->clk = devm_clk_get(dev, NULL); 1167 if (IS_ERR(ebi->clk)) 1168 return PTR_ERR(ebi->clk); 1169 1170 rstc = devm_reset_control_get(dev, NULL); 1171 if (PTR_ERR(rstc) == -EPROBE_DEFER) 1172 return -EPROBE_DEFER; 1173 1174 ret = clk_prepare_enable(ebi->clk); 1175 if (ret) 1176 return ret; 1177 1178 if (!IS_ERR(rstc)) { 1179 reset_control_assert(rstc); 1180 reset_control_deassert(rstc); 1181 } 1182 1183 ret = stm32_fmc2_ebi_parse_dt(ebi); 1184 if (ret) 1185 goto err_release; 1186 1187 ret = stm32_fmc2_ebi_save_setup(ebi); 1188 if (ret) 1189 goto err_release; 1190 1191 platform_set_drvdata(pdev, ebi); 1192 1193 return 0; 1194 1195 err_release: 1196 stm32_fmc2_ebi_disable_banks(ebi); 1197 stm32_fmc2_ebi_disable(ebi); 1198 clk_disable_unprepare(ebi->clk); 1199 1200 return ret; 1201 } 1202 1203 static int stm32_fmc2_ebi_remove(struct platform_device *pdev) 1204 { 1205 struct stm32_fmc2_ebi *ebi = platform_get_drvdata(pdev); 1206 1207 of_platform_depopulate(&pdev->dev); 1208 stm32_fmc2_ebi_disable_banks(ebi); 1209 stm32_fmc2_ebi_disable(ebi); 1210 clk_disable_unprepare(ebi->clk); 1211 1212 return 0; 1213 } 1214 1215 static int __maybe_unused stm32_fmc2_ebi_suspend(struct device *dev) 1216 { 1217 struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev); 1218 1219 stm32_fmc2_ebi_disable(ebi); 1220 clk_disable_unprepare(ebi->clk); 1221 pinctrl_pm_select_sleep_state(dev); 1222 1223 return 0; 1224 } 1225 1226 static int __maybe_unused stm32_fmc2_ebi_resume(struct device *dev) 1227 { 1228 struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev); 1229 int ret; 1230 1231 pinctrl_pm_select_default_state(dev); 1232 1233 ret = clk_prepare_enable(ebi->clk); 1234 if (ret) 1235 return ret; 1236 1237 stm32_fmc2_ebi_set_setup(ebi); 1238 stm32_fmc2_ebi_enable(ebi); 1239 1240 return 0; 1241 } 1242 1243 static SIMPLE_DEV_PM_OPS(stm32_fmc2_ebi_pm_ops, stm32_fmc2_ebi_suspend, 1244 stm32_fmc2_ebi_resume); 1245 1246 static const struct of_device_id stm32_fmc2_ebi_match[] = { 1247 {.compatible = "st,stm32mp1-fmc2-ebi"}, 1248 {} 1249 }; 1250 MODULE_DEVICE_TABLE(of, stm32_fmc2_ebi_match); 1251 1252 static struct platform_driver stm32_fmc2_ebi_driver = { 1253 .probe = stm32_fmc2_ebi_probe, 1254 .remove = stm32_fmc2_ebi_remove, 1255 .driver = { 1256 .name = "stm32_fmc2_ebi", 1257 .of_match_table = stm32_fmc2_ebi_match, 1258 .pm = &stm32_fmc2_ebi_pm_ops, 1259 }, 1260 }; 1261 module_platform_driver(stm32_fmc2_ebi_driver); 1262 1263 MODULE_ALIAS("platform:stm32_fmc2_ebi"); 1264 MODULE_AUTHOR("Christophe Kerello <christophe.kerello@st.com>"); 1265 MODULE_DESCRIPTION("STMicroelectronics STM32 FMC2 ebi driver"); 1266 MODULE_LICENSE("GPL v2"); 1267