1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RPC-IF core driver 4 * 5 * Copyright (C) 2018-2019 Renesas Solutions Corp. 6 * Copyright (C) 2019 Macronix International Co., Ltd. 7 * Copyright (C) 2019-2020 Cogent Embedded, Inc. 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/of.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 19 #include <memory/renesas-rpc-if.h> 20 21 #define RPCIF_CMNCR 0x0000 /* R/W */ 22 #define RPCIF_CMNCR_MD BIT(31) 23 #define RPCIF_CMNCR_SFDE BIT(24) /* undocumented but must be set */ 24 #define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22) 25 #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20) 26 #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18) 27 #define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16) 28 #define RPCIF_CMNCR_MOIIO_HIZ (RPCIF_CMNCR_MOIIO0(3) | \ 29 RPCIF_CMNCR_MOIIO1(3) | \ 30 RPCIF_CMNCR_MOIIO2(3) | RPCIF_CMNCR_MOIIO3(3)) 31 #define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* undocumented */ 32 #define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* undocumented */ 33 #define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8) 34 #define RPCIF_CMNCR_IOFV_HIZ (RPCIF_CMNCR_IO0FV(3) | RPCIF_CMNCR_IO2FV(3) | \ 35 RPCIF_CMNCR_IO3FV(3)) 36 #define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0) 37 38 #define RPCIF_SSLDR 0x0004 /* R/W */ 39 #define RPCIF_SSLDR_SPNDL(d) (((d) & 0x7) << 16) 40 #define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8) 41 #define RPCIF_SSLDR_SCKDL(d) (((d) & 0x7) << 0) 42 43 #define RPCIF_DRCR 0x000C /* R/W */ 44 #define RPCIF_DRCR_SSLN BIT(24) 45 #define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16) 46 #define RPCIF_DRCR_RCF BIT(9) 47 #define RPCIF_DRCR_RBE BIT(8) 48 #define RPCIF_DRCR_SSLE BIT(0) 49 50 #define RPCIF_DRCMR 0x0010 /* R/W */ 51 #define RPCIF_DRCMR_CMD(c) (((c) & 0xFF) << 16) 52 #define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0) 53 54 #define RPCIF_DREAR 0x0014 /* R/W */ 55 #define RPCIF_DREAR_EAV(c) (((c) & 0xF) << 16) 56 #define RPCIF_DREAR_EAC(c) (((c) & 0x7) << 0) 57 58 #define RPCIF_DROPR 0x0018 /* R/W */ 59 60 #define RPCIF_DRENR 0x001C /* R/W */ 61 #define RPCIF_DRENR_CDB(o) (u32)((((o) & 0x3) << 30)) 62 #define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28) 63 #define RPCIF_DRENR_ADB(o) (((o) & 0x3) << 24) 64 #define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20) 65 #define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16) 66 #define RPCIF_DRENR_DME BIT(15) 67 #define RPCIF_DRENR_CDE BIT(14) 68 #define RPCIF_DRENR_OCDE BIT(12) 69 #define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8) 70 #define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4) 71 72 #define RPCIF_SMCR 0x0020 /* R/W */ 73 #define RPCIF_SMCR_SSLKP BIT(8) 74 #define RPCIF_SMCR_SPIRE BIT(2) 75 #define RPCIF_SMCR_SPIWE BIT(1) 76 #define RPCIF_SMCR_SPIE BIT(0) 77 78 #define RPCIF_SMCMR 0x0024 /* R/W */ 79 #define RPCIF_SMCMR_CMD(c) (((c) & 0xFF) << 16) 80 #define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0) 81 82 #define RPCIF_SMADR 0x0028 /* R/W */ 83 84 #define RPCIF_SMOPR 0x002C /* R/W */ 85 #define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24) 86 #define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16) 87 #define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8) 88 #define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0) 89 90 #define RPCIF_SMENR 0x0030 /* R/W */ 91 #define RPCIF_SMENR_CDB(o) (((o) & 0x3) << 30) 92 #define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28) 93 #define RPCIF_SMENR_ADB(o) (((o) & 0x3) << 24) 94 #define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20) 95 #define RPCIF_SMENR_SPIDB(o) (((o) & 0x3) << 16) 96 #define RPCIF_SMENR_DME BIT(15) 97 #define RPCIF_SMENR_CDE BIT(14) 98 #define RPCIF_SMENR_OCDE BIT(12) 99 #define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8) 100 #define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4) 101 #define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0) 102 103 #define RPCIF_SMRDR0 0x0038 /* R */ 104 #define RPCIF_SMRDR1 0x003C /* R */ 105 #define RPCIF_SMWDR0 0x0040 /* W */ 106 #define RPCIF_SMWDR1 0x0044 /* W */ 107 108 #define RPCIF_CMNSR 0x0048 /* R */ 109 #define RPCIF_CMNSR_SSLF BIT(1) 110 #define RPCIF_CMNSR_TEND BIT(0) 111 112 #define RPCIF_DRDMCR 0x0058 /* R/W */ 113 #define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0) 114 115 #define RPCIF_DRDRENR 0x005C /* R/W */ 116 #define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12) 117 #define RPCIF_DRDRENR_ADDRE BIT(8) 118 #define RPCIF_DRDRENR_OPDRE BIT(4) 119 #define RPCIF_DRDRENR_DRDRE BIT(0) 120 121 #define RPCIF_SMDMCR 0x0060 /* R/W */ 122 #define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0) 123 124 #define RPCIF_SMDRENR 0x0064 /* R/W */ 125 #define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12) 126 #define RPCIF_SMDRENR_ADDRE BIT(8) 127 #define RPCIF_SMDRENR_OPDRE BIT(4) 128 #define RPCIF_SMDRENR_SPIDRE BIT(0) 129 130 #define RPCIF_PHYCNT 0x007C /* R/W */ 131 #define RPCIF_PHYCNT_CAL BIT(31) 132 #define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22) 133 #define RPCIF_PHYCNT_EXDS BIT(21) 134 #define RPCIF_PHYCNT_OCT BIT(20) 135 #define RPCIF_PHYCNT_DDRCAL BIT(19) 136 #define RPCIF_PHYCNT_HS BIT(18) 137 #define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15) 138 #define RPCIF_PHYCNT_WBUF2 BIT(4) 139 #define RPCIF_PHYCNT_WBUF BIT(2) 140 #define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0) 141 142 #define RPCIF_PHYOFFSET1 0x0080 /* R/W */ 143 #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28) 144 145 #define RPCIF_PHYOFFSET2 0x0084 /* R/W */ 146 #define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8) 147 148 #define RPCIF_PHYINT 0x0088 /* R/W */ 149 #define RPCIF_PHYINT_WPVAL BIT(1) 150 151 #define RPCIF_DIRMAP_SIZE 0x4000000 152 153 static const struct regmap_range rpcif_volatile_ranges[] = { 154 regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1), 155 regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1), 156 regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR), 157 }; 158 159 static const struct regmap_access_table rpcif_volatile_table = { 160 .yes_ranges = rpcif_volatile_ranges, 161 .n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges), 162 }; 163 164 static const struct regmap_config rpcif_regmap_config = { 165 .reg_bits = 32, 166 .val_bits = 32, 167 .reg_stride = 4, 168 .fast_io = true, 169 .max_register = RPCIF_PHYINT, 170 .volatile_table = &rpcif_volatile_table, 171 }; 172 173 int rpcif_sw_init(struct rpcif *rpc, struct device *dev) 174 { 175 struct platform_device *pdev = to_platform_device(dev); 176 struct resource *res; 177 void __iomem *base; 178 179 rpc->dev = dev; 180 181 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); 182 base = devm_ioremap_resource(&pdev->dev, res); 183 if (IS_ERR(base)) 184 return PTR_ERR(base); 185 186 rpc->regmap = devm_regmap_init_mmio(&pdev->dev, base, 187 &rpcif_regmap_config); 188 if (IS_ERR(rpc->regmap)) { 189 dev_err(&pdev->dev, 190 "failed to init regmap for rpcif, error %ld\n", 191 PTR_ERR(rpc->regmap)); 192 return PTR_ERR(rpc->regmap); 193 } 194 195 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap"); 196 rpc->size = resource_size(res); 197 rpc->dirmap = devm_ioremap_resource(&pdev->dev, res); 198 if (IS_ERR(rpc->dirmap)) 199 rpc->dirmap = NULL; 200 201 rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 202 if (IS_ERR(rpc->rstc)) 203 return PTR_ERR(rpc->rstc); 204 205 return 0; 206 } 207 EXPORT_SYMBOL(rpcif_sw_init); 208 209 void rpcif_enable_rpm(struct rpcif *rpc) 210 { 211 pm_runtime_enable(rpc->dev); 212 } 213 EXPORT_SYMBOL(rpcif_enable_rpm); 214 215 void rpcif_disable_rpm(struct rpcif *rpc) 216 { 217 pm_runtime_put_sync(rpc->dev); 218 } 219 EXPORT_SYMBOL(rpcif_disable_rpm); 220 221 void rpcif_hw_init(struct rpcif *rpc, bool hyperflash) 222 { 223 u32 dummy; 224 225 pm_runtime_get_sync(rpc->dev); 226 227 /* 228 * NOTE: The 0x260 are undocumented bits, but they must be set. 229 * RPCIF_PHYCNT_STRTIM is strobe timing adjustment bits, 230 * 0x0 : the delay is biggest, 231 * 0x1 : the delay is 2nd biggest, 232 * On H3 ES1.x, the value should be 0, while on others, 233 * the value should be 7. 234 */ 235 regmap_write(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_STRTIM(7) | 236 RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0) | 0x260); 237 238 /* 239 * NOTE: The 0x1511144 are undocumented bits, but they must be set 240 * for RPCIF_PHYOFFSET1. 241 * The 0x31 are undocumented bits, but they must be set 242 * for RPCIF_PHYOFFSET2. 243 */ 244 regmap_write(rpc->regmap, RPCIF_PHYOFFSET1, 0x1511144 | 245 RPCIF_PHYOFFSET1_DDRTMG(3)); 246 regmap_write(rpc->regmap, RPCIF_PHYOFFSET2, 0x31 | 247 RPCIF_PHYOFFSET2_OCTTMG(4)); 248 249 if (hyperflash) 250 regmap_update_bits(rpc->regmap, RPCIF_PHYINT, 251 RPCIF_PHYINT_WPVAL, 0); 252 253 regmap_write(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_SFDE | 254 RPCIF_CMNCR_MOIIO_HIZ | RPCIF_CMNCR_IOFV_HIZ | 255 RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); 256 /* Set RCF after BSZ update */ 257 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF); 258 /* Dummy read according to spec */ 259 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy); 260 regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) | 261 RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7)); 262 263 pm_runtime_put(rpc->dev); 264 265 rpc->bus_size = hyperflash ? 2 : 1; 266 } 267 EXPORT_SYMBOL(rpcif_hw_init); 268 269 static int wait_msg_xfer_end(struct rpcif *rpc) 270 { 271 u32 sts; 272 273 return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts, 274 sts & RPCIF_CMNSR_TEND, 0, 275 USEC_PER_SEC); 276 } 277 278 static u8 rpcif_bits_set(struct rpcif *rpc, u32 nbytes) 279 { 280 if (rpc->bus_size == 2) 281 nbytes /= 2; 282 nbytes = clamp(nbytes, 1U, 4U); 283 return GENMASK(3, 4 - nbytes); 284 } 285 286 static u8 rpcif_bit_size(u8 buswidth) 287 { 288 return buswidth > 4 ? 2 : ilog2(buswidth); 289 } 290 291 void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs, 292 size_t *len) 293 { 294 rpc->smcr = 0; 295 rpc->smadr = 0; 296 rpc->enable = 0; 297 rpc->command = 0; 298 rpc->option = 0; 299 rpc->dummy = 0; 300 rpc->ddr = 0; 301 rpc->xferlen = 0; 302 303 if (op->cmd.buswidth) { 304 rpc->enable = RPCIF_SMENR_CDE | 305 RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth)); 306 rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode); 307 if (op->cmd.ddr) 308 rpc->ddr = RPCIF_SMDRENR_HYPE(0x5); 309 } 310 if (op->ocmd.buswidth) { 311 rpc->enable |= RPCIF_SMENR_OCDE | 312 RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth)); 313 rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode); 314 } 315 316 if (op->addr.buswidth) { 317 rpc->enable |= 318 RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth)); 319 if (op->addr.nbytes == 4) 320 rpc->enable |= RPCIF_SMENR_ADE(0xF); 321 else 322 rpc->enable |= RPCIF_SMENR_ADE(GENMASK( 323 2, 3 - op->addr.nbytes)); 324 if (op->addr.ddr) 325 rpc->ddr |= RPCIF_SMDRENR_ADDRE; 326 327 if (offs && len) 328 rpc->smadr = *offs; 329 else 330 rpc->smadr = op->addr.val; 331 } 332 333 if (op->dummy.buswidth) { 334 rpc->enable |= RPCIF_SMENR_DME; 335 rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles / 336 op->dummy.buswidth); 337 } 338 339 if (op->option.buswidth) { 340 rpc->enable |= RPCIF_SMENR_OPDE( 341 rpcif_bits_set(rpc, op->option.nbytes)) | 342 RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth)); 343 if (op->option.ddr) 344 rpc->ddr |= RPCIF_SMDRENR_OPDRE; 345 rpc->option = op->option.val; 346 } 347 348 rpc->dir = op->data.dir; 349 if (op->data.buswidth) { 350 u32 nbytes; 351 352 rpc->buffer = op->data.buf.in; 353 switch (op->data.dir) { 354 case RPCIF_DATA_IN: 355 rpc->smcr = RPCIF_SMCR_SPIRE; 356 break; 357 case RPCIF_DATA_OUT: 358 rpc->smcr = RPCIF_SMCR_SPIWE; 359 break; 360 default: 361 break; 362 } 363 if (op->data.ddr) 364 rpc->ddr |= RPCIF_SMDRENR_SPIDRE; 365 366 if (offs && len) 367 nbytes = *len; 368 else 369 nbytes = op->data.nbytes; 370 rpc->xferlen = nbytes; 371 372 rpc->enable |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes)) | 373 RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth)); 374 } 375 } 376 EXPORT_SYMBOL(rpcif_prepare); 377 378 int rpcif_manual_xfer(struct rpcif *rpc) 379 { 380 u32 smenr, smcr, pos = 0, max = 4; 381 int ret = 0; 382 383 if (rpc->bus_size == 2) 384 max = 8; 385 386 pm_runtime_get_sync(rpc->dev); 387 388 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, 389 RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL); 390 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 391 RPCIF_CMNCR_MD, RPCIF_CMNCR_MD); 392 regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command); 393 regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option); 394 regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy); 395 regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr); 396 smenr = rpc->enable; 397 398 switch (rpc->dir) { 399 case RPCIF_DATA_OUT: 400 while (pos < rpc->xferlen) { 401 u32 nbytes = rpc->xferlen - pos; 402 u32 data[2]; 403 404 smcr = rpc->smcr | RPCIF_SMCR_SPIE; 405 if (nbytes > max) { 406 nbytes = max; 407 smcr |= RPCIF_SMCR_SSLKP; 408 } 409 410 memcpy(data, rpc->buffer + pos, nbytes); 411 if (nbytes > 4) { 412 regmap_write(rpc->regmap, RPCIF_SMWDR1, 413 data[0]); 414 regmap_write(rpc->regmap, RPCIF_SMWDR0, 415 data[1]); 416 } else if (nbytes > 2) { 417 regmap_write(rpc->regmap, RPCIF_SMWDR0, 418 data[0]); 419 } else { 420 regmap_write(rpc->regmap, RPCIF_SMWDR0, 421 data[0] << 16); 422 } 423 424 regmap_write(rpc->regmap, RPCIF_SMADR, 425 rpc->smadr + pos); 426 regmap_write(rpc->regmap, RPCIF_SMENR, smenr); 427 regmap_write(rpc->regmap, RPCIF_SMCR, smcr); 428 ret = wait_msg_xfer_end(rpc); 429 if (ret) 430 goto err_out; 431 432 pos += nbytes; 433 smenr = rpc->enable & 434 ~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF); 435 } 436 break; 437 case RPCIF_DATA_IN: 438 /* 439 * RPC-IF spoils the data for the commands without an address 440 * phase (like RDID) in the manual mode, so we'll have to work 441 * around this issue by using the external address space read 442 * mode instead. 443 */ 444 if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) { 445 u32 dummy; 446 447 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 448 RPCIF_CMNCR_MD, 0); 449 regmap_write(rpc->regmap, RPCIF_DRCR, 450 RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE); 451 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command); 452 regmap_write(rpc->regmap, RPCIF_DREAR, 453 RPCIF_DREAR_EAC(1)); 454 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option); 455 regmap_write(rpc->regmap, RPCIF_DRENR, 456 smenr & ~RPCIF_SMENR_SPIDE(0xF)); 457 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy); 458 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr); 459 memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen); 460 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF); 461 /* Dummy read according to spec */ 462 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy); 463 break; 464 } 465 while (pos < rpc->xferlen) { 466 u32 nbytes = rpc->xferlen - pos; 467 u32 data[2]; 468 469 if (nbytes > max) 470 nbytes = max; 471 472 regmap_write(rpc->regmap, RPCIF_SMADR, 473 rpc->smadr + pos); 474 regmap_write(rpc->regmap, RPCIF_SMENR, smenr); 475 regmap_write(rpc->regmap, RPCIF_SMCR, 476 rpc->smcr | RPCIF_SMCR_SPIE); 477 ret = wait_msg_xfer_end(rpc); 478 if (ret) 479 goto err_out; 480 481 if (nbytes > 4) { 482 regmap_read(rpc->regmap, RPCIF_SMRDR1, 483 &data[0]); 484 regmap_read(rpc->regmap, RPCIF_SMRDR0, 485 &data[1]); 486 } else if (nbytes > 2) { 487 regmap_read(rpc->regmap, RPCIF_SMRDR0, 488 &data[0]); 489 } else { 490 regmap_read(rpc->regmap, RPCIF_SMRDR0, 491 &data[0]); 492 data[0] >>= 16; 493 } 494 memcpy(rpc->buffer + pos, data, nbytes); 495 496 pos += nbytes; 497 } 498 break; 499 default: 500 regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable); 501 regmap_write(rpc->regmap, RPCIF_SMCR, 502 rpc->smcr | RPCIF_SMCR_SPIE); 503 ret = wait_msg_xfer_end(rpc); 504 if (ret) 505 goto err_out; 506 } 507 508 exit: 509 pm_runtime_put(rpc->dev); 510 return ret; 511 512 err_out: 513 ret = reset_control_reset(rpc->rstc); 514 rpcif_hw_init(rpc, rpc->bus_size == 2); 515 goto exit; 516 } 517 EXPORT_SYMBOL(rpcif_manual_xfer); 518 519 ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf) 520 { 521 loff_t from = offs & (RPCIF_DIRMAP_SIZE - 1); 522 size_t size = RPCIF_DIRMAP_SIZE - from; 523 524 if (len > size) 525 len = size; 526 527 pm_runtime_get_sync(rpc->dev); 528 529 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0); 530 regmap_write(rpc->regmap, RPCIF_DRCR, 0); 531 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command); 532 regmap_write(rpc->regmap, RPCIF_DREAR, 533 RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1)); 534 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option); 535 regmap_write(rpc->regmap, RPCIF_DRENR, 536 rpc->enable & ~RPCIF_SMENR_SPIDE(0xF)); 537 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy); 538 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr); 539 540 memcpy_fromio(buf, rpc->dirmap + from, len); 541 542 pm_runtime_put(rpc->dev); 543 544 return len; 545 } 546 EXPORT_SYMBOL(rpcif_dirmap_read); 547 548 static int rpcif_probe(struct platform_device *pdev) 549 { 550 struct platform_device *vdev; 551 struct device_node *flash; 552 const char *name; 553 554 flash = of_get_next_child(pdev->dev.of_node, NULL); 555 if (!flash) { 556 dev_warn(&pdev->dev, "no flash node found\n"); 557 return -ENODEV; 558 } 559 560 if (of_device_is_compatible(flash, "jedec,spi-nor")) { 561 name = "rpc-if-spi"; 562 } else if (of_device_is_compatible(flash, "cfi-flash")) { 563 name = "rpc-if-hyperflash"; 564 } else { 565 dev_warn(&pdev->dev, "unknown flash type\n"); 566 return -ENODEV; 567 } 568 569 vdev = platform_device_alloc(name, pdev->id); 570 if (!vdev) 571 return -ENOMEM; 572 vdev->dev.parent = &pdev->dev; 573 platform_set_drvdata(pdev, vdev); 574 return platform_device_add(vdev); 575 } 576 577 static int rpcif_remove(struct platform_device *pdev) 578 { 579 struct platform_device *vdev = platform_get_drvdata(pdev); 580 581 platform_device_unregister(vdev); 582 583 return 0; 584 } 585 586 static const struct of_device_id rpcif_of_match[] = { 587 { .compatible = "renesas,rcar-gen3-rpc-if", }, 588 {}, 589 }; 590 MODULE_DEVICE_TABLE(of, rpcif_of_match); 591 592 static struct platform_driver rpcif_driver = { 593 .probe = rpcif_probe, 594 .remove = rpcif_remove, 595 .driver = { 596 .name = "rpc-if", 597 .of_match_table = rpcif_of_match, 598 }, 599 }; 600 module_platform_driver(rpcif_driver); 601 602 MODULE_DESCRIPTION("Renesas RPC-IF core driver"); 603 MODULE_LICENSE("GPL v2"); 604