1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RPC-IF core driver 4 * 5 * Copyright (C) 2018-2019 Renesas Solutions Corp. 6 * Copyright (C) 2019 Macronix International Co., Ltd. 7 * Copyright (C) 2019-2020 Cogent Embedded, Inc. 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 19 #include <memory/renesas-rpc-if.h> 20 21 #define RPCIF_CMNCR 0x0000 /* R/W */ 22 #define RPCIF_CMNCR_MD BIT(31) 23 #define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22) 24 #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20) 25 #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18) 26 #define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16) 27 #define RPCIF_CMNCR_MOIIO(val) (RPCIF_CMNCR_MOIIO0(val) | RPCIF_CMNCR_MOIIO1(val) | \ 28 RPCIF_CMNCR_MOIIO2(val) | RPCIF_CMNCR_MOIIO3(val)) 29 #define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* documented for RZ/G2L */ 30 #define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* documented for RZ/G2L */ 31 #define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8) 32 #define RPCIF_CMNCR_IOFV(val) (RPCIF_CMNCR_IO0FV(val) | RPCIF_CMNCR_IO2FV(val) | \ 33 RPCIF_CMNCR_IO3FV(val)) 34 #define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0) 35 36 #define RPCIF_SSLDR 0x0004 /* R/W */ 37 #define RPCIF_SSLDR_SPNDL(d) (((d) & 0x7) << 16) 38 #define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8) 39 #define RPCIF_SSLDR_SCKDL(d) (((d) & 0x7) << 0) 40 41 #define RPCIF_DRCR 0x000C /* R/W */ 42 #define RPCIF_DRCR_SSLN BIT(24) 43 #define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16) 44 #define RPCIF_DRCR_RCF BIT(9) 45 #define RPCIF_DRCR_RBE BIT(8) 46 #define RPCIF_DRCR_SSLE BIT(0) 47 48 #define RPCIF_DRCMR 0x0010 /* R/W */ 49 #define RPCIF_DRCMR_CMD(c) (((c) & 0xFF) << 16) 50 #define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0) 51 52 #define RPCIF_DREAR 0x0014 /* R/W */ 53 #define RPCIF_DREAR_EAV(c) (((c) & 0xF) << 16) 54 #define RPCIF_DREAR_EAC(c) (((c) & 0x7) << 0) 55 56 #define RPCIF_DROPR 0x0018 /* R/W */ 57 58 #define RPCIF_DRENR 0x001C /* R/W */ 59 #define RPCIF_DRENR_CDB(o) (u32)((((o) & 0x3) << 30)) 60 #define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28) 61 #define RPCIF_DRENR_ADB(o) (((o) & 0x3) << 24) 62 #define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20) 63 #define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16) 64 #define RPCIF_DRENR_DME BIT(15) 65 #define RPCIF_DRENR_CDE BIT(14) 66 #define RPCIF_DRENR_OCDE BIT(12) 67 #define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8) 68 #define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4) 69 70 #define RPCIF_SMCR 0x0020 /* R/W */ 71 #define RPCIF_SMCR_SSLKP BIT(8) 72 #define RPCIF_SMCR_SPIRE BIT(2) 73 #define RPCIF_SMCR_SPIWE BIT(1) 74 #define RPCIF_SMCR_SPIE BIT(0) 75 76 #define RPCIF_SMCMR 0x0024 /* R/W */ 77 #define RPCIF_SMCMR_CMD(c) (((c) & 0xFF) << 16) 78 #define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0) 79 80 #define RPCIF_SMADR 0x0028 /* R/W */ 81 82 #define RPCIF_SMOPR 0x002C /* R/W */ 83 #define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24) 84 #define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16) 85 #define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8) 86 #define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0) 87 88 #define RPCIF_SMENR 0x0030 /* R/W */ 89 #define RPCIF_SMENR_CDB(o) (((o) & 0x3) << 30) 90 #define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28) 91 #define RPCIF_SMENR_ADB(o) (((o) & 0x3) << 24) 92 #define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20) 93 #define RPCIF_SMENR_SPIDB(o) (((o) & 0x3) << 16) 94 #define RPCIF_SMENR_DME BIT(15) 95 #define RPCIF_SMENR_CDE BIT(14) 96 #define RPCIF_SMENR_OCDE BIT(12) 97 #define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8) 98 #define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4) 99 #define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0) 100 101 #define RPCIF_SMRDR0 0x0038 /* R */ 102 #define RPCIF_SMRDR1 0x003C /* R */ 103 #define RPCIF_SMWDR0 0x0040 /* W */ 104 #define RPCIF_SMWDR1 0x0044 /* W */ 105 106 #define RPCIF_CMNSR 0x0048 /* R */ 107 #define RPCIF_CMNSR_SSLF BIT(1) 108 #define RPCIF_CMNSR_TEND BIT(0) 109 110 #define RPCIF_DRDMCR 0x0058 /* R/W */ 111 #define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0) 112 113 #define RPCIF_DRDRENR 0x005C /* R/W */ 114 #define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12) 115 #define RPCIF_DRDRENR_ADDRE BIT(8) 116 #define RPCIF_DRDRENR_OPDRE BIT(4) 117 #define RPCIF_DRDRENR_DRDRE BIT(0) 118 119 #define RPCIF_SMDMCR 0x0060 /* R/W */ 120 #define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0) 121 122 #define RPCIF_SMDRENR 0x0064 /* R/W */ 123 #define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12) 124 #define RPCIF_SMDRENR_ADDRE BIT(8) 125 #define RPCIF_SMDRENR_OPDRE BIT(4) 126 #define RPCIF_SMDRENR_SPIDRE BIT(0) 127 128 #define RPCIF_PHYADD 0x0070 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */ 129 #define RPCIF_PHYWR 0x0074 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */ 130 131 #define RPCIF_PHYCNT 0x007C /* R/W */ 132 #define RPCIF_PHYCNT_CAL BIT(31) 133 #define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22) 134 #define RPCIF_PHYCNT_EXDS BIT(21) 135 #define RPCIF_PHYCNT_OCT BIT(20) 136 #define RPCIF_PHYCNT_DDRCAL BIT(19) 137 #define RPCIF_PHYCNT_HS BIT(18) 138 #define RPCIF_PHYCNT_CKSEL(v) (((v) & 0x3) << 16) /* valid only for RZ/G2L */ 139 #define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15) /* valid for R-Car and RZ/G2{E,H,M,N} */ 140 #define RPCIF_PHYCNT_WBUF2 BIT(4) 141 #define RPCIF_PHYCNT_WBUF BIT(2) 142 #define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0) 143 #define RPCIF_PHYCNT_PHYMEM_MASK GENMASK(1, 0) 144 145 #define RPCIF_PHYOFFSET1 0x0080 /* R/W */ 146 #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28) 147 148 #define RPCIF_PHYOFFSET2 0x0084 /* R/W */ 149 #define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8) 150 151 #define RPCIF_PHYINT 0x0088 /* R/W */ 152 #define RPCIF_PHYINT_WPVAL BIT(1) 153 154 static const struct regmap_range rpcif_volatile_ranges[] = { 155 regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1), 156 regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1), 157 regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR), 158 }; 159 160 static const struct regmap_access_table rpcif_volatile_table = { 161 .yes_ranges = rpcif_volatile_ranges, 162 .n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges), 163 }; 164 165 166 /* 167 * Custom accessor functions to ensure SM[RW]DR[01] are always accessed with 168 * proper width. Requires rpcif.xfer_size to be correctly set before! 169 */ 170 static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val) 171 { 172 struct rpcif *rpc = context; 173 174 switch (reg) { 175 case RPCIF_SMRDR0: 176 case RPCIF_SMWDR0: 177 switch (rpc->xfer_size) { 178 case 1: 179 *val = readb(rpc->base + reg); 180 return 0; 181 182 case 2: 183 *val = readw(rpc->base + reg); 184 return 0; 185 186 case 4: 187 case 8: 188 *val = readl(rpc->base + reg); 189 return 0; 190 191 default: 192 return -EILSEQ; 193 } 194 195 case RPCIF_SMRDR1: 196 case RPCIF_SMWDR1: 197 if (rpc->xfer_size != 8) 198 return -EILSEQ; 199 break; 200 } 201 202 *val = readl(rpc->base + reg); 203 return 0; 204 } 205 206 static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val) 207 { 208 struct rpcif *rpc = context; 209 210 switch (reg) { 211 case RPCIF_SMWDR0: 212 switch (rpc->xfer_size) { 213 case 1: 214 writeb(val, rpc->base + reg); 215 return 0; 216 217 case 2: 218 writew(val, rpc->base + reg); 219 return 0; 220 221 case 4: 222 case 8: 223 writel(val, rpc->base + reg); 224 return 0; 225 226 default: 227 return -EILSEQ; 228 } 229 230 case RPCIF_SMWDR1: 231 if (rpc->xfer_size != 8) 232 return -EILSEQ; 233 break; 234 235 case RPCIF_SMRDR0: 236 case RPCIF_SMRDR1: 237 return -EPERM; 238 } 239 240 writel(val, rpc->base + reg); 241 return 0; 242 } 243 244 static const struct regmap_config rpcif_regmap_config = { 245 .reg_bits = 32, 246 .val_bits = 32, 247 .reg_stride = 4, 248 .reg_read = rpcif_reg_read, 249 .reg_write = rpcif_reg_write, 250 .fast_io = true, 251 .max_register = RPCIF_PHYINT, 252 .volatile_table = &rpcif_volatile_table, 253 }; 254 255 int rpcif_sw_init(struct rpcif *rpc, struct device *dev) 256 { 257 struct platform_device *pdev = to_platform_device(dev); 258 struct resource *res; 259 260 rpc->dev = dev; 261 262 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); 263 rpc->base = devm_ioremap_resource(&pdev->dev, res); 264 if (IS_ERR(rpc->base)) 265 return PTR_ERR(rpc->base); 266 267 rpc->regmap = devm_regmap_init(&pdev->dev, NULL, rpc, &rpcif_regmap_config); 268 if (IS_ERR(rpc->regmap)) { 269 dev_err(&pdev->dev, 270 "failed to init regmap for rpcif, error %ld\n", 271 PTR_ERR(rpc->regmap)); 272 return PTR_ERR(rpc->regmap); 273 } 274 275 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap"); 276 rpc->dirmap = devm_ioremap_resource(&pdev->dev, res); 277 if (IS_ERR(rpc->dirmap)) 278 return PTR_ERR(rpc->dirmap); 279 rpc->size = resource_size(res); 280 281 rpc->type = (uintptr_t)of_device_get_match_data(dev); 282 rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 283 284 return PTR_ERR_OR_ZERO(rpc->rstc); 285 } 286 EXPORT_SYMBOL(rpcif_sw_init); 287 288 static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif *rpc) 289 { 290 regmap_write(rpc->regmap, RPCIF_PHYWR, 0xa5390000); 291 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000000); 292 regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080); 293 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000022); 294 regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080); 295 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000024); 296 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_CKSEL(3), 297 RPCIF_PHYCNT_CKSEL(3)); 298 regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030); 299 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032); 300 } 301 302 int rpcif_hw_init(struct rpcif *rpc, bool hyperflash) 303 { 304 u32 dummy; 305 306 pm_runtime_get_sync(rpc->dev); 307 308 if (rpc->type == RPCIF_RZ_G2L) { 309 int ret; 310 311 ret = reset_control_reset(rpc->rstc); 312 if (ret) 313 return ret; 314 usleep_range(200, 300); 315 rpcif_rzg2l_timing_adjust_sdr(rpc); 316 } 317 318 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_PHYMEM_MASK, 319 RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0)); 320 321 if (rpc->type == RPCIF_RCAR_GEN3) 322 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, 323 RPCIF_PHYCNT_STRTIM(7), RPCIF_PHYCNT_STRTIM(7)); 324 325 regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET1, RPCIF_PHYOFFSET1_DDRTMG(3), 326 RPCIF_PHYOFFSET1_DDRTMG(3)); 327 regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET2, RPCIF_PHYOFFSET2_OCTTMG(7), 328 RPCIF_PHYOFFSET2_OCTTMG(4)); 329 330 if (hyperflash) 331 regmap_update_bits(rpc->regmap, RPCIF_PHYINT, 332 RPCIF_PHYINT_WPVAL, 0); 333 334 if (rpc->type == RPCIF_RCAR_GEN3) 335 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 336 RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(3), 337 RPCIF_CMNCR_MOIIO(3) | 338 RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); 339 else 340 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 341 RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) | 342 RPCIF_CMNCR_BSZ(3), 343 RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) | 344 RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); 345 346 /* Set RCF after BSZ update */ 347 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF); 348 /* Dummy read according to spec */ 349 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy); 350 regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) | 351 RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7)); 352 353 pm_runtime_put(rpc->dev); 354 355 rpc->bus_size = hyperflash ? 2 : 1; 356 357 return 0; 358 } 359 EXPORT_SYMBOL(rpcif_hw_init); 360 361 static int wait_msg_xfer_end(struct rpcif *rpc) 362 { 363 u32 sts; 364 365 return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts, 366 sts & RPCIF_CMNSR_TEND, 0, 367 USEC_PER_SEC); 368 } 369 370 static u8 rpcif_bits_set(struct rpcif *rpc, u32 nbytes) 371 { 372 if (rpc->bus_size == 2) 373 nbytes /= 2; 374 nbytes = clamp(nbytes, 1U, 4U); 375 return GENMASK(3, 4 - nbytes); 376 } 377 378 static u8 rpcif_bit_size(u8 buswidth) 379 { 380 return buswidth > 4 ? 2 : ilog2(buswidth); 381 } 382 383 void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs, 384 size_t *len) 385 { 386 rpc->smcr = 0; 387 rpc->smadr = 0; 388 rpc->enable = 0; 389 rpc->command = 0; 390 rpc->option = 0; 391 rpc->dummy = 0; 392 rpc->ddr = 0; 393 rpc->xferlen = 0; 394 395 if (op->cmd.buswidth) { 396 rpc->enable = RPCIF_SMENR_CDE | 397 RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth)); 398 rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode); 399 if (op->cmd.ddr) 400 rpc->ddr = RPCIF_SMDRENR_HYPE(0x5); 401 } 402 if (op->ocmd.buswidth) { 403 rpc->enable |= RPCIF_SMENR_OCDE | 404 RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth)); 405 rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode); 406 } 407 408 if (op->addr.buswidth) { 409 rpc->enable |= 410 RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth)); 411 if (op->addr.nbytes == 4) 412 rpc->enable |= RPCIF_SMENR_ADE(0xF); 413 else 414 rpc->enable |= RPCIF_SMENR_ADE(GENMASK( 415 2, 3 - op->addr.nbytes)); 416 if (op->addr.ddr) 417 rpc->ddr |= RPCIF_SMDRENR_ADDRE; 418 419 if (offs && len) 420 rpc->smadr = *offs; 421 else 422 rpc->smadr = op->addr.val; 423 } 424 425 if (op->dummy.buswidth) { 426 rpc->enable |= RPCIF_SMENR_DME; 427 rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles / 428 op->dummy.buswidth); 429 } 430 431 if (op->option.buswidth) { 432 rpc->enable |= RPCIF_SMENR_OPDE( 433 rpcif_bits_set(rpc, op->option.nbytes)) | 434 RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth)); 435 if (op->option.ddr) 436 rpc->ddr |= RPCIF_SMDRENR_OPDRE; 437 rpc->option = op->option.val; 438 } 439 440 rpc->dir = op->data.dir; 441 if (op->data.buswidth) { 442 u32 nbytes; 443 444 rpc->buffer = op->data.buf.in; 445 switch (op->data.dir) { 446 case RPCIF_DATA_IN: 447 rpc->smcr = RPCIF_SMCR_SPIRE; 448 break; 449 case RPCIF_DATA_OUT: 450 rpc->smcr = RPCIF_SMCR_SPIWE; 451 break; 452 default: 453 break; 454 } 455 if (op->data.ddr) 456 rpc->ddr |= RPCIF_SMDRENR_SPIDRE; 457 458 if (offs && len) 459 nbytes = *len; 460 else 461 nbytes = op->data.nbytes; 462 rpc->xferlen = nbytes; 463 464 rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth)); 465 } 466 } 467 EXPORT_SYMBOL(rpcif_prepare); 468 469 int rpcif_manual_xfer(struct rpcif *rpc) 470 { 471 u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4; 472 int ret = 0; 473 474 pm_runtime_get_sync(rpc->dev); 475 476 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, 477 RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL); 478 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 479 RPCIF_CMNCR_MD, RPCIF_CMNCR_MD); 480 regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command); 481 regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option); 482 regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy); 483 regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr); 484 regmap_write(rpc->regmap, RPCIF_SMADR, rpc->smadr); 485 smenr = rpc->enable; 486 487 switch (rpc->dir) { 488 case RPCIF_DATA_OUT: 489 while (pos < rpc->xferlen) { 490 u32 bytes_left = rpc->xferlen - pos; 491 u32 nbytes, data[2]; 492 493 smcr = rpc->smcr | RPCIF_SMCR_SPIE; 494 495 /* nbytes may only be 1, 2, 4, or 8 */ 496 nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left)); 497 if (bytes_left > nbytes) 498 smcr |= RPCIF_SMCR_SSLKP; 499 500 smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes)); 501 regmap_write(rpc->regmap, RPCIF_SMENR, smenr); 502 rpc->xfer_size = nbytes; 503 504 memcpy(data, rpc->buffer + pos, nbytes); 505 if (nbytes == 8) { 506 regmap_write(rpc->regmap, RPCIF_SMWDR1, 507 data[0]); 508 regmap_write(rpc->regmap, RPCIF_SMWDR0, 509 data[1]); 510 } else { 511 regmap_write(rpc->regmap, RPCIF_SMWDR0, 512 data[0]); 513 } 514 515 regmap_write(rpc->regmap, RPCIF_SMCR, smcr); 516 ret = wait_msg_xfer_end(rpc); 517 if (ret) 518 goto err_out; 519 520 pos += nbytes; 521 smenr = rpc->enable & 522 ~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF); 523 } 524 break; 525 case RPCIF_DATA_IN: 526 /* 527 * RPC-IF spoils the data for the commands without an address 528 * phase (like RDID) in the manual mode, so we'll have to work 529 * around this issue by using the external address space read 530 * mode instead. 531 */ 532 if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) { 533 u32 dummy; 534 535 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 536 RPCIF_CMNCR_MD, 0); 537 regmap_write(rpc->regmap, RPCIF_DRCR, 538 RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE); 539 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command); 540 regmap_write(rpc->regmap, RPCIF_DREAR, 541 RPCIF_DREAR_EAC(1)); 542 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option); 543 regmap_write(rpc->regmap, RPCIF_DRENR, 544 smenr & ~RPCIF_SMENR_SPIDE(0xF)); 545 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy); 546 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr); 547 memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen); 548 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF); 549 /* Dummy read according to spec */ 550 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy); 551 break; 552 } 553 while (pos < rpc->xferlen) { 554 u32 bytes_left = rpc->xferlen - pos; 555 u32 nbytes, data[2]; 556 557 /* nbytes may only be 1, 2, 4, or 8 */ 558 nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left)); 559 560 regmap_write(rpc->regmap, RPCIF_SMADR, 561 rpc->smadr + pos); 562 smenr &= ~RPCIF_SMENR_SPIDE(0xF); 563 smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes)); 564 regmap_write(rpc->regmap, RPCIF_SMENR, smenr); 565 regmap_write(rpc->regmap, RPCIF_SMCR, 566 rpc->smcr | RPCIF_SMCR_SPIE); 567 rpc->xfer_size = nbytes; 568 ret = wait_msg_xfer_end(rpc); 569 if (ret) 570 goto err_out; 571 572 if (nbytes == 8) { 573 regmap_read(rpc->regmap, RPCIF_SMRDR1, 574 &data[0]); 575 regmap_read(rpc->regmap, RPCIF_SMRDR0, 576 &data[1]); 577 } else { 578 regmap_read(rpc->regmap, RPCIF_SMRDR0, 579 &data[0]); 580 } 581 memcpy(rpc->buffer + pos, data, nbytes); 582 583 pos += nbytes; 584 } 585 break; 586 default: 587 regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable); 588 regmap_write(rpc->regmap, RPCIF_SMCR, 589 rpc->smcr | RPCIF_SMCR_SPIE); 590 ret = wait_msg_xfer_end(rpc); 591 if (ret) 592 goto err_out; 593 } 594 595 exit: 596 pm_runtime_put(rpc->dev); 597 return ret; 598 599 err_out: 600 if (reset_control_reset(rpc->rstc)) 601 dev_err(rpc->dev, "Failed to reset HW\n"); 602 rpcif_hw_init(rpc, rpc->bus_size == 2); 603 goto exit; 604 } 605 EXPORT_SYMBOL(rpcif_manual_xfer); 606 607 static void memcpy_fromio_readw(void *to, 608 const void __iomem *from, 609 size_t count) 610 { 611 const int maxw = (IS_ENABLED(CONFIG_64BIT)) ? 8 : 4; 612 u8 buf[2]; 613 614 if (count && ((unsigned long)from & 1)) { 615 *(u16 *)buf = __raw_readw((void __iomem *)((unsigned long)from & ~1)); 616 *(u8 *)to = buf[1]; 617 from++; 618 to++; 619 count--; 620 } 621 while (count >= 2 && !IS_ALIGNED((unsigned long)from, maxw)) { 622 *(u16 *)to = __raw_readw(from); 623 from += 2; 624 to += 2; 625 count -= 2; 626 } 627 while (count >= maxw) { 628 #ifdef CONFIG_64BIT 629 *(u64 *)to = __raw_readq(from); 630 #else 631 *(u32 *)to = __raw_readl(from); 632 #endif 633 from += maxw; 634 to += maxw; 635 count -= maxw; 636 } 637 while (count >= 2) { 638 *(u16 *)to = __raw_readw(from); 639 from += 2; 640 to += 2; 641 count -= 2; 642 } 643 if (count) { 644 *(u16 *)buf = __raw_readw(from); 645 *(u8 *)to = buf[0]; 646 } 647 } 648 649 ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf) 650 { 651 loff_t from = offs & (rpc->size - 1); 652 size_t size = rpc->size - from; 653 654 if (len > size) 655 len = size; 656 657 pm_runtime_get_sync(rpc->dev); 658 659 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0); 660 regmap_write(rpc->regmap, RPCIF_DRCR, 0); 661 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command); 662 regmap_write(rpc->regmap, RPCIF_DREAR, 663 RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1)); 664 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option); 665 regmap_write(rpc->regmap, RPCIF_DRENR, 666 rpc->enable & ~RPCIF_SMENR_SPIDE(0xF)); 667 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy); 668 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr); 669 670 if (rpc->bus_size == 2) 671 memcpy_fromio_readw(buf, rpc->dirmap + from, len); 672 else 673 memcpy_fromio(buf, rpc->dirmap + from, len); 674 675 pm_runtime_put(rpc->dev); 676 677 return len; 678 } 679 EXPORT_SYMBOL(rpcif_dirmap_read); 680 681 static int rpcif_probe(struct platform_device *pdev) 682 { 683 struct platform_device *vdev; 684 struct device_node *flash; 685 const char *name; 686 int ret; 687 688 flash = of_get_next_child(pdev->dev.of_node, NULL); 689 if (!flash) { 690 dev_warn(&pdev->dev, "no flash node found\n"); 691 return -ENODEV; 692 } 693 694 if (of_device_is_compatible(flash, "jedec,spi-nor")) { 695 name = "rpc-if-spi"; 696 } else if (of_device_is_compatible(flash, "cfi-flash")) { 697 name = "rpc-if-hyperflash"; 698 } else { 699 of_node_put(flash); 700 dev_warn(&pdev->dev, "unknown flash type\n"); 701 return -ENODEV; 702 } 703 of_node_put(flash); 704 705 vdev = platform_device_alloc(name, pdev->id); 706 if (!vdev) 707 return -ENOMEM; 708 vdev->dev.parent = &pdev->dev; 709 platform_set_drvdata(pdev, vdev); 710 711 ret = platform_device_add(vdev); 712 if (ret) { 713 platform_device_put(vdev); 714 return ret; 715 } 716 717 return 0; 718 } 719 720 static int rpcif_remove(struct platform_device *pdev) 721 { 722 struct platform_device *vdev = platform_get_drvdata(pdev); 723 724 platform_device_unregister(vdev); 725 726 return 0; 727 } 728 729 static const struct of_device_id rpcif_of_match[] = { 730 { .compatible = "renesas,rcar-gen3-rpc-if", .data = (void *)RPCIF_RCAR_GEN3 }, 731 { .compatible = "renesas,rzg2l-rpc-if", .data = (void *)RPCIF_RZ_G2L }, 732 {}, 733 }; 734 MODULE_DEVICE_TABLE(of, rpcif_of_match); 735 736 static struct platform_driver rpcif_driver = { 737 .probe = rpcif_probe, 738 .remove = rpcif_remove, 739 .driver = { 740 .name = "rpc-if", 741 .of_match_table = rpcif_of_match, 742 }, 743 }; 744 module_platform_driver(rpcif_driver); 745 746 MODULE_DESCRIPTION("Renesas RPC-IF core driver"); 747 MODULE_LICENSE("GPL v2"); 748