1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RPC-IF core driver 4 * 5 * Copyright (C) 2018-2019 Renesas Solutions Corp. 6 * Copyright (C) 2019 Macronix International Co., Ltd. 7 * Copyright (C) 2019-2020 Cogent Embedded, Inc. 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 19 #include <memory/renesas-rpc-if.h> 20 21 #define RPCIF_CMNCR 0x0000 /* R/W */ 22 #define RPCIF_CMNCR_MD BIT(31) 23 #define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22) 24 #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20) 25 #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18) 26 #define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16) 27 #define RPCIF_CMNCR_MOIIO(val) (RPCIF_CMNCR_MOIIO0(val) | RPCIF_CMNCR_MOIIO1(val) | \ 28 RPCIF_CMNCR_MOIIO2(val) | RPCIF_CMNCR_MOIIO3(val)) 29 #define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* documented for RZ/G2L */ 30 #define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* documented for RZ/G2L */ 31 #define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8) 32 #define RPCIF_CMNCR_IOFV(val) (RPCIF_CMNCR_IO0FV(val) | RPCIF_CMNCR_IO2FV(val) | \ 33 RPCIF_CMNCR_IO3FV(val)) 34 #define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0) 35 36 #define RPCIF_SSLDR 0x0004 /* R/W */ 37 #define RPCIF_SSLDR_SPNDL(d) (((d) & 0x7) << 16) 38 #define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8) 39 #define RPCIF_SSLDR_SCKDL(d) (((d) & 0x7) << 0) 40 41 #define RPCIF_DRCR 0x000C /* R/W */ 42 #define RPCIF_DRCR_SSLN BIT(24) 43 #define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16) 44 #define RPCIF_DRCR_RCF BIT(9) 45 #define RPCIF_DRCR_RBE BIT(8) 46 #define RPCIF_DRCR_SSLE BIT(0) 47 48 #define RPCIF_DRCMR 0x0010 /* R/W */ 49 #define RPCIF_DRCMR_CMD(c) (((c) & 0xFF) << 16) 50 #define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0) 51 52 #define RPCIF_DREAR 0x0014 /* R/W */ 53 #define RPCIF_DREAR_EAV(c) (((c) & 0xF) << 16) 54 #define RPCIF_DREAR_EAC(c) (((c) & 0x7) << 0) 55 56 #define RPCIF_DROPR 0x0018 /* R/W */ 57 58 #define RPCIF_DRENR 0x001C /* R/W */ 59 #define RPCIF_DRENR_CDB(o) (u32)((((o) & 0x3) << 30)) 60 #define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28) 61 #define RPCIF_DRENR_ADB(o) (((o) & 0x3) << 24) 62 #define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20) 63 #define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16) 64 #define RPCIF_DRENR_DME BIT(15) 65 #define RPCIF_DRENR_CDE BIT(14) 66 #define RPCIF_DRENR_OCDE BIT(12) 67 #define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8) 68 #define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4) 69 70 #define RPCIF_SMCR 0x0020 /* R/W */ 71 #define RPCIF_SMCR_SSLKP BIT(8) 72 #define RPCIF_SMCR_SPIRE BIT(2) 73 #define RPCIF_SMCR_SPIWE BIT(1) 74 #define RPCIF_SMCR_SPIE BIT(0) 75 76 #define RPCIF_SMCMR 0x0024 /* R/W */ 77 #define RPCIF_SMCMR_CMD(c) (((c) & 0xFF) << 16) 78 #define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0) 79 80 #define RPCIF_SMADR 0x0028 /* R/W */ 81 82 #define RPCIF_SMOPR 0x002C /* R/W */ 83 #define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24) 84 #define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16) 85 #define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8) 86 #define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0) 87 88 #define RPCIF_SMENR 0x0030 /* R/W */ 89 #define RPCIF_SMENR_CDB(o) (((o) & 0x3) << 30) 90 #define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28) 91 #define RPCIF_SMENR_ADB(o) (((o) & 0x3) << 24) 92 #define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20) 93 #define RPCIF_SMENR_SPIDB(o) (((o) & 0x3) << 16) 94 #define RPCIF_SMENR_DME BIT(15) 95 #define RPCIF_SMENR_CDE BIT(14) 96 #define RPCIF_SMENR_OCDE BIT(12) 97 #define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8) 98 #define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4) 99 #define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0) 100 101 #define RPCIF_SMRDR0 0x0038 /* R */ 102 #define RPCIF_SMRDR1 0x003C /* R */ 103 #define RPCIF_SMWDR0 0x0040 /* W */ 104 #define RPCIF_SMWDR1 0x0044 /* W */ 105 106 #define RPCIF_CMNSR 0x0048 /* R */ 107 #define RPCIF_CMNSR_SSLF BIT(1) 108 #define RPCIF_CMNSR_TEND BIT(0) 109 110 #define RPCIF_DRDMCR 0x0058 /* R/W */ 111 #define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0) 112 113 #define RPCIF_DRDRENR 0x005C /* R/W */ 114 #define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12) 115 #define RPCIF_DRDRENR_ADDRE BIT(8) 116 #define RPCIF_DRDRENR_OPDRE BIT(4) 117 #define RPCIF_DRDRENR_DRDRE BIT(0) 118 119 #define RPCIF_SMDMCR 0x0060 /* R/W */ 120 #define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0) 121 122 #define RPCIF_SMDRENR 0x0064 /* R/W */ 123 #define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12) 124 #define RPCIF_SMDRENR_ADDRE BIT(8) 125 #define RPCIF_SMDRENR_OPDRE BIT(4) 126 #define RPCIF_SMDRENR_SPIDRE BIT(0) 127 128 #define RPCIF_PHYADD 0x0070 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */ 129 #define RPCIF_PHYWR 0x0074 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */ 130 131 #define RPCIF_PHYCNT 0x007C /* R/W */ 132 #define RPCIF_PHYCNT_CAL BIT(31) 133 #define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22) 134 #define RPCIF_PHYCNT_EXDS BIT(21) 135 #define RPCIF_PHYCNT_OCT BIT(20) 136 #define RPCIF_PHYCNT_DDRCAL BIT(19) 137 #define RPCIF_PHYCNT_HS BIT(18) 138 #define RPCIF_PHYCNT_CKSEL(v) (((v) & 0x3) << 16) /* valid only for RZ/G2L */ 139 #define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15 | ((v) & 0x8) << 24) /* valid for R-Car and RZ/G2{E,H,M,N} */ 140 141 #define RPCIF_PHYCNT_WBUF2 BIT(4) 142 #define RPCIF_PHYCNT_WBUF BIT(2) 143 #define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0) 144 #define RPCIF_PHYCNT_PHYMEM_MASK GENMASK(1, 0) 145 146 #define RPCIF_PHYOFFSET1 0x0080 /* R/W */ 147 #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28) 148 149 #define RPCIF_PHYOFFSET2 0x0084 /* R/W */ 150 #define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8) 151 152 #define RPCIF_PHYINT 0x0088 /* R/W */ 153 #define RPCIF_PHYINT_WPVAL BIT(1) 154 155 static const struct regmap_range rpcif_volatile_ranges[] = { 156 regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1), 157 regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1), 158 regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR), 159 }; 160 161 static const struct regmap_access_table rpcif_volatile_table = { 162 .yes_ranges = rpcif_volatile_ranges, 163 .n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges), 164 }; 165 166 struct rpcif_priv { 167 struct device *dev; 168 void __iomem *base; 169 void __iomem *dirmap; 170 struct regmap *regmap; 171 struct reset_control *rstc; 172 struct platform_device *vdev; 173 size_t size; 174 enum rpcif_type type; 175 enum rpcif_data_dir dir; 176 u8 bus_size; 177 u8 xfer_size; 178 void *buffer; 179 u32 xferlen; 180 u32 smcr; 181 u32 smadr; 182 u32 command; /* DRCMR or SMCMR */ 183 u32 option; /* DROPR or SMOPR */ 184 u32 enable; /* DRENR or SMENR */ 185 u32 dummy; /* DRDMCR or SMDMCR */ 186 u32 ddr; /* DRDRENR or SMDRENR */ 187 }; 188 189 /* 190 * Custom accessor functions to ensure SM[RW]DR[01] are always accessed with 191 * proper width. Requires rpcif_priv.xfer_size to be correctly set before! 192 */ 193 static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val) 194 { 195 struct rpcif_priv *rpc = context; 196 197 switch (reg) { 198 case RPCIF_SMRDR0: 199 case RPCIF_SMWDR0: 200 switch (rpc->xfer_size) { 201 case 1: 202 *val = readb(rpc->base + reg); 203 return 0; 204 205 case 2: 206 *val = readw(rpc->base + reg); 207 return 0; 208 209 case 4: 210 case 8: 211 *val = readl(rpc->base + reg); 212 return 0; 213 214 default: 215 return -EILSEQ; 216 } 217 218 case RPCIF_SMRDR1: 219 case RPCIF_SMWDR1: 220 if (rpc->xfer_size != 8) 221 return -EILSEQ; 222 break; 223 } 224 225 *val = readl(rpc->base + reg); 226 return 0; 227 } 228 229 static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val) 230 { 231 struct rpcif_priv *rpc = context; 232 233 switch (reg) { 234 case RPCIF_SMWDR0: 235 switch (rpc->xfer_size) { 236 case 1: 237 writeb(val, rpc->base + reg); 238 return 0; 239 240 case 2: 241 writew(val, rpc->base + reg); 242 return 0; 243 244 case 4: 245 case 8: 246 writel(val, rpc->base + reg); 247 return 0; 248 249 default: 250 return -EILSEQ; 251 } 252 253 case RPCIF_SMWDR1: 254 if (rpc->xfer_size != 8) 255 return -EILSEQ; 256 break; 257 258 case RPCIF_SMRDR0: 259 case RPCIF_SMRDR1: 260 return -EPERM; 261 } 262 263 writel(val, rpc->base + reg); 264 return 0; 265 } 266 267 static const struct regmap_config rpcif_regmap_config = { 268 .reg_bits = 32, 269 .val_bits = 32, 270 .reg_stride = 4, 271 .reg_read = rpcif_reg_read, 272 .reg_write = rpcif_reg_write, 273 .fast_io = true, 274 .max_register = RPCIF_PHYINT, 275 .volatile_table = &rpcif_volatile_table, 276 }; 277 278 int rpcif_sw_init(struct rpcif *rpcif, struct device *dev) 279 { 280 struct rpcif_priv *rpc = dev_get_drvdata(dev); 281 282 rpcif->dev = dev; 283 rpcif->dirmap = rpc->dirmap; 284 rpcif->size = rpc->size; 285 return 0; 286 } 287 EXPORT_SYMBOL(rpcif_sw_init); 288 289 static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif_priv *rpc) 290 { 291 regmap_write(rpc->regmap, RPCIF_PHYWR, 0xa5390000); 292 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000000); 293 regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080); 294 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000022); 295 regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080); 296 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000024); 297 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_CKSEL(3), 298 RPCIF_PHYCNT_CKSEL(3)); 299 regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030); 300 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032); 301 } 302 303 int rpcif_hw_init(struct device *dev, bool hyperflash) 304 { 305 struct rpcif_priv *rpc = dev_get_drvdata(dev); 306 u32 dummy; 307 int ret; 308 309 ret = pm_runtime_resume_and_get(dev); 310 if (ret) 311 return ret; 312 313 if (rpc->type == RPCIF_RZ_G2L) { 314 ret = reset_control_reset(rpc->rstc); 315 if (ret) 316 return ret; 317 usleep_range(200, 300); 318 rpcif_rzg2l_timing_adjust_sdr(rpc); 319 } 320 321 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_PHYMEM_MASK, 322 RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0)); 323 324 /* DMA Transfer is not supported */ 325 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_HS, 0); 326 327 if (rpc->type == RPCIF_RCAR_GEN3) 328 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, 329 RPCIF_PHYCNT_STRTIM(7), RPCIF_PHYCNT_STRTIM(7)); 330 else if (rpc->type == RPCIF_RCAR_GEN4) 331 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, 332 RPCIF_PHYCNT_STRTIM(15), RPCIF_PHYCNT_STRTIM(15)); 333 334 regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET1, RPCIF_PHYOFFSET1_DDRTMG(3), 335 RPCIF_PHYOFFSET1_DDRTMG(3)); 336 regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET2, RPCIF_PHYOFFSET2_OCTTMG(7), 337 RPCIF_PHYOFFSET2_OCTTMG(4)); 338 339 if (hyperflash) 340 regmap_update_bits(rpc->regmap, RPCIF_PHYINT, 341 RPCIF_PHYINT_WPVAL, 0); 342 343 if (rpc->type == RPCIF_RZ_G2L) 344 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 345 RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) | 346 RPCIF_CMNCR_BSZ(3), 347 RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) | 348 RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); 349 else 350 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 351 RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(3), 352 RPCIF_CMNCR_MOIIO(3) | 353 RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); 354 355 /* Set RCF after BSZ update */ 356 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF); 357 /* Dummy read according to spec */ 358 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy); 359 regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) | 360 RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7)); 361 362 pm_runtime_put(dev); 363 364 rpc->bus_size = hyperflash ? 2 : 1; 365 366 return 0; 367 } 368 EXPORT_SYMBOL(rpcif_hw_init); 369 370 static int wait_msg_xfer_end(struct rpcif_priv *rpc) 371 { 372 u32 sts; 373 374 return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts, 375 sts & RPCIF_CMNSR_TEND, 0, 376 USEC_PER_SEC); 377 } 378 379 static u8 rpcif_bits_set(struct rpcif_priv *rpc, u32 nbytes) 380 { 381 if (rpc->bus_size == 2) 382 nbytes /= 2; 383 nbytes = clamp(nbytes, 1U, 4U); 384 return GENMASK(3, 4 - nbytes); 385 } 386 387 static u8 rpcif_bit_size(u8 buswidth) 388 { 389 return buswidth > 4 ? 2 : ilog2(buswidth); 390 } 391 392 void rpcif_prepare(struct device *dev, const struct rpcif_op *op, u64 *offs, 393 size_t *len) 394 { 395 struct rpcif_priv *rpc = dev_get_drvdata(dev); 396 397 rpc->smcr = 0; 398 rpc->smadr = 0; 399 rpc->enable = 0; 400 rpc->command = 0; 401 rpc->option = 0; 402 rpc->dummy = 0; 403 rpc->ddr = 0; 404 rpc->xferlen = 0; 405 406 if (op->cmd.buswidth) { 407 rpc->enable = RPCIF_SMENR_CDE | 408 RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth)); 409 rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode); 410 if (op->cmd.ddr) 411 rpc->ddr = RPCIF_SMDRENR_HYPE(0x5); 412 } 413 if (op->ocmd.buswidth) { 414 rpc->enable |= RPCIF_SMENR_OCDE | 415 RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth)); 416 rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode); 417 } 418 419 if (op->addr.buswidth) { 420 rpc->enable |= 421 RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth)); 422 if (op->addr.nbytes == 4) 423 rpc->enable |= RPCIF_SMENR_ADE(0xF); 424 else 425 rpc->enable |= RPCIF_SMENR_ADE(GENMASK( 426 2, 3 - op->addr.nbytes)); 427 if (op->addr.ddr) 428 rpc->ddr |= RPCIF_SMDRENR_ADDRE; 429 430 if (offs && len) 431 rpc->smadr = *offs; 432 else 433 rpc->smadr = op->addr.val; 434 } 435 436 if (op->dummy.buswidth) { 437 rpc->enable |= RPCIF_SMENR_DME; 438 rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles); 439 } 440 441 if (op->option.buswidth) { 442 rpc->enable |= RPCIF_SMENR_OPDE( 443 rpcif_bits_set(rpc, op->option.nbytes)) | 444 RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth)); 445 if (op->option.ddr) 446 rpc->ddr |= RPCIF_SMDRENR_OPDRE; 447 rpc->option = op->option.val; 448 } 449 450 rpc->dir = op->data.dir; 451 if (op->data.buswidth) { 452 u32 nbytes; 453 454 rpc->buffer = op->data.buf.in; 455 switch (op->data.dir) { 456 case RPCIF_DATA_IN: 457 rpc->smcr = RPCIF_SMCR_SPIRE; 458 break; 459 case RPCIF_DATA_OUT: 460 rpc->smcr = RPCIF_SMCR_SPIWE; 461 break; 462 default: 463 break; 464 } 465 if (op->data.ddr) 466 rpc->ddr |= RPCIF_SMDRENR_SPIDRE; 467 468 if (offs && len) 469 nbytes = *len; 470 else 471 nbytes = op->data.nbytes; 472 rpc->xferlen = nbytes; 473 474 rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth)); 475 } 476 } 477 EXPORT_SYMBOL(rpcif_prepare); 478 479 int rpcif_manual_xfer(struct device *dev) 480 { 481 struct rpcif_priv *rpc = dev_get_drvdata(dev); 482 u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4; 483 int ret = 0; 484 485 ret = pm_runtime_resume_and_get(dev); 486 if (ret < 0) 487 return ret; 488 489 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, 490 RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL); 491 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 492 RPCIF_CMNCR_MD, RPCIF_CMNCR_MD); 493 regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command); 494 regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option); 495 regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy); 496 regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr); 497 regmap_write(rpc->regmap, RPCIF_SMADR, rpc->smadr); 498 smenr = rpc->enable; 499 500 switch (rpc->dir) { 501 case RPCIF_DATA_OUT: 502 while (pos < rpc->xferlen) { 503 u32 bytes_left = rpc->xferlen - pos; 504 u32 nbytes, data[2], *p = data; 505 506 smcr = rpc->smcr | RPCIF_SMCR_SPIE; 507 508 /* nbytes may only be 1, 2, 4, or 8 */ 509 nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left)); 510 if (bytes_left > nbytes) 511 smcr |= RPCIF_SMCR_SSLKP; 512 513 smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes)); 514 regmap_write(rpc->regmap, RPCIF_SMENR, smenr); 515 rpc->xfer_size = nbytes; 516 517 memcpy(data, rpc->buffer + pos, nbytes); 518 if (nbytes == 8) 519 regmap_write(rpc->regmap, RPCIF_SMWDR1, *p++); 520 regmap_write(rpc->regmap, RPCIF_SMWDR0, *p); 521 522 regmap_write(rpc->regmap, RPCIF_SMCR, smcr); 523 ret = wait_msg_xfer_end(rpc); 524 if (ret) 525 goto err_out; 526 527 pos += nbytes; 528 smenr = rpc->enable & 529 ~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF); 530 } 531 break; 532 case RPCIF_DATA_IN: 533 /* 534 * RPC-IF spoils the data for the commands without an address 535 * phase (like RDID) in the manual mode, so we'll have to work 536 * around this issue by using the external address space read 537 * mode instead. 538 */ 539 if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) { 540 u32 dummy; 541 542 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 543 RPCIF_CMNCR_MD, 0); 544 regmap_write(rpc->regmap, RPCIF_DRCR, 545 RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE); 546 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command); 547 regmap_write(rpc->regmap, RPCIF_DREAR, 548 RPCIF_DREAR_EAC(1)); 549 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option); 550 regmap_write(rpc->regmap, RPCIF_DRENR, 551 smenr & ~RPCIF_SMENR_SPIDE(0xF)); 552 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy); 553 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr); 554 memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen); 555 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF); 556 /* Dummy read according to spec */ 557 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy); 558 break; 559 } 560 while (pos < rpc->xferlen) { 561 u32 bytes_left = rpc->xferlen - pos; 562 u32 nbytes, data[2], *p = data; 563 564 /* nbytes may only be 1, 2, 4, or 8 */ 565 nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left)); 566 567 regmap_write(rpc->regmap, RPCIF_SMADR, 568 rpc->smadr + pos); 569 smenr &= ~RPCIF_SMENR_SPIDE(0xF); 570 smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes)); 571 regmap_write(rpc->regmap, RPCIF_SMENR, smenr); 572 regmap_write(rpc->regmap, RPCIF_SMCR, 573 rpc->smcr | RPCIF_SMCR_SPIE); 574 rpc->xfer_size = nbytes; 575 ret = wait_msg_xfer_end(rpc); 576 if (ret) 577 goto err_out; 578 579 if (nbytes == 8) 580 regmap_read(rpc->regmap, RPCIF_SMRDR1, p++); 581 regmap_read(rpc->regmap, RPCIF_SMRDR0, p); 582 memcpy(rpc->buffer + pos, data, nbytes); 583 584 pos += nbytes; 585 } 586 break; 587 default: 588 regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable); 589 regmap_write(rpc->regmap, RPCIF_SMCR, 590 rpc->smcr | RPCIF_SMCR_SPIE); 591 ret = wait_msg_xfer_end(rpc); 592 if (ret) 593 goto err_out; 594 } 595 596 exit: 597 pm_runtime_put(dev); 598 return ret; 599 600 err_out: 601 if (reset_control_reset(rpc->rstc)) 602 dev_err(dev, "Failed to reset HW\n"); 603 rpcif_hw_init(dev, rpc->bus_size == 2); 604 goto exit; 605 } 606 EXPORT_SYMBOL(rpcif_manual_xfer); 607 608 static void memcpy_fromio_readw(void *to, 609 const void __iomem *from, 610 size_t count) 611 { 612 const int maxw = (IS_ENABLED(CONFIG_64BIT)) ? 8 : 4; 613 u8 buf[2]; 614 615 if (count && ((unsigned long)from & 1)) { 616 *(u16 *)buf = __raw_readw((void __iomem *)((unsigned long)from & ~1)); 617 *(u8 *)to = buf[1]; 618 from++; 619 to++; 620 count--; 621 } 622 while (count >= 2 && !IS_ALIGNED((unsigned long)from, maxw)) { 623 *(u16 *)to = __raw_readw(from); 624 from += 2; 625 to += 2; 626 count -= 2; 627 } 628 while (count >= maxw) { 629 #ifdef CONFIG_64BIT 630 *(u64 *)to = __raw_readq(from); 631 #else 632 *(u32 *)to = __raw_readl(from); 633 #endif 634 from += maxw; 635 to += maxw; 636 count -= maxw; 637 } 638 while (count >= 2) { 639 *(u16 *)to = __raw_readw(from); 640 from += 2; 641 to += 2; 642 count -= 2; 643 } 644 if (count) { 645 *(u16 *)buf = __raw_readw(from); 646 *(u8 *)to = buf[0]; 647 } 648 } 649 650 ssize_t rpcif_dirmap_read(struct device *dev, u64 offs, size_t len, void *buf) 651 { 652 struct rpcif_priv *rpc = dev_get_drvdata(dev); 653 loff_t from = offs & (rpc->size - 1); 654 size_t size = rpc->size - from; 655 int ret; 656 657 if (len > size) 658 len = size; 659 660 ret = pm_runtime_resume_and_get(dev); 661 if (ret < 0) 662 return ret; 663 664 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0); 665 regmap_write(rpc->regmap, RPCIF_DRCR, 0); 666 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command); 667 regmap_write(rpc->regmap, RPCIF_DREAR, 668 RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1)); 669 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option); 670 regmap_write(rpc->regmap, RPCIF_DRENR, 671 rpc->enable & ~RPCIF_SMENR_SPIDE(0xF)); 672 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy); 673 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr); 674 675 if (rpc->bus_size == 2) 676 memcpy_fromio_readw(buf, rpc->dirmap + from, len); 677 else 678 memcpy_fromio(buf, rpc->dirmap + from, len); 679 680 pm_runtime_put(dev); 681 682 return len; 683 } 684 EXPORT_SYMBOL(rpcif_dirmap_read); 685 686 static int rpcif_probe(struct platform_device *pdev) 687 { 688 struct device *dev = &pdev->dev; 689 struct platform_device *vdev; 690 struct device_node *flash; 691 struct rpcif_priv *rpc; 692 struct resource *res; 693 const char *name; 694 int ret; 695 696 flash = of_get_next_child(dev->of_node, NULL); 697 if (!flash) { 698 dev_warn(dev, "no flash node found\n"); 699 return -ENODEV; 700 } 701 702 if (of_device_is_compatible(flash, "jedec,spi-nor")) { 703 name = "rpc-if-spi"; 704 } else if (of_device_is_compatible(flash, "cfi-flash")) { 705 name = "rpc-if-hyperflash"; 706 } else { 707 of_node_put(flash); 708 dev_warn(dev, "unknown flash type\n"); 709 return -ENODEV; 710 } 711 of_node_put(flash); 712 713 rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL); 714 if (!rpc) 715 return -ENOMEM; 716 717 rpc->base = devm_platform_ioremap_resource_byname(pdev, "regs"); 718 if (IS_ERR(rpc->base)) 719 return PTR_ERR(rpc->base); 720 721 rpc->regmap = devm_regmap_init(dev, NULL, rpc, &rpcif_regmap_config); 722 if (IS_ERR(rpc->regmap)) { 723 dev_err(dev, "failed to init regmap for rpcif, error %ld\n", 724 PTR_ERR(rpc->regmap)); 725 return PTR_ERR(rpc->regmap); 726 } 727 728 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap"); 729 rpc->dirmap = devm_ioremap_resource(dev, res); 730 if (IS_ERR(rpc->dirmap)) 731 return PTR_ERR(rpc->dirmap); 732 rpc->size = resource_size(res); 733 734 rpc->type = (uintptr_t)of_device_get_match_data(dev); 735 rpc->rstc = devm_reset_control_get_exclusive(dev, NULL); 736 if (IS_ERR(rpc->rstc)) 737 return PTR_ERR(rpc->rstc); 738 739 vdev = platform_device_alloc(name, pdev->id); 740 if (!vdev) 741 return -ENOMEM; 742 vdev->dev.parent = dev; 743 744 rpc->dev = dev; 745 rpc->vdev = vdev; 746 platform_set_drvdata(pdev, rpc); 747 748 ret = platform_device_add(vdev); 749 if (ret) { 750 platform_device_put(vdev); 751 return ret; 752 } 753 754 return 0; 755 } 756 757 static int rpcif_remove(struct platform_device *pdev) 758 { 759 struct rpcif_priv *rpc = platform_get_drvdata(pdev); 760 761 platform_device_unregister(rpc->vdev); 762 763 return 0; 764 } 765 766 static const struct of_device_id rpcif_of_match[] = { 767 { .compatible = "renesas,rcar-gen3-rpc-if", .data = (void *)RPCIF_RCAR_GEN3 }, 768 { .compatible = "renesas,rcar-gen4-rpc-if", .data = (void *)RPCIF_RCAR_GEN4 }, 769 { .compatible = "renesas,rzg2l-rpc-if", .data = (void *)RPCIF_RZ_G2L }, 770 {}, 771 }; 772 MODULE_DEVICE_TABLE(of, rpcif_of_match); 773 774 static struct platform_driver rpcif_driver = { 775 .probe = rpcif_probe, 776 .remove = rpcif_remove, 777 .driver = { 778 .name = "rpc-if", 779 .of_match_table = rpcif_of_match, 780 }, 781 }; 782 module_platform_driver(rpcif_driver); 783 784 MODULE_DESCRIPTION("Renesas RPC-IF core driver"); 785 MODULE_LICENSE("GPL v2"); 786