1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPMC support functions 4 * 5 * Copyright (C) 2005-2006 Nokia Corporation 6 * 7 * Author: Juha Yrjola 8 * 9 * Copyright (C) 2009 Texas Instruments 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 11 */ 12 #include <linux/irq.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/err.h> 16 #include <linux/clk.h> 17 #include <linux/ioport.h> 18 #include <linux/spinlock.h> 19 #include <linux/io.h> 20 #include <linux/gpio/driver.h> 21 #include <linux/gpio/consumer.h> /* GPIO descriptor enum */ 22 #include <linux/interrupt.h> 23 #include <linux/irqdomain.h> 24 #include <linux/platform_device.h> 25 #include <linux/of.h> 26 #include <linux/of_address.h> 27 #include <linux/of_device.h> 28 #include <linux/of_platform.h> 29 #include <linux/omap-gpmc.h> 30 #include <linux/pm_runtime.h> 31 32 #include <linux/platform_data/mtd-nand-omap2.h> 33 34 #include <asm/mach-types.h> 35 36 #define DEVICE_NAME "omap-gpmc" 37 38 /* GPMC register offsets */ 39 #define GPMC_REVISION 0x00 40 #define GPMC_SYSCONFIG 0x10 41 #define GPMC_SYSSTATUS 0x14 42 #define GPMC_IRQSTATUS 0x18 43 #define GPMC_IRQENABLE 0x1c 44 #define GPMC_TIMEOUT_CONTROL 0x40 45 #define GPMC_ERR_ADDRESS 0x44 46 #define GPMC_ERR_TYPE 0x48 47 #define GPMC_CONFIG 0x50 48 #define GPMC_STATUS 0x54 49 #define GPMC_PREFETCH_CONFIG1 0x1e0 50 #define GPMC_PREFETCH_CONFIG2 0x1e4 51 #define GPMC_PREFETCH_CONTROL 0x1ec 52 #define GPMC_PREFETCH_STATUS 0x1f0 53 #define GPMC_ECC_CONFIG 0x1f4 54 #define GPMC_ECC_CONTROL 0x1f8 55 #define GPMC_ECC_SIZE_CONFIG 0x1fc 56 #define GPMC_ECC1_RESULT 0x200 57 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */ 58 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */ 59 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */ 60 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */ 61 #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */ 62 #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */ 63 #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */ 64 65 /* GPMC ECC control settings */ 66 #define GPMC_ECC_CTRL_ECCCLEAR 0x100 67 #define GPMC_ECC_CTRL_ECCDISABLE 0x000 68 #define GPMC_ECC_CTRL_ECCREG1 0x001 69 #define GPMC_ECC_CTRL_ECCREG2 0x002 70 #define GPMC_ECC_CTRL_ECCREG3 0x003 71 #define GPMC_ECC_CTRL_ECCREG4 0x004 72 #define GPMC_ECC_CTRL_ECCREG5 0x005 73 #define GPMC_ECC_CTRL_ECCREG6 0x006 74 #define GPMC_ECC_CTRL_ECCREG7 0x007 75 #define GPMC_ECC_CTRL_ECCREG8 0x008 76 #define GPMC_ECC_CTRL_ECCREG9 0x009 77 78 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1) 79 80 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0) 81 82 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7) 83 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7) 84 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7) 85 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23) 86 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6) 87 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7) 88 89 #define GPMC_CS0_OFFSET 0x60 90 #define GPMC_CS_SIZE 0x30 91 #define GPMC_BCH_SIZE 0x10 92 93 /* 94 * The first 1MB of GPMC address space is typically mapped to 95 * the internal ROM. Never allocate the first page, to 96 * facilitate bug detection; even if we didn't boot from ROM. 97 * As GPMC minimum partition size is 16MB we can only start from 98 * there. 99 */ 100 #define GPMC_MEM_START 0x1000000 101 #define GPMC_MEM_END 0x3FFFFFFF 102 103 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ 104 #define GPMC_SECTION_SHIFT 28 /* 128 MB */ 105 106 #define CS_NUM_SHIFT 24 107 #define ENABLE_PREFETCH (0x1 << 7) 108 #define DMA_MPU_MODE 2 109 110 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf) 111 #define GPMC_REVISION_MINOR(l) (l & 0xf) 112 113 #define GPMC_HAS_WR_ACCESS 0x1 114 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2 115 #define GPMC_HAS_MUX_AAD 0x4 116 117 #define GPMC_NR_WAITPINS 4 118 119 #define GPMC_CS_CONFIG1 0x00 120 #define GPMC_CS_CONFIG2 0x04 121 #define GPMC_CS_CONFIG3 0x08 122 #define GPMC_CS_CONFIG4 0x0c 123 #define GPMC_CS_CONFIG5 0x10 124 #define GPMC_CS_CONFIG6 0x14 125 #define GPMC_CS_CONFIG7 0x18 126 #define GPMC_CS_NAND_COMMAND 0x1c 127 #define GPMC_CS_NAND_ADDRESS 0x20 128 #define GPMC_CS_NAND_DATA 0x24 129 130 /* Control Commands */ 131 #define GPMC_CONFIG_RDY_BSY 0x00000001 132 #define GPMC_CONFIG_DEV_SIZE 0x00000002 133 #define GPMC_CONFIG_DEV_TYPE 0x00000003 134 135 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) 136 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) 137 #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) 138 #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) 139 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) 140 #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) 141 #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) 142 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) 143 /** CLKACTIVATIONTIME Max Ticks */ 144 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2 145 #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23) 146 /** ATTACHEDDEVICEPAGELENGTH Max Value */ 147 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2 148 #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) 149 #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) 150 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18) 151 /** WAITMONITORINGTIME Max Ticks */ 152 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2 153 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16) 154 #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12) 155 #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) 156 /** DEVICESIZE Max Value */ 157 #define GPMC_CONFIG1_DEVICESIZE_MAX 1 158 #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) 159 #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) 160 #define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8) 161 #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) 162 #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) 163 #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) 164 #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) 165 #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) 166 #define GPMC_CONFIG7_CSVALID (1 << 6) 167 168 #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f 169 #define GPMC_CONFIG7_CSVALID_MASK BIT(6) 170 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8 171 #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET) 172 /* All CONFIG7 bits except reserved bits */ 173 #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \ 174 GPMC_CONFIG7_CSVALID_MASK | \ 175 GPMC_CONFIG7_MASKADDRESS_MASK) 176 177 #define GPMC_DEVICETYPE_NOR 0 178 #define GPMC_DEVICETYPE_NAND 2 179 #define GPMC_CONFIG_WRITEPROTECT 0x00000010 180 #define WR_RD_PIN_MONITORING 0x00600000 181 182 /* ECC commands */ 183 #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ 184 #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ 185 #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */ 186 187 #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */ 188 189 enum gpmc_clk_domain { 190 GPMC_CD_FCLK, 191 GPMC_CD_CLK 192 }; 193 194 struct gpmc_cs_data { 195 const char *name; 196 197 #define GPMC_CS_RESERVED (1 << 0) 198 u32 flags; 199 200 struct resource mem; 201 }; 202 203 /* Structure to save gpmc cs context */ 204 struct gpmc_cs_config { 205 u32 config1; 206 u32 config2; 207 u32 config3; 208 u32 config4; 209 u32 config5; 210 u32 config6; 211 u32 config7; 212 int is_valid; 213 }; 214 215 /* 216 * Structure to save/restore gpmc context 217 * to support core off on OMAP3 218 */ 219 struct omap3_gpmc_regs { 220 u32 sysconfig; 221 u32 irqenable; 222 u32 timeout_ctrl; 223 u32 config; 224 u32 prefetch_config1; 225 u32 prefetch_config2; 226 u32 prefetch_control; 227 struct gpmc_cs_config cs_context[GPMC_CS_NUM]; 228 }; 229 230 struct gpmc_device { 231 struct device *dev; 232 int irq; 233 struct irq_chip irq_chip; 234 struct gpio_chip gpio_chip; 235 int nirqs; 236 }; 237 238 static struct irq_domain *gpmc_irq_domain; 239 240 static struct resource gpmc_mem_root; 241 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM]; 242 static DEFINE_SPINLOCK(gpmc_mem_lock); 243 /* Define chip-selects as reserved by default until probe completes */ 244 static unsigned int gpmc_cs_num = GPMC_CS_NUM; 245 static unsigned int gpmc_nr_waitpins; 246 static resource_size_t phys_base, mem_size; 247 static unsigned gpmc_capability; 248 static void __iomem *gpmc_base; 249 250 static struct clk *gpmc_l3_clk; 251 252 static irqreturn_t gpmc_handle_irq(int irq, void *dev); 253 254 static void gpmc_write_reg(int idx, u32 val) 255 { 256 writel_relaxed(val, gpmc_base + idx); 257 } 258 259 static u32 gpmc_read_reg(int idx) 260 { 261 return readl_relaxed(gpmc_base + idx); 262 } 263 264 void gpmc_cs_write_reg(int cs, int idx, u32 val) 265 { 266 void __iomem *reg_addr; 267 268 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; 269 writel_relaxed(val, reg_addr); 270 } 271 272 static u32 gpmc_cs_read_reg(int cs, int idx) 273 { 274 void __iomem *reg_addr; 275 276 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; 277 return readl_relaxed(reg_addr); 278 } 279 280 /* TODO: Add support for gpmc_fck to clock framework and use it */ 281 static unsigned long gpmc_get_fclk_period(void) 282 { 283 unsigned long rate = clk_get_rate(gpmc_l3_clk); 284 285 rate /= 1000; 286 rate = 1000000000 / rate; /* In picoseconds */ 287 288 return rate; 289 } 290 291 /** 292 * gpmc_get_clk_period - get period of selected clock domain in ps 293 * @cs Chip Select Region. 294 * @cd Clock Domain. 295 * 296 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup 297 * prior to calling this function with GPMC_CD_CLK. 298 */ 299 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd) 300 { 301 302 unsigned long tick_ps = gpmc_get_fclk_period(); 303 u32 l; 304 int div; 305 306 switch (cd) { 307 case GPMC_CD_CLK: 308 /* get current clk divider */ 309 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); 310 div = (l & 0x03) + 1; 311 /* get GPMC_CLK period */ 312 tick_ps *= div; 313 break; 314 case GPMC_CD_FCLK: 315 /* FALL-THROUGH */ 316 default: 317 break; 318 } 319 320 return tick_ps; 321 322 } 323 324 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs, 325 enum gpmc_clk_domain cd) 326 { 327 unsigned long tick_ps; 328 329 /* Calculate in picosecs to yield more exact results */ 330 tick_ps = gpmc_get_clk_period(cs, cd); 331 332 return (time_ns * 1000 + tick_ps - 1) / tick_ps; 333 } 334 335 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns) 336 { 337 return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK); 338 } 339 340 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps) 341 { 342 unsigned long tick_ps; 343 344 /* Calculate in picosecs to yield more exact results */ 345 tick_ps = gpmc_get_fclk_period(); 346 347 return (time_ps + tick_ps - 1) / tick_ps; 348 } 349 350 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs, 351 enum gpmc_clk_domain cd) 352 { 353 return ticks * gpmc_get_clk_period(cs, cd) / 1000; 354 } 355 356 unsigned int gpmc_ticks_to_ns(unsigned int ticks) 357 { 358 return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK); 359 } 360 361 static unsigned int gpmc_ticks_to_ps(unsigned int ticks) 362 { 363 return ticks * gpmc_get_fclk_period(); 364 } 365 366 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps) 367 { 368 unsigned long ticks = gpmc_ps_to_ticks(time_ps); 369 370 return ticks * gpmc_get_fclk_period(); 371 } 372 373 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value) 374 { 375 u32 l; 376 377 l = gpmc_cs_read_reg(cs, reg); 378 if (value) 379 l |= mask; 380 else 381 l &= ~mask; 382 gpmc_cs_write_reg(cs, reg, l); 383 } 384 385 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) 386 { 387 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1, 388 GPMC_CONFIG1_TIME_PARA_GRAN, 389 p->time_para_granularity); 390 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2, 391 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay); 392 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3, 393 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay); 394 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, 395 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay); 396 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, 397 GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay); 398 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, 399 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN, 400 p->cycle2cyclesamecsen); 401 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, 402 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN, 403 p->cycle2cyclediffcsen); 404 } 405 406 #ifdef CONFIG_OMAP_GPMC_DEBUG 407 /** 408 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it. 409 * @cs: Chip Select Region 410 * @reg: GPMC_CS_CONFIGn register offset. 411 * @st_bit: Start Bit 412 * @end_bit: End Bit. Must be >= @st_bit. 413 * @ma:x Maximum parameter value (before optional @shift). 414 * If 0, maximum is as high as @st_bit and @end_bit allow. 415 * @name: DTS node name, w/o "gpmc," 416 * @cd: Clock Domain of timing parameter. 417 * @shift: Parameter value left shifts @shift, which is then printed instead of value. 418 * @raw: Raw Format Option. 419 * raw format: gpmc,name = <value> 420 * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/ 421 * Where x ns -- y ns result in the same tick value. 422 * When @max is exceeded, "invalid" is printed inside comment. 423 * @noval: Parameter values equal to 0 are not printed. 424 * @return: Specified timing parameter (after optional @shift). 425 * 426 */ 427 static int get_gpmc_timing_reg( 428 /* timing specifiers */ 429 int cs, int reg, int st_bit, int end_bit, int max, 430 const char *name, const enum gpmc_clk_domain cd, 431 /* value transform */ 432 int shift, 433 /* format specifiers */ 434 bool raw, bool noval) 435 { 436 u32 l; 437 int nr_bits; 438 int mask; 439 bool invalid; 440 441 l = gpmc_cs_read_reg(cs, reg); 442 nr_bits = end_bit - st_bit + 1; 443 mask = (1 << nr_bits) - 1; 444 l = (l >> st_bit) & mask; 445 if (!max) 446 max = mask; 447 invalid = l > max; 448 if (shift) 449 l = (shift << l); 450 if (noval && (l == 0)) 451 return 0; 452 if (!raw) { 453 /* DTS tick format for timings in ns */ 454 unsigned int time_ns; 455 unsigned int time_ns_min = 0; 456 457 if (l) 458 time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1; 459 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd); 460 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n", 461 name, time_ns, time_ns_min, time_ns, l, 462 invalid ? "; invalid " : " "); 463 } else { 464 /* raw format */ 465 pr_info("gpmc,%s = <%u>;%s\n", name, l, 466 invalid ? " /* invalid */" : ""); 467 } 468 469 return l; 470 } 471 472 #define GPMC_PRINT_CONFIG(cs, config) \ 473 pr_info("cs%i %s: 0x%08x\n", cs, #config, \ 474 gpmc_cs_read_reg(cs, config)) 475 #define GPMC_GET_RAW(reg, st, end, field) \ 476 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0) 477 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \ 478 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0) 479 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \ 480 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1) 481 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \ 482 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1) 483 #define GPMC_GET_TICKS(reg, st, end, field) \ 484 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0) 485 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \ 486 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0) 487 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \ 488 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0) 489 490 static void gpmc_show_regs(int cs, const char *desc) 491 { 492 pr_info("gpmc cs%i %s:\n", cs, desc); 493 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1); 494 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2); 495 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3); 496 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4); 497 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5); 498 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6); 499 } 500 501 /* 502 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available, 503 * see commit c9fb809. 504 */ 505 static void gpmc_cs_show_timings(int cs, const char *desc) 506 { 507 gpmc_show_regs(cs, desc); 508 509 pr_info("gpmc cs%i access configuration:\n", cs); 510 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity"); 511 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data"); 512 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1, 513 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width"); 514 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin"); 515 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write"); 516 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read"); 517 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4, 518 GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX, 519 "burst-length"); 520 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write"); 521 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write"); 522 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read"); 523 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read"); 524 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap"); 525 526 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay"); 527 528 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay"); 529 530 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay"); 531 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay"); 532 533 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen"); 534 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen"); 535 536 pr_info("gpmc cs%i timings configuration:\n", cs); 537 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns"); 538 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns"); 539 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns"); 540 541 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns"); 542 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns"); 543 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns"); 544 if (gpmc_capability & GPMC_HAS_MUX_AAD) { 545 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns"); 546 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26, 547 "adv-aad-mux-rd-off-ns"); 548 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30, 549 "adv-aad-mux-wr-off-ns"); 550 } 551 552 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns"); 553 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns"); 554 if (gpmc_capability & GPMC_HAS_MUX_AAD) { 555 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns"); 556 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns"); 557 } 558 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns"); 559 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns"); 560 561 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns"); 562 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns"); 563 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns"); 564 565 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns"); 566 567 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns"); 568 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns"); 569 570 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19, 571 GPMC_CONFIG1_WAITMONITORINGTIME_MAX, 572 "wait-monitoring-ns", GPMC_CD_CLK); 573 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26, 574 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX, 575 "clk-activation-ns", GPMC_CD_FCLK); 576 577 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns"); 578 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns"); 579 } 580 #else 581 static inline void gpmc_cs_show_timings(int cs, const char *desc) 582 { 583 } 584 #endif 585 586 /** 587 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region. 588 * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER 589 * prior to calling this function with @cd equal to GPMC_CD_CLK. 590 * 591 * @cs: Chip Select Region. 592 * @reg: GPMC_CS_CONFIGn register offset. 593 * @st_bit: Start Bit 594 * @end_bit: End Bit. Must be >= @st_bit. 595 * @max: Maximum parameter value. 596 * If 0, maximum is as high as @st_bit and @end_bit allow. 597 * @time: Timing parameter in ns. 598 * @cd: Timing parameter clock domain. 599 * @name: Timing parameter name. 600 * @return: 0 on success, -1 on error. 601 */ 602 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max, 603 int time, enum gpmc_clk_domain cd, const char *name) 604 { 605 u32 l; 606 int ticks, mask, nr_bits; 607 608 if (time == 0) 609 ticks = 0; 610 else 611 ticks = gpmc_ns_to_clk_ticks(time, cs, cd); 612 nr_bits = end_bit - st_bit + 1; 613 mask = (1 << nr_bits) - 1; 614 615 if (!max) 616 max = mask; 617 618 if (ticks > max) { 619 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n", 620 __func__, cs, name, time, ticks, max); 621 622 return -1; 623 } 624 625 l = gpmc_cs_read_reg(cs, reg); 626 #ifdef CONFIG_OMAP_GPMC_DEBUG 627 pr_info( 628 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", 629 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000, 630 (l >> st_bit) & mask, time); 631 #endif 632 l &= ~(mask << st_bit); 633 l |= ticks << st_bit; 634 gpmc_cs_write_reg(cs, reg, l); 635 636 return 0; 637 } 638 639 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd) \ 640 if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \ 641 t->field, (cd), #field) < 0) \ 642 return -1 643 644 #define GPMC_SET_ONE(reg, st, end, field) \ 645 GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK) 646 647 /** 648 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME 649 * WAITMONITORINGTIME will be _at least_ as long as desired, i.e. 650 * read --> don't sample bus too early 651 * write --> data is longer on bus 652 * 653 * Formula: 654 * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns) 655 * / waitmonitoring_ticks) 656 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by 657 * div <= 0 check. 658 * 659 * @wait_monitoring: WAITMONITORINGTIME in ns. 660 * @return: -1 on failure to scale, else proper divider > 0. 661 */ 662 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring) 663 { 664 665 int div = gpmc_ns_to_ticks(wait_monitoring); 666 667 div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1; 668 div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX; 669 670 if (div > 4) 671 return -1; 672 if (div <= 0) 673 div = 1; 674 675 return div; 676 677 } 678 679 /** 680 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period. 681 * @sync_clk: GPMC_CLK period in ps. 682 * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK. 683 * Else, returns -1. 684 */ 685 int gpmc_calc_divider(unsigned int sync_clk) 686 { 687 int div = gpmc_ps_to_ticks(sync_clk); 688 689 if (div > 4) 690 return -1; 691 if (div <= 0) 692 div = 1; 693 694 return div; 695 } 696 697 /** 698 * gpmc_cs_set_timings - program timing parameters for Chip Select Region. 699 * @cs: Chip Select Region. 700 * @t: GPMC timing parameters. 701 * @s: GPMC timing settings. 702 * @return: 0 on success, -1 on error. 703 */ 704 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t, 705 const struct gpmc_settings *s) 706 { 707 int div; 708 u32 l; 709 710 div = gpmc_calc_divider(t->sync_clk); 711 if (div < 0) 712 return div; 713 714 /* 715 * See if we need to change the divider for waitmonitoringtime. 716 * 717 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for 718 * pure asynchronous accesses, i.e. both read and write asynchronous. 719 * However, only do so if WAITMONITORINGTIME is actually used, i.e. 720 * either WAITREADMONITORING or WAITWRITEMONITORING is set. 721 * 722 * This statement must not change div to scale async WAITMONITORINGTIME 723 * to protect mixed synchronous and asynchronous accesses. 724 * 725 * We raise an error later if WAITMONITORINGTIME does not fit. 726 */ 727 if (!s->sync_read && !s->sync_write && 728 (s->wait_on_read || s->wait_on_write) 729 ) { 730 731 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring); 732 if (div < 0) { 733 pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n", 734 __func__, 735 t->wait_monitoring 736 ); 737 return -1; 738 } 739 } 740 741 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); 742 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); 743 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); 744 745 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on); 746 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off); 747 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off); 748 if (gpmc_capability & GPMC_HAS_MUX_AAD) { 749 GPMC_SET_ONE(GPMC_CS_CONFIG3, 4, 6, adv_aad_mux_on); 750 GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off); 751 GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off); 752 } 753 754 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on); 755 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off); 756 if (gpmc_capability & GPMC_HAS_MUX_AAD) { 757 GPMC_SET_ONE(GPMC_CS_CONFIG4, 4, 6, oe_aad_mux_on); 758 GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off); 759 } 760 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on); 761 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off); 762 763 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle); 764 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle); 765 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access); 766 767 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); 768 769 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround); 770 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay); 771 772 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) 773 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); 774 if (gpmc_capability & GPMC_HAS_WR_ACCESS) 775 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); 776 777 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); 778 l &= ~0x03; 779 l |= (div - 1); 780 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); 781 782 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19, 783 GPMC_CONFIG1_WAITMONITORINGTIME_MAX, 784 wait_monitoring, GPMC_CD_CLK); 785 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26, 786 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX, 787 clk_activation, GPMC_CD_FCLK); 788 789 #ifdef CONFIG_OMAP_GPMC_DEBUG 790 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n", 791 cs, (div * gpmc_get_fclk_period()) / 1000, div); 792 #endif 793 794 gpmc_cs_bool_timings(cs, &t->bool_timings); 795 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings"); 796 797 return 0; 798 } 799 800 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size) 801 { 802 u32 l; 803 u32 mask; 804 805 /* 806 * Ensure that base address is aligned on a 807 * boundary equal to or greater than size. 808 */ 809 if (base & (size - 1)) 810 return -EINVAL; 811 812 base >>= GPMC_CHUNK_SHIFT; 813 mask = (1 << GPMC_SECTION_SHIFT) - size; 814 mask >>= GPMC_CHUNK_SHIFT; 815 mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET; 816 817 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 818 l &= ~GPMC_CONFIG7_MASK; 819 l |= base & GPMC_CONFIG7_BASEADDRESS_MASK; 820 l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK; 821 l |= GPMC_CONFIG7_CSVALID; 822 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 823 824 return 0; 825 } 826 827 static void gpmc_cs_enable_mem(int cs) 828 { 829 u32 l; 830 831 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 832 l |= GPMC_CONFIG7_CSVALID; 833 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 834 } 835 836 static void gpmc_cs_disable_mem(int cs) 837 { 838 u32 l; 839 840 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 841 l &= ~GPMC_CONFIG7_CSVALID; 842 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 843 } 844 845 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) 846 { 847 u32 l; 848 u32 mask; 849 850 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 851 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; 852 mask = (l >> 8) & 0x0f; 853 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); 854 } 855 856 static int gpmc_cs_mem_enabled(int cs) 857 { 858 u32 l; 859 860 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 861 return l & GPMC_CONFIG7_CSVALID; 862 } 863 864 static void gpmc_cs_set_reserved(int cs, int reserved) 865 { 866 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 867 868 gpmc->flags |= GPMC_CS_RESERVED; 869 } 870 871 static bool gpmc_cs_reserved(int cs) 872 { 873 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 874 875 return gpmc->flags & GPMC_CS_RESERVED; 876 } 877 878 static void gpmc_cs_set_name(int cs, const char *name) 879 { 880 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 881 882 gpmc->name = name; 883 } 884 885 static const char *gpmc_cs_get_name(int cs) 886 { 887 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 888 889 return gpmc->name; 890 } 891 892 static unsigned long gpmc_mem_align(unsigned long size) 893 { 894 int order; 895 896 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); 897 order = GPMC_CHUNK_SHIFT - 1; 898 do { 899 size >>= 1; 900 order++; 901 } while (size); 902 size = 1 << order; 903 return size; 904 } 905 906 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) 907 { 908 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 909 struct resource *res = &gpmc->mem; 910 int r; 911 912 size = gpmc_mem_align(size); 913 spin_lock(&gpmc_mem_lock); 914 res->start = base; 915 res->end = base + size - 1; 916 r = request_resource(&gpmc_mem_root, res); 917 spin_unlock(&gpmc_mem_lock); 918 919 return r; 920 } 921 922 static int gpmc_cs_delete_mem(int cs) 923 { 924 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 925 struct resource *res = &gpmc->mem; 926 int r; 927 928 spin_lock(&gpmc_mem_lock); 929 r = release_resource(res); 930 res->start = 0; 931 res->end = 0; 932 spin_unlock(&gpmc_mem_lock); 933 934 return r; 935 } 936 937 /** 938 * gpmc_cs_remap - remaps a chip-select physical base address 939 * @cs: chip-select to remap 940 * @base: physical base address to re-map chip-select to 941 * 942 * Re-maps a chip-select to a new physical base address specified by 943 * "base". Returns 0 on success and appropriate negative error code 944 * on failure. 945 */ 946 static int gpmc_cs_remap(int cs, u32 base) 947 { 948 int ret; 949 u32 old_base, size; 950 951 if (cs > gpmc_cs_num) { 952 pr_err("%s: requested chip-select is disabled\n", __func__); 953 return -ENODEV; 954 } 955 956 /* 957 * Make sure we ignore any device offsets from the GPMC partition 958 * allocated for the chip select and that the new base confirms 959 * to the GPMC 16MB minimum granularity. 960 */ 961 base &= ~(SZ_16M - 1); 962 963 gpmc_cs_get_memconf(cs, &old_base, &size); 964 if (base == old_base) 965 return 0; 966 967 ret = gpmc_cs_delete_mem(cs); 968 if (ret < 0) 969 return ret; 970 971 ret = gpmc_cs_insert_mem(cs, base, size); 972 if (ret < 0) 973 return ret; 974 975 ret = gpmc_cs_set_memconf(cs, base, size); 976 977 return ret; 978 } 979 980 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) 981 { 982 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 983 struct resource *res = &gpmc->mem; 984 int r = -1; 985 986 if (cs > gpmc_cs_num) { 987 pr_err("%s: requested chip-select is disabled\n", __func__); 988 return -ENODEV; 989 } 990 size = gpmc_mem_align(size); 991 if (size > (1 << GPMC_SECTION_SHIFT)) 992 return -ENOMEM; 993 994 spin_lock(&gpmc_mem_lock); 995 if (gpmc_cs_reserved(cs)) { 996 r = -EBUSY; 997 goto out; 998 } 999 if (gpmc_cs_mem_enabled(cs)) 1000 r = adjust_resource(res, res->start & ~(size - 1), size); 1001 if (r < 0) 1002 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, 1003 size, NULL, NULL); 1004 if (r < 0) 1005 goto out; 1006 1007 /* Disable CS while changing base address and size mask */ 1008 gpmc_cs_disable_mem(cs); 1009 1010 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res)); 1011 if (r < 0) { 1012 release_resource(res); 1013 goto out; 1014 } 1015 1016 /* Enable CS */ 1017 gpmc_cs_enable_mem(cs); 1018 *base = res->start; 1019 gpmc_cs_set_reserved(cs, 1); 1020 out: 1021 spin_unlock(&gpmc_mem_lock); 1022 return r; 1023 } 1024 EXPORT_SYMBOL(gpmc_cs_request); 1025 1026 void gpmc_cs_free(int cs) 1027 { 1028 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 1029 struct resource *res = &gpmc->mem; 1030 1031 spin_lock(&gpmc_mem_lock); 1032 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) { 1033 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); 1034 BUG(); 1035 spin_unlock(&gpmc_mem_lock); 1036 return; 1037 } 1038 gpmc_cs_disable_mem(cs); 1039 if (res->flags) 1040 release_resource(res); 1041 gpmc_cs_set_reserved(cs, 0); 1042 spin_unlock(&gpmc_mem_lock); 1043 } 1044 EXPORT_SYMBOL(gpmc_cs_free); 1045 1046 /** 1047 * gpmc_configure - write request to configure gpmc 1048 * @cmd: command type 1049 * @wval: value to write 1050 * @return status of the operation 1051 */ 1052 int gpmc_configure(int cmd, int wval) 1053 { 1054 u32 regval; 1055 1056 switch (cmd) { 1057 case GPMC_CONFIG_WP: 1058 regval = gpmc_read_reg(GPMC_CONFIG); 1059 if (wval) 1060 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ 1061 else 1062 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ 1063 gpmc_write_reg(GPMC_CONFIG, regval); 1064 break; 1065 1066 default: 1067 pr_err("%s: command not supported\n", __func__); 1068 return -EINVAL; 1069 } 1070 1071 return 0; 1072 } 1073 EXPORT_SYMBOL(gpmc_configure); 1074 1075 static bool gpmc_nand_writebuffer_empty(void) 1076 { 1077 if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS) 1078 return true; 1079 1080 return false; 1081 } 1082 1083 static struct gpmc_nand_ops nand_ops = { 1084 .nand_writebuffer_empty = gpmc_nand_writebuffer_empty, 1085 }; 1086 1087 /** 1088 * gpmc_omap_get_nand_ops - Get the GPMC NAND interface 1089 * @regs: the GPMC NAND register map exclusive for NAND use. 1090 * @cs: GPMC chip select number on which the NAND sits. The 1091 * register map returned will be specific to this chip select. 1092 * 1093 * Returns NULL on error e.g. invalid cs. 1094 */ 1095 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs) 1096 { 1097 int i; 1098 1099 if (cs >= gpmc_cs_num) 1100 return NULL; 1101 1102 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + 1103 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; 1104 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + 1105 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; 1106 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + 1107 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; 1108 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; 1109 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; 1110 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; 1111 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; 1112 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; 1113 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; 1114 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; 1115 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; 1116 1117 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) { 1118 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 + 1119 GPMC_BCH_SIZE * i; 1120 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 + 1121 GPMC_BCH_SIZE * i; 1122 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 + 1123 GPMC_BCH_SIZE * i; 1124 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 + 1125 GPMC_BCH_SIZE * i; 1126 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 + 1127 i * GPMC_BCH_SIZE; 1128 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 + 1129 i * GPMC_BCH_SIZE; 1130 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 + 1131 i * GPMC_BCH_SIZE; 1132 } 1133 1134 return &nand_ops; 1135 } 1136 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops); 1137 1138 static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t, 1139 struct gpmc_settings *s, 1140 int freq, int latency) 1141 { 1142 struct gpmc_device_timings dev_t; 1143 const int t_cer = 15; 1144 const int t_avdp = 12; 1145 const int t_cez = 20; /* max of t_cez, t_oez */ 1146 const int t_wpl = 40; 1147 const int t_wph = 30; 1148 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; 1149 1150 switch (freq) { 1151 case 104: 1152 min_gpmc_clk_period = 9600; /* 104 MHz */ 1153 t_ces = 3; 1154 t_avds = 4; 1155 t_avdh = 2; 1156 t_ach = 3; 1157 t_aavdh = 6; 1158 t_rdyo = 6; 1159 break; 1160 case 83: 1161 min_gpmc_clk_period = 12000; /* 83 MHz */ 1162 t_ces = 5; 1163 t_avds = 4; 1164 t_avdh = 2; 1165 t_ach = 6; 1166 t_aavdh = 6; 1167 t_rdyo = 9; 1168 break; 1169 case 66: 1170 min_gpmc_clk_period = 15000; /* 66 MHz */ 1171 t_ces = 6; 1172 t_avds = 5; 1173 t_avdh = 2; 1174 t_ach = 6; 1175 t_aavdh = 6; 1176 t_rdyo = 11; 1177 break; 1178 default: 1179 min_gpmc_clk_period = 18500; /* 54 MHz */ 1180 t_ces = 7; 1181 t_avds = 7; 1182 t_avdh = 7; 1183 t_ach = 9; 1184 t_aavdh = 7; 1185 t_rdyo = 15; 1186 break; 1187 } 1188 1189 /* Set synchronous read timings */ 1190 memset(&dev_t, 0, sizeof(dev_t)); 1191 1192 if (!s->sync_write) { 1193 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000; 1194 dev_t.t_wpl = t_wpl * 1000; 1195 dev_t.t_wph = t_wph * 1000; 1196 dev_t.t_aavdh = t_aavdh * 1000; 1197 } 1198 dev_t.ce_xdelay = true; 1199 dev_t.avd_xdelay = true; 1200 dev_t.oe_xdelay = true; 1201 dev_t.we_xdelay = true; 1202 dev_t.clk = min_gpmc_clk_period; 1203 dev_t.t_bacc = dev_t.clk; 1204 dev_t.t_ces = t_ces * 1000; 1205 dev_t.t_avds = t_avds * 1000; 1206 dev_t.t_avdh = t_avdh * 1000; 1207 dev_t.t_ach = t_ach * 1000; 1208 dev_t.cyc_iaa = (latency + 1); 1209 dev_t.t_cez_r = t_cez * 1000; 1210 dev_t.t_cez_w = dev_t.t_cez_r; 1211 dev_t.cyc_aavdh_oe = 1; 1212 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period; 1213 1214 gpmc_calc_timings(t, s, &dev_t); 1215 } 1216 1217 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq, 1218 int latency, 1219 struct gpmc_onenand_info *info) 1220 { 1221 int ret; 1222 struct gpmc_timings gpmc_t; 1223 struct gpmc_settings gpmc_s; 1224 1225 gpmc_read_settings_dt(dev->of_node, &gpmc_s); 1226 1227 info->sync_read = gpmc_s.sync_read; 1228 info->sync_write = gpmc_s.sync_write; 1229 info->burst_len = gpmc_s.burst_len; 1230 1231 if (!gpmc_s.sync_read && !gpmc_s.sync_write) 1232 return 0; 1233 1234 gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency); 1235 1236 ret = gpmc_cs_program_settings(cs, &gpmc_s); 1237 if (ret < 0) 1238 return ret; 1239 1240 return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s); 1241 } 1242 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings); 1243 1244 int gpmc_get_client_irq(unsigned irq_config) 1245 { 1246 if (!gpmc_irq_domain) { 1247 pr_warn("%s called before GPMC IRQ domain available\n", 1248 __func__); 1249 return 0; 1250 } 1251 1252 /* we restrict this to NAND IRQs only */ 1253 if (irq_config >= GPMC_NR_NAND_IRQS) 1254 return 0; 1255 1256 return irq_create_mapping(gpmc_irq_domain, irq_config); 1257 } 1258 1259 static int gpmc_irq_endis(unsigned long hwirq, bool endis) 1260 { 1261 u32 regval; 1262 1263 /* bits GPMC_NR_NAND_IRQS to 8 are reserved */ 1264 if (hwirq >= GPMC_NR_NAND_IRQS) 1265 hwirq += 8 - GPMC_NR_NAND_IRQS; 1266 1267 regval = gpmc_read_reg(GPMC_IRQENABLE); 1268 if (endis) 1269 regval |= BIT(hwirq); 1270 else 1271 regval &= ~BIT(hwirq); 1272 gpmc_write_reg(GPMC_IRQENABLE, regval); 1273 1274 return 0; 1275 } 1276 1277 static void gpmc_irq_disable(struct irq_data *p) 1278 { 1279 gpmc_irq_endis(p->hwirq, false); 1280 } 1281 1282 static void gpmc_irq_enable(struct irq_data *p) 1283 { 1284 gpmc_irq_endis(p->hwirq, true); 1285 } 1286 1287 static void gpmc_irq_mask(struct irq_data *d) 1288 { 1289 gpmc_irq_endis(d->hwirq, false); 1290 } 1291 1292 static void gpmc_irq_unmask(struct irq_data *d) 1293 { 1294 gpmc_irq_endis(d->hwirq, true); 1295 } 1296 1297 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge) 1298 { 1299 u32 regval; 1300 1301 /* NAND IRQs polarity is not configurable */ 1302 if (hwirq < GPMC_NR_NAND_IRQS) 1303 return; 1304 1305 /* WAITPIN starts at BIT 8 */ 1306 hwirq += 8 - GPMC_NR_NAND_IRQS; 1307 1308 regval = gpmc_read_reg(GPMC_CONFIG); 1309 if (rising_edge) 1310 regval &= ~BIT(hwirq); 1311 else 1312 regval |= BIT(hwirq); 1313 1314 gpmc_write_reg(GPMC_CONFIG, regval); 1315 } 1316 1317 static void gpmc_irq_ack(struct irq_data *d) 1318 { 1319 unsigned int hwirq = d->hwirq; 1320 1321 /* skip reserved bits */ 1322 if (hwirq >= GPMC_NR_NAND_IRQS) 1323 hwirq += 8 - GPMC_NR_NAND_IRQS; 1324 1325 /* Setting bit to 1 clears (or Acks) the interrupt */ 1326 gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq)); 1327 } 1328 1329 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger) 1330 { 1331 /* can't set type for NAND IRQs */ 1332 if (d->hwirq < GPMC_NR_NAND_IRQS) 1333 return -EINVAL; 1334 1335 /* We can support either rising or falling edge at a time */ 1336 if (trigger == IRQ_TYPE_EDGE_FALLING) 1337 gpmc_irq_edge_config(d->hwirq, false); 1338 else if (trigger == IRQ_TYPE_EDGE_RISING) 1339 gpmc_irq_edge_config(d->hwirq, true); 1340 else 1341 return -EINVAL; 1342 1343 return 0; 1344 } 1345 1346 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq, 1347 irq_hw_number_t hw) 1348 { 1349 struct gpmc_device *gpmc = d->host_data; 1350 1351 irq_set_chip_data(virq, gpmc); 1352 if (hw < GPMC_NR_NAND_IRQS) { 1353 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN); 1354 irq_set_chip_and_handler(virq, &gpmc->irq_chip, 1355 handle_simple_irq); 1356 } else { 1357 irq_set_chip_and_handler(virq, &gpmc->irq_chip, 1358 handle_edge_irq); 1359 } 1360 1361 return 0; 1362 } 1363 1364 static const struct irq_domain_ops gpmc_irq_domain_ops = { 1365 .map = gpmc_irq_map, 1366 .xlate = irq_domain_xlate_twocell, 1367 }; 1368 1369 static irqreturn_t gpmc_handle_irq(int irq, void *data) 1370 { 1371 int hwirq, virq; 1372 u32 regval, regvalx; 1373 struct gpmc_device *gpmc = data; 1374 1375 regval = gpmc_read_reg(GPMC_IRQSTATUS); 1376 regvalx = regval; 1377 1378 if (!regval) 1379 return IRQ_NONE; 1380 1381 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) { 1382 /* skip reserved status bits */ 1383 if (hwirq == GPMC_NR_NAND_IRQS) 1384 regvalx >>= 8 - GPMC_NR_NAND_IRQS; 1385 1386 if (regvalx & BIT(hwirq)) { 1387 virq = irq_find_mapping(gpmc_irq_domain, hwirq); 1388 if (!virq) { 1389 dev_warn(gpmc->dev, 1390 "spurious irq detected hwirq %d, virq %d\n", 1391 hwirq, virq); 1392 } 1393 1394 generic_handle_irq(virq); 1395 } 1396 } 1397 1398 gpmc_write_reg(GPMC_IRQSTATUS, regval); 1399 1400 return IRQ_HANDLED; 1401 } 1402 1403 static int gpmc_setup_irq(struct gpmc_device *gpmc) 1404 { 1405 u32 regval; 1406 int rc; 1407 1408 /* Disable interrupts */ 1409 gpmc_write_reg(GPMC_IRQENABLE, 0); 1410 1411 /* clear interrupts */ 1412 regval = gpmc_read_reg(GPMC_IRQSTATUS); 1413 gpmc_write_reg(GPMC_IRQSTATUS, regval); 1414 1415 gpmc->irq_chip.name = "gpmc"; 1416 gpmc->irq_chip.irq_enable = gpmc_irq_enable; 1417 gpmc->irq_chip.irq_disable = gpmc_irq_disable; 1418 gpmc->irq_chip.irq_ack = gpmc_irq_ack; 1419 gpmc->irq_chip.irq_mask = gpmc_irq_mask; 1420 gpmc->irq_chip.irq_unmask = gpmc_irq_unmask; 1421 gpmc->irq_chip.irq_set_type = gpmc_irq_set_type; 1422 1423 gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node, 1424 gpmc->nirqs, 1425 &gpmc_irq_domain_ops, 1426 gpmc); 1427 if (!gpmc_irq_domain) { 1428 dev_err(gpmc->dev, "IRQ domain add failed\n"); 1429 return -ENODEV; 1430 } 1431 1432 rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc); 1433 if (rc) { 1434 dev_err(gpmc->dev, "failed to request irq %d: %d\n", 1435 gpmc->irq, rc); 1436 irq_domain_remove(gpmc_irq_domain); 1437 gpmc_irq_domain = NULL; 1438 } 1439 1440 return rc; 1441 } 1442 1443 static int gpmc_free_irq(struct gpmc_device *gpmc) 1444 { 1445 int hwirq; 1446 1447 free_irq(gpmc->irq, gpmc); 1448 1449 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) 1450 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq)); 1451 1452 irq_domain_remove(gpmc_irq_domain); 1453 gpmc_irq_domain = NULL; 1454 1455 return 0; 1456 } 1457 1458 static void gpmc_mem_exit(void) 1459 { 1460 int cs; 1461 1462 for (cs = 0; cs < gpmc_cs_num; cs++) { 1463 if (!gpmc_cs_mem_enabled(cs)) 1464 continue; 1465 gpmc_cs_delete_mem(cs); 1466 } 1467 1468 } 1469 1470 static void gpmc_mem_init(void) 1471 { 1472 int cs; 1473 1474 gpmc_mem_root.start = GPMC_MEM_START; 1475 gpmc_mem_root.end = GPMC_MEM_END; 1476 1477 /* Reserve all regions that has been set up by bootloader */ 1478 for (cs = 0; cs < gpmc_cs_num; cs++) { 1479 u32 base, size; 1480 1481 if (!gpmc_cs_mem_enabled(cs)) 1482 continue; 1483 gpmc_cs_get_memconf(cs, &base, &size); 1484 if (gpmc_cs_insert_mem(cs, base, size)) { 1485 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n", 1486 __func__, cs, base, base + size); 1487 gpmc_cs_disable_mem(cs); 1488 } 1489 } 1490 } 1491 1492 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk) 1493 { 1494 u32 temp; 1495 int div; 1496 1497 div = gpmc_calc_divider(sync_clk); 1498 temp = gpmc_ps_to_ticks(time_ps); 1499 temp = (temp + div - 1) / div; 1500 return gpmc_ticks_to_ps(temp * div); 1501 } 1502 1503 /* XXX: can the cycles be avoided ? */ 1504 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, 1505 struct gpmc_device_timings *dev_t, 1506 bool mux) 1507 { 1508 u32 temp; 1509 1510 /* adv_rd_off */ 1511 temp = dev_t->t_avdp_r; 1512 /* XXX: mux check required ? */ 1513 if (mux) { 1514 /* XXX: t_avdp not to be required for sync, only added for tusb 1515 * this indirectly necessitates requirement of t_avdp_r and 1516 * t_avdp_w instead of having a single t_avdp 1517 */ 1518 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh); 1519 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 1520 } 1521 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); 1522 1523 /* oe_on */ 1524 temp = dev_t->t_oeasu; /* XXX: remove this ? */ 1525 if (mux) { 1526 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach); 1527 temp = max_t(u32, temp, gpmc_t->adv_rd_off + 1528 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe)); 1529 } 1530 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); 1531 1532 /* access */ 1533 /* XXX: any scope for improvement ?, by combining oe_on 1534 * and clk_activation, need to check whether 1535 * access = clk_activation + round to sync clk ? 1536 */ 1537 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk); 1538 temp += gpmc_t->clk_activation; 1539 if (dev_t->cyc_oe) 1540 temp = max_t(u32, temp, gpmc_t->oe_on + 1541 gpmc_ticks_to_ps(dev_t->cyc_oe)); 1542 gpmc_t->access = gpmc_round_ps_to_ticks(temp); 1543 1544 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); 1545 gpmc_t->cs_rd_off = gpmc_t->oe_off; 1546 1547 /* rd_cycle */ 1548 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez); 1549 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) + 1550 gpmc_t->access; 1551 /* XXX: barter t_ce_rdyz with t_cez_r ? */ 1552 if (dev_t->t_ce_rdyz) 1553 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz); 1554 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); 1555 1556 return 0; 1557 } 1558 1559 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, 1560 struct gpmc_device_timings *dev_t, 1561 bool mux) 1562 { 1563 u32 temp; 1564 1565 /* adv_wr_off */ 1566 temp = dev_t->t_avdp_w; 1567 if (mux) { 1568 temp = max_t(u32, temp, 1569 gpmc_t->clk_activation + dev_t->t_avdh); 1570 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 1571 } 1572 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); 1573 1574 /* wr_data_mux_bus */ 1575 temp = max_t(u32, dev_t->t_weasu, 1576 gpmc_t->clk_activation + dev_t->t_rdyo); 1577 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?, 1578 * and in that case remember to handle we_on properly 1579 */ 1580 if (mux) { 1581 temp = max_t(u32, temp, 1582 gpmc_t->adv_wr_off + dev_t->t_aavdh); 1583 temp = max_t(u32, temp, gpmc_t->adv_wr_off + 1584 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); 1585 } 1586 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); 1587 1588 /* we_on */ 1589 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) 1590 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); 1591 else 1592 gpmc_t->we_on = gpmc_t->wr_data_mux_bus; 1593 1594 /* wr_access */ 1595 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */ 1596 gpmc_t->wr_access = gpmc_t->access; 1597 1598 /* we_off */ 1599 temp = gpmc_t->we_on + dev_t->t_wpl; 1600 temp = max_t(u32, temp, 1601 gpmc_t->wr_access + gpmc_ticks_to_ps(1)); 1602 temp = max_t(u32, temp, 1603 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl)); 1604 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); 1605 1606 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + 1607 dev_t->t_wph); 1608 1609 /* wr_cycle */ 1610 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk); 1611 temp += gpmc_t->wr_access; 1612 /* XXX: barter t_ce_rdyz with t_cez_w ? */ 1613 if (dev_t->t_ce_rdyz) 1614 temp = max_t(u32, temp, 1615 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz); 1616 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); 1617 1618 return 0; 1619 } 1620 1621 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, 1622 struct gpmc_device_timings *dev_t, 1623 bool mux) 1624 { 1625 u32 temp; 1626 1627 /* adv_rd_off */ 1628 temp = dev_t->t_avdp_r; 1629 if (mux) 1630 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 1631 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); 1632 1633 /* oe_on */ 1634 temp = dev_t->t_oeasu; 1635 if (mux) 1636 temp = max_t(u32, temp, 1637 gpmc_t->adv_rd_off + dev_t->t_aavdh); 1638 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); 1639 1640 /* access */ 1641 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */ 1642 gpmc_t->oe_on + dev_t->t_oe); 1643 temp = max_t(u32, temp, 1644 gpmc_t->cs_on + dev_t->t_ce); 1645 temp = max_t(u32, temp, 1646 gpmc_t->adv_on + dev_t->t_aa); 1647 gpmc_t->access = gpmc_round_ps_to_ticks(temp); 1648 1649 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); 1650 gpmc_t->cs_rd_off = gpmc_t->oe_off; 1651 1652 /* rd_cycle */ 1653 temp = max_t(u32, dev_t->t_rd_cycle, 1654 gpmc_t->cs_rd_off + dev_t->t_cez_r); 1655 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez); 1656 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); 1657 1658 return 0; 1659 } 1660 1661 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t, 1662 struct gpmc_device_timings *dev_t, 1663 bool mux) 1664 { 1665 u32 temp; 1666 1667 /* adv_wr_off */ 1668 temp = dev_t->t_avdp_w; 1669 if (mux) 1670 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 1671 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); 1672 1673 /* wr_data_mux_bus */ 1674 temp = dev_t->t_weasu; 1675 if (mux) { 1676 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh); 1677 temp = max_t(u32, temp, gpmc_t->adv_wr_off + 1678 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); 1679 } 1680 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); 1681 1682 /* we_on */ 1683 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) 1684 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); 1685 else 1686 gpmc_t->we_on = gpmc_t->wr_data_mux_bus; 1687 1688 /* we_off */ 1689 temp = gpmc_t->we_on + dev_t->t_wpl; 1690 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); 1691 1692 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + 1693 dev_t->t_wph); 1694 1695 /* wr_cycle */ 1696 temp = max_t(u32, dev_t->t_wr_cycle, 1697 gpmc_t->cs_wr_off + dev_t->t_cez_w); 1698 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); 1699 1700 return 0; 1701 } 1702 1703 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t, 1704 struct gpmc_device_timings *dev_t) 1705 { 1706 u32 temp; 1707 1708 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) * 1709 gpmc_get_fclk_period(); 1710 1711 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk( 1712 dev_t->t_bacc, 1713 gpmc_t->sync_clk); 1714 1715 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds); 1716 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp); 1717 1718 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1) 1719 return 0; 1720 1721 if (dev_t->ce_xdelay) 1722 gpmc_t->bool_timings.cs_extra_delay = true; 1723 if (dev_t->avd_xdelay) 1724 gpmc_t->bool_timings.adv_extra_delay = true; 1725 if (dev_t->oe_xdelay) 1726 gpmc_t->bool_timings.oe_extra_delay = true; 1727 if (dev_t->we_xdelay) 1728 gpmc_t->bool_timings.we_extra_delay = true; 1729 1730 return 0; 1731 } 1732 1733 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t, 1734 struct gpmc_device_timings *dev_t, 1735 bool sync) 1736 { 1737 u32 temp; 1738 1739 /* cs_on */ 1740 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu); 1741 1742 /* adv_on */ 1743 temp = dev_t->t_avdasu; 1744 if (dev_t->t_ce_avd) 1745 temp = max_t(u32, temp, 1746 gpmc_t->cs_on + dev_t->t_ce_avd); 1747 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp); 1748 1749 if (sync) 1750 gpmc_calc_sync_common_timings(gpmc_t, dev_t); 1751 1752 return 0; 1753 } 1754 1755 /* TODO: remove this function once all peripherals are confirmed to 1756 * work with generic timing. Simultaneously gpmc_cs_set_timings() 1757 * has to be modified to handle timings in ps instead of ns 1758 */ 1759 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t) 1760 { 1761 t->cs_on /= 1000; 1762 t->cs_rd_off /= 1000; 1763 t->cs_wr_off /= 1000; 1764 t->adv_on /= 1000; 1765 t->adv_rd_off /= 1000; 1766 t->adv_wr_off /= 1000; 1767 t->we_on /= 1000; 1768 t->we_off /= 1000; 1769 t->oe_on /= 1000; 1770 t->oe_off /= 1000; 1771 t->page_burst_access /= 1000; 1772 t->access /= 1000; 1773 t->rd_cycle /= 1000; 1774 t->wr_cycle /= 1000; 1775 t->bus_turnaround /= 1000; 1776 t->cycle2cycle_delay /= 1000; 1777 t->wait_monitoring /= 1000; 1778 t->clk_activation /= 1000; 1779 t->wr_access /= 1000; 1780 t->wr_data_mux_bus /= 1000; 1781 } 1782 1783 int gpmc_calc_timings(struct gpmc_timings *gpmc_t, 1784 struct gpmc_settings *gpmc_s, 1785 struct gpmc_device_timings *dev_t) 1786 { 1787 bool mux = false, sync = false; 1788 1789 if (gpmc_s) { 1790 mux = gpmc_s->mux_add_data ? true : false; 1791 sync = (gpmc_s->sync_read || gpmc_s->sync_write); 1792 } 1793 1794 memset(gpmc_t, 0, sizeof(*gpmc_t)); 1795 1796 gpmc_calc_common_timings(gpmc_t, dev_t, sync); 1797 1798 if (gpmc_s && gpmc_s->sync_read) 1799 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux); 1800 else 1801 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux); 1802 1803 if (gpmc_s && gpmc_s->sync_write) 1804 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux); 1805 else 1806 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux); 1807 1808 /* TODO: remove, see function definition */ 1809 gpmc_convert_ps_to_ns(gpmc_t); 1810 1811 return 0; 1812 } 1813 1814 /** 1815 * gpmc_cs_program_settings - programs non-timing related settings 1816 * @cs: GPMC chip-select to program 1817 * @p: pointer to GPMC settings structure 1818 * 1819 * Programs non-timing related settings for a GPMC chip-select, such as 1820 * bus-width, burst configuration, etc. Function should be called once 1821 * for each chip-select that is being used and must be called before 1822 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1 1823 * register will be initialised to zero by this function. Returns 0 on 1824 * success and appropriate negative error code on failure. 1825 */ 1826 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) 1827 { 1828 u32 config1; 1829 1830 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) { 1831 pr_err("%s: invalid width %d!", __func__, p->device_width); 1832 return -EINVAL; 1833 } 1834 1835 /* Address-data multiplexing not supported for NAND devices */ 1836 if (p->device_nand && p->mux_add_data) { 1837 pr_err("%s: invalid configuration!\n", __func__); 1838 return -EINVAL; 1839 } 1840 1841 if ((p->mux_add_data > GPMC_MUX_AD) || 1842 ((p->mux_add_data == GPMC_MUX_AAD) && 1843 !(gpmc_capability & GPMC_HAS_MUX_AAD))) { 1844 pr_err("%s: invalid multiplex configuration!\n", __func__); 1845 return -EINVAL; 1846 } 1847 1848 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */ 1849 if (p->burst_read || p->burst_write) { 1850 switch (p->burst_len) { 1851 case GPMC_BURST_4: 1852 case GPMC_BURST_8: 1853 case GPMC_BURST_16: 1854 break; 1855 default: 1856 pr_err("%s: invalid page/burst-length (%d)\n", 1857 __func__, p->burst_len); 1858 return -EINVAL; 1859 } 1860 } 1861 1862 if (p->wait_pin > gpmc_nr_waitpins) { 1863 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin); 1864 return -EINVAL; 1865 } 1866 1867 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1)); 1868 1869 if (p->sync_read) 1870 config1 |= GPMC_CONFIG1_READTYPE_SYNC; 1871 if (p->sync_write) 1872 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC; 1873 if (p->wait_on_read) 1874 config1 |= GPMC_CONFIG1_WAIT_READ_MON; 1875 if (p->wait_on_write) 1876 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON; 1877 if (p->wait_on_read || p->wait_on_write) 1878 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin); 1879 if (p->device_nand) 1880 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND); 1881 if (p->mux_add_data) 1882 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data); 1883 if (p->burst_read) 1884 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP; 1885 if (p->burst_write) 1886 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP; 1887 if (p->burst_read || p->burst_write) { 1888 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3); 1889 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0; 1890 } 1891 1892 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1); 1893 1894 return 0; 1895 } 1896 1897 #ifdef CONFIG_OF 1898 static const struct of_device_id gpmc_dt_ids[] = { 1899 { .compatible = "ti,omap2420-gpmc" }, 1900 { .compatible = "ti,omap2430-gpmc" }, 1901 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */ 1902 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */ 1903 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */ 1904 { } 1905 }; 1906 1907 /** 1908 * gpmc_read_settings_dt - read gpmc settings from device-tree 1909 * @np: pointer to device-tree node for a gpmc child device 1910 * @p: pointer to gpmc settings structure 1911 * 1912 * Reads the GPMC settings for a GPMC child device from device-tree and 1913 * stores them in the GPMC settings structure passed. The GPMC settings 1914 * structure is initialised to zero by this function and so any 1915 * previously stored settings will be cleared. 1916 */ 1917 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) 1918 { 1919 memset(p, 0, sizeof(struct gpmc_settings)); 1920 1921 p->sync_read = of_property_read_bool(np, "gpmc,sync-read"); 1922 p->sync_write = of_property_read_bool(np, "gpmc,sync-write"); 1923 of_property_read_u32(np, "gpmc,device-width", &p->device_width); 1924 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); 1925 1926 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) { 1927 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap"); 1928 p->burst_read = of_property_read_bool(np, "gpmc,burst-read"); 1929 p->burst_write = of_property_read_bool(np, "gpmc,burst-write"); 1930 if (!p->burst_read && !p->burst_write) 1931 pr_warn("%s: page/burst-length set but not used!\n", 1932 __func__); 1933 } 1934 1935 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) { 1936 p->wait_on_read = of_property_read_bool(np, 1937 "gpmc,wait-on-read"); 1938 p->wait_on_write = of_property_read_bool(np, 1939 "gpmc,wait-on-write"); 1940 if (!p->wait_on_read && !p->wait_on_write) 1941 pr_debug("%s: rd/wr wait monitoring not enabled!\n", 1942 __func__); 1943 } 1944 } 1945 1946 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np, 1947 struct gpmc_timings *gpmc_t) 1948 { 1949 struct gpmc_bool_timings *p; 1950 1951 if (!np || !gpmc_t) 1952 return; 1953 1954 memset(gpmc_t, 0, sizeof(*gpmc_t)); 1955 1956 /* minimum clock period for syncronous mode */ 1957 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk); 1958 1959 /* chip select timtings */ 1960 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on); 1961 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off); 1962 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off); 1963 1964 /* ADV signal timings */ 1965 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on); 1966 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off); 1967 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off); 1968 of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns", 1969 &gpmc_t->adv_aad_mux_on); 1970 of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns", 1971 &gpmc_t->adv_aad_mux_rd_off); 1972 of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns", 1973 &gpmc_t->adv_aad_mux_wr_off); 1974 1975 /* WE signal timings */ 1976 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on); 1977 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off); 1978 1979 /* OE signal timings */ 1980 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on); 1981 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off); 1982 of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns", 1983 &gpmc_t->oe_aad_mux_on); 1984 of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns", 1985 &gpmc_t->oe_aad_mux_off); 1986 1987 /* access and cycle timings */ 1988 of_property_read_u32(np, "gpmc,page-burst-access-ns", 1989 &gpmc_t->page_burst_access); 1990 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access); 1991 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle); 1992 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle); 1993 of_property_read_u32(np, "gpmc,bus-turnaround-ns", 1994 &gpmc_t->bus_turnaround); 1995 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns", 1996 &gpmc_t->cycle2cycle_delay); 1997 of_property_read_u32(np, "gpmc,wait-monitoring-ns", 1998 &gpmc_t->wait_monitoring); 1999 of_property_read_u32(np, "gpmc,clk-activation-ns", 2000 &gpmc_t->clk_activation); 2001 2002 /* only applicable to OMAP3+ */ 2003 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access); 2004 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns", 2005 &gpmc_t->wr_data_mux_bus); 2006 2007 /* bool timing parameters */ 2008 p = &gpmc_t->bool_timings; 2009 2010 p->cycle2cyclediffcsen = 2011 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen"); 2012 p->cycle2cyclesamecsen = 2013 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen"); 2014 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay"); 2015 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay"); 2016 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay"); 2017 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay"); 2018 p->time_para_granularity = 2019 of_property_read_bool(np, "gpmc,time-para-granularity"); 2020 } 2021 2022 /** 2023 * gpmc_probe_generic_child - configures the gpmc for a child device 2024 * @pdev: pointer to gpmc platform device 2025 * @child: pointer to device-tree node for child device 2026 * 2027 * Allocates and configures a GPMC chip-select for a child device. 2028 * Returns 0 on success and appropriate negative error code on failure. 2029 */ 2030 static int gpmc_probe_generic_child(struct platform_device *pdev, 2031 struct device_node *child) 2032 { 2033 struct gpmc_settings gpmc_s; 2034 struct gpmc_timings gpmc_t; 2035 struct resource res; 2036 unsigned long base; 2037 const char *name; 2038 int ret, cs; 2039 u32 val; 2040 struct gpio_desc *waitpin_desc = NULL; 2041 struct gpmc_device *gpmc = platform_get_drvdata(pdev); 2042 2043 if (of_property_read_u32(child, "reg", &cs) < 0) { 2044 dev_err(&pdev->dev, "%pOF has no 'reg' property\n", 2045 child); 2046 return -ENODEV; 2047 } 2048 2049 if (of_address_to_resource(child, 0, &res) < 0) { 2050 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n", 2051 child); 2052 return -ENODEV; 2053 } 2054 2055 /* 2056 * Check if we have multiple instances of the same device 2057 * on a single chip select. If so, use the already initialized 2058 * timings. 2059 */ 2060 name = gpmc_cs_get_name(cs); 2061 if (name && of_node_name_eq(child, name)) 2062 goto no_timings; 2063 2064 ret = gpmc_cs_request(cs, resource_size(&res), &base); 2065 if (ret < 0) { 2066 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs); 2067 return ret; 2068 } 2069 gpmc_cs_set_name(cs, child->full_name); 2070 2071 gpmc_read_settings_dt(child, &gpmc_s); 2072 gpmc_read_timings_dt(child, &gpmc_t); 2073 2074 /* 2075 * For some GPMC devices we still need to rely on the bootloader 2076 * timings because the devices can be connected via FPGA. 2077 * REVISIT: Add timing support from slls644g.pdf. 2078 */ 2079 if (!gpmc_t.cs_rd_off) { 2080 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n", 2081 cs); 2082 gpmc_cs_show_timings(cs, 2083 "please add GPMC bootloader timings to .dts"); 2084 goto no_timings; 2085 } 2086 2087 /* CS must be disabled while making changes to gpmc configuration */ 2088 gpmc_cs_disable_mem(cs); 2089 2090 /* 2091 * FIXME: gpmc_cs_request() will map the CS to an arbitary 2092 * location in the gpmc address space. When booting with 2093 * device-tree we want the NOR flash to be mapped to the 2094 * location specified in the device-tree blob. So remap the 2095 * CS to this location. Once DT migration is complete should 2096 * just make gpmc_cs_request() map a specific address. 2097 */ 2098 ret = gpmc_cs_remap(cs, res.start); 2099 if (ret < 0) { 2100 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n", 2101 cs, &res.start); 2102 if (res.start < GPMC_MEM_START) { 2103 dev_info(&pdev->dev, 2104 "GPMC CS %d start cannot be lesser than 0x%x\n", 2105 cs, GPMC_MEM_START); 2106 } else if (res.end > GPMC_MEM_END) { 2107 dev_info(&pdev->dev, 2108 "GPMC CS %d end cannot be greater than 0x%x\n", 2109 cs, GPMC_MEM_END); 2110 } 2111 goto err; 2112 } 2113 2114 if (of_node_name_eq(child, "nand")) { 2115 /* Warn about older DT blobs with no compatible property */ 2116 if (!of_property_read_bool(child, "compatible")) { 2117 dev_warn(&pdev->dev, 2118 "Incompatible NAND node: missing compatible"); 2119 ret = -EINVAL; 2120 goto err; 2121 } 2122 } 2123 2124 if (of_node_name_eq(child, "onenand")) { 2125 /* Warn about older DT blobs with no compatible property */ 2126 if (!of_property_read_bool(child, "compatible")) { 2127 dev_warn(&pdev->dev, 2128 "Incompatible OneNAND node: missing compatible"); 2129 ret = -EINVAL; 2130 goto err; 2131 } 2132 } 2133 2134 if (of_device_is_compatible(child, "ti,omap2-nand")) { 2135 /* NAND specific setup */ 2136 val = 8; 2137 of_property_read_u32(child, "nand-bus-width", &val); 2138 switch (val) { 2139 case 8: 2140 gpmc_s.device_width = GPMC_DEVWIDTH_8BIT; 2141 break; 2142 case 16: 2143 gpmc_s.device_width = GPMC_DEVWIDTH_16BIT; 2144 break; 2145 default: 2146 dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n", 2147 child); 2148 ret = -EINVAL; 2149 goto err; 2150 } 2151 2152 /* disable write protect */ 2153 gpmc_configure(GPMC_CONFIG_WP, 0); 2154 gpmc_s.device_nand = true; 2155 } else { 2156 ret = of_property_read_u32(child, "bank-width", 2157 &gpmc_s.device_width); 2158 if (ret < 0 && !gpmc_s.device_width) { 2159 dev_err(&pdev->dev, 2160 "%pOF has no 'gpmc,device-width' property\n", 2161 child); 2162 goto err; 2163 } 2164 } 2165 2166 /* Reserve wait pin if it is required and valid */ 2167 if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) { 2168 unsigned int wait_pin = gpmc_s.wait_pin; 2169 2170 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip, 2171 wait_pin, "WAITPIN", 2172 0); 2173 if (IS_ERR(waitpin_desc)) { 2174 dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin); 2175 ret = PTR_ERR(waitpin_desc); 2176 goto err; 2177 } 2178 } 2179 2180 gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings"); 2181 2182 ret = gpmc_cs_program_settings(cs, &gpmc_s); 2183 if (ret < 0) 2184 goto err_cs; 2185 2186 ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s); 2187 if (ret) { 2188 dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n", 2189 child); 2190 goto err_cs; 2191 } 2192 2193 /* Clear limited address i.e. enable A26-A11 */ 2194 val = gpmc_read_reg(GPMC_CONFIG); 2195 val &= ~GPMC_CONFIG_LIMITEDADDRESS; 2196 gpmc_write_reg(GPMC_CONFIG, val); 2197 2198 /* Enable CS region */ 2199 gpmc_cs_enable_mem(cs); 2200 2201 no_timings: 2202 2203 /* create platform device, NULL on error or when disabled */ 2204 if (!of_platform_device_create(child, NULL, &pdev->dev)) 2205 goto err_child_fail; 2206 2207 /* is child a common bus? */ 2208 if (of_match_node(of_default_bus_match_table, child)) 2209 /* create children and other common bus children */ 2210 if (of_platform_default_populate(child, NULL, &pdev->dev)) 2211 goto err_child_fail; 2212 2213 return 0; 2214 2215 err_child_fail: 2216 2217 dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child); 2218 ret = -ENODEV; 2219 2220 err_cs: 2221 gpiochip_free_own_desc(waitpin_desc); 2222 err: 2223 gpmc_cs_free(cs); 2224 2225 return ret; 2226 } 2227 2228 static int gpmc_probe_dt(struct platform_device *pdev) 2229 { 2230 int ret; 2231 const struct of_device_id *of_id = 2232 of_match_device(gpmc_dt_ids, &pdev->dev); 2233 2234 if (!of_id) 2235 return 0; 2236 2237 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs", 2238 &gpmc_cs_num); 2239 if (ret < 0) { 2240 pr_err("%s: number of chip-selects not defined\n", __func__); 2241 return ret; 2242 } else if (gpmc_cs_num < 1) { 2243 pr_err("%s: all chip-selects are disabled\n", __func__); 2244 return -EINVAL; 2245 } else if (gpmc_cs_num > GPMC_CS_NUM) { 2246 pr_err("%s: number of supported chip-selects cannot be > %d\n", 2247 __func__, GPMC_CS_NUM); 2248 return -EINVAL; 2249 } 2250 2251 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", 2252 &gpmc_nr_waitpins); 2253 if (ret < 0) { 2254 pr_err("%s: number of wait pins not found!\n", __func__); 2255 return ret; 2256 } 2257 2258 return 0; 2259 } 2260 2261 static void gpmc_probe_dt_children(struct platform_device *pdev) 2262 { 2263 int ret; 2264 struct device_node *child; 2265 2266 for_each_available_child_of_node(pdev->dev.of_node, child) { 2267 ret = gpmc_probe_generic_child(pdev, child); 2268 if (ret) { 2269 dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n", 2270 child, ret); 2271 } 2272 } 2273 } 2274 #else 2275 static int gpmc_probe_dt(struct platform_device *pdev) 2276 { 2277 return 0; 2278 } 2279 2280 static void gpmc_probe_dt_children(struct platform_device *pdev) 2281 { 2282 } 2283 #endif /* CONFIG_OF */ 2284 2285 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 2286 { 2287 return 1; /* we're input only */ 2288 } 2289 2290 static int gpmc_gpio_direction_input(struct gpio_chip *chip, 2291 unsigned int offset) 2292 { 2293 return 0; /* we're input only */ 2294 } 2295 2296 static int gpmc_gpio_direction_output(struct gpio_chip *chip, 2297 unsigned int offset, int value) 2298 { 2299 return -EINVAL; /* we're input only */ 2300 } 2301 2302 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset, 2303 int value) 2304 { 2305 } 2306 2307 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset) 2308 { 2309 u32 reg; 2310 2311 offset += 8; 2312 2313 reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset); 2314 2315 return !!reg; 2316 } 2317 2318 static int gpmc_gpio_init(struct gpmc_device *gpmc) 2319 { 2320 int ret; 2321 2322 gpmc->gpio_chip.parent = gpmc->dev; 2323 gpmc->gpio_chip.owner = THIS_MODULE; 2324 gpmc->gpio_chip.label = DEVICE_NAME; 2325 gpmc->gpio_chip.ngpio = gpmc_nr_waitpins; 2326 gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction; 2327 gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input; 2328 gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output; 2329 gpmc->gpio_chip.set = gpmc_gpio_set; 2330 gpmc->gpio_chip.get = gpmc_gpio_get; 2331 gpmc->gpio_chip.base = -1; 2332 2333 ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL); 2334 if (ret < 0) { 2335 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret); 2336 return ret; 2337 } 2338 2339 return 0; 2340 } 2341 2342 static int gpmc_probe(struct platform_device *pdev) 2343 { 2344 int rc; 2345 u32 l; 2346 struct resource *res; 2347 struct gpmc_device *gpmc; 2348 2349 gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL); 2350 if (!gpmc) 2351 return -ENOMEM; 2352 2353 gpmc->dev = &pdev->dev; 2354 platform_set_drvdata(pdev, gpmc); 2355 2356 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2357 if (res == NULL) 2358 return -ENOENT; 2359 2360 phys_base = res->start; 2361 mem_size = resource_size(res); 2362 2363 gpmc_base = devm_ioremap_resource(&pdev->dev, res); 2364 if (IS_ERR(gpmc_base)) 2365 return PTR_ERR(gpmc_base); 2366 2367 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 2368 if (!res) { 2369 dev_err(&pdev->dev, "Failed to get resource: irq\n"); 2370 return -ENOENT; 2371 } 2372 2373 gpmc->irq = res->start; 2374 2375 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck"); 2376 if (IS_ERR(gpmc_l3_clk)) { 2377 dev_err(&pdev->dev, "Failed to get GPMC fck\n"); 2378 return PTR_ERR(gpmc_l3_clk); 2379 } 2380 2381 if (!clk_get_rate(gpmc_l3_clk)) { 2382 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n"); 2383 return -EINVAL; 2384 } 2385 2386 if (pdev->dev.of_node) { 2387 rc = gpmc_probe_dt(pdev); 2388 if (rc) 2389 return rc; 2390 } else { 2391 gpmc_cs_num = GPMC_CS_NUM; 2392 gpmc_nr_waitpins = GPMC_NR_WAITPINS; 2393 } 2394 2395 pm_runtime_enable(&pdev->dev); 2396 pm_runtime_get_sync(&pdev->dev); 2397 2398 l = gpmc_read_reg(GPMC_REVISION); 2399 2400 /* 2401 * FIXME: Once device-tree migration is complete the below flags 2402 * should be populated based upon the device-tree compatible 2403 * string. For now just use the IP revision. OMAP3+ devices have 2404 * the wr_access and wr_data_mux_bus register fields. OMAP4+ 2405 * devices support the addr-addr-data multiplex protocol. 2406 * 2407 * GPMC IP revisions: 2408 * - OMAP24xx = 2.0 2409 * - OMAP3xxx = 5.0 2410 * - OMAP44xx/54xx/AM335x = 6.0 2411 */ 2412 if (GPMC_REVISION_MAJOR(l) > 0x4) 2413 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; 2414 if (GPMC_REVISION_MAJOR(l) > 0x5) 2415 gpmc_capability |= GPMC_HAS_MUX_AAD; 2416 dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), 2417 GPMC_REVISION_MINOR(l)); 2418 2419 gpmc_mem_init(); 2420 rc = gpmc_gpio_init(gpmc); 2421 if (rc) 2422 goto gpio_init_failed; 2423 2424 gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins; 2425 rc = gpmc_setup_irq(gpmc); 2426 if (rc) { 2427 dev_err(gpmc->dev, "gpmc_setup_irq failed\n"); 2428 goto gpio_init_failed; 2429 } 2430 2431 gpmc_probe_dt_children(pdev); 2432 2433 return 0; 2434 2435 gpio_init_failed: 2436 gpmc_mem_exit(); 2437 pm_runtime_put_sync(&pdev->dev); 2438 pm_runtime_disable(&pdev->dev); 2439 2440 return rc; 2441 } 2442 2443 static int gpmc_remove(struct platform_device *pdev) 2444 { 2445 struct gpmc_device *gpmc = platform_get_drvdata(pdev); 2446 2447 gpmc_free_irq(gpmc); 2448 gpmc_mem_exit(); 2449 pm_runtime_put_sync(&pdev->dev); 2450 pm_runtime_disable(&pdev->dev); 2451 2452 return 0; 2453 } 2454 2455 #ifdef CONFIG_PM_SLEEP 2456 static int gpmc_suspend(struct device *dev) 2457 { 2458 omap3_gpmc_save_context(); 2459 pm_runtime_put_sync(dev); 2460 return 0; 2461 } 2462 2463 static int gpmc_resume(struct device *dev) 2464 { 2465 pm_runtime_get_sync(dev); 2466 omap3_gpmc_restore_context(); 2467 return 0; 2468 } 2469 #endif 2470 2471 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume); 2472 2473 static struct platform_driver gpmc_driver = { 2474 .probe = gpmc_probe, 2475 .remove = gpmc_remove, 2476 .driver = { 2477 .name = DEVICE_NAME, 2478 .of_match_table = of_match_ptr(gpmc_dt_ids), 2479 .pm = &gpmc_pm_ops, 2480 }, 2481 }; 2482 2483 static __init int gpmc_init(void) 2484 { 2485 return platform_driver_register(&gpmc_driver); 2486 } 2487 postcore_initcall(gpmc_init); 2488 2489 static struct omap3_gpmc_regs gpmc_context; 2490 2491 void omap3_gpmc_save_context(void) 2492 { 2493 int i; 2494 2495 if (!gpmc_base) 2496 return; 2497 2498 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); 2499 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); 2500 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); 2501 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG); 2502 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); 2503 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); 2504 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); 2505 for (i = 0; i < gpmc_cs_num; i++) { 2506 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); 2507 if (gpmc_context.cs_context[i].is_valid) { 2508 gpmc_context.cs_context[i].config1 = 2509 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1); 2510 gpmc_context.cs_context[i].config2 = 2511 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2); 2512 gpmc_context.cs_context[i].config3 = 2513 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3); 2514 gpmc_context.cs_context[i].config4 = 2515 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4); 2516 gpmc_context.cs_context[i].config5 = 2517 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5); 2518 gpmc_context.cs_context[i].config6 = 2519 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6); 2520 gpmc_context.cs_context[i].config7 = 2521 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7); 2522 } 2523 } 2524 } 2525 2526 void omap3_gpmc_restore_context(void) 2527 { 2528 int i; 2529 2530 if (!gpmc_base) 2531 return; 2532 2533 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); 2534 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); 2535 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); 2536 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config); 2537 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); 2538 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); 2539 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); 2540 for (i = 0; i < gpmc_cs_num; i++) { 2541 if (gpmc_context.cs_context[i].is_valid) { 2542 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, 2543 gpmc_context.cs_context[i].config1); 2544 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2, 2545 gpmc_context.cs_context[i].config2); 2546 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3, 2547 gpmc_context.cs_context[i].config3); 2548 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4, 2549 gpmc_context.cs_context[i].config4); 2550 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5, 2551 gpmc_context.cs_context[i].config5); 2552 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6, 2553 gpmc_context.cs_context[i].config6); 2554 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, 2555 gpmc_context.cs_context[i].config7); 2556 } 2557 } 2558 } 2559