1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Yong Wu <yong.wu@mediatek.com> 5 */ 6 #include <linux/clk.h> 7 #include <linux/component.h> 8 #include <linux/device.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <soc/mediatek/smi.h> 17 #include <dt-bindings/memory/mt2701-larb-port.h> 18 #include <dt-bindings/memory/mtk-memory-port.h> 19 20 /* SMI COMMON */ 21 #define SMI_L1LEN 0x100 22 23 #define SMI_BUS_SEL 0x220 24 #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) 25 /* All are MMU0 defaultly. Only specialize mmu1 here. */ 26 #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) 27 28 #define SMI_M4U_TH 0x234 29 #define SMI_FIFO_TH1 0x238 30 #define SMI_FIFO_TH2 0x23c 31 #define SMI_DCM 0x300 32 #define SMI_DUMMY 0x444 33 34 /* SMI LARB */ 35 #define SMI_LARB_CMD_THRT_CON 0x24 36 #define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4) 37 #define SMI_LARB_THRT_RD_NU_LMT (5 << 4) 38 39 #define SMI_LARB_SW_FLAG 0x40 40 #define SMI_LARB_SW_FLAG_1 0x1 41 42 #define SMI_LARB_OSTDL_PORT 0x200 43 #define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2)) 44 45 /* Below are about mmu enable registers, they are different in SoCs */ 46 /* gen1: mt2701 */ 47 #define REG_SMI_SECUR_CON_BASE 0x5c0 48 49 /* every register control 8 port, register offset 0x4 */ 50 #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2) 51 #define REG_SMI_SECUR_CON_ADDR(id) \ 52 (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id)) 53 54 /* 55 * every port have 4 bit to control, bit[port + 3] control virtual or physical, 56 * bit[port + 2 : port + 1] control the domain, bit[port] control the security 57 * or non-security. 58 */ 59 #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2))) 60 #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3) 61 /* mt2701 domain should be set to 3 */ 62 #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) 63 64 /* gen2: */ 65 /* mt8167 */ 66 #define MT8167_SMI_LARB_MMU_EN 0xfc0 67 68 /* mt8173 */ 69 #define MT8173_SMI_LARB_MMU_EN 0xf00 70 71 /* general */ 72 #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) 73 #define F_MMU_EN BIT(0) 74 #define BANK_SEL(id) ({ \ 75 u32 _id = (id) & 0x3; \ 76 (_id << 8 | _id << 10 | _id << 12 | _id << 14); \ 77 }) 78 79 #define SMI_COMMON_INIT_REGS_NR 6 80 #define SMI_LARB_PORT_NR_MAX 32 81 82 #define MTK_SMI_FLAG_THRT_UPDATE BIT(0) 83 #define MTK_SMI_FLAG_SW_FLAG BIT(1) 84 #define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x))) 85 86 struct mtk_smi_reg_pair { 87 unsigned int offset; 88 u32 value; 89 }; 90 91 enum mtk_smi_type { 92 MTK_SMI_GEN1, 93 MTK_SMI_GEN2, /* gen2 smi common */ 94 MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */ 95 }; 96 97 #define MTK_SMI_CLK_NR_MAX 4 98 99 /* larbs: Require apb/smi clocks while gals is optional. */ 100 static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"}; 101 #define MTK_SMI_LARB_REQ_CLK_NR 2 102 #define MTK_SMI_LARB_OPT_CLK_NR 1 103 104 /* 105 * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required. 106 * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required. 107 */ 108 static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"}; 109 #define MTK_SMI_COM_REQ_CLK_NR 2 110 #define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX 111 #define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3 112 113 struct mtk_smi_common_plat { 114 enum mtk_smi_type type; 115 bool has_gals; 116 u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ 117 118 const struct mtk_smi_reg_pair *init; 119 }; 120 121 struct mtk_smi_larb_gen { 122 int port_in_larb[MTK_LARB_NR_MAX + 1]; 123 void (*config_port)(struct device *dev); 124 unsigned int larb_direct_to_common_mask; 125 unsigned int flags_general; 126 const u8 (*ostd)[SMI_LARB_PORT_NR_MAX]; 127 }; 128 129 struct mtk_smi { 130 struct device *dev; 131 unsigned int clk_num; 132 struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX]; 133 struct clk *clk_async; /*only needed by mt2701*/ 134 union { 135 void __iomem *smi_ao_base; /* only for gen1 */ 136 void __iomem *base; /* only for gen2 */ 137 }; 138 struct device *smi_common_dev; /* for sub common */ 139 const struct mtk_smi_common_plat *plat; 140 }; 141 142 struct mtk_smi_larb { /* larb: local arbiter */ 143 struct mtk_smi smi; 144 void __iomem *base; 145 struct device *smi_common_dev; /* common or sub-common dev */ 146 const struct mtk_smi_larb_gen *larb_gen; 147 int larbid; 148 u32 *mmu; 149 unsigned char *bank; 150 }; 151 152 int mtk_smi_larb_get(struct device *larbdev) 153 { 154 int ret = pm_runtime_resume_and_get(larbdev); 155 156 return (ret < 0) ? ret : 0; 157 } 158 EXPORT_SYMBOL_GPL(mtk_smi_larb_get); 159 160 void mtk_smi_larb_put(struct device *larbdev) 161 { 162 pm_runtime_put_sync(larbdev); 163 } 164 EXPORT_SYMBOL_GPL(mtk_smi_larb_put); 165 166 static int 167 mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) 168 { 169 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 170 struct mtk_smi_larb_iommu *larb_mmu = data; 171 unsigned int i; 172 173 for (i = 0; i < MTK_LARB_NR_MAX; i++) { 174 if (dev == larb_mmu[i].dev) { 175 larb->larbid = i; 176 larb->mmu = &larb_mmu[i].mmu; 177 larb->bank = larb_mmu[i].bank; 178 return 0; 179 } 180 } 181 return -ENODEV; 182 } 183 184 static void 185 mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) 186 { 187 /* Do nothing as the iommu is always enabled. */ 188 } 189 190 static const struct component_ops mtk_smi_larb_component_ops = { 191 .bind = mtk_smi_larb_bind, 192 .unbind = mtk_smi_larb_unbind, 193 }; 194 195 static void mtk_smi_larb_config_port_gen1(struct device *dev) 196 { 197 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 198 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 199 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); 200 int i, m4u_port_id, larb_port_num; 201 u32 sec_con_val, reg_val; 202 203 m4u_port_id = larb_gen->port_in_larb[larb->larbid]; 204 larb_port_num = larb_gen->port_in_larb[larb->larbid + 1] 205 - larb_gen->port_in_larb[larb->larbid]; 206 207 for (i = 0; i < larb_port_num; i++, m4u_port_id++) { 208 if (*larb->mmu & BIT(i)) { 209 /* bit[port + 3] controls the virtual or physical */ 210 sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id); 211 } else { 212 /* do not need to enable m4u for this port */ 213 continue; 214 } 215 reg_val = readl(common->smi_ao_base 216 + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 217 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); 218 reg_val |= sec_con_val; 219 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); 220 writel(reg_val, 221 common->smi_ao_base 222 + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 223 } 224 } 225 226 static void mtk_smi_larb_config_port_mt8167(struct device *dev) 227 { 228 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 229 230 writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); 231 } 232 233 static void mtk_smi_larb_config_port_mt8173(struct device *dev) 234 { 235 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 236 237 writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN); 238 } 239 240 static void mtk_smi_larb_config_port_gen2_general(struct device *dev) 241 { 242 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 243 u32 reg, flags_general = larb->larb_gen->flags_general; 244 const u8 *larbostd = larb->larb_gen->ostd[larb->larbid]; 245 int i; 246 247 if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) 248 return; 249 250 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) { 251 reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON); 252 reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK; 253 reg |= SMI_LARB_THRT_RD_NU_LMT; 254 writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON); 255 } 256 257 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG)) 258 writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); 259 260 for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) 261 writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); 262 263 for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { 264 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); 265 reg |= F_MMU_EN; 266 reg |= BANK_SEL(larb->bank[i]); 267 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); 268 } 269 } 270 271 static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = { 272 [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */ 273 [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */ 274 [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, /* ... */ 275 [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,}, 276 [4] = {0x06, 0x01, 0x17, 0x06, 0x0a,}, 277 [5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,}, 278 [6] = {0x06, 0x01, 0x06, 0x0a,}, 279 [7] = {0x0c, 0x0c, 0x12,}, 280 [8] = {0x0c, 0x0c, 0x12,}, 281 [9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a, 282 0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,}, 283 [10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10, 284 0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d, 285 0x0d, 0x06, 0x10, 0x10,}, 286 [11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,}, 287 [12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,}, 288 [13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,}, 289 [14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01, 290 0x01, 0x02, 0x02, 0x08, 0x02,}, 291 [15] = {}, 292 [16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a, 293 0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,}, 294 [17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 295 [18] = {0x12, 0x06, 0x12, 0x06,}, 296 [19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 297 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 298 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 299 [20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 300 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 301 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 302 [21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 303 [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 304 [23] = {0x18, 0x01,}, 305 [24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01, 306 0x01, 0x01,}, 307 [25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 308 0x02, 0x01,}, 309 [26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 310 0x02, 0x01,}, 311 [27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 312 0x02, 0x01,}, 313 [28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 314 }; 315 316 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { 317 .port_in_larb = { 318 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 319 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 320 }, 321 .config_port = mtk_smi_larb_config_port_gen1, 322 }; 323 324 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { 325 .config_port = mtk_smi_larb_config_port_gen2_general, 326 .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ 327 }; 328 329 static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { 330 .config_port = mtk_smi_larb_config_port_gen2_general, 331 .larb_direct_to_common_mask = 332 BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), 333 /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ 334 }; 335 336 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = { 337 /* mt8167 do not need the port in larb */ 338 .config_port = mtk_smi_larb_config_port_mt8167, 339 }; 340 341 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { 342 /* mt8173 do not need the port in larb */ 343 .config_port = mtk_smi_larb_config_port_mt8173, 344 }; 345 346 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { 347 .config_port = mtk_smi_larb_config_port_gen2_general, 348 .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), 349 /* IPU0 | IPU1 | CCU */ 350 }; 351 352 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { 353 .config_port = mtk_smi_larb_config_port_gen2_general, 354 }; 355 356 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = { 357 .config_port = mtk_smi_larb_config_port_gen2_general, 358 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG, 359 .ostd = mtk_smi_larb_mt8195_ostd, 360 }; 361 362 static const struct of_device_id mtk_smi_larb_of_ids[] = { 363 {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701}, 364 {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712}, 365 {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779}, 366 {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167}, 367 {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173}, 368 {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, 369 {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, 370 {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195}, 371 {} 372 }; 373 374 static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev) 375 { 376 struct platform_device *smi_com_pdev; 377 struct device_node *smi_com_node; 378 struct device *smi_com_dev; 379 struct device_link *link; 380 381 smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); 382 if (!smi_com_node) 383 return -EINVAL; 384 385 smi_com_pdev = of_find_device_by_node(smi_com_node); 386 of_node_put(smi_com_node); 387 if (smi_com_pdev) { 388 /* smi common is the supplier, Make sure it is ready before */ 389 if (!platform_get_drvdata(smi_com_pdev)) 390 return -EPROBE_DEFER; 391 smi_com_dev = &smi_com_pdev->dev; 392 link = device_link_add(dev, smi_com_dev, 393 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 394 if (!link) { 395 dev_err(dev, "Unable to link smi-common dev\n"); 396 return -ENODEV; 397 } 398 *com_dev = smi_com_dev; 399 } else { 400 dev_err(dev, "Failed to get the smi_common device\n"); 401 return -EINVAL; 402 } 403 return 0; 404 } 405 406 static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi, 407 const char * const clks[], 408 unsigned int clk_nr_required, 409 unsigned int clk_nr_optional) 410 { 411 int i, ret; 412 413 for (i = 0; i < clk_nr_required; i++) 414 smi->clks[i].id = clks[i]; 415 ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks); 416 if (ret) 417 return ret; 418 419 for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++) 420 smi->clks[i].id = clks[i]; 421 ret = devm_clk_bulk_get_optional(dev, clk_nr_optional, 422 smi->clks + clk_nr_required); 423 smi->clk_num = clk_nr_required + clk_nr_optional; 424 return ret; 425 } 426 427 static int mtk_smi_larb_probe(struct platform_device *pdev) 428 { 429 struct mtk_smi_larb *larb; 430 struct device *dev = &pdev->dev; 431 int ret; 432 433 larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); 434 if (!larb) 435 return -ENOMEM; 436 437 larb->larb_gen = of_device_get_match_data(dev); 438 larb->base = devm_platform_ioremap_resource(pdev, 0); 439 if (IS_ERR(larb->base)) 440 return PTR_ERR(larb->base); 441 442 ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks, 443 MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR); 444 if (ret) 445 return ret; 446 447 larb->smi.dev = dev; 448 449 ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev); 450 if (ret < 0) 451 return ret; 452 453 pm_runtime_enable(dev); 454 platform_set_drvdata(pdev, larb); 455 ret = component_add(dev, &mtk_smi_larb_component_ops); 456 if (ret) 457 goto err_pm_disable; 458 return 0; 459 460 err_pm_disable: 461 pm_runtime_disable(dev); 462 device_link_remove(dev, larb->smi_common_dev); 463 return ret; 464 } 465 466 static int mtk_smi_larb_remove(struct platform_device *pdev) 467 { 468 struct mtk_smi_larb *larb = platform_get_drvdata(pdev); 469 470 device_link_remove(&pdev->dev, larb->smi_common_dev); 471 pm_runtime_disable(&pdev->dev); 472 component_del(&pdev->dev, &mtk_smi_larb_component_ops); 473 return 0; 474 } 475 476 static int __maybe_unused mtk_smi_larb_resume(struct device *dev) 477 { 478 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 479 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 480 int ret; 481 482 ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks); 483 if (ret < 0) 484 return ret; 485 486 /* Configure the basic setting for this larb */ 487 larb_gen->config_port(dev); 488 489 return 0; 490 } 491 492 static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) 493 { 494 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 495 496 clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks); 497 return 0; 498 } 499 500 static const struct dev_pm_ops smi_larb_pm_ops = { 501 SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL) 502 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 503 pm_runtime_force_resume) 504 }; 505 506 static struct platform_driver mtk_smi_larb_driver = { 507 .probe = mtk_smi_larb_probe, 508 .remove = mtk_smi_larb_remove, 509 .driver = { 510 .name = "mtk-smi-larb", 511 .of_match_table = mtk_smi_larb_of_ids, 512 .pm = &smi_larb_pm_ops, 513 } 514 }; 515 516 static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = { 517 {SMI_L1LEN, 0xb}, 518 {SMI_M4U_TH, 0xe100e10}, 519 {SMI_FIFO_TH1, 0x506090a}, 520 {SMI_FIFO_TH2, 0x506090a}, 521 {SMI_DCM, 0x4f1}, 522 {SMI_DUMMY, 0x1}, 523 }; 524 525 static const struct mtk_smi_common_plat mtk_smi_common_gen1 = { 526 .type = MTK_SMI_GEN1, 527 }; 528 529 static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { 530 .type = MTK_SMI_GEN2, 531 }; 532 533 static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { 534 .type = MTK_SMI_GEN2, 535 .has_gals = true, 536 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | 537 F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), 538 }; 539 540 static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { 541 .type = MTK_SMI_GEN2, 542 .has_gals = true, 543 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 544 F_MMU1_LARB(7), 545 }; 546 547 static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { 548 .type = MTK_SMI_GEN2, 549 .has_gals = true, 550 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 551 F_MMU1_LARB(6), 552 }; 553 554 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = { 555 .type = MTK_SMI_GEN2, 556 .has_gals = true, 557 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) | 558 F_MMU1_LARB(7), 559 .init = mtk_smi_common_mt8195_init, 560 }; 561 562 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = { 563 .type = MTK_SMI_GEN2, 564 .has_gals = true, 565 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7), 566 .init = mtk_smi_common_mt8195_init, 567 }; 568 569 static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = { 570 .type = MTK_SMI_GEN2_SUB_COMM, 571 .has_gals = true, 572 }; 573 574 static const struct of_device_id mtk_smi_common_of_ids[] = { 575 {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1}, 576 {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2}, 577 {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779}, 578 {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2}, 579 {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2}, 580 {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183}, 581 {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, 582 {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, 583 {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, 584 {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195}, 585 {} 586 }; 587 588 static int mtk_smi_common_probe(struct platform_device *pdev) 589 { 590 struct device *dev = &pdev->dev; 591 struct mtk_smi *common; 592 int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR; 593 594 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); 595 if (!common) 596 return -ENOMEM; 597 common->dev = dev; 598 common->plat = of_device_get_match_data(dev); 599 600 if (common->plat->has_gals) { 601 if (common->plat->type == MTK_SMI_GEN2) 602 clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR; 603 else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 604 clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR; 605 } 606 ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0); 607 if (ret) 608 return ret; 609 610 /* 611 * for mtk smi gen 1, we need to get the ao(always on) base to config 612 * m4u port, and we need to enable the aync clock for transform the smi 613 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao 614 * base. 615 */ 616 if (common->plat->type == MTK_SMI_GEN1) { 617 common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0); 618 if (IS_ERR(common->smi_ao_base)) 619 return PTR_ERR(common->smi_ao_base); 620 621 common->clk_async = devm_clk_get(dev, "async"); 622 if (IS_ERR(common->clk_async)) 623 return PTR_ERR(common->clk_async); 624 625 ret = clk_prepare_enable(common->clk_async); 626 if (ret) 627 return ret; 628 } else { 629 common->base = devm_platform_ioremap_resource(pdev, 0); 630 if (IS_ERR(common->base)) 631 return PTR_ERR(common->base); 632 } 633 634 /* link its smi-common if this is smi-sub-common */ 635 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) { 636 ret = mtk_smi_device_link_common(dev, &common->smi_common_dev); 637 if (ret < 0) 638 return ret; 639 } 640 641 pm_runtime_enable(dev); 642 platform_set_drvdata(pdev, common); 643 return 0; 644 } 645 646 static int mtk_smi_common_remove(struct platform_device *pdev) 647 { 648 struct mtk_smi *common = dev_get_drvdata(&pdev->dev); 649 650 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 651 device_link_remove(&pdev->dev, common->smi_common_dev); 652 pm_runtime_disable(&pdev->dev); 653 return 0; 654 } 655 656 static int __maybe_unused mtk_smi_common_resume(struct device *dev) 657 { 658 struct mtk_smi *common = dev_get_drvdata(dev); 659 const struct mtk_smi_reg_pair *init = common->plat->init; 660 u32 bus_sel = common->plat->bus_sel; /* default is 0 */ 661 int ret, i; 662 663 ret = clk_bulk_prepare_enable(common->clk_num, common->clks); 664 if (ret) 665 return ret; 666 667 if (common->plat->type != MTK_SMI_GEN2) 668 return 0; 669 670 for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++) 671 writel_relaxed(init[i].value, common->base + init[i].offset); 672 673 writel(bus_sel, common->base + SMI_BUS_SEL); 674 return 0; 675 } 676 677 static int __maybe_unused mtk_smi_common_suspend(struct device *dev) 678 { 679 struct mtk_smi *common = dev_get_drvdata(dev); 680 681 clk_bulk_disable_unprepare(common->clk_num, common->clks); 682 return 0; 683 } 684 685 static const struct dev_pm_ops smi_common_pm_ops = { 686 SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL) 687 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 688 pm_runtime_force_resume) 689 }; 690 691 static struct platform_driver mtk_smi_common_driver = { 692 .probe = mtk_smi_common_probe, 693 .remove = mtk_smi_common_remove, 694 .driver = { 695 .name = "mtk-smi-common", 696 .of_match_table = mtk_smi_common_of_ids, 697 .pm = &smi_common_pm_ops, 698 } 699 }; 700 701 static struct platform_driver * const smidrivers[] = { 702 &mtk_smi_common_driver, 703 &mtk_smi_larb_driver, 704 }; 705 706 static int __init mtk_smi_init(void) 707 { 708 return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 709 } 710 module_init(mtk_smi_init); 711 712 static void __exit mtk_smi_exit(void) 713 { 714 platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 715 } 716 module_exit(mtk_smi_exit); 717 718 MODULE_DESCRIPTION("MediaTek SMI driver"); 719 MODULE_LICENSE("GPL v2"); 720