1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Yong Wu <yong.wu@mediatek.com> 5 */ 6 #include <linux/clk.h> 7 #include <linux/component.h> 8 #include <linux/device.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_platform.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <soc/mediatek/smi.h> 18 #include <dt-bindings/memory/mt2701-larb-port.h> 19 #include <dt-bindings/memory/mtk-memory-port.h> 20 21 /* SMI COMMON */ 22 #define SMI_L1LEN 0x100 23 24 #define SMI_BUS_SEL 0x220 25 #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) 26 /* All are MMU0 defaultly. Only specialize mmu1 here. */ 27 #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) 28 29 #define SMI_M4U_TH 0x234 30 #define SMI_FIFO_TH1 0x238 31 #define SMI_FIFO_TH2 0x23c 32 #define SMI_DCM 0x300 33 #define SMI_DUMMY 0x444 34 35 /* SMI LARB */ 36 #define SMI_LARB_SLP_CON 0xc 37 #define SLP_PROT_EN BIT(0) 38 #define SLP_PROT_RDY BIT(16) 39 40 #define SMI_LARB_CMD_THRT_CON 0x24 41 #define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4) 42 #define SMI_LARB_THRT_RD_NU_LMT (5 << 4) 43 44 #define SMI_LARB_SW_FLAG 0x40 45 #define SMI_LARB_SW_FLAG_1 0x1 46 47 #define SMI_LARB_OSTDL_PORT 0x200 48 #define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2)) 49 50 /* Below are about mmu enable registers, they are different in SoCs */ 51 /* gen1: mt2701 */ 52 #define REG_SMI_SECUR_CON_BASE 0x5c0 53 54 /* every register control 8 port, register offset 0x4 */ 55 #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2) 56 #define REG_SMI_SECUR_CON_ADDR(id) \ 57 (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id)) 58 59 /* 60 * every port have 4 bit to control, bit[port + 3] control virtual or physical, 61 * bit[port + 2 : port + 1] control the domain, bit[port] control the security 62 * or non-security. 63 */ 64 #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2))) 65 #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3) 66 /* mt2701 domain should be set to 3 */ 67 #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) 68 69 /* gen2: */ 70 /* mt8167 */ 71 #define MT8167_SMI_LARB_MMU_EN 0xfc0 72 73 /* mt8173 */ 74 #define MT8173_SMI_LARB_MMU_EN 0xf00 75 76 /* general */ 77 #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) 78 #define F_MMU_EN BIT(0) 79 #define BANK_SEL(id) ({ \ 80 u32 _id = (id) & 0x3; \ 81 (_id << 8 | _id << 10 | _id << 12 | _id << 14); \ 82 }) 83 84 #define SMI_COMMON_INIT_REGS_NR 6 85 #define SMI_LARB_PORT_NR_MAX 32 86 87 #define MTK_SMI_FLAG_THRT_UPDATE BIT(0) 88 #define MTK_SMI_FLAG_SW_FLAG BIT(1) 89 #define MTK_SMI_FLAG_SLEEP_CTL BIT(2) 90 #define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x))) 91 92 struct mtk_smi_reg_pair { 93 unsigned int offset; 94 u32 value; 95 }; 96 97 enum mtk_smi_type { 98 MTK_SMI_GEN1, 99 MTK_SMI_GEN2, /* gen2 smi common */ 100 MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */ 101 }; 102 103 /* larbs: Require apb/smi clocks while gals is optional. */ 104 static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"}; 105 #define MTK_SMI_LARB_REQ_CLK_NR 2 106 #define MTK_SMI_LARB_OPT_CLK_NR 1 107 108 /* 109 * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required. 110 * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required. 111 */ 112 static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"}; 113 #define MTK_SMI_CLK_NR_MAX ARRAY_SIZE(mtk_smi_common_clks) 114 #define MTK_SMI_COM_REQ_CLK_NR 2 115 #define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX 116 #define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3 117 118 struct mtk_smi_common_plat { 119 enum mtk_smi_type type; 120 bool has_gals; 121 u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ 122 123 const struct mtk_smi_reg_pair *init; 124 }; 125 126 struct mtk_smi_larb_gen { 127 int port_in_larb[MTK_LARB_NR_MAX + 1]; 128 void (*config_port)(struct device *dev); 129 unsigned int larb_direct_to_common_mask; 130 unsigned int flags_general; 131 const u8 (*ostd)[SMI_LARB_PORT_NR_MAX]; 132 }; 133 134 struct mtk_smi { 135 struct device *dev; 136 unsigned int clk_num; 137 struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX]; 138 struct clk *clk_async; /*only needed by mt2701*/ 139 union { 140 void __iomem *smi_ao_base; /* only for gen1 */ 141 void __iomem *base; /* only for gen2 */ 142 }; 143 struct device *smi_common_dev; /* for sub common */ 144 const struct mtk_smi_common_plat *plat; 145 }; 146 147 struct mtk_smi_larb { /* larb: local arbiter */ 148 struct mtk_smi smi; 149 void __iomem *base; 150 struct device *smi_common_dev; /* common or sub-common dev */ 151 const struct mtk_smi_larb_gen *larb_gen; 152 int larbid; 153 u32 *mmu; 154 unsigned char *bank; 155 }; 156 157 int mtk_smi_larb_get(struct device *larbdev) 158 { 159 int ret = pm_runtime_resume_and_get(larbdev); 160 161 return (ret < 0) ? ret : 0; 162 } 163 EXPORT_SYMBOL_GPL(mtk_smi_larb_get); 164 165 void mtk_smi_larb_put(struct device *larbdev) 166 { 167 pm_runtime_put_sync(larbdev); 168 } 169 EXPORT_SYMBOL_GPL(mtk_smi_larb_put); 170 171 static int 172 mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) 173 { 174 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 175 struct mtk_smi_larb_iommu *larb_mmu = data; 176 unsigned int i; 177 178 for (i = 0; i < MTK_LARB_NR_MAX; i++) { 179 if (dev == larb_mmu[i].dev) { 180 larb->larbid = i; 181 larb->mmu = &larb_mmu[i].mmu; 182 larb->bank = larb_mmu[i].bank; 183 return 0; 184 } 185 } 186 return -ENODEV; 187 } 188 189 static void 190 mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) 191 { 192 /* Do nothing as the iommu is always enabled. */ 193 } 194 195 static const struct component_ops mtk_smi_larb_component_ops = { 196 .bind = mtk_smi_larb_bind, 197 .unbind = mtk_smi_larb_unbind, 198 }; 199 200 static void mtk_smi_larb_config_port_gen1(struct device *dev) 201 { 202 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 203 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 204 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); 205 int i, m4u_port_id, larb_port_num; 206 u32 sec_con_val, reg_val; 207 208 m4u_port_id = larb_gen->port_in_larb[larb->larbid]; 209 larb_port_num = larb_gen->port_in_larb[larb->larbid + 1] 210 - larb_gen->port_in_larb[larb->larbid]; 211 212 for (i = 0; i < larb_port_num; i++, m4u_port_id++) { 213 if (*larb->mmu & BIT(i)) { 214 /* bit[port + 3] controls the virtual or physical */ 215 sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id); 216 } else { 217 /* do not need to enable m4u for this port */ 218 continue; 219 } 220 reg_val = readl(common->smi_ao_base 221 + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 222 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); 223 reg_val |= sec_con_val; 224 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); 225 writel(reg_val, 226 common->smi_ao_base 227 + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 228 } 229 } 230 231 static void mtk_smi_larb_config_port_mt8167(struct device *dev) 232 { 233 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 234 235 writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); 236 } 237 238 static void mtk_smi_larb_config_port_mt8173(struct device *dev) 239 { 240 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 241 242 writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN); 243 } 244 245 static void mtk_smi_larb_config_port_gen2_general(struct device *dev) 246 { 247 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 248 u32 reg, flags_general = larb->larb_gen->flags_general; 249 const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL; 250 int i; 251 252 if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) 253 return; 254 255 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) { 256 reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON); 257 reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK; 258 reg |= SMI_LARB_THRT_RD_NU_LMT; 259 writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON); 260 } 261 262 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG)) 263 writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); 264 265 for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) 266 writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); 267 268 for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { 269 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); 270 reg |= F_MMU_EN; 271 reg |= BANK_SEL(larb->bank[i]); 272 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); 273 } 274 } 275 276 static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = { 277 [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */ 278 [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */ 279 [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, /* ... */ 280 [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,}, 281 [4] = {0x06, 0x01, 0x17, 0x06, 0x0a,}, 282 [5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,}, 283 [6] = {0x06, 0x01, 0x06, 0x0a,}, 284 [7] = {0x0c, 0x0c, 0x12,}, 285 [8] = {0x0c, 0x0c, 0x12,}, 286 [9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a, 287 0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,}, 288 [10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10, 289 0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d, 290 0x0d, 0x06, 0x10, 0x10,}, 291 [11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,}, 292 [12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,}, 293 [13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,}, 294 [14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01, 295 0x01, 0x02, 0x02, 0x08, 0x02,}, 296 [15] = {}, 297 [16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a, 298 0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,}, 299 [17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 300 [18] = {0x12, 0x06, 0x12, 0x06,}, 301 [19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 302 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 303 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 304 [20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 305 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 306 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 307 [21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 308 [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 309 [23] = {0x18, 0x01,}, 310 [24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01, 311 0x01, 0x01,}, 312 [25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 313 0x02, 0x01,}, 314 [26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 315 0x02, 0x01,}, 316 [27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 317 0x02, 0x01,}, 318 [28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 319 }; 320 321 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { 322 .port_in_larb = { 323 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 324 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 325 }, 326 .config_port = mtk_smi_larb_config_port_gen1, 327 }; 328 329 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { 330 .config_port = mtk_smi_larb_config_port_gen2_general, 331 .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ 332 }; 333 334 static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { 335 .config_port = mtk_smi_larb_config_port_gen2_general, 336 .larb_direct_to_common_mask = 337 BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), 338 /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ 339 }; 340 341 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = { 342 /* mt8167 do not need the port in larb */ 343 .config_port = mtk_smi_larb_config_port_mt8167, 344 }; 345 346 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { 347 /* mt8173 do not need the port in larb */ 348 .config_port = mtk_smi_larb_config_port_mt8173, 349 }; 350 351 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { 352 .config_port = mtk_smi_larb_config_port_gen2_general, 353 .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), 354 /* IPU0 | IPU1 | CCU */ 355 }; 356 357 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = { 358 .config_port = mtk_smi_larb_config_port_gen2_general, 359 .flags_general = MTK_SMI_FLAG_SLEEP_CTL, 360 }; 361 362 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { 363 .config_port = mtk_smi_larb_config_port_gen2_general, 364 }; 365 366 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = { 367 .config_port = mtk_smi_larb_config_port_gen2_general, 368 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG | 369 MTK_SMI_FLAG_SLEEP_CTL, 370 .ostd = mtk_smi_larb_mt8195_ostd, 371 }; 372 373 static const struct of_device_id mtk_smi_larb_of_ids[] = { 374 {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701}, 375 {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712}, 376 {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779}, 377 {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167}, 378 {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173}, 379 {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, 380 {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186}, 381 {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, 382 {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195}, 383 {} 384 }; 385 386 static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb) 387 { 388 int ret; 389 u32 tmp; 390 391 writel_relaxed(SLP_PROT_EN, larb->base + SMI_LARB_SLP_CON); 392 ret = readl_poll_timeout_atomic(larb->base + SMI_LARB_SLP_CON, 393 tmp, !!(tmp & SLP_PROT_RDY), 10, 1000); 394 if (ret) { 395 /* TODO: Reset this larb if it fails here. */ 396 dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp); 397 } 398 return ret; 399 } 400 401 static void mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb *larb) 402 { 403 writel_relaxed(0, larb->base + SMI_LARB_SLP_CON); 404 } 405 406 static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev) 407 { 408 struct platform_device *smi_com_pdev; 409 struct device_node *smi_com_node; 410 struct device *smi_com_dev; 411 struct device_link *link; 412 413 smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); 414 if (!smi_com_node) 415 return -EINVAL; 416 417 smi_com_pdev = of_find_device_by_node(smi_com_node); 418 of_node_put(smi_com_node); 419 if (smi_com_pdev) { 420 /* smi common is the supplier, Make sure it is ready before */ 421 if (!platform_get_drvdata(smi_com_pdev)) 422 return -EPROBE_DEFER; 423 smi_com_dev = &smi_com_pdev->dev; 424 link = device_link_add(dev, smi_com_dev, 425 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 426 if (!link) { 427 dev_err(dev, "Unable to link smi-common dev\n"); 428 return -ENODEV; 429 } 430 *com_dev = smi_com_dev; 431 } else { 432 dev_err(dev, "Failed to get the smi_common device\n"); 433 return -EINVAL; 434 } 435 return 0; 436 } 437 438 static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi, 439 const char * const clks[], 440 unsigned int clk_nr_required, 441 unsigned int clk_nr_optional) 442 { 443 int i, ret; 444 445 for (i = 0; i < clk_nr_required; i++) 446 smi->clks[i].id = clks[i]; 447 ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks); 448 if (ret) 449 return ret; 450 451 for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++) 452 smi->clks[i].id = clks[i]; 453 ret = devm_clk_bulk_get_optional(dev, clk_nr_optional, 454 smi->clks + clk_nr_required); 455 smi->clk_num = clk_nr_required + clk_nr_optional; 456 return ret; 457 } 458 459 static int mtk_smi_larb_probe(struct platform_device *pdev) 460 { 461 struct mtk_smi_larb *larb; 462 struct device *dev = &pdev->dev; 463 int ret; 464 465 larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); 466 if (!larb) 467 return -ENOMEM; 468 469 larb->larb_gen = of_device_get_match_data(dev); 470 larb->base = devm_platform_ioremap_resource(pdev, 0); 471 if (IS_ERR(larb->base)) 472 return PTR_ERR(larb->base); 473 474 ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks, 475 MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR); 476 if (ret) 477 return ret; 478 479 larb->smi.dev = dev; 480 481 ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev); 482 if (ret < 0) 483 return ret; 484 485 pm_runtime_enable(dev); 486 platform_set_drvdata(pdev, larb); 487 ret = component_add(dev, &mtk_smi_larb_component_ops); 488 if (ret) 489 goto err_pm_disable; 490 return 0; 491 492 err_pm_disable: 493 pm_runtime_disable(dev); 494 device_link_remove(dev, larb->smi_common_dev); 495 return ret; 496 } 497 498 static int mtk_smi_larb_remove(struct platform_device *pdev) 499 { 500 struct mtk_smi_larb *larb = platform_get_drvdata(pdev); 501 502 device_link_remove(&pdev->dev, larb->smi_common_dev); 503 pm_runtime_disable(&pdev->dev); 504 component_del(&pdev->dev, &mtk_smi_larb_component_ops); 505 return 0; 506 } 507 508 static int __maybe_unused mtk_smi_larb_resume(struct device *dev) 509 { 510 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 511 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 512 int ret; 513 514 ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks); 515 if (ret) 516 return ret; 517 518 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) 519 mtk_smi_larb_sleep_ctrl_disable(larb); 520 521 /* Configure the basic setting for this larb */ 522 larb_gen->config_port(dev); 523 524 return 0; 525 } 526 527 static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) 528 { 529 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 530 int ret; 531 532 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) { 533 ret = mtk_smi_larb_sleep_ctrl_enable(larb); 534 if (ret) 535 return ret; 536 } 537 538 clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks); 539 return 0; 540 } 541 542 static const struct dev_pm_ops smi_larb_pm_ops = { 543 SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL) 544 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 545 pm_runtime_force_resume) 546 }; 547 548 static struct platform_driver mtk_smi_larb_driver = { 549 .probe = mtk_smi_larb_probe, 550 .remove = mtk_smi_larb_remove, 551 .driver = { 552 .name = "mtk-smi-larb", 553 .of_match_table = mtk_smi_larb_of_ids, 554 .pm = &smi_larb_pm_ops, 555 } 556 }; 557 558 static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = { 559 {SMI_L1LEN, 0xb}, 560 {SMI_M4U_TH, 0xe100e10}, 561 {SMI_FIFO_TH1, 0x506090a}, 562 {SMI_FIFO_TH2, 0x506090a}, 563 {SMI_DCM, 0x4f1}, 564 {SMI_DUMMY, 0x1}, 565 }; 566 567 static const struct mtk_smi_common_plat mtk_smi_common_gen1 = { 568 .type = MTK_SMI_GEN1, 569 }; 570 571 static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { 572 .type = MTK_SMI_GEN2, 573 }; 574 575 static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { 576 .type = MTK_SMI_GEN2, 577 .has_gals = true, 578 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | 579 F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), 580 }; 581 582 static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { 583 .type = MTK_SMI_GEN2, 584 .has_gals = true, 585 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 586 F_MMU1_LARB(7), 587 }; 588 589 static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = { 590 .type = MTK_SMI_GEN2, 591 .has_gals = true, 592 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7), 593 }; 594 595 static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { 596 .type = MTK_SMI_GEN2, 597 .has_gals = true, 598 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 599 F_MMU1_LARB(6), 600 }; 601 602 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = { 603 .type = MTK_SMI_GEN2, 604 .has_gals = true, 605 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) | 606 F_MMU1_LARB(7), 607 .init = mtk_smi_common_mt8195_init, 608 }; 609 610 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = { 611 .type = MTK_SMI_GEN2, 612 .has_gals = true, 613 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7), 614 .init = mtk_smi_common_mt8195_init, 615 }; 616 617 static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = { 618 .type = MTK_SMI_GEN2_SUB_COMM, 619 .has_gals = true, 620 }; 621 622 static const struct of_device_id mtk_smi_common_of_ids[] = { 623 {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1}, 624 {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2}, 625 {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779}, 626 {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2}, 627 {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2}, 628 {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183}, 629 {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186}, 630 {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, 631 {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, 632 {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, 633 {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195}, 634 {} 635 }; 636 637 static int mtk_smi_common_probe(struct platform_device *pdev) 638 { 639 struct device *dev = &pdev->dev; 640 struct mtk_smi *common; 641 int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR; 642 643 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); 644 if (!common) 645 return -ENOMEM; 646 common->dev = dev; 647 common->plat = of_device_get_match_data(dev); 648 649 if (common->plat->has_gals) { 650 if (common->plat->type == MTK_SMI_GEN2) 651 clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR; 652 else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 653 clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR; 654 } 655 ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0); 656 if (ret) 657 return ret; 658 659 /* 660 * for mtk smi gen 1, we need to get the ao(always on) base to config 661 * m4u port, and we need to enable the aync clock for transform the smi 662 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao 663 * base. 664 */ 665 if (common->plat->type == MTK_SMI_GEN1) { 666 common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0); 667 if (IS_ERR(common->smi_ao_base)) 668 return PTR_ERR(common->smi_ao_base); 669 670 common->clk_async = devm_clk_get(dev, "async"); 671 if (IS_ERR(common->clk_async)) 672 return PTR_ERR(common->clk_async); 673 674 ret = clk_prepare_enable(common->clk_async); 675 if (ret) 676 return ret; 677 } else { 678 common->base = devm_platform_ioremap_resource(pdev, 0); 679 if (IS_ERR(common->base)) 680 return PTR_ERR(common->base); 681 } 682 683 /* link its smi-common if this is smi-sub-common */ 684 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) { 685 ret = mtk_smi_device_link_common(dev, &common->smi_common_dev); 686 if (ret < 0) 687 return ret; 688 } 689 690 pm_runtime_enable(dev); 691 platform_set_drvdata(pdev, common); 692 return 0; 693 } 694 695 static int mtk_smi_common_remove(struct platform_device *pdev) 696 { 697 struct mtk_smi *common = dev_get_drvdata(&pdev->dev); 698 699 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 700 device_link_remove(&pdev->dev, common->smi_common_dev); 701 pm_runtime_disable(&pdev->dev); 702 return 0; 703 } 704 705 static int __maybe_unused mtk_smi_common_resume(struct device *dev) 706 { 707 struct mtk_smi *common = dev_get_drvdata(dev); 708 const struct mtk_smi_reg_pair *init = common->plat->init; 709 u32 bus_sel = common->plat->bus_sel; /* default is 0 */ 710 int ret, i; 711 712 ret = clk_bulk_prepare_enable(common->clk_num, common->clks); 713 if (ret) 714 return ret; 715 716 if (common->plat->type != MTK_SMI_GEN2) 717 return 0; 718 719 for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++) 720 writel_relaxed(init[i].value, common->base + init[i].offset); 721 722 writel(bus_sel, common->base + SMI_BUS_SEL); 723 return 0; 724 } 725 726 static int __maybe_unused mtk_smi_common_suspend(struct device *dev) 727 { 728 struct mtk_smi *common = dev_get_drvdata(dev); 729 730 clk_bulk_disable_unprepare(common->clk_num, common->clks); 731 return 0; 732 } 733 734 static const struct dev_pm_ops smi_common_pm_ops = { 735 SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL) 736 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 737 pm_runtime_force_resume) 738 }; 739 740 static struct platform_driver mtk_smi_common_driver = { 741 .probe = mtk_smi_common_probe, 742 .remove = mtk_smi_common_remove, 743 .driver = { 744 .name = "mtk-smi-common", 745 .of_match_table = mtk_smi_common_of_ids, 746 .pm = &smi_common_pm_ops, 747 } 748 }; 749 750 static struct platform_driver * const smidrivers[] = { 751 &mtk_smi_common_driver, 752 &mtk_smi_larb_driver, 753 }; 754 755 static int __init mtk_smi_init(void) 756 { 757 return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 758 } 759 module_init(mtk_smi_init); 760 761 static void __exit mtk_smi_exit(void) 762 { 763 platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 764 } 765 module_exit(mtk_smi_exit); 766 767 MODULE_DESCRIPTION("MediaTek SMI driver"); 768 MODULE_LICENSE("GPL v2"); 769