1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Yong Wu <yong.wu@mediatek.com> 5 */ 6 #include <linux/clk.h> 7 #include <linux/component.h> 8 #include <linux/device.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <soc/mediatek/smi.h> 17 #include <dt-bindings/memory/mt2701-larb-port.h> 18 19 /* mt8173 */ 20 #define SMI_LARB_MMU_EN 0xf00 21 22 /* mt2701 */ 23 #define REG_SMI_SECUR_CON_BASE 0x5c0 24 25 /* every register control 8 port, register offset 0x4 */ 26 #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2) 27 #define REG_SMI_SECUR_CON_ADDR(id) \ 28 (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id)) 29 30 /* 31 * every port have 4 bit to control, bit[port + 3] control virtual or physical, 32 * bit[port + 2 : port + 1] control the domain, bit[port] control the security 33 * or non-security. 34 */ 35 #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2))) 36 #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3) 37 /* mt2701 domain should be set to 3 */ 38 #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) 39 40 /* mt2712 */ 41 #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) 42 #define F_MMU_EN BIT(0) 43 44 /* SMI COMMON */ 45 #define SMI_BUS_SEL 0x220 46 #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) 47 /* All are MMU0 defaultly. Only specialize mmu1 here. */ 48 #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) 49 50 enum mtk_smi_gen { 51 MTK_SMI_GEN1, 52 MTK_SMI_GEN2 53 }; 54 55 struct mtk_smi_common_plat { 56 enum mtk_smi_gen gen; 57 bool has_gals; 58 u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ 59 }; 60 61 struct mtk_smi_larb_gen { 62 int port_in_larb[MTK_LARB_NR_MAX + 1]; 63 void (*config_port)(struct device *dev); 64 unsigned int larb_direct_to_common_mask; 65 bool has_gals; 66 }; 67 68 struct mtk_smi { 69 struct device *dev; 70 struct clk *clk_apb, *clk_smi; 71 struct clk *clk_gals0, *clk_gals1; 72 struct clk *clk_async; /*only needed by mt2701*/ 73 union { 74 void __iomem *smi_ao_base; /* only for gen1 */ 75 void __iomem *base; /* only for gen2 */ 76 }; 77 const struct mtk_smi_common_plat *plat; 78 }; 79 80 struct mtk_smi_larb { /* larb: local arbiter */ 81 struct mtk_smi smi; 82 void __iomem *base; 83 struct device *smi_common_dev; 84 const struct mtk_smi_larb_gen *larb_gen; 85 int larbid; 86 u32 *mmu; 87 }; 88 89 static int mtk_smi_clk_enable(const struct mtk_smi *smi) 90 { 91 int ret; 92 93 ret = clk_prepare_enable(smi->clk_apb); 94 if (ret) 95 return ret; 96 97 ret = clk_prepare_enable(smi->clk_smi); 98 if (ret) 99 goto err_disable_apb; 100 101 ret = clk_prepare_enable(smi->clk_gals0); 102 if (ret) 103 goto err_disable_smi; 104 105 ret = clk_prepare_enable(smi->clk_gals1); 106 if (ret) 107 goto err_disable_gals0; 108 109 return 0; 110 111 err_disable_gals0: 112 clk_disable_unprepare(smi->clk_gals0); 113 err_disable_smi: 114 clk_disable_unprepare(smi->clk_smi); 115 err_disable_apb: 116 clk_disable_unprepare(smi->clk_apb); 117 return ret; 118 } 119 120 static void mtk_smi_clk_disable(const struct mtk_smi *smi) 121 { 122 clk_disable_unprepare(smi->clk_gals1); 123 clk_disable_unprepare(smi->clk_gals0); 124 clk_disable_unprepare(smi->clk_smi); 125 clk_disable_unprepare(smi->clk_apb); 126 } 127 128 int mtk_smi_larb_get(struct device *larbdev) 129 { 130 int ret = pm_runtime_get_sync(larbdev); 131 132 return (ret < 0) ? ret : 0; 133 } 134 EXPORT_SYMBOL_GPL(mtk_smi_larb_get); 135 136 void mtk_smi_larb_put(struct device *larbdev) 137 { 138 pm_runtime_put_sync(larbdev); 139 } 140 EXPORT_SYMBOL_GPL(mtk_smi_larb_put); 141 142 static int 143 mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) 144 { 145 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 146 struct mtk_smi_larb_iommu *larb_mmu = data; 147 unsigned int i; 148 149 for (i = 0; i < MTK_LARB_NR_MAX; i++) { 150 if (dev == larb_mmu[i].dev) { 151 larb->larbid = i; 152 larb->mmu = &larb_mmu[i].mmu; 153 return 0; 154 } 155 } 156 return -ENODEV; 157 } 158 159 static void mtk_smi_larb_config_port_gen2_general(struct device *dev) 160 { 161 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 162 u32 reg; 163 int i; 164 165 if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) 166 return; 167 168 for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { 169 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); 170 reg |= F_MMU_EN; 171 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); 172 } 173 } 174 175 static void mtk_smi_larb_config_port_mt8173(struct device *dev) 176 { 177 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 178 179 writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN); 180 } 181 182 static void mtk_smi_larb_config_port_gen1(struct device *dev) 183 { 184 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 185 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 186 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); 187 int i, m4u_port_id, larb_port_num; 188 u32 sec_con_val, reg_val; 189 190 m4u_port_id = larb_gen->port_in_larb[larb->larbid]; 191 larb_port_num = larb_gen->port_in_larb[larb->larbid + 1] 192 - larb_gen->port_in_larb[larb->larbid]; 193 194 for (i = 0; i < larb_port_num; i++, m4u_port_id++) { 195 if (*larb->mmu & BIT(i)) { 196 /* bit[port + 3] controls the virtual or physical */ 197 sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id); 198 } else { 199 /* do not need to enable m4u for this port */ 200 continue; 201 } 202 reg_val = readl(common->smi_ao_base 203 + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 204 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); 205 reg_val |= sec_con_val; 206 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); 207 writel(reg_val, 208 common->smi_ao_base 209 + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 210 } 211 } 212 213 static void 214 mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) 215 { 216 /* Do nothing as the iommu is always enabled. */ 217 } 218 219 static const struct component_ops mtk_smi_larb_component_ops = { 220 .bind = mtk_smi_larb_bind, 221 .unbind = mtk_smi_larb_unbind, 222 }; 223 224 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { 225 /* mt8173 do not need the port in larb */ 226 .config_port = mtk_smi_larb_config_port_mt8173, 227 }; 228 229 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { 230 .port_in_larb = { 231 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 232 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 233 }, 234 .config_port = mtk_smi_larb_config_port_gen1, 235 }; 236 237 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { 238 .config_port = mtk_smi_larb_config_port_gen2_general, 239 .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ 240 }; 241 242 static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { 243 .config_port = mtk_smi_larb_config_port_gen2_general, 244 .larb_direct_to_common_mask = 245 BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), 246 /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ 247 }; 248 249 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { 250 .has_gals = true, 251 .config_port = mtk_smi_larb_config_port_gen2_general, 252 .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), 253 /* IPU0 | IPU1 | CCU */ 254 }; 255 256 static const struct of_device_id mtk_smi_larb_of_ids[] = { 257 { 258 .compatible = "mediatek,mt8173-smi-larb", 259 .data = &mtk_smi_larb_mt8173 260 }, 261 { 262 .compatible = "mediatek,mt2701-smi-larb", 263 .data = &mtk_smi_larb_mt2701 264 }, 265 { 266 .compatible = "mediatek,mt2712-smi-larb", 267 .data = &mtk_smi_larb_mt2712 268 }, 269 { 270 .compatible = "mediatek,mt6779-smi-larb", 271 .data = &mtk_smi_larb_mt6779 272 }, 273 { 274 .compatible = "mediatek,mt8183-smi-larb", 275 .data = &mtk_smi_larb_mt8183 276 }, 277 {} 278 }; 279 280 static int mtk_smi_larb_probe(struct platform_device *pdev) 281 { 282 struct mtk_smi_larb *larb; 283 struct resource *res; 284 struct device *dev = &pdev->dev; 285 struct device_node *smi_node; 286 struct platform_device *smi_pdev; 287 288 larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); 289 if (!larb) 290 return -ENOMEM; 291 292 larb->larb_gen = of_device_get_match_data(dev); 293 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 294 larb->base = devm_ioremap_resource(dev, res); 295 if (IS_ERR(larb->base)) 296 return PTR_ERR(larb->base); 297 298 larb->smi.clk_apb = devm_clk_get(dev, "apb"); 299 if (IS_ERR(larb->smi.clk_apb)) 300 return PTR_ERR(larb->smi.clk_apb); 301 302 larb->smi.clk_smi = devm_clk_get(dev, "smi"); 303 if (IS_ERR(larb->smi.clk_smi)) 304 return PTR_ERR(larb->smi.clk_smi); 305 306 if (larb->larb_gen->has_gals) { 307 /* The larbs may still haven't gals even if the SoC support.*/ 308 larb->smi.clk_gals0 = devm_clk_get(dev, "gals"); 309 if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT) 310 larb->smi.clk_gals0 = NULL; 311 else if (IS_ERR(larb->smi.clk_gals0)) 312 return PTR_ERR(larb->smi.clk_gals0); 313 } 314 larb->smi.dev = dev; 315 316 smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); 317 if (!smi_node) 318 return -EINVAL; 319 320 smi_pdev = of_find_device_by_node(smi_node); 321 of_node_put(smi_node); 322 if (smi_pdev) { 323 if (!platform_get_drvdata(smi_pdev)) 324 return -EPROBE_DEFER; 325 larb->smi_common_dev = &smi_pdev->dev; 326 } else { 327 dev_err(dev, "Failed to get the smi_common device\n"); 328 return -EINVAL; 329 } 330 331 pm_runtime_enable(dev); 332 platform_set_drvdata(pdev, larb); 333 return component_add(dev, &mtk_smi_larb_component_ops); 334 } 335 336 static int mtk_smi_larb_remove(struct platform_device *pdev) 337 { 338 pm_runtime_disable(&pdev->dev); 339 component_del(&pdev->dev, &mtk_smi_larb_component_ops); 340 return 0; 341 } 342 343 static int __maybe_unused mtk_smi_larb_resume(struct device *dev) 344 { 345 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 346 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 347 int ret; 348 349 /* Power on smi-common. */ 350 ret = pm_runtime_get_sync(larb->smi_common_dev); 351 if (ret < 0) { 352 dev_err(dev, "Failed to pm get for smi-common(%d).\n", ret); 353 return ret; 354 } 355 356 ret = mtk_smi_clk_enable(&larb->smi); 357 if (ret < 0) { 358 dev_err(dev, "Failed to enable clock(%d).\n", ret); 359 pm_runtime_put_sync(larb->smi_common_dev); 360 return ret; 361 } 362 363 /* Configure the basic setting for this larb */ 364 larb_gen->config_port(dev); 365 366 return 0; 367 } 368 369 static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) 370 { 371 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 372 373 mtk_smi_clk_disable(&larb->smi); 374 pm_runtime_put_sync(larb->smi_common_dev); 375 return 0; 376 } 377 378 static const struct dev_pm_ops smi_larb_pm_ops = { 379 SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL) 380 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 381 pm_runtime_force_resume) 382 }; 383 384 static struct platform_driver mtk_smi_larb_driver = { 385 .probe = mtk_smi_larb_probe, 386 .remove = mtk_smi_larb_remove, 387 .driver = { 388 .name = "mtk-smi-larb", 389 .of_match_table = mtk_smi_larb_of_ids, 390 .pm = &smi_larb_pm_ops, 391 } 392 }; 393 394 static const struct mtk_smi_common_plat mtk_smi_common_gen1 = { 395 .gen = MTK_SMI_GEN1, 396 }; 397 398 static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { 399 .gen = MTK_SMI_GEN2, 400 }; 401 402 static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { 403 .gen = MTK_SMI_GEN2, 404 .has_gals = true, 405 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | 406 F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), 407 }; 408 409 static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { 410 .gen = MTK_SMI_GEN2, 411 .has_gals = true, 412 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 413 F_MMU1_LARB(7), 414 }; 415 416 static const struct of_device_id mtk_smi_common_of_ids[] = { 417 { 418 .compatible = "mediatek,mt8173-smi-common", 419 .data = &mtk_smi_common_gen2, 420 }, 421 { 422 .compatible = "mediatek,mt2701-smi-common", 423 .data = &mtk_smi_common_gen1, 424 }, 425 { 426 .compatible = "mediatek,mt2712-smi-common", 427 .data = &mtk_smi_common_gen2, 428 }, 429 { 430 .compatible = "mediatek,mt6779-smi-common", 431 .data = &mtk_smi_common_mt6779, 432 }, 433 { 434 .compatible = "mediatek,mt8183-smi-common", 435 .data = &mtk_smi_common_mt8183, 436 }, 437 {} 438 }; 439 440 static int mtk_smi_common_probe(struct platform_device *pdev) 441 { 442 struct device *dev = &pdev->dev; 443 struct mtk_smi *common; 444 struct resource *res; 445 int ret; 446 447 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); 448 if (!common) 449 return -ENOMEM; 450 common->dev = dev; 451 common->plat = of_device_get_match_data(dev); 452 453 common->clk_apb = devm_clk_get(dev, "apb"); 454 if (IS_ERR(common->clk_apb)) 455 return PTR_ERR(common->clk_apb); 456 457 common->clk_smi = devm_clk_get(dev, "smi"); 458 if (IS_ERR(common->clk_smi)) 459 return PTR_ERR(common->clk_smi); 460 461 if (common->plat->has_gals) { 462 common->clk_gals0 = devm_clk_get(dev, "gals0"); 463 if (IS_ERR(common->clk_gals0)) 464 return PTR_ERR(common->clk_gals0); 465 466 common->clk_gals1 = devm_clk_get(dev, "gals1"); 467 if (IS_ERR(common->clk_gals1)) 468 return PTR_ERR(common->clk_gals1); 469 } 470 471 /* 472 * for mtk smi gen 1, we need to get the ao(always on) base to config 473 * m4u port, and we need to enable the aync clock for transform the smi 474 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao 475 * base. 476 */ 477 if (common->plat->gen == MTK_SMI_GEN1) { 478 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 479 common->smi_ao_base = devm_ioremap_resource(dev, res); 480 if (IS_ERR(common->smi_ao_base)) 481 return PTR_ERR(common->smi_ao_base); 482 483 common->clk_async = devm_clk_get(dev, "async"); 484 if (IS_ERR(common->clk_async)) 485 return PTR_ERR(common->clk_async); 486 487 ret = clk_prepare_enable(common->clk_async); 488 if (ret) 489 return ret; 490 } else { 491 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 492 common->base = devm_ioremap_resource(dev, res); 493 if (IS_ERR(common->base)) 494 return PTR_ERR(common->base); 495 } 496 pm_runtime_enable(dev); 497 platform_set_drvdata(pdev, common); 498 return 0; 499 } 500 501 static int mtk_smi_common_remove(struct platform_device *pdev) 502 { 503 pm_runtime_disable(&pdev->dev); 504 return 0; 505 } 506 507 static int __maybe_unused mtk_smi_common_resume(struct device *dev) 508 { 509 struct mtk_smi *common = dev_get_drvdata(dev); 510 u32 bus_sel = common->plat->bus_sel; 511 int ret; 512 513 ret = mtk_smi_clk_enable(common); 514 if (ret) { 515 dev_err(common->dev, "Failed to enable clock(%d).\n", ret); 516 return ret; 517 } 518 519 if (common->plat->gen == MTK_SMI_GEN2 && bus_sel) 520 writel(bus_sel, common->base + SMI_BUS_SEL); 521 return 0; 522 } 523 524 static int __maybe_unused mtk_smi_common_suspend(struct device *dev) 525 { 526 struct mtk_smi *common = dev_get_drvdata(dev); 527 528 mtk_smi_clk_disable(common); 529 return 0; 530 } 531 532 static const struct dev_pm_ops smi_common_pm_ops = { 533 SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL) 534 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 535 pm_runtime_force_resume) 536 }; 537 538 static struct platform_driver mtk_smi_common_driver = { 539 .probe = mtk_smi_common_probe, 540 .remove = mtk_smi_common_remove, 541 .driver = { 542 .name = "mtk-smi-common", 543 .of_match_table = mtk_smi_common_of_ids, 544 .pm = &smi_common_pm_ops, 545 } 546 }; 547 548 static int __init mtk_smi_init(void) 549 { 550 int ret; 551 552 ret = platform_driver_register(&mtk_smi_common_driver); 553 if (ret != 0) { 554 pr_err("Failed to register SMI driver\n"); 555 return ret; 556 } 557 558 ret = platform_driver_register(&mtk_smi_larb_driver); 559 if (ret != 0) { 560 pr_err("Failed to register SMI-LARB driver\n"); 561 goto err_unreg_smi; 562 } 563 return ret; 564 565 err_unreg_smi: 566 platform_driver_unregister(&mtk_smi_common_driver); 567 return ret; 568 } 569 570 module_init(mtk_smi_init); 571