1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Yong Wu <yong.wu@mediatek.com> 5 */ 6 #include <linux/clk.h> 7 #include <linux/component.h> 8 #include <linux/device.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_platform.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <soc/mediatek/smi.h> 18 #include <dt-bindings/memory/mt2701-larb-port.h> 19 #include <dt-bindings/memory/mtk-memory-port.h> 20 21 /* SMI COMMON */ 22 #define SMI_L1LEN 0x100 23 24 #define SMI_BUS_SEL 0x220 25 #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) 26 /* All are MMU0 defaultly. Only specialize mmu1 here. */ 27 #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) 28 29 #define SMI_M4U_TH 0x234 30 #define SMI_FIFO_TH1 0x238 31 #define SMI_FIFO_TH2 0x23c 32 #define SMI_DCM 0x300 33 #define SMI_DUMMY 0x444 34 35 /* SMI LARB */ 36 #define SMI_LARB_SLP_CON 0xc 37 #define SLP_PROT_EN BIT(0) 38 #define SLP_PROT_RDY BIT(16) 39 40 #define SMI_LARB_CMD_THRT_CON 0x24 41 #define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4) 42 #define SMI_LARB_THRT_RD_NU_LMT (5 << 4) 43 44 #define SMI_LARB_SW_FLAG 0x40 45 #define SMI_LARB_SW_FLAG_1 0x1 46 47 #define SMI_LARB_OSTDL_PORT 0x200 48 #define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2)) 49 50 /* Below are about mmu enable registers, they are different in SoCs */ 51 /* gen1: mt2701 */ 52 #define REG_SMI_SECUR_CON_BASE 0x5c0 53 54 /* every register control 8 port, register offset 0x4 */ 55 #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2) 56 #define REG_SMI_SECUR_CON_ADDR(id) \ 57 (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id)) 58 59 /* 60 * every port have 4 bit to control, bit[port + 3] control virtual or physical, 61 * bit[port + 2 : port + 1] control the domain, bit[port] control the security 62 * or non-security. 63 */ 64 #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2))) 65 #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3) 66 /* mt2701 domain should be set to 3 */ 67 #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) 68 69 /* gen2: */ 70 /* mt8167 */ 71 #define MT8167_SMI_LARB_MMU_EN 0xfc0 72 73 /* mt8173 */ 74 #define MT8173_SMI_LARB_MMU_EN 0xf00 75 76 /* general */ 77 #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) 78 #define F_MMU_EN BIT(0) 79 #define BANK_SEL(id) ({ \ 80 u32 _id = (id) & 0x3; \ 81 (_id << 8 | _id << 10 | _id << 12 | _id << 14); \ 82 }) 83 84 #define SMI_COMMON_INIT_REGS_NR 6 85 #define SMI_LARB_PORT_NR_MAX 32 86 87 #define MTK_SMI_FLAG_THRT_UPDATE BIT(0) 88 #define MTK_SMI_FLAG_SW_FLAG BIT(1) 89 #define MTK_SMI_FLAG_SLEEP_CTL BIT(2) 90 #define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x))) 91 92 struct mtk_smi_reg_pair { 93 unsigned int offset; 94 u32 value; 95 }; 96 97 enum mtk_smi_type { 98 MTK_SMI_GEN1, 99 MTK_SMI_GEN2, /* gen2 smi common */ 100 MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */ 101 }; 102 103 /* larbs: Require apb/smi clocks while gals is optional. */ 104 static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"}; 105 #define MTK_SMI_LARB_REQ_CLK_NR 2 106 #define MTK_SMI_LARB_OPT_CLK_NR 1 107 108 /* 109 * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required. 110 * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required. 111 */ 112 static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"}; 113 #define MTK_SMI_CLK_NR_MAX ARRAY_SIZE(mtk_smi_common_clks) 114 #define MTK_SMI_COM_REQ_CLK_NR 2 115 #define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX 116 #define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3 117 118 struct mtk_smi_common_plat { 119 enum mtk_smi_type type; 120 bool has_gals; 121 u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ 122 123 const struct mtk_smi_reg_pair *init; 124 }; 125 126 struct mtk_smi_larb_gen { 127 int port_in_larb[MTK_LARB_NR_MAX + 1]; 128 void (*config_port)(struct device *dev); 129 unsigned int larb_direct_to_common_mask; 130 unsigned int flags_general; 131 const u8 (*ostd)[SMI_LARB_PORT_NR_MAX]; 132 }; 133 134 struct mtk_smi { 135 struct device *dev; 136 unsigned int clk_num; 137 struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX]; 138 struct clk *clk_async; /*only needed by mt2701*/ 139 union { 140 void __iomem *smi_ao_base; /* only for gen1 */ 141 void __iomem *base; /* only for gen2 */ 142 }; 143 struct device *smi_common_dev; /* for sub common */ 144 const struct mtk_smi_common_plat *plat; 145 }; 146 147 struct mtk_smi_larb { /* larb: local arbiter */ 148 struct mtk_smi smi; 149 void __iomem *base; 150 struct device *smi_common_dev; /* common or sub-common dev */ 151 const struct mtk_smi_larb_gen *larb_gen; 152 int larbid; 153 u32 *mmu; 154 unsigned char *bank; 155 }; 156 157 static int 158 mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) 159 { 160 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 161 struct mtk_smi_larb_iommu *larb_mmu = data; 162 unsigned int i; 163 164 for (i = 0; i < MTK_LARB_NR_MAX; i++) { 165 if (dev == larb_mmu[i].dev) { 166 larb->larbid = i; 167 larb->mmu = &larb_mmu[i].mmu; 168 larb->bank = larb_mmu[i].bank; 169 return 0; 170 } 171 } 172 return -ENODEV; 173 } 174 175 static void 176 mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) 177 { 178 /* Do nothing as the iommu is always enabled. */ 179 } 180 181 static const struct component_ops mtk_smi_larb_component_ops = { 182 .bind = mtk_smi_larb_bind, 183 .unbind = mtk_smi_larb_unbind, 184 }; 185 186 static void mtk_smi_larb_config_port_gen1(struct device *dev) 187 { 188 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 189 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 190 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); 191 int i, m4u_port_id, larb_port_num; 192 u32 sec_con_val, reg_val; 193 194 m4u_port_id = larb_gen->port_in_larb[larb->larbid]; 195 larb_port_num = larb_gen->port_in_larb[larb->larbid + 1] 196 - larb_gen->port_in_larb[larb->larbid]; 197 198 for (i = 0; i < larb_port_num; i++, m4u_port_id++) { 199 if (*larb->mmu & BIT(i)) { 200 /* bit[port + 3] controls the virtual or physical */ 201 sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id); 202 } else { 203 /* do not need to enable m4u for this port */ 204 continue; 205 } 206 reg_val = readl(common->smi_ao_base 207 + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 208 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); 209 reg_val |= sec_con_val; 210 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); 211 writel(reg_val, 212 common->smi_ao_base 213 + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 214 } 215 } 216 217 static void mtk_smi_larb_config_port_mt8167(struct device *dev) 218 { 219 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 220 221 writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); 222 } 223 224 static void mtk_smi_larb_config_port_mt8173(struct device *dev) 225 { 226 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 227 228 writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN); 229 } 230 231 static void mtk_smi_larb_config_port_gen2_general(struct device *dev) 232 { 233 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 234 u32 reg, flags_general = larb->larb_gen->flags_general; 235 const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL; 236 int i; 237 238 if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) 239 return; 240 241 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) { 242 reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON); 243 reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK; 244 reg |= SMI_LARB_THRT_RD_NU_LMT; 245 writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON); 246 } 247 248 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG)) 249 writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); 250 251 for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) 252 writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); 253 254 for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { 255 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); 256 reg |= F_MMU_EN; 257 reg |= BANK_SEL(larb->bank[i]); 258 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); 259 } 260 } 261 262 static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = { 263 [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */ 264 [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */ 265 [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, /* ... */ 266 [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,}, 267 [4] = {0x06, 0x01, 0x17, 0x06, 0x0a,}, 268 [5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,}, 269 [6] = {0x06, 0x01, 0x06, 0x0a,}, 270 [7] = {0x0c, 0x0c, 0x12,}, 271 [8] = {0x0c, 0x0c, 0x12,}, 272 [9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a, 273 0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,}, 274 [10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10, 275 0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d, 276 0x0d, 0x06, 0x10, 0x10,}, 277 [11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,}, 278 [12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,}, 279 [13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,}, 280 [14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01, 281 0x01, 0x02, 0x02, 0x08, 0x02,}, 282 [15] = {}, 283 [16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a, 284 0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,}, 285 [17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 286 [18] = {0x12, 0x06, 0x12, 0x06,}, 287 [19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 288 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 289 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 290 [20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 291 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 292 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 293 [21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 294 [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 295 [23] = {0x18, 0x01,}, 296 [24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01, 297 0x01, 0x01,}, 298 [25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 299 0x02, 0x01,}, 300 [26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 301 0x02, 0x01,}, 302 [27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 303 0x02, 0x01,}, 304 [28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 305 }; 306 307 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { 308 .port_in_larb = { 309 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 310 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 311 }, 312 .config_port = mtk_smi_larb_config_port_gen1, 313 }; 314 315 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { 316 .config_port = mtk_smi_larb_config_port_gen2_general, 317 .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ 318 }; 319 320 static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { 321 .config_port = mtk_smi_larb_config_port_gen2_general, 322 .larb_direct_to_common_mask = 323 BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), 324 /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ 325 }; 326 327 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = { 328 /* mt8167 do not need the port in larb */ 329 .config_port = mtk_smi_larb_config_port_mt8167, 330 }; 331 332 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { 333 /* mt8173 do not need the port in larb */ 334 .config_port = mtk_smi_larb_config_port_mt8173, 335 }; 336 337 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { 338 .config_port = mtk_smi_larb_config_port_gen2_general, 339 .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), 340 /* IPU0 | IPU1 | CCU */ 341 }; 342 343 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = { 344 .config_port = mtk_smi_larb_config_port_gen2_general, 345 .flags_general = MTK_SMI_FLAG_SLEEP_CTL, 346 }; 347 348 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { 349 .config_port = mtk_smi_larb_config_port_gen2_general, 350 }; 351 352 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = { 353 .config_port = mtk_smi_larb_config_port_gen2_general, 354 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG | 355 MTK_SMI_FLAG_SLEEP_CTL, 356 .ostd = mtk_smi_larb_mt8195_ostd, 357 }; 358 359 static const struct of_device_id mtk_smi_larb_of_ids[] = { 360 {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701}, 361 {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712}, 362 {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779}, 363 {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167}, 364 {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173}, 365 {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, 366 {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186}, 367 {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, 368 {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195}, 369 {} 370 }; 371 372 static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb) 373 { 374 int ret; 375 u32 tmp; 376 377 writel_relaxed(SLP_PROT_EN, larb->base + SMI_LARB_SLP_CON); 378 ret = readl_poll_timeout_atomic(larb->base + SMI_LARB_SLP_CON, 379 tmp, !!(tmp & SLP_PROT_RDY), 10, 1000); 380 if (ret) { 381 /* TODO: Reset this larb if it fails here. */ 382 dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp); 383 } 384 return ret; 385 } 386 387 static void mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb *larb) 388 { 389 writel_relaxed(0, larb->base + SMI_LARB_SLP_CON); 390 } 391 392 static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev) 393 { 394 struct platform_device *smi_com_pdev; 395 struct device_node *smi_com_node; 396 struct device *smi_com_dev; 397 struct device_link *link; 398 399 smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); 400 if (!smi_com_node) 401 return -EINVAL; 402 403 smi_com_pdev = of_find_device_by_node(smi_com_node); 404 of_node_put(smi_com_node); 405 if (smi_com_pdev) { 406 /* smi common is the supplier, Make sure it is ready before */ 407 if (!platform_get_drvdata(smi_com_pdev)) { 408 put_device(&smi_com_pdev->dev); 409 return -EPROBE_DEFER; 410 } 411 smi_com_dev = &smi_com_pdev->dev; 412 link = device_link_add(dev, smi_com_dev, 413 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 414 if (!link) { 415 dev_err(dev, "Unable to link smi-common dev\n"); 416 put_device(&smi_com_pdev->dev); 417 return -ENODEV; 418 } 419 *com_dev = smi_com_dev; 420 } else { 421 dev_err(dev, "Failed to get the smi_common device\n"); 422 return -EINVAL; 423 } 424 return 0; 425 } 426 427 static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi, 428 const char * const clks[], 429 unsigned int clk_nr_required, 430 unsigned int clk_nr_optional) 431 { 432 int i, ret; 433 434 for (i = 0; i < clk_nr_required; i++) 435 smi->clks[i].id = clks[i]; 436 ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks); 437 if (ret) 438 return ret; 439 440 for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++) 441 smi->clks[i].id = clks[i]; 442 ret = devm_clk_bulk_get_optional(dev, clk_nr_optional, 443 smi->clks + clk_nr_required); 444 smi->clk_num = clk_nr_required + clk_nr_optional; 445 return ret; 446 } 447 448 static int mtk_smi_larb_probe(struct platform_device *pdev) 449 { 450 struct mtk_smi_larb *larb; 451 struct device *dev = &pdev->dev; 452 int ret; 453 454 larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); 455 if (!larb) 456 return -ENOMEM; 457 458 larb->larb_gen = of_device_get_match_data(dev); 459 larb->base = devm_platform_ioremap_resource(pdev, 0); 460 if (IS_ERR(larb->base)) 461 return PTR_ERR(larb->base); 462 463 ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks, 464 MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR); 465 if (ret) 466 return ret; 467 468 larb->smi.dev = dev; 469 470 ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev); 471 if (ret < 0) 472 return ret; 473 474 pm_runtime_enable(dev); 475 platform_set_drvdata(pdev, larb); 476 ret = component_add(dev, &mtk_smi_larb_component_ops); 477 if (ret) 478 goto err_pm_disable; 479 return 0; 480 481 err_pm_disable: 482 pm_runtime_disable(dev); 483 device_link_remove(dev, larb->smi_common_dev); 484 return ret; 485 } 486 487 static int mtk_smi_larb_remove(struct platform_device *pdev) 488 { 489 struct mtk_smi_larb *larb = platform_get_drvdata(pdev); 490 491 device_link_remove(&pdev->dev, larb->smi_common_dev); 492 pm_runtime_disable(&pdev->dev); 493 component_del(&pdev->dev, &mtk_smi_larb_component_ops); 494 return 0; 495 } 496 497 static int __maybe_unused mtk_smi_larb_resume(struct device *dev) 498 { 499 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 500 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 501 int ret; 502 503 ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks); 504 if (ret) 505 return ret; 506 507 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) 508 mtk_smi_larb_sleep_ctrl_disable(larb); 509 510 /* Configure the basic setting for this larb */ 511 larb_gen->config_port(dev); 512 513 return 0; 514 } 515 516 static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) 517 { 518 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 519 int ret; 520 521 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) { 522 ret = mtk_smi_larb_sleep_ctrl_enable(larb); 523 if (ret) 524 return ret; 525 } 526 527 clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks); 528 return 0; 529 } 530 531 static const struct dev_pm_ops smi_larb_pm_ops = { 532 SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL) 533 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 534 pm_runtime_force_resume) 535 }; 536 537 static struct platform_driver mtk_smi_larb_driver = { 538 .probe = mtk_smi_larb_probe, 539 .remove = mtk_smi_larb_remove, 540 .driver = { 541 .name = "mtk-smi-larb", 542 .of_match_table = mtk_smi_larb_of_ids, 543 .pm = &smi_larb_pm_ops, 544 } 545 }; 546 547 static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = { 548 {SMI_L1LEN, 0xb}, 549 {SMI_M4U_TH, 0xe100e10}, 550 {SMI_FIFO_TH1, 0x506090a}, 551 {SMI_FIFO_TH2, 0x506090a}, 552 {SMI_DCM, 0x4f1}, 553 {SMI_DUMMY, 0x1}, 554 }; 555 556 static const struct mtk_smi_common_plat mtk_smi_common_gen1 = { 557 .type = MTK_SMI_GEN1, 558 }; 559 560 static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { 561 .type = MTK_SMI_GEN2, 562 }; 563 564 static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { 565 .type = MTK_SMI_GEN2, 566 .has_gals = true, 567 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | 568 F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), 569 }; 570 571 static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { 572 .type = MTK_SMI_GEN2, 573 .has_gals = true, 574 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 575 F_MMU1_LARB(7), 576 }; 577 578 static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = { 579 .type = MTK_SMI_GEN2, 580 .has_gals = true, 581 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7), 582 }; 583 584 static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { 585 .type = MTK_SMI_GEN2, 586 .has_gals = true, 587 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 588 F_MMU1_LARB(6), 589 }; 590 591 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = { 592 .type = MTK_SMI_GEN2, 593 .has_gals = true, 594 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) | 595 F_MMU1_LARB(7), 596 .init = mtk_smi_common_mt8195_init, 597 }; 598 599 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = { 600 .type = MTK_SMI_GEN2, 601 .has_gals = true, 602 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7), 603 .init = mtk_smi_common_mt8195_init, 604 }; 605 606 static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = { 607 .type = MTK_SMI_GEN2_SUB_COMM, 608 .has_gals = true, 609 }; 610 611 static const struct of_device_id mtk_smi_common_of_ids[] = { 612 {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1}, 613 {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2}, 614 {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779}, 615 {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2}, 616 {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2}, 617 {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183}, 618 {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186}, 619 {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, 620 {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, 621 {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, 622 {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195}, 623 {} 624 }; 625 626 static int mtk_smi_common_probe(struct platform_device *pdev) 627 { 628 struct device *dev = &pdev->dev; 629 struct mtk_smi *common; 630 int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR; 631 632 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); 633 if (!common) 634 return -ENOMEM; 635 common->dev = dev; 636 common->plat = of_device_get_match_data(dev); 637 638 if (common->plat->has_gals) { 639 if (common->plat->type == MTK_SMI_GEN2) 640 clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR; 641 else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 642 clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR; 643 } 644 ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0); 645 if (ret) 646 return ret; 647 648 /* 649 * for mtk smi gen 1, we need to get the ao(always on) base to config 650 * m4u port, and we need to enable the aync clock for transform the smi 651 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao 652 * base. 653 */ 654 if (common->plat->type == MTK_SMI_GEN1) { 655 common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0); 656 if (IS_ERR(common->smi_ao_base)) 657 return PTR_ERR(common->smi_ao_base); 658 659 common->clk_async = devm_clk_get(dev, "async"); 660 if (IS_ERR(common->clk_async)) 661 return PTR_ERR(common->clk_async); 662 663 ret = clk_prepare_enable(common->clk_async); 664 if (ret) 665 return ret; 666 } else { 667 common->base = devm_platform_ioremap_resource(pdev, 0); 668 if (IS_ERR(common->base)) 669 return PTR_ERR(common->base); 670 } 671 672 /* link its smi-common if this is smi-sub-common */ 673 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) { 674 ret = mtk_smi_device_link_common(dev, &common->smi_common_dev); 675 if (ret < 0) 676 return ret; 677 } 678 679 pm_runtime_enable(dev); 680 platform_set_drvdata(pdev, common); 681 return 0; 682 } 683 684 static int mtk_smi_common_remove(struct platform_device *pdev) 685 { 686 struct mtk_smi *common = dev_get_drvdata(&pdev->dev); 687 688 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 689 device_link_remove(&pdev->dev, common->smi_common_dev); 690 pm_runtime_disable(&pdev->dev); 691 return 0; 692 } 693 694 static int __maybe_unused mtk_smi_common_resume(struct device *dev) 695 { 696 struct mtk_smi *common = dev_get_drvdata(dev); 697 const struct mtk_smi_reg_pair *init = common->plat->init; 698 u32 bus_sel = common->plat->bus_sel; /* default is 0 */ 699 int ret, i; 700 701 ret = clk_bulk_prepare_enable(common->clk_num, common->clks); 702 if (ret) 703 return ret; 704 705 if (common->plat->type != MTK_SMI_GEN2) 706 return 0; 707 708 for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++) 709 writel_relaxed(init[i].value, common->base + init[i].offset); 710 711 writel(bus_sel, common->base + SMI_BUS_SEL); 712 return 0; 713 } 714 715 static int __maybe_unused mtk_smi_common_suspend(struct device *dev) 716 { 717 struct mtk_smi *common = dev_get_drvdata(dev); 718 719 clk_bulk_disable_unprepare(common->clk_num, common->clks); 720 return 0; 721 } 722 723 static const struct dev_pm_ops smi_common_pm_ops = { 724 SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL) 725 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 726 pm_runtime_force_resume) 727 }; 728 729 static struct platform_driver mtk_smi_common_driver = { 730 .probe = mtk_smi_common_probe, 731 .remove = mtk_smi_common_remove, 732 .driver = { 733 .name = "mtk-smi-common", 734 .of_match_table = mtk_smi_common_of_ids, 735 .pm = &smi_common_pm_ops, 736 } 737 }; 738 739 static struct platform_driver * const smidrivers[] = { 740 &mtk_smi_common_driver, 741 &mtk_smi_larb_driver, 742 }; 743 744 static int __init mtk_smi_init(void) 745 { 746 return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 747 } 748 module_init(mtk_smi_init); 749 750 static void __exit mtk_smi_exit(void) 751 { 752 platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 753 } 754 module_exit(mtk_smi_exit); 755 756 MODULE_DESCRIPTION("MediaTek SMI driver"); 757 MODULE_LICENSE("GPL v2"); 758