11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2cc8bbe1aSYong Wu /* 3cc8bbe1aSYong Wu * Copyright (c) 2015-2016 MediaTek Inc. 4cc8bbe1aSYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 5cc8bbe1aSYong Wu */ 6cc8bbe1aSYong Wu #include <linux/clk.h> 7cc8bbe1aSYong Wu #include <linux/component.h> 8cc8bbe1aSYong Wu #include <linux/device.h> 9cc8bbe1aSYong Wu #include <linux/err.h> 10cc8bbe1aSYong Wu #include <linux/io.h> 114f608d38SYong Wu #include <linux/module.h> 12cc8bbe1aSYong Wu #include <linux/of.h> 13cc8bbe1aSYong Wu #include <linux/of_platform.h> 14cc8bbe1aSYong Wu #include <linux/platform_device.h> 15cc8bbe1aSYong Wu #include <linux/pm_runtime.h> 16cc8bbe1aSYong Wu #include <soc/mediatek/smi.h> 173c8f4ad8SHonghui Zhang #include <dt-bindings/memory/mt2701-larb-port.h> 1866a28915SYong Wu #include <dt-bindings/memory/mtk-memory-port.h> 19cc8bbe1aSYong Wu 20534e0ad2SYong Wu /* SMI COMMON */ 21534e0ad2SYong Wu #define SMI_BUS_SEL 0x220 22534e0ad2SYong Wu #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) 23534e0ad2SYong Wu /* All are MMU0 defaultly. Only specialize mmu1 here. */ 24534e0ad2SYong Wu #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) 25e6dec923SYong Wu 26534e0ad2SYong Wu /* SMI LARB */ 27a8529f3bSFabien Parent 28534e0ad2SYong Wu /* Below are about mmu enable registers, they are different in SoCs */ 29534e0ad2SYong Wu /* gen1: mt2701 */ 303c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_BASE 0x5c0 313c8f4ad8SHonghui Zhang 323c8f4ad8SHonghui Zhang /* every register control 8 port, register offset 0x4 */ 333c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2) 343c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_ADDR(id) \ 353c8f4ad8SHonghui Zhang (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id)) 363c8f4ad8SHonghui Zhang 373c8f4ad8SHonghui Zhang /* 383c8f4ad8SHonghui Zhang * every port have 4 bit to control, bit[port + 3] control virtual or physical, 393c8f4ad8SHonghui Zhang * bit[port + 2 : port + 1] control the domain, bit[port] control the security 403c8f4ad8SHonghui Zhang * or non-security. 413c8f4ad8SHonghui Zhang */ 423c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2))) 433c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3) 443c8f4ad8SHonghui Zhang /* mt2701 domain should be set to 3 */ 453c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) 463c8f4ad8SHonghui Zhang 47534e0ad2SYong Wu /* gen2: */ 48534e0ad2SYong Wu /* mt8167 */ 49534e0ad2SYong Wu #define MT8167_SMI_LARB_MMU_EN 0xfc0 50534e0ad2SYong Wu 51534e0ad2SYong Wu /* mt8173 */ 52534e0ad2SYong Wu #define MT8173_SMI_LARB_MMU_EN 0xf00 53534e0ad2SYong Wu 54534e0ad2SYong Wu /* general */ 55e6dec923SYong Wu #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) 56e6dec923SYong Wu #define F_MMU_EN BIT(0) 578d2c749eSYong Wu #define BANK_SEL(id) ({ \ 588d2c749eSYong Wu u32 _id = (id) & 0x3; \ 598d2c749eSYong Wu (_id << 8 | _id << 10 | _id << 12 | _id << 14); \ 608d2c749eSYong Wu }) 61e6dec923SYong Wu 62a5c18986SYong Wu enum mtk_smi_type { 6342d42c76SYong Wu MTK_SMI_GEN1, 6447404757SYong Wu MTK_SMI_GEN2, /* gen2 smi common */ 6547404757SYong Wu MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */ 6642d42c76SYong Wu }; 6742d42c76SYong Wu 680e14917cSYong Wu #define MTK_SMI_CLK_NR_MAX 4 690e14917cSYong Wu 700e14917cSYong Wu /* larbs: Require apb/smi clocks while gals is optional. */ 710e14917cSYong Wu static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"}; 720e14917cSYong Wu #define MTK_SMI_LARB_REQ_CLK_NR 2 730e14917cSYong Wu #define MTK_SMI_LARB_OPT_CLK_NR 1 740e14917cSYong Wu 750e14917cSYong Wu /* 760e14917cSYong Wu * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required. 773e4f74e0SYong Wu * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required. 780e14917cSYong Wu */ 790e14917cSYong Wu static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"}; 800e14917cSYong Wu #define MTK_SMI_COM_REQ_CLK_NR 2 810e14917cSYong Wu #define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX 823e4f74e0SYong Wu #define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3 830e14917cSYong Wu 8442d42c76SYong Wu struct mtk_smi_common_plat { 85a5c18986SYong Wu enum mtk_smi_type type; 8664fea74aSYong Wu bool has_gals; 87567e58cfSYong Wu u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ 8842d42c76SYong Wu }; 8942d42c76SYong Wu 903c8f4ad8SHonghui Zhang struct mtk_smi_larb_gen { 913c8f4ad8SHonghui Zhang int port_in_larb[MTK_LARB_NR_MAX + 1]; 923aa5a6c2SKrzysztof Kozlowski void (*config_port)(struct device *dev); 932e9b0908SYong Wu unsigned int larb_direct_to_common_mask; 943c8f4ad8SHonghui Zhang }; 95cc8bbe1aSYong Wu 96cc8bbe1aSYong Wu struct mtk_smi { 97cc8bbe1aSYong Wu struct device *dev; 980e14917cSYong Wu unsigned int clk_num; 990e14917cSYong Wu struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX]; 1003c8f4ad8SHonghui Zhang struct clk *clk_async; /*only needed by mt2701*/ 101567e58cfSYong Wu union { 102567e58cfSYong Wu void __iomem *smi_ao_base; /* only for gen1 */ 103567e58cfSYong Wu void __iomem *base; /* only for gen2 */ 104567e58cfSYong Wu }; 10547404757SYong Wu struct device *smi_common_dev; /* for sub common */ 10642d42c76SYong Wu const struct mtk_smi_common_plat *plat; 107cc8bbe1aSYong Wu }; 108cc8bbe1aSYong Wu 109cc8bbe1aSYong Wu struct mtk_smi_larb { /* larb: local arbiter */ 110cc8bbe1aSYong Wu struct mtk_smi smi; 111cc8bbe1aSYong Wu void __iomem *base; 11247404757SYong Wu struct device *smi_common_dev; /* common or sub-common dev */ 1133c8f4ad8SHonghui Zhang const struct mtk_smi_larb_gen *larb_gen; 1143c8f4ad8SHonghui Zhang int larbid; 115cc8bbe1aSYong Wu u32 *mmu; 1168d2c749eSYong Wu unsigned char *bank; 117cc8bbe1aSYong Wu }; 118cc8bbe1aSYong Wu 119cc8bbe1aSYong Wu int mtk_smi_larb_get(struct device *larbdev) 120cc8bbe1aSYong Wu { 121a2d522ffSZhang Qilong int ret = pm_runtime_resume_and_get(larbdev); 122cc8bbe1aSYong Wu 1234f0a1a1aSYong Wu return (ret < 0) ? ret : 0; 124cc8bbe1aSYong Wu } 125cb1b5dffSPhilipp Zabel EXPORT_SYMBOL_GPL(mtk_smi_larb_get); 126cc8bbe1aSYong Wu 127cc8bbe1aSYong Wu void mtk_smi_larb_put(struct device *larbdev) 128cc8bbe1aSYong Wu { 1294f0a1a1aSYong Wu pm_runtime_put_sync(larbdev); 130cc8bbe1aSYong Wu } 131cb1b5dffSPhilipp Zabel EXPORT_SYMBOL_GPL(mtk_smi_larb_put); 132cc8bbe1aSYong Wu 133cc8bbe1aSYong Wu static int 134cc8bbe1aSYong Wu mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) 135cc8bbe1aSYong Wu { 136cc8bbe1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 1371ee9feb2SYong Wu struct mtk_smi_larb_iommu *larb_mmu = data; 138cc8bbe1aSYong Wu unsigned int i; 139cc8bbe1aSYong Wu 140ec2da07cSYong Wu for (i = 0; i < MTK_LARB_NR_MAX; i++) { 1411ee9feb2SYong Wu if (dev == larb_mmu[i].dev) { 142ec2da07cSYong Wu larb->larbid = i; 1431ee9feb2SYong Wu larb->mmu = &larb_mmu[i].mmu; 1448d2c749eSYong Wu larb->bank = larb_mmu[i].bank; 145cc8bbe1aSYong Wu return 0; 146cc8bbe1aSYong Wu } 147cc8bbe1aSYong Wu } 148cc8bbe1aSYong Wu return -ENODEV; 149cc8bbe1aSYong Wu } 150cc8bbe1aSYong Wu 151534e0ad2SYong Wu static void 152534e0ad2SYong Wu mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) 153e6dec923SYong Wu { 154534e0ad2SYong Wu /* Do nothing as the iommu is always enabled. */ 155e6dec923SYong Wu } 156e6dec923SYong Wu 157534e0ad2SYong Wu static const struct component_ops mtk_smi_larb_component_ops = { 158534e0ad2SYong Wu .bind = mtk_smi_larb_bind, 159534e0ad2SYong Wu .unbind = mtk_smi_larb_unbind, 160534e0ad2SYong Wu }; 161a8529f3bSFabien Parent 1623c8f4ad8SHonghui Zhang static void mtk_smi_larb_config_port_gen1(struct device *dev) 1633c8f4ad8SHonghui Zhang { 1643c8f4ad8SHonghui Zhang struct mtk_smi_larb *larb = dev_get_drvdata(dev); 1653c8f4ad8SHonghui Zhang const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 1663c8f4ad8SHonghui Zhang struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); 1673c8f4ad8SHonghui Zhang int i, m4u_port_id, larb_port_num; 1683c8f4ad8SHonghui Zhang u32 sec_con_val, reg_val; 1693c8f4ad8SHonghui Zhang 1703c8f4ad8SHonghui Zhang m4u_port_id = larb_gen->port_in_larb[larb->larbid]; 1713c8f4ad8SHonghui Zhang larb_port_num = larb_gen->port_in_larb[larb->larbid + 1] 1723c8f4ad8SHonghui Zhang - larb_gen->port_in_larb[larb->larbid]; 1733c8f4ad8SHonghui Zhang 1743c8f4ad8SHonghui Zhang for (i = 0; i < larb_port_num; i++, m4u_port_id++) { 1753c8f4ad8SHonghui Zhang if (*larb->mmu & BIT(i)) { 1763c8f4ad8SHonghui Zhang /* bit[port + 3] controls the virtual or physical */ 1773c8f4ad8SHonghui Zhang sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id); 1783c8f4ad8SHonghui Zhang } else { 1793c8f4ad8SHonghui Zhang /* do not need to enable m4u for this port */ 1803c8f4ad8SHonghui Zhang continue; 1813c8f4ad8SHonghui Zhang } 1823c8f4ad8SHonghui Zhang reg_val = readl(common->smi_ao_base 1833c8f4ad8SHonghui Zhang + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 1843c8f4ad8SHonghui Zhang reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); 1853c8f4ad8SHonghui Zhang reg_val |= sec_con_val; 1863c8f4ad8SHonghui Zhang reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); 1873c8f4ad8SHonghui Zhang writel(reg_val, 1883c8f4ad8SHonghui Zhang common->smi_ao_base 1893c8f4ad8SHonghui Zhang + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 1903c8f4ad8SHonghui Zhang } 1913c8f4ad8SHonghui Zhang } 1923c8f4ad8SHonghui Zhang 193534e0ad2SYong Wu static void mtk_smi_larb_config_port_mt8167(struct device *dev) 194cc8bbe1aSYong Wu { 195534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 196534e0ad2SYong Wu 197534e0ad2SYong Wu writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); 198cc8bbe1aSYong Wu } 199cc8bbe1aSYong Wu 200534e0ad2SYong Wu static void mtk_smi_larb_config_port_mt8173(struct device *dev) 201534e0ad2SYong Wu { 202534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 203cc8bbe1aSYong Wu 204534e0ad2SYong Wu writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN); 205534e0ad2SYong Wu } 2063c8f4ad8SHonghui Zhang 207534e0ad2SYong Wu static void mtk_smi_larb_config_port_gen2_general(struct device *dev) 208534e0ad2SYong Wu { 209534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 210534e0ad2SYong Wu u32 reg; 211534e0ad2SYong Wu int i; 212534e0ad2SYong Wu 213534e0ad2SYong Wu if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) 214534e0ad2SYong Wu return; 215534e0ad2SYong Wu 216534e0ad2SYong Wu for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { 217534e0ad2SYong Wu reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); 218534e0ad2SYong Wu reg |= F_MMU_EN; 219534e0ad2SYong Wu reg |= BANK_SEL(larb->bank[i]); 220534e0ad2SYong Wu writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); 221534e0ad2SYong Wu } 222534e0ad2SYong Wu } 223a8529f3bSFabien Parent 2243c8f4ad8SHonghui Zhang static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { 2253c8f4ad8SHonghui Zhang .port_in_larb = { 2263c8f4ad8SHonghui Zhang LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 2273c8f4ad8SHonghui Zhang LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 2283c8f4ad8SHonghui Zhang }, 2293c8f4ad8SHonghui Zhang .config_port = mtk_smi_larb_config_port_gen1, 2303c8f4ad8SHonghui Zhang }; 2313c8f4ad8SHonghui Zhang 232e6dec923SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { 2332e9b0908SYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 2342e9b0908SYong Wu .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ 235e6dec923SYong Wu }; 236e6dec923SYong Wu 237fc492f33SMing-Fan Chen static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { 238fc492f33SMing-Fan Chen .config_port = mtk_smi_larb_config_port_gen2_general, 239fc492f33SMing-Fan Chen .larb_direct_to_common_mask = 240fc492f33SMing-Fan Chen BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), 241fc492f33SMing-Fan Chen /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ 242fc492f33SMing-Fan Chen }; 243fc492f33SMing-Fan Chen 244534e0ad2SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = { 245534e0ad2SYong Wu /* mt8167 do not need the port in larb */ 246534e0ad2SYong Wu .config_port = mtk_smi_larb_config_port_mt8167, 247534e0ad2SYong Wu }; 248534e0ad2SYong Wu 249534e0ad2SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { 250534e0ad2SYong Wu /* mt8173 do not need the port in larb */ 251534e0ad2SYong Wu .config_port = mtk_smi_larb_config_port_mt8173, 252534e0ad2SYong Wu }; 253534e0ad2SYong Wu 254907ba6a1SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { 255907ba6a1SYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 256907ba6a1SYong Wu .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), 257907ba6a1SYong Wu /* IPU0 | IPU1 | CCU */ 258907ba6a1SYong Wu }; 259907ba6a1SYong Wu 26002c02ddcSYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { 26102c02ddcSYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 26202c02ddcSYong Wu }; 26302c02ddcSYong Wu 264*cc4f9dcdSYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = { 265*cc4f9dcdSYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 266*cc4f9dcdSYong Wu }; 267*cc4f9dcdSYong Wu 2683c8f4ad8SHonghui Zhang static const struct of_device_id mtk_smi_larb_of_ids[] = { 269534e0ad2SYong Wu {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701}, 270534e0ad2SYong Wu {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712}, 271534e0ad2SYong Wu {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779}, 272534e0ad2SYong Wu {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167}, 273534e0ad2SYong Wu {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173}, 274534e0ad2SYong Wu {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, 275534e0ad2SYong Wu {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, 276*cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195}, 2773c8f4ad8SHonghui Zhang {} 2783c8f4ad8SHonghui Zhang }; 2793c8f4ad8SHonghui Zhang 28047404757SYong Wu static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev) 28147404757SYong Wu { 28247404757SYong Wu struct platform_device *smi_com_pdev; 28347404757SYong Wu struct device_node *smi_com_node; 28447404757SYong Wu struct device *smi_com_dev; 28547404757SYong Wu struct device_link *link; 28647404757SYong Wu 28747404757SYong Wu smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); 28847404757SYong Wu if (!smi_com_node) 28947404757SYong Wu return -EINVAL; 29047404757SYong Wu 29147404757SYong Wu smi_com_pdev = of_find_device_by_node(smi_com_node); 29247404757SYong Wu of_node_put(smi_com_node); 29347404757SYong Wu if (smi_com_pdev) { 29447404757SYong Wu /* smi common is the supplier, Make sure it is ready before */ 29547404757SYong Wu if (!platform_get_drvdata(smi_com_pdev)) 29647404757SYong Wu return -EPROBE_DEFER; 29747404757SYong Wu smi_com_dev = &smi_com_pdev->dev; 29847404757SYong Wu link = device_link_add(dev, smi_com_dev, 29947404757SYong Wu DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 30047404757SYong Wu if (!link) { 30147404757SYong Wu dev_err(dev, "Unable to link smi-common dev\n"); 30247404757SYong Wu return -ENODEV; 30347404757SYong Wu } 30447404757SYong Wu *com_dev = smi_com_dev; 30547404757SYong Wu } else { 30647404757SYong Wu dev_err(dev, "Failed to get the smi_common device\n"); 30747404757SYong Wu return -EINVAL; 30847404757SYong Wu } 30947404757SYong Wu return 0; 31047404757SYong Wu } 31147404757SYong Wu 3120e14917cSYong Wu static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi, 3130e14917cSYong Wu const char * const clks[], 3140e14917cSYong Wu unsigned int clk_nr_required, 3150e14917cSYong Wu unsigned int clk_nr_optional) 3160e14917cSYong Wu { 3170e14917cSYong Wu int i, ret; 3180e14917cSYong Wu 3190e14917cSYong Wu for (i = 0; i < clk_nr_required; i++) 3200e14917cSYong Wu smi->clks[i].id = clks[i]; 3210e14917cSYong Wu ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks); 3220e14917cSYong Wu if (ret) 3230e14917cSYong Wu return ret; 3240e14917cSYong Wu 3250e14917cSYong Wu for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++) 3260e14917cSYong Wu smi->clks[i].id = clks[i]; 3270e14917cSYong Wu ret = devm_clk_bulk_get_optional(dev, clk_nr_optional, 3280e14917cSYong Wu smi->clks + clk_nr_required); 3290e14917cSYong Wu smi->clk_num = clk_nr_required + clk_nr_optional; 3300e14917cSYong Wu return ret; 3310e14917cSYong Wu } 3320e14917cSYong Wu 333cc8bbe1aSYong Wu static int mtk_smi_larb_probe(struct platform_device *pdev) 334cc8bbe1aSYong Wu { 335cc8bbe1aSYong Wu struct mtk_smi_larb *larb; 336cc8bbe1aSYong Wu struct device *dev = &pdev->dev; 3370e14917cSYong Wu int ret; 338cc8bbe1aSYong Wu 339cc8bbe1aSYong Wu larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); 340cc8bbe1aSYong Wu if (!larb) 341cc8bbe1aSYong Wu return -ENOMEM; 342cc8bbe1aSYong Wu 34375487860SHonghui Zhang larb->larb_gen = of_device_get_match_data(dev); 344912fea8bSYong Wu larb->base = devm_platform_ioremap_resource(pdev, 0); 345cc8bbe1aSYong Wu if (IS_ERR(larb->base)) 346cc8bbe1aSYong Wu return PTR_ERR(larb->base); 347cc8bbe1aSYong Wu 3480e14917cSYong Wu ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks, 3490e14917cSYong Wu MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR); 3500e14917cSYong Wu if (ret) 3510e14917cSYong Wu return ret; 352cc8bbe1aSYong Wu 353cc8bbe1aSYong Wu larb->smi.dev = dev; 354cc8bbe1aSYong Wu 35547404757SYong Wu ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev); 35647404757SYong Wu if (ret < 0) 35747404757SYong Wu return ret; 358cc8bbe1aSYong Wu 359cc8bbe1aSYong Wu pm_runtime_enable(dev); 360cc8bbe1aSYong Wu platform_set_drvdata(pdev, larb); 36130b869e7SYong Wu ret = component_add(dev, &mtk_smi_larb_component_ops); 36230b869e7SYong Wu if (ret) 36330b869e7SYong Wu goto err_pm_disable; 36430b869e7SYong Wu return 0; 36530b869e7SYong Wu 36630b869e7SYong Wu err_pm_disable: 36730b869e7SYong Wu pm_runtime_disable(dev); 36830b869e7SYong Wu device_link_remove(dev, larb->smi_common_dev); 36930b869e7SYong Wu return ret; 370cc8bbe1aSYong Wu } 371cc8bbe1aSYong Wu 372cc8bbe1aSYong Wu static int mtk_smi_larb_remove(struct platform_device *pdev) 373cc8bbe1aSYong Wu { 3746ce2c05bSYong Wu struct mtk_smi_larb *larb = platform_get_drvdata(pdev); 3756ce2c05bSYong Wu 3766ce2c05bSYong Wu device_link_remove(&pdev->dev, larb->smi_common_dev); 377cc8bbe1aSYong Wu pm_runtime_disable(&pdev->dev); 378cc8bbe1aSYong Wu component_del(&pdev->dev, &mtk_smi_larb_component_ops); 379cc8bbe1aSYong Wu return 0; 380cc8bbe1aSYong Wu } 381cc8bbe1aSYong Wu 3824f0a1a1aSYong Wu static int __maybe_unused mtk_smi_larb_resume(struct device *dev) 3834f0a1a1aSYong Wu { 3844f0a1a1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 3854f0a1a1aSYong Wu const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 3864f0a1a1aSYong Wu int ret; 3874f0a1a1aSYong Wu 3880e14917cSYong Wu ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks); 3890e14917cSYong Wu if (ret < 0) 3904f0a1a1aSYong Wu return ret; 3914f0a1a1aSYong Wu 3924f0a1a1aSYong Wu /* Configure the basic setting for this larb */ 3934f0a1a1aSYong Wu larb_gen->config_port(dev); 3944f0a1a1aSYong Wu 3954f0a1a1aSYong Wu return 0; 3964f0a1a1aSYong Wu } 3974f0a1a1aSYong Wu 3984f0a1a1aSYong Wu static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) 3994f0a1a1aSYong Wu { 4004f0a1a1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 4014f0a1a1aSYong Wu 4020e14917cSYong Wu clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks); 4034f0a1a1aSYong Wu return 0; 4044f0a1a1aSYong Wu } 4054f0a1a1aSYong Wu 4064f0a1a1aSYong Wu static const struct dev_pm_ops smi_larb_pm_ops = { 4074f0a1a1aSYong Wu SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL) 408fb03082aSYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 409fb03082aSYong Wu pm_runtime_force_resume) 4104f0a1a1aSYong Wu }; 4114f0a1a1aSYong Wu 412cc8bbe1aSYong Wu static struct platform_driver mtk_smi_larb_driver = { 413cc8bbe1aSYong Wu .probe = mtk_smi_larb_probe, 414cc8bbe1aSYong Wu .remove = mtk_smi_larb_remove, 415cc8bbe1aSYong Wu .driver = { 416cc8bbe1aSYong Wu .name = "mtk-smi-larb", 417cc8bbe1aSYong Wu .of_match_table = mtk_smi_larb_of_ids, 4184f0a1a1aSYong Wu .pm = &smi_larb_pm_ops, 419cc8bbe1aSYong Wu } 420cc8bbe1aSYong Wu }; 421cc8bbe1aSYong Wu 42242d42c76SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_gen1 = { 423a5c18986SYong Wu .type = MTK_SMI_GEN1, 42442d42c76SYong Wu }; 42542d42c76SYong Wu 42642d42c76SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { 427a5c18986SYong Wu .type = MTK_SMI_GEN2, 42842d42c76SYong Wu }; 42942d42c76SYong Wu 430fc492f33SMing-Fan Chen static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { 431a5c18986SYong Wu .type = MTK_SMI_GEN2, 432fc492f33SMing-Fan Chen .has_gals = true, 433fc492f33SMing-Fan Chen .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | 434fc492f33SMing-Fan Chen F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), 435fc492f33SMing-Fan Chen }; 436fc492f33SMing-Fan Chen 437907ba6a1SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { 438a5c18986SYong Wu .type = MTK_SMI_GEN2, 439907ba6a1SYong Wu .has_gals = true, 440567e58cfSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 441567e58cfSYong Wu F_MMU1_LARB(7), 442907ba6a1SYong Wu }; 443907ba6a1SYong Wu 44402c02ddcSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { 445a5c18986SYong Wu .type = MTK_SMI_GEN2, 44602c02ddcSYong Wu .has_gals = true, 44702c02ddcSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 44802c02ddcSYong Wu F_MMU1_LARB(6), 44902c02ddcSYong Wu }; 45002c02ddcSYong Wu 451*cc4f9dcdSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = { 452*cc4f9dcdSYong Wu .type = MTK_SMI_GEN2, 453*cc4f9dcdSYong Wu .has_gals = true, 454*cc4f9dcdSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) | 455*cc4f9dcdSYong Wu F_MMU1_LARB(7), 456*cc4f9dcdSYong Wu }; 457*cc4f9dcdSYong Wu 458*cc4f9dcdSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = { 459*cc4f9dcdSYong Wu .type = MTK_SMI_GEN2, 460*cc4f9dcdSYong Wu .has_gals = true, 461*cc4f9dcdSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7), 462*cc4f9dcdSYong Wu }; 463*cc4f9dcdSYong Wu 464*cc4f9dcdSYong Wu static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = { 465*cc4f9dcdSYong Wu .type = MTK_SMI_GEN2_SUB_COMM, 466*cc4f9dcdSYong Wu .has_gals = true, 467*cc4f9dcdSYong Wu }; 468*cc4f9dcdSYong Wu 4693c8f4ad8SHonghui Zhang static const struct of_device_id mtk_smi_common_of_ids[] = { 470534e0ad2SYong Wu {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1}, 471534e0ad2SYong Wu {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2}, 472534e0ad2SYong Wu {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779}, 473534e0ad2SYong Wu {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2}, 474534e0ad2SYong Wu {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2}, 475534e0ad2SYong Wu {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183}, 476534e0ad2SYong Wu {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, 477*cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, 478*cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, 479*cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195}, 4803c8f4ad8SHonghui Zhang {} 4813c8f4ad8SHonghui Zhang }; 4823c8f4ad8SHonghui Zhang 483cc8bbe1aSYong Wu static int mtk_smi_common_probe(struct platform_device *pdev) 484cc8bbe1aSYong Wu { 485cc8bbe1aSYong Wu struct device *dev = &pdev->dev; 486cc8bbe1aSYong Wu struct mtk_smi *common; 4870e14917cSYong Wu int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR; 488cc8bbe1aSYong Wu 489cc8bbe1aSYong Wu common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); 490cc8bbe1aSYong Wu if (!common) 491cc8bbe1aSYong Wu return -ENOMEM; 492cc8bbe1aSYong Wu common->dev = dev; 49342d42c76SYong Wu common->plat = of_device_get_match_data(dev); 494cc8bbe1aSYong Wu 4953e4f74e0SYong Wu if (common->plat->has_gals) { 4963e4f74e0SYong Wu if (common->plat->type == MTK_SMI_GEN2) 4970e14917cSYong Wu clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR; 4983e4f74e0SYong Wu else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 4993e4f74e0SYong Wu clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR; 5003e4f74e0SYong Wu } 5010e14917cSYong Wu ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0); 5020e14917cSYong Wu if (ret) 5030e14917cSYong Wu return ret; 50464fea74aSYong Wu 5053c8f4ad8SHonghui Zhang /* 5063c8f4ad8SHonghui Zhang * for mtk smi gen 1, we need to get the ao(always on) base to config 5073c8f4ad8SHonghui Zhang * m4u port, and we need to enable the aync clock for transform the smi 5083c8f4ad8SHonghui Zhang * clock into emi clock domain, but for mtk smi gen2, there's no smi ao 5093c8f4ad8SHonghui Zhang * base. 5103c8f4ad8SHonghui Zhang */ 511a5c18986SYong Wu if (common->plat->type == MTK_SMI_GEN1) { 512912fea8bSYong Wu common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0); 5133c8f4ad8SHonghui Zhang if (IS_ERR(common->smi_ao_base)) 5143c8f4ad8SHonghui Zhang return PTR_ERR(common->smi_ao_base); 5153c8f4ad8SHonghui Zhang 5163c8f4ad8SHonghui Zhang common->clk_async = devm_clk_get(dev, "async"); 5173c8f4ad8SHonghui Zhang if (IS_ERR(common->clk_async)) 5183c8f4ad8SHonghui Zhang return PTR_ERR(common->clk_async); 5193c8f4ad8SHonghui Zhang 52046cc815dSArvind Yadav ret = clk_prepare_enable(common->clk_async); 52146cc815dSArvind Yadav if (ret) 52246cc815dSArvind Yadav return ret; 523567e58cfSYong Wu } else { 524912fea8bSYong Wu common->base = devm_platform_ioremap_resource(pdev, 0); 525567e58cfSYong Wu if (IS_ERR(common->base)) 526567e58cfSYong Wu return PTR_ERR(common->base); 5273c8f4ad8SHonghui Zhang } 52847404757SYong Wu 52947404757SYong Wu /* link its smi-common if this is smi-sub-common */ 53047404757SYong Wu if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) { 53147404757SYong Wu ret = mtk_smi_device_link_common(dev, &common->smi_common_dev); 53247404757SYong Wu if (ret < 0) 53347404757SYong Wu return ret; 53447404757SYong Wu } 53547404757SYong Wu 536cc8bbe1aSYong Wu pm_runtime_enable(dev); 537cc8bbe1aSYong Wu platform_set_drvdata(pdev, common); 538cc8bbe1aSYong Wu return 0; 539cc8bbe1aSYong Wu } 540cc8bbe1aSYong Wu 541cc8bbe1aSYong Wu static int mtk_smi_common_remove(struct platform_device *pdev) 542cc8bbe1aSYong Wu { 54347404757SYong Wu struct mtk_smi *common = dev_get_drvdata(&pdev->dev); 54447404757SYong Wu 54547404757SYong Wu if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 54647404757SYong Wu device_link_remove(&pdev->dev, common->smi_common_dev); 547cc8bbe1aSYong Wu pm_runtime_disable(&pdev->dev); 548cc8bbe1aSYong Wu return 0; 549cc8bbe1aSYong Wu } 550cc8bbe1aSYong Wu 5514f0a1a1aSYong Wu static int __maybe_unused mtk_smi_common_resume(struct device *dev) 5524f0a1a1aSYong Wu { 5534f0a1a1aSYong Wu struct mtk_smi *common = dev_get_drvdata(dev); 554567e58cfSYong Wu u32 bus_sel = common->plat->bus_sel; 5554f0a1a1aSYong Wu int ret; 5564f0a1a1aSYong Wu 5570e14917cSYong Wu ret = clk_bulk_prepare_enable(common->clk_num, common->clks); 5580e14917cSYong Wu if (ret) 5594f0a1a1aSYong Wu return ret; 560567e58cfSYong Wu 561a5c18986SYong Wu if (common->plat->type == MTK_SMI_GEN2 && bus_sel) 562567e58cfSYong Wu writel(bus_sel, common->base + SMI_BUS_SEL); 5634f0a1a1aSYong Wu return 0; 5644f0a1a1aSYong Wu } 5654f0a1a1aSYong Wu 5664f0a1a1aSYong Wu static int __maybe_unused mtk_smi_common_suspend(struct device *dev) 5674f0a1a1aSYong Wu { 5684f0a1a1aSYong Wu struct mtk_smi *common = dev_get_drvdata(dev); 5694f0a1a1aSYong Wu 5700e14917cSYong Wu clk_bulk_disable_unprepare(common->clk_num, common->clks); 5714f0a1a1aSYong Wu return 0; 5724f0a1a1aSYong Wu } 5734f0a1a1aSYong Wu 5744f0a1a1aSYong Wu static const struct dev_pm_ops smi_common_pm_ops = { 5754f0a1a1aSYong Wu SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL) 576fb03082aSYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 577fb03082aSYong Wu pm_runtime_force_resume) 5784f0a1a1aSYong Wu }; 5794f0a1a1aSYong Wu 580cc8bbe1aSYong Wu static struct platform_driver mtk_smi_common_driver = { 581cc8bbe1aSYong Wu .probe = mtk_smi_common_probe, 582cc8bbe1aSYong Wu .remove = mtk_smi_common_remove, 583cc8bbe1aSYong Wu .driver = { 584cc8bbe1aSYong Wu .name = "mtk-smi-common", 585cc8bbe1aSYong Wu .of_match_table = mtk_smi_common_of_ids, 5864f0a1a1aSYong Wu .pm = &smi_common_pm_ops, 587cc8bbe1aSYong Wu } 588cc8bbe1aSYong Wu }; 589cc8bbe1aSYong Wu 59018212031SYong Wu static struct platform_driver * const smidrivers[] = { 59118212031SYong Wu &mtk_smi_common_driver, 59218212031SYong Wu &mtk_smi_larb_driver, 59318212031SYong Wu }; 59418212031SYong Wu 595cc8bbe1aSYong Wu static int __init mtk_smi_init(void) 596cc8bbe1aSYong Wu { 59718212031SYong Wu return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 598cc8bbe1aSYong Wu } 5994f608d38SYong Wu module_init(mtk_smi_init); 60050fc8d92SYong Wu 60150fc8d92SYong Wu static void __exit mtk_smi_exit(void) 60250fc8d92SYong Wu { 60350fc8d92SYong Wu platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 60450fc8d92SYong Wu } 60550fc8d92SYong Wu module_exit(mtk_smi_exit); 60650fc8d92SYong Wu 60750fc8d92SYong Wu MODULE_DESCRIPTION("MediaTek SMI driver"); 60850fc8d92SYong Wu MODULE_LICENSE("GPL v2"); 609