11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2cc8bbe1aSYong Wu /* 3cc8bbe1aSYong Wu * Copyright (c) 2015-2016 MediaTek Inc. 4cc8bbe1aSYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 5cc8bbe1aSYong Wu */ 6cc8bbe1aSYong Wu #include <linux/clk.h> 7cc8bbe1aSYong Wu #include <linux/component.h> 8cc8bbe1aSYong Wu #include <linux/device.h> 9cc8bbe1aSYong Wu #include <linux/err.h> 10cc8bbe1aSYong Wu #include <linux/io.h> 114f608d38SYong Wu #include <linux/module.h> 12cc8bbe1aSYong Wu #include <linux/of.h> 13cc8bbe1aSYong Wu #include <linux/of_platform.h> 14cc8bbe1aSYong Wu #include <linux/platform_device.h> 15cc8bbe1aSYong Wu #include <linux/pm_runtime.h> 16cc8bbe1aSYong Wu #include <soc/mediatek/smi.h> 173c8f4ad8SHonghui Zhang #include <dt-bindings/memory/mt2701-larb-port.h> 1866a28915SYong Wu #include <dt-bindings/memory/mtk-memory-port.h> 19cc8bbe1aSYong Wu 20534e0ad2SYong Wu /* SMI COMMON */ 21431e9cabSYong Wu #define SMI_L1LEN 0x100 22431e9cabSYong Wu 23534e0ad2SYong Wu #define SMI_BUS_SEL 0x220 24534e0ad2SYong Wu #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) 25534e0ad2SYong Wu /* All are MMU0 defaultly. Only specialize mmu1 here. */ 26534e0ad2SYong Wu #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) 27e6dec923SYong Wu 28431e9cabSYong Wu #define SMI_M4U_TH 0x234 29431e9cabSYong Wu #define SMI_FIFO_TH1 0x238 30431e9cabSYong Wu #define SMI_FIFO_TH2 0x23c 31431e9cabSYong Wu #define SMI_DCM 0x300 32431e9cabSYong Wu #define SMI_DUMMY 0x444 33431e9cabSYong Wu 34534e0ad2SYong Wu /* SMI LARB */ 35fe6dd2a4SYong Wu #define SMI_LARB_CMD_THRT_CON 0x24 36fe6dd2a4SYong Wu #define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4) 37fe6dd2a4SYong Wu #define SMI_LARB_THRT_RD_NU_LMT (5 << 4) 38fe6dd2a4SYong Wu 39fe6dd2a4SYong Wu #define SMI_LARB_SW_FLAG 0x40 40fe6dd2a4SYong Wu #define SMI_LARB_SW_FLAG_1 0x1 41fe6dd2a4SYong Wu 42fe6dd2a4SYong Wu #define SMI_LARB_OSTDL_PORT 0x200 43fe6dd2a4SYong Wu #define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2)) 44a8529f3bSFabien Parent 45534e0ad2SYong Wu /* Below are about mmu enable registers, they are different in SoCs */ 46534e0ad2SYong Wu /* gen1: mt2701 */ 473c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_BASE 0x5c0 483c8f4ad8SHonghui Zhang 493c8f4ad8SHonghui Zhang /* every register control 8 port, register offset 0x4 */ 503c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2) 513c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_ADDR(id) \ 523c8f4ad8SHonghui Zhang (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id)) 533c8f4ad8SHonghui Zhang 543c8f4ad8SHonghui Zhang /* 553c8f4ad8SHonghui Zhang * every port have 4 bit to control, bit[port + 3] control virtual or physical, 563c8f4ad8SHonghui Zhang * bit[port + 2 : port + 1] control the domain, bit[port] control the security 573c8f4ad8SHonghui Zhang * or non-security. 583c8f4ad8SHonghui Zhang */ 593c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2))) 603c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3) 613c8f4ad8SHonghui Zhang /* mt2701 domain should be set to 3 */ 623c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) 633c8f4ad8SHonghui Zhang 64534e0ad2SYong Wu /* gen2: */ 65534e0ad2SYong Wu /* mt8167 */ 66534e0ad2SYong Wu #define MT8167_SMI_LARB_MMU_EN 0xfc0 67534e0ad2SYong Wu 68534e0ad2SYong Wu /* mt8173 */ 69534e0ad2SYong Wu #define MT8173_SMI_LARB_MMU_EN 0xf00 70534e0ad2SYong Wu 71534e0ad2SYong Wu /* general */ 72e6dec923SYong Wu #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) 73e6dec923SYong Wu #define F_MMU_EN BIT(0) 748d2c749eSYong Wu #define BANK_SEL(id) ({ \ 758d2c749eSYong Wu u32 _id = (id) & 0x3; \ 768d2c749eSYong Wu (_id << 8 | _id << 10 | _id << 12 | _id << 14); \ 778d2c749eSYong Wu }) 78e6dec923SYong Wu 79431e9cabSYong Wu #define SMI_COMMON_INIT_REGS_NR 6 80fe6dd2a4SYong Wu #define SMI_LARB_PORT_NR_MAX 32 81fe6dd2a4SYong Wu 82fe6dd2a4SYong Wu #define MTK_SMI_FLAG_THRT_UPDATE BIT(0) 83fe6dd2a4SYong Wu #define MTK_SMI_FLAG_SW_FLAG BIT(1) 84fe6dd2a4SYong Wu #define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x))) 85431e9cabSYong Wu 86431e9cabSYong Wu struct mtk_smi_reg_pair { 87431e9cabSYong Wu unsigned int offset; 88431e9cabSYong Wu u32 value; 89431e9cabSYong Wu }; 90431e9cabSYong Wu 91a5c18986SYong Wu enum mtk_smi_type { 9242d42c76SYong Wu MTK_SMI_GEN1, 9347404757SYong Wu MTK_SMI_GEN2, /* gen2 smi common */ 9447404757SYong Wu MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */ 9542d42c76SYong Wu }; 9642d42c76SYong Wu 970e14917cSYong Wu #define MTK_SMI_CLK_NR_MAX 4 980e14917cSYong Wu 990e14917cSYong Wu /* larbs: Require apb/smi clocks while gals is optional. */ 1000e14917cSYong Wu static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"}; 1010e14917cSYong Wu #define MTK_SMI_LARB_REQ_CLK_NR 2 1020e14917cSYong Wu #define MTK_SMI_LARB_OPT_CLK_NR 1 1030e14917cSYong Wu 1040e14917cSYong Wu /* 1050e14917cSYong Wu * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required. 1063e4f74e0SYong Wu * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required. 1070e14917cSYong Wu */ 1080e14917cSYong Wu static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"}; 1090e14917cSYong Wu #define MTK_SMI_COM_REQ_CLK_NR 2 1100e14917cSYong Wu #define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX 1113e4f74e0SYong Wu #define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3 1120e14917cSYong Wu 11342d42c76SYong Wu struct mtk_smi_common_plat { 114a5c18986SYong Wu enum mtk_smi_type type; 11564fea74aSYong Wu bool has_gals; 116567e58cfSYong Wu u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ 117431e9cabSYong Wu 118431e9cabSYong Wu const struct mtk_smi_reg_pair *init; 11942d42c76SYong Wu }; 12042d42c76SYong Wu 1213c8f4ad8SHonghui Zhang struct mtk_smi_larb_gen { 1223c8f4ad8SHonghui Zhang int port_in_larb[MTK_LARB_NR_MAX + 1]; 1233aa5a6c2SKrzysztof Kozlowski void (*config_port)(struct device *dev); 1242e9b0908SYong Wu unsigned int larb_direct_to_common_mask; 125fe6dd2a4SYong Wu unsigned int flags_general; 126fe6dd2a4SYong Wu const u8 (*ostd)[SMI_LARB_PORT_NR_MAX]; 1273c8f4ad8SHonghui Zhang }; 128cc8bbe1aSYong Wu 129cc8bbe1aSYong Wu struct mtk_smi { 130cc8bbe1aSYong Wu struct device *dev; 1310e14917cSYong Wu unsigned int clk_num; 1320e14917cSYong Wu struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX]; 1333c8f4ad8SHonghui Zhang struct clk *clk_async; /*only needed by mt2701*/ 134567e58cfSYong Wu union { 135567e58cfSYong Wu void __iomem *smi_ao_base; /* only for gen1 */ 136567e58cfSYong Wu void __iomem *base; /* only for gen2 */ 137567e58cfSYong Wu }; 13847404757SYong Wu struct device *smi_common_dev; /* for sub common */ 13942d42c76SYong Wu const struct mtk_smi_common_plat *plat; 140cc8bbe1aSYong Wu }; 141cc8bbe1aSYong Wu 142cc8bbe1aSYong Wu struct mtk_smi_larb { /* larb: local arbiter */ 143cc8bbe1aSYong Wu struct mtk_smi smi; 144cc8bbe1aSYong Wu void __iomem *base; 14547404757SYong Wu struct device *smi_common_dev; /* common or sub-common dev */ 1463c8f4ad8SHonghui Zhang const struct mtk_smi_larb_gen *larb_gen; 1473c8f4ad8SHonghui Zhang int larbid; 148cc8bbe1aSYong Wu u32 *mmu; 1498d2c749eSYong Wu unsigned char *bank; 150cc8bbe1aSYong Wu }; 151cc8bbe1aSYong Wu 152cc8bbe1aSYong Wu int mtk_smi_larb_get(struct device *larbdev) 153cc8bbe1aSYong Wu { 154a2d522ffSZhang Qilong int ret = pm_runtime_resume_and_get(larbdev); 155cc8bbe1aSYong Wu 1564f0a1a1aSYong Wu return (ret < 0) ? ret : 0; 157cc8bbe1aSYong Wu } 158cb1b5dffSPhilipp Zabel EXPORT_SYMBOL_GPL(mtk_smi_larb_get); 159cc8bbe1aSYong Wu 160cc8bbe1aSYong Wu void mtk_smi_larb_put(struct device *larbdev) 161cc8bbe1aSYong Wu { 1624f0a1a1aSYong Wu pm_runtime_put_sync(larbdev); 163cc8bbe1aSYong Wu } 164cb1b5dffSPhilipp Zabel EXPORT_SYMBOL_GPL(mtk_smi_larb_put); 165cc8bbe1aSYong Wu 166cc8bbe1aSYong Wu static int 167cc8bbe1aSYong Wu mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) 168cc8bbe1aSYong Wu { 169cc8bbe1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 1701ee9feb2SYong Wu struct mtk_smi_larb_iommu *larb_mmu = data; 171cc8bbe1aSYong Wu unsigned int i; 172cc8bbe1aSYong Wu 173ec2da07cSYong Wu for (i = 0; i < MTK_LARB_NR_MAX; i++) { 1741ee9feb2SYong Wu if (dev == larb_mmu[i].dev) { 175ec2da07cSYong Wu larb->larbid = i; 1761ee9feb2SYong Wu larb->mmu = &larb_mmu[i].mmu; 1778d2c749eSYong Wu larb->bank = larb_mmu[i].bank; 178cc8bbe1aSYong Wu return 0; 179cc8bbe1aSYong Wu } 180cc8bbe1aSYong Wu } 181cc8bbe1aSYong Wu return -ENODEV; 182cc8bbe1aSYong Wu } 183cc8bbe1aSYong Wu 184534e0ad2SYong Wu static void 185534e0ad2SYong Wu mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) 186e6dec923SYong Wu { 187534e0ad2SYong Wu /* Do nothing as the iommu is always enabled. */ 188e6dec923SYong Wu } 189e6dec923SYong Wu 190534e0ad2SYong Wu static const struct component_ops mtk_smi_larb_component_ops = { 191534e0ad2SYong Wu .bind = mtk_smi_larb_bind, 192534e0ad2SYong Wu .unbind = mtk_smi_larb_unbind, 193534e0ad2SYong Wu }; 194a8529f3bSFabien Parent 1953c8f4ad8SHonghui Zhang static void mtk_smi_larb_config_port_gen1(struct device *dev) 1963c8f4ad8SHonghui Zhang { 1973c8f4ad8SHonghui Zhang struct mtk_smi_larb *larb = dev_get_drvdata(dev); 1983c8f4ad8SHonghui Zhang const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 1993c8f4ad8SHonghui Zhang struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); 2003c8f4ad8SHonghui Zhang int i, m4u_port_id, larb_port_num; 2013c8f4ad8SHonghui Zhang u32 sec_con_val, reg_val; 2023c8f4ad8SHonghui Zhang 2033c8f4ad8SHonghui Zhang m4u_port_id = larb_gen->port_in_larb[larb->larbid]; 2043c8f4ad8SHonghui Zhang larb_port_num = larb_gen->port_in_larb[larb->larbid + 1] 2053c8f4ad8SHonghui Zhang - larb_gen->port_in_larb[larb->larbid]; 2063c8f4ad8SHonghui Zhang 2073c8f4ad8SHonghui Zhang for (i = 0; i < larb_port_num; i++, m4u_port_id++) { 2083c8f4ad8SHonghui Zhang if (*larb->mmu & BIT(i)) { 2093c8f4ad8SHonghui Zhang /* bit[port + 3] controls the virtual or physical */ 2103c8f4ad8SHonghui Zhang sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id); 2113c8f4ad8SHonghui Zhang } else { 2123c8f4ad8SHonghui Zhang /* do not need to enable m4u for this port */ 2133c8f4ad8SHonghui Zhang continue; 2143c8f4ad8SHonghui Zhang } 2153c8f4ad8SHonghui Zhang reg_val = readl(common->smi_ao_base 2163c8f4ad8SHonghui Zhang + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 2173c8f4ad8SHonghui Zhang reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); 2183c8f4ad8SHonghui Zhang reg_val |= sec_con_val; 2193c8f4ad8SHonghui Zhang reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); 2203c8f4ad8SHonghui Zhang writel(reg_val, 2213c8f4ad8SHonghui Zhang common->smi_ao_base 2223c8f4ad8SHonghui Zhang + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 2233c8f4ad8SHonghui Zhang } 2243c8f4ad8SHonghui Zhang } 2253c8f4ad8SHonghui Zhang 226534e0ad2SYong Wu static void mtk_smi_larb_config_port_mt8167(struct device *dev) 227cc8bbe1aSYong Wu { 228534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 229534e0ad2SYong Wu 230534e0ad2SYong Wu writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); 231cc8bbe1aSYong Wu } 232cc8bbe1aSYong Wu 233534e0ad2SYong Wu static void mtk_smi_larb_config_port_mt8173(struct device *dev) 234534e0ad2SYong Wu { 235534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 236cc8bbe1aSYong Wu 237534e0ad2SYong Wu writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN); 238534e0ad2SYong Wu } 2393c8f4ad8SHonghui Zhang 240534e0ad2SYong Wu static void mtk_smi_larb_config_port_gen2_general(struct device *dev) 241534e0ad2SYong Wu { 242534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 243fe6dd2a4SYong Wu u32 reg, flags_general = larb->larb_gen->flags_general; 244383a44aeSYong Wu const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL; 245534e0ad2SYong Wu int i; 246534e0ad2SYong Wu 247534e0ad2SYong Wu if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) 248534e0ad2SYong Wu return; 249534e0ad2SYong Wu 250fe6dd2a4SYong Wu if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) { 251fe6dd2a4SYong Wu reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON); 252fe6dd2a4SYong Wu reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK; 253fe6dd2a4SYong Wu reg |= SMI_LARB_THRT_RD_NU_LMT; 254fe6dd2a4SYong Wu writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON); 255fe6dd2a4SYong Wu } 256fe6dd2a4SYong Wu 257fe6dd2a4SYong Wu if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG)) 258fe6dd2a4SYong Wu writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); 259fe6dd2a4SYong Wu 260fe6dd2a4SYong Wu for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) 261fe6dd2a4SYong Wu writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); 262fe6dd2a4SYong Wu 263534e0ad2SYong Wu for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { 264534e0ad2SYong Wu reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); 265534e0ad2SYong Wu reg |= F_MMU_EN; 266534e0ad2SYong Wu reg |= BANK_SEL(larb->bank[i]); 267534e0ad2SYong Wu writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); 268534e0ad2SYong Wu } 269534e0ad2SYong Wu } 270a8529f3bSFabien Parent 271fe6dd2a4SYong Wu static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = { 272fe6dd2a4SYong Wu [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */ 273fe6dd2a4SYong Wu [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */ 274fe6dd2a4SYong Wu [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, /* ... */ 275fe6dd2a4SYong Wu [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,}, 276fe6dd2a4SYong Wu [4] = {0x06, 0x01, 0x17, 0x06, 0x0a,}, 277fe6dd2a4SYong Wu [5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,}, 278fe6dd2a4SYong Wu [6] = {0x06, 0x01, 0x06, 0x0a,}, 279fe6dd2a4SYong Wu [7] = {0x0c, 0x0c, 0x12,}, 280fe6dd2a4SYong Wu [8] = {0x0c, 0x0c, 0x12,}, 281fe6dd2a4SYong Wu [9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a, 282fe6dd2a4SYong Wu 0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,}, 283fe6dd2a4SYong Wu [10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10, 284fe6dd2a4SYong Wu 0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d, 285fe6dd2a4SYong Wu 0x0d, 0x06, 0x10, 0x10,}, 286fe6dd2a4SYong Wu [11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,}, 287fe6dd2a4SYong Wu [12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,}, 288fe6dd2a4SYong Wu [13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,}, 289fe6dd2a4SYong Wu [14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01, 290fe6dd2a4SYong Wu 0x01, 0x02, 0x02, 0x08, 0x02,}, 291fe6dd2a4SYong Wu [15] = {}, 292fe6dd2a4SYong Wu [16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a, 293fe6dd2a4SYong Wu 0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,}, 294fe6dd2a4SYong Wu [17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 295fe6dd2a4SYong Wu [18] = {0x12, 0x06, 0x12, 0x06,}, 296fe6dd2a4SYong Wu [19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 297fe6dd2a4SYong Wu 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 298fe6dd2a4SYong Wu 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 299fe6dd2a4SYong Wu [20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 300fe6dd2a4SYong Wu 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 301fe6dd2a4SYong Wu 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 302fe6dd2a4SYong Wu [21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 303fe6dd2a4SYong Wu [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 304fe6dd2a4SYong Wu [23] = {0x18, 0x01,}, 305fe6dd2a4SYong Wu [24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01, 306fe6dd2a4SYong Wu 0x01, 0x01,}, 307fe6dd2a4SYong Wu [25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 308fe6dd2a4SYong Wu 0x02, 0x01,}, 309fe6dd2a4SYong Wu [26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 310fe6dd2a4SYong Wu 0x02, 0x01,}, 311fe6dd2a4SYong Wu [27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 312fe6dd2a4SYong Wu 0x02, 0x01,}, 313fe6dd2a4SYong Wu [28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 314fe6dd2a4SYong Wu }; 315fe6dd2a4SYong Wu 3163c8f4ad8SHonghui Zhang static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { 3173c8f4ad8SHonghui Zhang .port_in_larb = { 3183c8f4ad8SHonghui Zhang LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 3193c8f4ad8SHonghui Zhang LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 3203c8f4ad8SHonghui Zhang }, 3213c8f4ad8SHonghui Zhang .config_port = mtk_smi_larb_config_port_gen1, 3223c8f4ad8SHonghui Zhang }; 3233c8f4ad8SHonghui Zhang 324e6dec923SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { 3252e9b0908SYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 3262e9b0908SYong Wu .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ 327e6dec923SYong Wu }; 328e6dec923SYong Wu 329fc492f33SMing-Fan Chen static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { 330fc492f33SMing-Fan Chen .config_port = mtk_smi_larb_config_port_gen2_general, 331fc492f33SMing-Fan Chen .larb_direct_to_common_mask = 332fc492f33SMing-Fan Chen BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), 333fc492f33SMing-Fan Chen /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ 334fc492f33SMing-Fan Chen }; 335fc492f33SMing-Fan Chen 336534e0ad2SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = { 337534e0ad2SYong Wu /* mt8167 do not need the port in larb */ 338534e0ad2SYong Wu .config_port = mtk_smi_larb_config_port_mt8167, 339534e0ad2SYong Wu }; 340534e0ad2SYong Wu 341534e0ad2SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { 342534e0ad2SYong Wu /* mt8173 do not need the port in larb */ 343534e0ad2SYong Wu .config_port = mtk_smi_larb_config_port_mt8173, 344534e0ad2SYong Wu }; 345534e0ad2SYong Wu 346907ba6a1SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { 347907ba6a1SYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 348907ba6a1SYong Wu .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), 349907ba6a1SYong Wu /* IPU0 | IPU1 | CCU */ 350907ba6a1SYong Wu }; 351907ba6a1SYong Wu 35202c02ddcSYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { 35302c02ddcSYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 35402c02ddcSYong Wu }; 35502c02ddcSYong Wu 356cc4f9dcdSYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = { 357cc4f9dcdSYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 358fe6dd2a4SYong Wu .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG, 359fe6dd2a4SYong Wu .ostd = mtk_smi_larb_mt8195_ostd, 360cc4f9dcdSYong Wu }; 361cc4f9dcdSYong Wu 3623c8f4ad8SHonghui Zhang static const struct of_device_id mtk_smi_larb_of_ids[] = { 363534e0ad2SYong Wu {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701}, 364534e0ad2SYong Wu {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712}, 365534e0ad2SYong Wu {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779}, 366534e0ad2SYong Wu {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167}, 367534e0ad2SYong Wu {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173}, 368534e0ad2SYong Wu {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, 369534e0ad2SYong Wu {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, 370cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195}, 3713c8f4ad8SHonghui Zhang {} 3723c8f4ad8SHonghui Zhang }; 3733c8f4ad8SHonghui Zhang 37447404757SYong Wu static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev) 37547404757SYong Wu { 37647404757SYong Wu struct platform_device *smi_com_pdev; 37747404757SYong Wu struct device_node *smi_com_node; 37847404757SYong Wu struct device *smi_com_dev; 37947404757SYong Wu struct device_link *link; 38047404757SYong Wu 38147404757SYong Wu smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); 38247404757SYong Wu if (!smi_com_node) 38347404757SYong Wu return -EINVAL; 38447404757SYong Wu 38547404757SYong Wu smi_com_pdev = of_find_device_by_node(smi_com_node); 38647404757SYong Wu of_node_put(smi_com_node); 38747404757SYong Wu if (smi_com_pdev) { 38847404757SYong Wu /* smi common is the supplier, Make sure it is ready before */ 38947404757SYong Wu if (!platform_get_drvdata(smi_com_pdev)) 39047404757SYong Wu return -EPROBE_DEFER; 39147404757SYong Wu smi_com_dev = &smi_com_pdev->dev; 39247404757SYong Wu link = device_link_add(dev, smi_com_dev, 39347404757SYong Wu DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 39447404757SYong Wu if (!link) { 39547404757SYong Wu dev_err(dev, "Unable to link smi-common dev\n"); 39647404757SYong Wu return -ENODEV; 39747404757SYong Wu } 39847404757SYong Wu *com_dev = smi_com_dev; 39947404757SYong Wu } else { 40047404757SYong Wu dev_err(dev, "Failed to get the smi_common device\n"); 40147404757SYong Wu return -EINVAL; 40247404757SYong Wu } 40347404757SYong Wu return 0; 40447404757SYong Wu } 40547404757SYong Wu 4060e14917cSYong Wu static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi, 4070e14917cSYong Wu const char * const clks[], 4080e14917cSYong Wu unsigned int clk_nr_required, 4090e14917cSYong Wu unsigned int clk_nr_optional) 4100e14917cSYong Wu { 4110e14917cSYong Wu int i, ret; 4120e14917cSYong Wu 4130e14917cSYong Wu for (i = 0; i < clk_nr_required; i++) 4140e14917cSYong Wu smi->clks[i].id = clks[i]; 4150e14917cSYong Wu ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks); 4160e14917cSYong Wu if (ret) 4170e14917cSYong Wu return ret; 4180e14917cSYong Wu 4190e14917cSYong Wu for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++) 4200e14917cSYong Wu smi->clks[i].id = clks[i]; 4210e14917cSYong Wu ret = devm_clk_bulk_get_optional(dev, clk_nr_optional, 4220e14917cSYong Wu smi->clks + clk_nr_required); 4230e14917cSYong Wu smi->clk_num = clk_nr_required + clk_nr_optional; 4240e14917cSYong Wu return ret; 4250e14917cSYong Wu } 4260e14917cSYong Wu 427cc8bbe1aSYong Wu static int mtk_smi_larb_probe(struct platform_device *pdev) 428cc8bbe1aSYong Wu { 429cc8bbe1aSYong Wu struct mtk_smi_larb *larb; 430cc8bbe1aSYong Wu struct device *dev = &pdev->dev; 4310e14917cSYong Wu int ret; 432cc8bbe1aSYong Wu 433cc8bbe1aSYong Wu larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); 434cc8bbe1aSYong Wu if (!larb) 435cc8bbe1aSYong Wu return -ENOMEM; 436cc8bbe1aSYong Wu 43775487860SHonghui Zhang larb->larb_gen = of_device_get_match_data(dev); 438912fea8bSYong Wu larb->base = devm_platform_ioremap_resource(pdev, 0); 439cc8bbe1aSYong Wu if (IS_ERR(larb->base)) 440cc8bbe1aSYong Wu return PTR_ERR(larb->base); 441cc8bbe1aSYong Wu 4420e14917cSYong Wu ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks, 4430e14917cSYong Wu MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR); 4440e14917cSYong Wu if (ret) 4450e14917cSYong Wu return ret; 446cc8bbe1aSYong Wu 447cc8bbe1aSYong Wu larb->smi.dev = dev; 448cc8bbe1aSYong Wu 44947404757SYong Wu ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev); 45047404757SYong Wu if (ret < 0) 45147404757SYong Wu return ret; 452cc8bbe1aSYong Wu 453cc8bbe1aSYong Wu pm_runtime_enable(dev); 454cc8bbe1aSYong Wu platform_set_drvdata(pdev, larb); 45530b869e7SYong Wu ret = component_add(dev, &mtk_smi_larb_component_ops); 45630b869e7SYong Wu if (ret) 45730b869e7SYong Wu goto err_pm_disable; 45830b869e7SYong Wu return 0; 45930b869e7SYong Wu 46030b869e7SYong Wu err_pm_disable: 46130b869e7SYong Wu pm_runtime_disable(dev); 46230b869e7SYong Wu device_link_remove(dev, larb->smi_common_dev); 46330b869e7SYong Wu return ret; 464cc8bbe1aSYong Wu } 465cc8bbe1aSYong Wu 466cc8bbe1aSYong Wu static int mtk_smi_larb_remove(struct platform_device *pdev) 467cc8bbe1aSYong Wu { 4686ce2c05bSYong Wu struct mtk_smi_larb *larb = platform_get_drvdata(pdev); 4696ce2c05bSYong Wu 4706ce2c05bSYong Wu device_link_remove(&pdev->dev, larb->smi_common_dev); 471cc8bbe1aSYong Wu pm_runtime_disable(&pdev->dev); 472cc8bbe1aSYong Wu component_del(&pdev->dev, &mtk_smi_larb_component_ops); 473cc8bbe1aSYong Wu return 0; 474cc8bbe1aSYong Wu } 475cc8bbe1aSYong Wu 4764f0a1a1aSYong Wu static int __maybe_unused mtk_smi_larb_resume(struct device *dev) 4774f0a1a1aSYong Wu { 4784f0a1a1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 4794f0a1a1aSYong Wu const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 4804f0a1a1aSYong Wu int ret; 4814f0a1a1aSYong Wu 4820e14917cSYong Wu ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks); 483*a6945f45SYong Wu if (ret) 4844f0a1a1aSYong Wu return ret; 4854f0a1a1aSYong Wu 4864f0a1a1aSYong Wu /* Configure the basic setting for this larb */ 4874f0a1a1aSYong Wu larb_gen->config_port(dev); 4884f0a1a1aSYong Wu 4894f0a1a1aSYong Wu return 0; 4904f0a1a1aSYong Wu } 4914f0a1a1aSYong Wu 4924f0a1a1aSYong Wu static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) 4934f0a1a1aSYong Wu { 4944f0a1a1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 4954f0a1a1aSYong Wu 4960e14917cSYong Wu clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks); 4974f0a1a1aSYong Wu return 0; 4984f0a1a1aSYong Wu } 4994f0a1a1aSYong Wu 5004f0a1a1aSYong Wu static const struct dev_pm_ops smi_larb_pm_ops = { 5014f0a1a1aSYong Wu SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL) 502fb03082aSYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 503fb03082aSYong Wu pm_runtime_force_resume) 5044f0a1a1aSYong Wu }; 5054f0a1a1aSYong Wu 506cc8bbe1aSYong Wu static struct platform_driver mtk_smi_larb_driver = { 507cc8bbe1aSYong Wu .probe = mtk_smi_larb_probe, 508cc8bbe1aSYong Wu .remove = mtk_smi_larb_remove, 509cc8bbe1aSYong Wu .driver = { 510cc8bbe1aSYong Wu .name = "mtk-smi-larb", 511cc8bbe1aSYong Wu .of_match_table = mtk_smi_larb_of_ids, 5124f0a1a1aSYong Wu .pm = &smi_larb_pm_ops, 513cc8bbe1aSYong Wu } 514cc8bbe1aSYong Wu }; 515cc8bbe1aSYong Wu 516431e9cabSYong Wu static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = { 517431e9cabSYong Wu {SMI_L1LEN, 0xb}, 518431e9cabSYong Wu {SMI_M4U_TH, 0xe100e10}, 519431e9cabSYong Wu {SMI_FIFO_TH1, 0x506090a}, 520431e9cabSYong Wu {SMI_FIFO_TH2, 0x506090a}, 521431e9cabSYong Wu {SMI_DCM, 0x4f1}, 522431e9cabSYong Wu {SMI_DUMMY, 0x1}, 523431e9cabSYong Wu }; 524431e9cabSYong Wu 52542d42c76SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_gen1 = { 526a5c18986SYong Wu .type = MTK_SMI_GEN1, 52742d42c76SYong Wu }; 52842d42c76SYong Wu 52942d42c76SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { 530a5c18986SYong Wu .type = MTK_SMI_GEN2, 53142d42c76SYong Wu }; 53242d42c76SYong Wu 533fc492f33SMing-Fan Chen static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { 534a5c18986SYong Wu .type = MTK_SMI_GEN2, 535fc492f33SMing-Fan Chen .has_gals = true, 536fc492f33SMing-Fan Chen .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | 537fc492f33SMing-Fan Chen F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), 538fc492f33SMing-Fan Chen }; 539fc492f33SMing-Fan Chen 540907ba6a1SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { 541a5c18986SYong Wu .type = MTK_SMI_GEN2, 542907ba6a1SYong Wu .has_gals = true, 543567e58cfSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 544567e58cfSYong Wu F_MMU1_LARB(7), 545907ba6a1SYong Wu }; 546907ba6a1SYong Wu 54702c02ddcSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { 548a5c18986SYong Wu .type = MTK_SMI_GEN2, 54902c02ddcSYong Wu .has_gals = true, 55002c02ddcSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 55102c02ddcSYong Wu F_MMU1_LARB(6), 55202c02ddcSYong Wu }; 55302c02ddcSYong Wu 554cc4f9dcdSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = { 555cc4f9dcdSYong Wu .type = MTK_SMI_GEN2, 556cc4f9dcdSYong Wu .has_gals = true, 557cc4f9dcdSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) | 558cc4f9dcdSYong Wu F_MMU1_LARB(7), 559431e9cabSYong Wu .init = mtk_smi_common_mt8195_init, 560cc4f9dcdSYong Wu }; 561cc4f9dcdSYong Wu 562cc4f9dcdSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = { 563cc4f9dcdSYong Wu .type = MTK_SMI_GEN2, 564cc4f9dcdSYong Wu .has_gals = true, 565cc4f9dcdSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7), 566431e9cabSYong Wu .init = mtk_smi_common_mt8195_init, 567cc4f9dcdSYong Wu }; 568cc4f9dcdSYong Wu 569cc4f9dcdSYong Wu static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = { 570cc4f9dcdSYong Wu .type = MTK_SMI_GEN2_SUB_COMM, 571cc4f9dcdSYong Wu .has_gals = true, 572cc4f9dcdSYong Wu }; 573cc4f9dcdSYong Wu 5743c8f4ad8SHonghui Zhang static const struct of_device_id mtk_smi_common_of_ids[] = { 575534e0ad2SYong Wu {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1}, 576534e0ad2SYong Wu {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2}, 577534e0ad2SYong Wu {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779}, 578534e0ad2SYong Wu {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2}, 579534e0ad2SYong Wu {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2}, 580534e0ad2SYong Wu {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183}, 581534e0ad2SYong Wu {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, 582cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, 583cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, 584cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195}, 5853c8f4ad8SHonghui Zhang {} 5863c8f4ad8SHonghui Zhang }; 5873c8f4ad8SHonghui Zhang 588cc8bbe1aSYong Wu static int mtk_smi_common_probe(struct platform_device *pdev) 589cc8bbe1aSYong Wu { 590cc8bbe1aSYong Wu struct device *dev = &pdev->dev; 591cc8bbe1aSYong Wu struct mtk_smi *common; 5920e14917cSYong Wu int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR; 593cc8bbe1aSYong Wu 594cc8bbe1aSYong Wu common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); 595cc8bbe1aSYong Wu if (!common) 596cc8bbe1aSYong Wu return -ENOMEM; 597cc8bbe1aSYong Wu common->dev = dev; 59842d42c76SYong Wu common->plat = of_device_get_match_data(dev); 599cc8bbe1aSYong Wu 6003e4f74e0SYong Wu if (common->plat->has_gals) { 6013e4f74e0SYong Wu if (common->plat->type == MTK_SMI_GEN2) 6020e14917cSYong Wu clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR; 6033e4f74e0SYong Wu else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 6043e4f74e0SYong Wu clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR; 6053e4f74e0SYong Wu } 6060e14917cSYong Wu ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0); 6070e14917cSYong Wu if (ret) 6080e14917cSYong Wu return ret; 60964fea74aSYong Wu 6103c8f4ad8SHonghui Zhang /* 6113c8f4ad8SHonghui Zhang * for mtk smi gen 1, we need to get the ao(always on) base to config 6123c8f4ad8SHonghui Zhang * m4u port, and we need to enable the aync clock for transform the smi 6133c8f4ad8SHonghui Zhang * clock into emi clock domain, but for mtk smi gen2, there's no smi ao 6143c8f4ad8SHonghui Zhang * base. 6153c8f4ad8SHonghui Zhang */ 616a5c18986SYong Wu if (common->plat->type == MTK_SMI_GEN1) { 617912fea8bSYong Wu common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0); 6183c8f4ad8SHonghui Zhang if (IS_ERR(common->smi_ao_base)) 6193c8f4ad8SHonghui Zhang return PTR_ERR(common->smi_ao_base); 6203c8f4ad8SHonghui Zhang 6213c8f4ad8SHonghui Zhang common->clk_async = devm_clk_get(dev, "async"); 6223c8f4ad8SHonghui Zhang if (IS_ERR(common->clk_async)) 6233c8f4ad8SHonghui Zhang return PTR_ERR(common->clk_async); 6243c8f4ad8SHonghui Zhang 62546cc815dSArvind Yadav ret = clk_prepare_enable(common->clk_async); 62646cc815dSArvind Yadav if (ret) 62746cc815dSArvind Yadav return ret; 628567e58cfSYong Wu } else { 629912fea8bSYong Wu common->base = devm_platform_ioremap_resource(pdev, 0); 630567e58cfSYong Wu if (IS_ERR(common->base)) 631567e58cfSYong Wu return PTR_ERR(common->base); 6323c8f4ad8SHonghui Zhang } 63347404757SYong Wu 63447404757SYong Wu /* link its smi-common if this is smi-sub-common */ 63547404757SYong Wu if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) { 63647404757SYong Wu ret = mtk_smi_device_link_common(dev, &common->smi_common_dev); 63747404757SYong Wu if (ret < 0) 63847404757SYong Wu return ret; 63947404757SYong Wu } 64047404757SYong Wu 641cc8bbe1aSYong Wu pm_runtime_enable(dev); 642cc8bbe1aSYong Wu platform_set_drvdata(pdev, common); 643cc8bbe1aSYong Wu return 0; 644cc8bbe1aSYong Wu } 645cc8bbe1aSYong Wu 646cc8bbe1aSYong Wu static int mtk_smi_common_remove(struct platform_device *pdev) 647cc8bbe1aSYong Wu { 64847404757SYong Wu struct mtk_smi *common = dev_get_drvdata(&pdev->dev); 64947404757SYong Wu 65047404757SYong Wu if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 65147404757SYong Wu device_link_remove(&pdev->dev, common->smi_common_dev); 652cc8bbe1aSYong Wu pm_runtime_disable(&pdev->dev); 653cc8bbe1aSYong Wu return 0; 654cc8bbe1aSYong Wu } 655cc8bbe1aSYong Wu 6564f0a1a1aSYong Wu static int __maybe_unused mtk_smi_common_resume(struct device *dev) 6574f0a1a1aSYong Wu { 6584f0a1a1aSYong Wu struct mtk_smi *common = dev_get_drvdata(dev); 659431e9cabSYong Wu const struct mtk_smi_reg_pair *init = common->plat->init; 660431e9cabSYong Wu u32 bus_sel = common->plat->bus_sel; /* default is 0 */ 661431e9cabSYong Wu int ret, i; 6624f0a1a1aSYong Wu 6630e14917cSYong Wu ret = clk_bulk_prepare_enable(common->clk_num, common->clks); 6640e14917cSYong Wu if (ret) 6654f0a1a1aSYong Wu return ret; 666567e58cfSYong Wu 667431e9cabSYong Wu if (common->plat->type != MTK_SMI_GEN2) 668431e9cabSYong Wu return 0; 669431e9cabSYong Wu 670431e9cabSYong Wu for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++) 671431e9cabSYong Wu writel_relaxed(init[i].value, common->base + init[i].offset); 672431e9cabSYong Wu 673567e58cfSYong Wu writel(bus_sel, common->base + SMI_BUS_SEL); 6744f0a1a1aSYong Wu return 0; 6754f0a1a1aSYong Wu } 6764f0a1a1aSYong Wu 6774f0a1a1aSYong Wu static int __maybe_unused mtk_smi_common_suspend(struct device *dev) 6784f0a1a1aSYong Wu { 6794f0a1a1aSYong Wu struct mtk_smi *common = dev_get_drvdata(dev); 6804f0a1a1aSYong Wu 6810e14917cSYong Wu clk_bulk_disable_unprepare(common->clk_num, common->clks); 6824f0a1a1aSYong Wu return 0; 6834f0a1a1aSYong Wu } 6844f0a1a1aSYong Wu 6854f0a1a1aSYong Wu static const struct dev_pm_ops smi_common_pm_ops = { 6864f0a1a1aSYong Wu SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL) 687fb03082aSYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 688fb03082aSYong Wu pm_runtime_force_resume) 6894f0a1a1aSYong Wu }; 6904f0a1a1aSYong Wu 691cc8bbe1aSYong Wu static struct platform_driver mtk_smi_common_driver = { 692cc8bbe1aSYong Wu .probe = mtk_smi_common_probe, 693cc8bbe1aSYong Wu .remove = mtk_smi_common_remove, 694cc8bbe1aSYong Wu .driver = { 695cc8bbe1aSYong Wu .name = "mtk-smi-common", 696cc8bbe1aSYong Wu .of_match_table = mtk_smi_common_of_ids, 6974f0a1a1aSYong Wu .pm = &smi_common_pm_ops, 698cc8bbe1aSYong Wu } 699cc8bbe1aSYong Wu }; 700cc8bbe1aSYong Wu 70118212031SYong Wu static struct platform_driver * const smidrivers[] = { 70218212031SYong Wu &mtk_smi_common_driver, 70318212031SYong Wu &mtk_smi_larb_driver, 70418212031SYong Wu }; 70518212031SYong Wu 706cc8bbe1aSYong Wu static int __init mtk_smi_init(void) 707cc8bbe1aSYong Wu { 70818212031SYong Wu return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 709cc8bbe1aSYong Wu } 7104f608d38SYong Wu module_init(mtk_smi_init); 71150fc8d92SYong Wu 71250fc8d92SYong Wu static void __exit mtk_smi_exit(void) 71350fc8d92SYong Wu { 71450fc8d92SYong Wu platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 71550fc8d92SYong Wu } 71650fc8d92SYong Wu module_exit(mtk_smi_exit); 71750fc8d92SYong Wu 71850fc8d92SYong Wu MODULE_DESCRIPTION("MediaTek SMI driver"); 71950fc8d92SYong Wu MODULE_LICENSE("GPL v2"); 720