11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2cc8bbe1aSYong Wu /* 3cc8bbe1aSYong Wu * Copyright (c) 2015-2016 MediaTek Inc. 4cc8bbe1aSYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 5cc8bbe1aSYong Wu */ 6cc8bbe1aSYong Wu #include <linux/clk.h> 7cc8bbe1aSYong Wu #include <linux/component.h> 8cc8bbe1aSYong Wu #include <linux/device.h> 9cc8bbe1aSYong Wu #include <linux/err.h> 10cc8bbe1aSYong Wu #include <linux/io.h> 118956500eSYong Wu #include <linux/iopoll.h> 124f608d38SYong Wu #include <linux/module.h> 13cc8bbe1aSYong Wu #include <linux/of.h> 14cc8bbe1aSYong Wu #include <linux/of_platform.h> 15cc8bbe1aSYong Wu #include <linux/platform_device.h> 16cc8bbe1aSYong Wu #include <linux/pm_runtime.h> 17cc8bbe1aSYong Wu #include <soc/mediatek/smi.h> 183c8f4ad8SHonghui Zhang #include <dt-bindings/memory/mt2701-larb-port.h> 1966a28915SYong Wu #include <dt-bindings/memory/mtk-memory-port.h> 20cc8bbe1aSYong Wu 21534e0ad2SYong Wu /* SMI COMMON */ 22431e9cabSYong Wu #define SMI_L1LEN 0x100 23431e9cabSYong Wu 240d97f217SAngeloGioacchino Del Regno #define SMI_L1_ARB 0x200 25534e0ad2SYong Wu #define SMI_BUS_SEL 0x220 26534e0ad2SYong Wu #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) 27534e0ad2SYong Wu /* All are MMU0 defaultly. Only specialize mmu1 here. */ 28534e0ad2SYong Wu #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) 29e6dec923SYong Wu 300d97f217SAngeloGioacchino Del Regno #define SMI_READ_FIFO_TH 0x230 31431e9cabSYong Wu #define SMI_M4U_TH 0x234 32431e9cabSYong Wu #define SMI_FIFO_TH1 0x238 33431e9cabSYong Wu #define SMI_FIFO_TH2 0x23c 34431e9cabSYong Wu #define SMI_DCM 0x300 35431e9cabSYong Wu #define SMI_DUMMY 0x444 36431e9cabSYong Wu 37534e0ad2SYong Wu /* SMI LARB */ 388956500eSYong Wu #define SMI_LARB_SLP_CON 0xc 398956500eSYong Wu #define SLP_PROT_EN BIT(0) 408956500eSYong Wu #define SLP_PROT_RDY BIT(16) 418956500eSYong Wu 42fe6dd2a4SYong Wu #define SMI_LARB_CMD_THRT_CON 0x24 43fe6dd2a4SYong Wu #define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4) 44fe6dd2a4SYong Wu #define SMI_LARB_THRT_RD_NU_LMT (5 << 4) 45fe6dd2a4SYong Wu 46fe6dd2a4SYong Wu #define SMI_LARB_SW_FLAG 0x40 47fe6dd2a4SYong Wu #define SMI_LARB_SW_FLAG_1 0x1 48fe6dd2a4SYong Wu 49fe6dd2a4SYong Wu #define SMI_LARB_OSTDL_PORT 0x200 50fe6dd2a4SYong Wu #define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2)) 51a8529f3bSFabien Parent 52534e0ad2SYong Wu /* Below are about mmu enable registers, they are different in SoCs */ 53534e0ad2SYong Wu /* gen1: mt2701 */ 543c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_BASE 0x5c0 553c8f4ad8SHonghui Zhang 563c8f4ad8SHonghui Zhang /* every register control 8 port, register offset 0x4 */ 573c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2) 583c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_ADDR(id) \ 593c8f4ad8SHonghui Zhang (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id)) 603c8f4ad8SHonghui Zhang 613c8f4ad8SHonghui Zhang /* 623c8f4ad8SHonghui Zhang * every port have 4 bit to control, bit[port + 3] control virtual or physical, 633c8f4ad8SHonghui Zhang * bit[port + 2 : port + 1] control the domain, bit[port] control the security 643c8f4ad8SHonghui Zhang * or non-security. 653c8f4ad8SHonghui Zhang */ 663c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2))) 673c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3) 683c8f4ad8SHonghui Zhang /* mt2701 domain should be set to 3 */ 693c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) 703c8f4ad8SHonghui Zhang 71534e0ad2SYong Wu /* gen2: */ 72534e0ad2SYong Wu /* mt8167 */ 73534e0ad2SYong Wu #define MT8167_SMI_LARB_MMU_EN 0xfc0 74534e0ad2SYong Wu 75534e0ad2SYong Wu /* mt8173 */ 76534e0ad2SYong Wu #define MT8173_SMI_LARB_MMU_EN 0xf00 77534e0ad2SYong Wu 78534e0ad2SYong Wu /* general */ 79e6dec923SYong Wu #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) 80e6dec923SYong Wu #define F_MMU_EN BIT(0) 818d2c749eSYong Wu #define BANK_SEL(id) ({ \ 828d2c749eSYong Wu u32 _id = (id) & 0x3; \ 838d2c749eSYong Wu (_id << 8 | _id << 10 | _id << 12 | _id << 14); \ 848d2c749eSYong Wu }) 85e6dec923SYong Wu 86431e9cabSYong Wu #define SMI_COMMON_INIT_REGS_NR 6 87fe6dd2a4SYong Wu #define SMI_LARB_PORT_NR_MAX 32 88fe6dd2a4SYong Wu 89fe6dd2a4SYong Wu #define MTK_SMI_FLAG_THRT_UPDATE BIT(0) 90fe6dd2a4SYong Wu #define MTK_SMI_FLAG_SW_FLAG BIT(1) 918956500eSYong Wu #define MTK_SMI_FLAG_SLEEP_CTL BIT(2) 92fe6dd2a4SYong Wu #define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x))) 93431e9cabSYong Wu 94431e9cabSYong Wu struct mtk_smi_reg_pair { 95431e9cabSYong Wu unsigned int offset; 96431e9cabSYong Wu u32 value; 97431e9cabSYong Wu }; 98431e9cabSYong Wu 99a5c18986SYong Wu enum mtk_smi_type { 10042d42c76SYong Wu MTK_SMI_GEN1, 10147404757SYong Wu MTK_SMI_GEN2, /* gen2 smi common */ 10247404757SYong Wu MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */ 10342d42c76SYong Wu }; 10442d42c76SYong Wu 1050e14917cSYong Wu /* larbs: Require apb/smi clocks while gals is optional. */ 1060e14917cSYong Wu static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"}; 1070e14917cSYong Wu #define MTK_SMI_LARB_REQ_CLK_NR 2 1080e14917cSYong Wu #define MTK_SMI_LARB_OPT_CLK_NR 1 1090e14917cSYong Wu 1100e14917cSYong Wu /* 1110e14917cSYong Wu * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required. 1123e4f74e0SYong Wu * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required. 1130e14917cSYong Wu */ 1140e14917cSYong Wu static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"}; 115205e1776SAngeloGioacchino Del Regno #define MTK_SMI_CLK_NR_MAX ARRAY_SIZE(mtk_smi_common_clks) 1160e14917cSYong Wu #define MTK_SMI_COM_REQ_CLK_NR 2 1170e14917cSYong Wu #define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX 1183e4f74e0SYong Wu #define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3 1190e14917cSYong Wu 12042d42c76SYong Wu struct mtk_smi_common_plat { 121a5c18986SYong Wu enum mtk_smi_type type; 12264fea74aSYong Wu bool has_gals; 123567e58cfSYong Wu u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ 124431e9cabSYong Wu 125431e9cabSYong Wu const struct mtk_smi_reg_pair *init; 12642d42c76SYong Wu }; 12742d42c76SYong Wu 1283c8f4ad8SHonghui Zhang struct mtk_smi_larb_gen { 1293c8f4ad8SHonghui Zhang int port_in_larb[MTK_LARB_NR_MAX + 1]; 130*8c1561edSChengci.Xu int (*config_port)(struct device *dev); 1312e9b0908SYong Wu unsigned int larb_direct_to_common_mask; 132fe6dd2a4SYong Wu unsigned int flags_general; 133fe6dd2a4SYong Wu const u8 (*ostd)[SMI_LARB_PORT_NR_MAX]; 1343c8f4ad8SHonghui Zhang }; 135cc8bbe1aSYong Wu 136cc8bbe1aSYong Wu struct mtk_smi { 137cc8bbe1aSYong Wu struct device *dev; 1380e14917cSYong Wu unsigned int clk_num; 1390e14917cSYong Wu struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX]; 1403c8f4ad8SHonghui Zhang struct clk *clk_async; /*only needed by mt2701*/ 141567e58cfSYong Wu union { 142567e58cfSYong Wu void __iomem *smi_ao_base; /* only for gen1 */ 143567e58cfSYong Wu void __iomem *base; /* only for gen2 */ 144567e58cfSYong Wu }; 14547404757SYong Wu struct device *smi_common_dev; /* for sub common */ 14642d42c76SYong Wu const struct mtk_smi_common_plat *plat; 147cc8bbe1aSYong Wu }; 148cc8bbe1aSYong Wu 149cc8bbe1aSYong Wu struct mtk_smi_larb { /* larb: local arbiter */ 150cc8bbe1aSYong Wu struct mtk_smi smi; 151cc8bbe1aSYong Wu void __iomem *base; 15247404757SYong Wu struct device *smi_common_dev; /* common or sub-common dev */ 1533c8f4ad8SHonghui Zhang const struct mtk_smi_larb_gen *larb_gen; 1543c8f4ad8SHonghui Zhang int larbid; 155cc8bbe1aSYong Wu u32 *mmu; 1568d2c749eSYong Wu unsigned char *bank; 157cc8bbe1aSYong Wu }; 158cc8bbe1aSYong Wu 159cc8bbe1aSYong Wu static int 160cc8bbe1aSYong Wu mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) 161cc8bbe1aSYong Wu { 162cc8bbe1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 1631ee9feb2SYong Wu struct mtk_smi_larb_iommu *larb_mmu = data; 164cc8bbe1aSYong Wu unsigned int i; 165cc8bbe1aSYong Wu 166ec2da07cSYong Wu for (i = 0; i < MTK_LARB_NR_MAX; i++) { 1671ee9feb2SYong Wu if (dev == larb_mmu[i].dev) { 168ec2da07cSYong Wu larb->larbid = i; 1691ee9feb2SYong Wu larb->mmu = &larb_mmu[i].mmu; 1708d2c749eSYong Wu larb->bank = larb_mmu[i].bank; 171cc8bbe1aSYong Wu return 0; 172cc8bbe1aSYong Wu } 173cc8bbe1aSYong Wu } 174cc8bbe1aSYong Wu return -ENODEV; 175cc8bbe1aSYong Wu } 176cc8bbe1aSYong Wu 177534e0ad2SYong Wu static void 178534e0ad2SYong Wu mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) 179e6dec923SYong Wu { 180534e0ad2SYong Wu /* Do nothing as the iommu is always enabled. */ 181e6dec923SYong Wu } 182e6dec923SYong Wu 183534e0ad2SYong Wu static const struct component_ops mtk_smi_larb_component_ops = { 184534e0ad2SYong Wu .bind = mtk_smi_larb_bind, 185534e0ad2SYong Wu .unbind = mtk_smi_larb_unbind, 186534e0ad2SYong Wu }; 187a8529f3bSFabien Parent 188*8c1561edSChengci.Xu static int mtk_smi_larb_config_port_gen1(struct device *dev) 1893c8f4ad8SHonghui Zhang { 1903c8f4ad8SHonghui Zhang struct mtk_smi_larb *larb = dev_get_drvdata(dev); 1913c8f4ad8SHonghui Zhang const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 1923c8f4ad8SHonghui Zhang struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); 1933c8f4ad8SHonghui Zhang int i, m4u_port_id, larb_port_num; 1943c8f4ad8SHonghui Zhang u32 sec_con_val, reg_val; 1953c8f4ad8SHonghui Zhang 1963c8f4ad8SHonghui Zhang m4u_port_id = larb_gen->port_in_larb[larb->larbid]; 1973c8f4ad8SHonghui Zhang larb_port_num = larb_gen->port_in_larb[larb->larbid + 1] 1983c8f4ad8SHonghui Zhang - larb_gen->port_in_larb[larb->larbid]; 1993c8f4ad8SHonghui Zhang 2003c8f4ad8SHonghui Zhang for (i = 0; i < larb_port_num; i++, m4u_port_id++) { 2013c8f4ad8SHonghui Zhang if (*larb->mmu & BIT(i)) { 2023c8f4ad8SHonghui Zhang /* bit[port + 3] controls the virtual or physical */ 2033c8f4ad8SHonghui Zhang sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id); 2043c8f4ad8SHonghui Zhang } else { 2053c8f4ad8SHonghui Zhang /* do not need to enable m4u for this port */ 2063c8f4ad8SHonghui Zhang continue; 2073c8f4ad8SHonghui Zhang } 2083c8f4ad8SHonghui Zhang reg_val = readl(common->smi_ao_base 2093c8f4ad8SHonghui Zhang + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 2103c8f4ad8SHonghui Zhang reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); 2113c8f4ad8SHonghui Zhang reg_val |= sec_con_val; 2123c8f4ad8SHonghui Zhang reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); 2133c8f4ad8SHonghui Zhang writel(reg_val, 2143c8f4ad8SHonghui Zhang common->smi_ao_base 2153c8f4ad8SHonghui Zhang + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 2163c8f4ad8SHonghui Zhang } 217*8c1561edSChengci.Xu return 0; 2183c8f4ad8SHonghui Zhang } 2193c8f4ad8SHonghui Zhang 220*8c1561edSChengci.Xu static int mtk_smi_larb_config_port_mt8167(struct device *dev) 221cc8bbe1aSYong Wu { 222534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 223534e0ad2SYong Wu 224534e0ad2SYong Wu writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); 225*8c1561edSChengci.Xu return 0; 226cc8bbe1aSYong Wu } 227cc8bbe1aSYong Wu 228*8c1561edSChengci.Xu static int mtk_smi_larb_config_port_mt8173(struct device *dev) 229534e0ad2SYong Wu { 230534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 231cc8bbe1aSYong Wu 232534e0ad2SYong Wu writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN); 233*8c1561edSChengci.Xu return 0; 234534e0ad2SYong Wu } 2353c8f4ad8SHonghui Zhang 236*8c1561edSChengci.Xu static int mtk_smi_larb_config_port_gen2_general(struct device *dev) 237534e0ad2SYong Wu { 238534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 239fe6dd2a4SYong Wu u32 reg, flags_general = larb->larb_gen->flags_general; 240383a44aeSYong Wu const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL; 241534e0ad2SYong Wu int i; 242534e0ad2SYong Wu 243534e0ad2SYong Wu if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) 244*8c1561edSChengci.Xu return 0; 245534e0ad2SYong Wu 246fe6dd2a4SYong Wu if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) { 247fe6dd2a4SYong Wu reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON); 248fe6dd2a4SYong Wu reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK; 249fe6dd2a4SYong Wu reg |= SMI_LARB_THRT_RD_NU_LMT; 250fe6dd2a4SYong Wu writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON); 251fe6dd2a4SYong Wu } 252fe6dd2a4SYong Wu 253fe6dd2a4SYong Wu if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG)) 254fe6dd2a4SYong Wu writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); 255fe6dd2a4SYong Wu 256fe6dd2a4SYong Wu for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) 257fe6dd2a4SYong Wu writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); 258fe6dd2a4SYong Wu 259534e0ad2SYong Wu for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { 260534e0ad2SYong Wu reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); 261534e0ad2SYong Wu reg |= F_MMU_EN; 262534e0ad2SYong Wu reg |= BANK_SEL(larb->bank[i]); 263534e0ad2SYong Wu writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); 264534e0ad2SYong Wu } 265*8c1561edSChengci.Xu return 0; 266534e0ad2SYong Wu } 267a8529f3bSFabien Parent 268fe6dd2a4SYong Wu static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = { 269fe6dd2a4SYong Wu [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */ 270fe6dd2a4SYong Wu [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */ 271fe6dd2a4SYong Wu [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, /* ... */ 272fe6dd2a4SYong Wu [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,}, 273fe6dd2a4SYong Wu [4] = {0x06, 0x01, 0x17, 0x06, 0x0a,}, 274fe6dd2a4SYong Wu [5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,}, 275fe6dd2a4SYong Wu [6] = {0x06, 0x01, 0x06, 0x0a,}, 276fe6dd2a4SYong Wu [7] = {0x0c, 0x0c, 0x12,}, 277fe6dd2a4SYong Wu [8] = {0x0c, 0x0c, 0x12,}, 278fe6dd2a4SYong Wu [9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a, 279fe6dd2a4SYong Wu 0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,}, 280fe6dd2a4SYong Wu [10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10, 281fe6dd2a4SYong Wu 0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d, 282fe6dd2a4SYong Wu 0x0d, 0x06, 0x10, 0x10,}, 283fe6dd2a4SYong Wu [11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,}, 284fe6dd2a4SYong Wu [12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,}, 285fe6dd2a4SYong Wu [13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,}, 286fe6dd2a4SYong Wu [14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01, 287fe6dd2a4SYong Wu 0x01, 0x02, 0x02, 0x08, 0x02,}, 288fe6dd2a4SYong Wu [15] = {}, 289fe6dd2a4SYong Wu [16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a, 290fe6dd2a4SYong Wu 0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,}, 291fe6dd2a4SYong Wu [17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 292fe6dd2a4SYong Wu [18] = {0x12, 0x06, 0x12, 0x06,}, 293fe6dd2a4SYong Wu [19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 294fe6dd2a4SYong Wu 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 295fe6dd2a4SYong Wu 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 296fe6dd2a4SYong Wu [20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 297fe6dd2a4SYong Wu 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 298fe6dd2a4SYong Wu 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 299fe6dd2a4SYong Wu [21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 300fe6dd2a4SYong Wu [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 301fe6dd2a4SYong Wu [23] = {0x18, 0x01,}, 302fe6dd2a4SYong Wu [24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01, 303fe6dd2a4SYong Wu 0x01, 0x01,}, 304fe6dd2a4SYong Wu [25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 305fe6dd2a4SYong Wu 0x02, 0x01,}, 306fe6dd2a4SYong Wu [26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 307fe6dd2a4SYong Wu 0x02, 0x01,}, 308fe6dd2a4SYong Wu [27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 309fe6dd2a4SYong Wu 0x02, 0x01,}, 310fe6dd2a4SYong Wu [28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 311fe6dd2a4SYong Wu }; 312fe6dd2a4SYong Wu 3133c8f4ad8SHonghui Zhang static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { 3143c8f4ad8SHonghui Zhang .port_in_larb = { 3153c8f4ad8SHonghui Zhang LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 3163c8f4ad8SHonghui Zhang LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 3173c8f4ad8SHonghui Zhang }, 3183c8f4ad8SHonghui Zhang .config_port = mtk_smi_larb_config_port_gen1, 3193c8f4ad8SHonghui Zhang }; 3203c8f4ad8SHonghui Zhang 321e6dec923SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { 3222e9b0908SYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 3232e9b0908SYong Wu .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ 324e6dec923SYong Wu }; 325e6dec923SYong Wu 326fc492f33SMing-Fan Chen static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { 327fc492f33SMing-Fan Chen .config_port = mtk_smi_larb_config_port_gen2_general, 328fc492f33SMing-Fan Chen .larb_direct_to_common_mask = 329fc492f33SMing-Fan Chen BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), 330fc492f33SMing-Fan Chen /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ 331fc492f33SMing-Fan Chen }; 332fc492f33SMing-Fan Chen 333534e0ad2SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = { 334534e0ad2SYong Wu /* mt8167 do not need the port in larb */ 335534e0ad2SYong Wu .config_port = mtk_smi_larb_config_port_mt8167, 336534e0ad2SYong Wu }; 337534e0ad2SYong Wu 338534e0ad2SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { 339534e0ad2SYong Wu /* mt8173 do not need the port in larb */ 340534e0ad2SYong Wu .config_port = mtk_smi_larb_config_port_mt8173, 341534e0ad2SYong Wu }; 342534e0ad2SYong Wu 343907ba6a1SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { 344907ba6a1SYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 345907ba6a1SYong Wu .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), 346907ba6a1SYong Wu /* IPU0 | IPU1 | CCU */ 347907ba6a1SYong Wu }; 348907ba6a1SYong Wu 34986a010bfSYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = { 35086a010bfSYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 35186a010bfSYong Wu .flags_general = MTK_SMI_FLAG_SLEEP_CTL, 35286a010bfSYong Wu }; 35386a010bfSYong Wu 35402c02ddcSYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { 35502c02ddcSYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 35602c02ddcSYong Wu }; 35702c02ddcSYong Wu 358cc4f9dcdSYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = { 359cc4f9dcdSYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 36012fbfd66SAngeloGioacchino Del Regno .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG | 36112fbfd66SAngeloGioacchino Del Regno MTK_SMI_FLAG_SLEEP_CTL, 362fe6dd2a4SYong Wu .ostd = mtk_smi_larb_mt8195_ostd, 363cc4f9dcdSYong Wu }; 364cc4f9dcdSYong Wu 3653c8f4ad8SHonghui Zhang static const struct of_device_id mtk_smi_larb_of_ids[] = { 366534e0ad2SYong Wu {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701}, 367534e0ad2SYong Wu {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712}, 368534e0ad2SYong Wu {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779}, 3690d97f217SAngeloGioacchino Del Regno {.compatible = "mediatek,mt6795-smi-larb", .data = &mtk_smi_larb_mt8173}, 370534e0ad2SYong Wu {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167}, 371534e0ad2SYong Wu {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173}, 372534e0ad2SYong Wu {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, 37386a010bfSYong Wu {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186}, 374534e0ad2SYong Wu {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, 375cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195}, 3763c8f4ad8SHonghui Zhang {} 3773c8f4ad8SHonghui Zhang }; 3783c8f4ad8SHonghui Zhang 3798956500eSYong Wu static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb) 3808956500eSYong Wu { 3818956500eSYong Wu int ret; 3828956500eSYong Wu u32 tmp; 3838956500eSYong Wu 3848956500eSYong Wu writel_relaxed(SLP_PROT_EN, larb->base + SMI_LARB_SLP_CON); 3858956500eSYong Wu ret = readl_poll_timeout_atomic(larb->base + SMI_LARB_SLP_CON, 3868956500eSYong Wu tmp, !!(tmp & SLP_PROT_RDY), 10, 1000); 3878956500eSYong Wu if (ret) { 3888956500eSYong Wu /* TODO: Reset this larb if it fails here. */ 3898956500eSYong Wu dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp); 3908956500eSYong Wu } 3918956500eSYong Wu return ret; 3928956500eSYong Wu } 3938956500eSYong Wu 3948956500eSYong Wu static void mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb *larb) 3958956500eSYong Wu { 3968956500eSYong Wu writel_relaxed(0, larb->base + SMI_LARB_SLP_CON); 3978956500eSYong Wu } 3988956500eSYong Wu 39947404757SYong Wu static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev) 40047404757SYong Wu { 40147404757SYong Wu struct platform_device *smi_com_pdev; 40247404757SYong Wu struct device_node *smi_com_node; 40347404757SYong Wu struct device *smi_com_dev; 40447404757SYong Wu struct device_link *link; 40547404757SYong Wu 40647404757SYong Wu smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); 40747404757SYong Wu if (!smi_com_node) 40847404757SYong Wu return -EINVAL; 40947404757SYong Wu 41047404757SYong Wu smi_com_pdev = of_find_device_by_node(smi_com_node); 41147404757SYong Wu of_node_put(smi_com_node); 41247404757SYong Wu if (smi_com_pdev) { 41347404757SYong Wu /* smi common is the supplier, Make sure it is ready before */ 414038ae37cSMiaoqian Lin if (!platform_get_drvdata(smi_com_pdev)) { 415038ae37cSMiaoqian Lin put_device(&smi_com_pdev->dev); 41647404757SYong Wu return -EPROBE_DEFER; 417038ae37cSMiaoqian Lin } 41847404757SYong Wu smi_com_dev = &smi_com_pdev->dev; 41947404757SYong Wu link = device_link_add(dev, smi_com_dev, 42047404757SYong Wu DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 42147404757SYong Wu if (!link) { 42247404757SYong Wu dev_err(dev, "Unable to link smi-common dev\n"); 423038ae37cSMiaoqian Lin put_device(&smi_com_pdev->dev); 42447404757SYong Wu return -ENODEV; 42547404757SYong Wu } 42647404757SYong Wu *com_dev = smi_com_dev; 42747404757SYong Wu } else { 42847404757SYong Wu dev_err(dev, "Failed to get the smi_common device\n"); 42947404757SYong Wu return -EINVAL; 43047404757SYong Wu } 43147404757SYong Wu return 0; 43247404757SYong Wu } 43347404757SYong Wu 4340e14917cSYong Wu static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi, 4350e14917cSYong Wu const char * const clks[], 4360e14917cSYong Wu unsigned int clk_nr_required, 4370e14917cSYong Wu unsigned int clk_nr_optional) 4380e14917cSYong Wu { 4390e14917cSYong Wu int i, ret; 4400e14917cSYong Wu 4410e14917cSYong Wu for (i = 0; i < clk_nr_required; i++) 4420e14917cSYong Wu smi->clks[i].id = clks[i]; 4430e14917cSYong Wu ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks); 4440e14917cSYong Wu if (ret) 4450e14917cSYong Wu return ret; 4460e14917cSYong Wu 4470e14917cSYong Wu for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++) 4480e14917cSYong Wu smi->clks[i].id = clks[i]; 4490e14917cSYong Wu ret = devm_clk_bulk_get_optional(dev, clk_nr_optional, 4500e14917cSYong Wu smi->clks + clk_nr_required); 4510e14917cSYong Wu smi->clk_num = clk_nr_required + clk_nr_optional; 4520e14917cSYong Wu return ret; 4530e14917cSYong Wu } 4540e14917cSYong Wu 455cc8bbe1aSYong Wu static int mtk_smi_larb_probe(struct platform_device *pdev) 456cc8bbe1aSYong Wu { 457cc8bbe1aSYong Wu struct mtk_smi_larb *larb; 458cc8bbe1aSYong Wu struct device *dev = &pdev->dev; 4590e14917cSYong Wu int ret; 460cc8bbe1aSYong Wu 461cc8bbe1aSYong Wu larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); 462cc8bbe1aSYong Wu if (!larb) 463cc8bbe1aSYong Wu return -ENOMEM; 464cc8bbe1aSYong Wu 46575487860SHonghui Zhang larb->larb_gen = of_device_get_match_data(dev); 466912fea8bSYong Wu larb->base = devm_platform_ioremap_resource(pdev, 0); 467cc8bbe1aSYong Wu if (IS_ERR(larb->base)) 468cc8bbe1aSYong Wu return PTR_ERR(larb->base); 469cc8bbe1aSYong Wu 4700e14917cSYong Wu ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks, 4710e14917cSYong Wu MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR); 4720e14917cSYong Wu if (ret) 4730e14917cSYong Wu return ret; 474cc8bbe1aSYong Wu 475cc8bbe1aSYong Wu larb->smi.dev = dev; 476cc8bbe1aSYong Wu 47747404757SYong Wu ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev); 47847404757SYong Wu if (ret < 0) 47947404757SYong Wu return ret; 480cc8bbe1aSYong Wu 481cc8bbe1aSYong Wu pm_runtime_enable(dev); 482cc8bbe1aSYong Wu platform_set_drvdata(pdev, larb); 48330b869e7SYong Wu ret = component_add(dev, &mtk_smi_larb_component_ops); 48430b869e7SYong Wu if (ret) 48530b869e7SYong Wu goto err_pm_disable; 48630b869e7SYong Wu return 0; 48730b869e7SYong Wu 48830b869e7SYong Wu err_pm_disable: 48930b869e7SYong Wu pm_runtime_disable(dev); 49030b869e7SYong Wu device_link_remove(dev, larb->smi_common_dev); 49130b869e7SYong Wu return ret; 492cc8bbe1aSYong Wu } 493cc8bbe1aSYong Wu 494cc8bbe1aSYong Wu static int mtk_smi_larb_remove(struct platform_device *pdev) 495cc8bbe1aSYong Wu { 4966ce2c05bSYong Wu struct mtk_smi_larb *larb = platform_get_drvdata(pdev); 4976ce2c05bSYong Wu 4986ce2c05bSYong Wu device_link_remove(&pdev->dev, larb->smi_common_dev); 499cc8bbe1aSYong Wu pm_runtime_disable(&pdev->dev); 500cc8bbe1aSYong Wu component_del(&pdev->dev, &mtk_smi_larb_component_ops); 501cc8bbe1aSYong Wu return 0; 502cc8bbe1aSYong Wu } 503cc8bbe1aSYong Wu 5044f0a1a1aSYong Wu static int __maybe_unused mtk_smi_larb_resume(struct device *dev) 5054f0a1a1aSYong Wu { 5064f0a1a1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 5074f0a1a1aSYong Wu const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 5084f0a1a1aSYong Wu int ret; 5094f0a1a1aSYong Wu 5100e14917cSYong Wu ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks); 511a6945f45SYong Wu if (ret) 5124f0a1a1aSYong Wu return ret; 5134f0a1a1aSYong Wu 5148956500eSYong Wu if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) 5158956500eSYong Wu mtk_smi_larb_sleep_ctrl_disable(larb); 5168956500eSYong Wu 5174f0a1a1aSYong Wu /* Configure the basic setting for this larb */ 518*8c1561edSChengci.Xu return larb_gen->config_port(dev); 5194f0a1a1aSYong Wu } 5204f0a1a1aSYong Wu 5214f0a1a1aSYong Wu static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) 5224f0a1a1aSYong Wu { 5234f0a1a1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 5248956500eSYong Wu int ret; 5258956500eSYong Wu 5268956500eSYong Wu if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) { 5278956500eSYong Wu ret = mtk_smi_larb_sleep_ctrl_enable(larb); 5288956500eSYong Wu if (ret) 5298956500eSYong Wu return ret; 5308956500eSYong Wu } 5314f0a1a1aSYong Wu 5320e14917cSYong Wu clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks); 5334f0a1a1aSYong Wu return 0; 5344f0a1a1aSYong Wu } 5354f0a1a1aSYong Wu 5364f0a1a1aSYong Wu static const struct dev_pm_ops smi_larb_pm_ops = { 5374f0a1a1aSYong Wu SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL) 538fb03082aSYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 539fb03082aSYong Wu pm_runtime_force_resume) 5404f0a1a1aSYong Wu }; 5414f0a1a1aSYong Wu 542cc8bbe1aSYong Wu static struct platform_driver mtk_smi_larb_driver = { 543cc8bbe1aSYong Wu .probe = mtk_smi_larb_probe, 544cc8bbe1aSYong Wu .remove = mtk_smi_larb_remove, 545cc8bbe1aSYong Wu .driver = { 546cc8bbe1aSYong Wu .name = "mtk-smi-larb", 547cc8bbe1aSYong Wu .of_match_table = mtk_smi_larb_of_ids, 5484f0a1a1aSYong Wu .pm = &smi_larb_pm_ops, 549cc8bbe1aSYong Wu } 550cc8bbe1aSYong Wu }; 551cc8bbe1aSYong Wu 5520d97f217SAngeloGioacchino Del Regno static const struct mtk_smi_reg_pair mtk_smi_common_mt6795_init[SMI_COMMON_INIT_REGS_NR] = { 5530d97f217SAngeloGioacchino Del Regno {SMI_L1_ARB, 0x1b}, 5540d97f217SAngeloGioacchino Del Regno {SMI_M4U_TH, 0xce810c85}, 5550d97f217SAngeloGioacchino Del Regno {SMI_FIFO_TH1, 0x43214c8}, 5560d97f217SAngeloGioacchino Del Regno {SMI_READ_FIFO_TH, 0x191f}, 5570d97f217SAngeloGioacchino Del Regno }; 5580d97f217SAngeloGioacchino Del Regno 559431e9cabSYong Wu static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = { 560431e9cabSYong Wu {SMI_L1LEN, 0xb}, 561431e9cabSYong Wu {SMI_M4U_TH, 0xe100e10}, 562431e9cabSYong Wu {SMI_FIFO_TH1, 0x506090a}, 563431e9cabSYong Wu {SMI_FIFO_TH2, 0x506090a}, 564431e9cabSYong Wu {SMI_DCM, 0x4f1}, 565431e9cabSYong Wu {SMI_DUMMY, 0x1}, 566431e9cabSYong Wu }; 567431e9cabSYong Wu 56842d42c76SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_gen1 = { 569a5c18986SYong Wu .type = MTK_SMI_GEN1, 57042d42c76SYong Wu }; 57142d42c76SYong Wu 57242d42c76SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { 573a5c18986SYong Wu .type = MTK_SMI_GEN2, 57442d42c76SYong Wu }; 57542d42c76SYong Wu 576fc492f33SMing-Fan Chen static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { 577a5c18986SYong Wu .type = MTK_SMI_GEN2, 578fc492f33SMing-Fan Chen .has_gals = true, 579fc492f33SMing-Fan Chen .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | 580fc492f33SMing-Fan Chen F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), 581fc492f33SMing-Fan Chen }; 582fc492f33SMing-Fan Chen 5830d97f217SAngeloGioacchino Del Regno static const struct mtk_smi_common_plat mtk_smi_common_mt6795 = { 5840d97f217SAngeloGioacchino Del Regno .type = MTK_SMI_GEN2, 5850d97f217SAngeloGioacchino Del Regno .bus_sel = F_MMU1_LARB(0), 5860d97f217SAngeloGioacchino Del Regno .init = mtk_smi_common_mt6795_init, 5870d97f217SAngeloGioacchino Del Regno }; 5880d97f217SAngeloGioacchino Del Regno 589907ba6a1SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { 590a5c18986SYong Wu .type = MTK_SMI_GEN2, 591907ba6a1SYong Wu .has_gals = true, 592567e58cfSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 593567e58cfSYong Wu F_MMU1_LARB(7), 594907ba6a1SYong Wu }; 595907ba6a1SYong Wu 59686a010bfSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = { 59786a010bfSYong Wu .type = MTK_SMI_GEN2, 59886a010bfSYong Wu .has_gals = true, 59986a010bfSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7), 60086a010bfSYong Wu }; 60186a010bfSYong Wu 60202c02ddcSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { 603a5c18986SYong Wu .type = MTK_SMI_GEN2, 60402c02ddcSYong Wu .has_gals = true, 60502c02ddcSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 60602c02ddcSYong Wu F_MMU1_LARB(6), 60702c02ddcSYong Wu }; 60802c02ddcSYong Wu 609cc4f9dcdSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = { 610cc4f9dcdSYong Wu .type = MTK_SMI_GEN2, 611cc4f9dcdSYong Wu .has_gals = true, 612cc4f9dcdSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) | 613cc4f9dcdSYong Wu F_MMU1_LARB(7), 614431e9cabSYong Wu .init = mtk_smi_common_mt8195_init, 615cc4f9dcdSYong Wu }; 616cc4f9dcdSYong Wu 617cc4f9dcdSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = { 618cc4f9dcdSYong Wu .type = MTK_SMI_GEN2, 619cc4f9dcdSYong Wu .has_gals = true, 620cc4f9dcdSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7), 621431e9cabSYong Wu .init = mtk_smi_common_mt8195_init, 622cc4f9dcdSYong Wu }; 623cc4f9dcdSYong Wu 624cc4f9dcdSYong Wu static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = { 625cc4f9dcdSYong Wu .type = MTK_SMI_GEN2_SUB_COMM, 626cc4f9dcdSYong Wu .has_gals = true, 627cc4f9dcdSYong Wu }; 628cc4f9dcdSYong Wu 6293c8f4ad8SHonghui Zhang static const struct of_device_id mtk_smi_common_of_ids[] = { 630534e0ad2SYong Wu {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1}, 631534e0ad2SYong Wu {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2}, 632534e0ad2SYong Wu {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779}, 6330d97f217SAngeloGioacchino Del Regno {.compatible = "mediatek,mt6795-smi-common", .data = &mtk_smi_common_mt6795}, 634534e0ad2SYong Wu {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2}, 635534e0ad2SYong Wu {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2}, 636534e0ad2SYong Wu {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183}, 63786a010bfSYong Wu {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186}, 638534e0ad2SYong Wu {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, 639cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, 640cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, 641cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195}, 6423c8f4ad8SHonghui Zhang {} 6433c8f4ad8SHonghui Zhang }; 6443c8f4ad8SHonghui Zhang 645cc8bbe1aSYong Wu static int mtk_smi_common_probe(struct platform_device *pdev) 646cc8bbe1aSYong Wu { 647cc8bbe1aSYong Wu struct device *dev = &pdev->dev; 648cc8bbe1aSYong Wu struct mtk_smi *common; 6490e14917cSYong Wu int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR; 650cc8bbe1aSYong Wu 651cc8bbe1aSYong Wu common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); 652cc8bbe1aSYong Wu if (!common) 653cc8bbe1aSYong Wu return -ENOMEM; 654cc8bbe1aSYong Wu common->dev = dev; 65542d42c76SYong Wu common->plat = of_device_get_match_data(dev); 656cc8bbe1aSYong Wu 6573e4f74e0SYong Wu if (common->plat->has_gals) { 6583e4f74e0SYong Wu if (common->plat->type == MTK_SMI_GEN2) 6590e14917cSYong Wu clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR; 6603e4f74e0SYong Wu else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 6613e4f74e0SYong Wu clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR; 6623e4f74e0SYong Wu } 6630e14917cSYong Wu ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0); 6640e14917cSYong Wu if (ret) 6650e14917cSYong Wu return ret; 66664fea74aSYong Wu 6673c8f4ad8SHonghui Zhang /* 6683c8f4ad8SHonghui Zhang * for mtk smi gen 1, we need to get the ao(always on) base to config 6693c8f4ad8SHonghui Zhang * m4u port, and we need to enable the aync clock for transform the smi 6703c8f4ad8SHonghui Zhang * clock into emi clock domain, but for mtk smi gen2, there's no smi ao 6713c8f4ad8SHonghui Zhang * base. 6723c8f4ad8SHonghui Zhang */ 673a5c18986SYong Wu if (common->plat->type == MTK_SMI_GEN1) { 674912fea8bSYong Wu common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0); 6753c8f4ad8SHonghui Zhang if (IS_ERR(common->smi_ao_base)) 6763c8f4ad8SHonghui Zhang return PTR_ERR(common->smi_ao_base); 6773c8f4ad8SHonghui Zhang 6783c8f4ad8SHonghui Zhang common->clk_async = devm_clk_get(dev, "async"); 6793c8f4ad8SHonghui Zhang if (IS_ERR(common->clk_async)) 6803c8f4ad8SHonghui Zhang return PTR_ERR(common->clk_async); 6813c8f4ad8SHonghui Zhang 68246cc815dSArvind Yadav ret = clk_prepare_enable(common->clk_async); 68346cc815dSArvind Yadav if (ret) 68446cc815dSArvind Yadav return ret; 685567e58cfSYong Wu } else { 686912fea8bSYong Wu common->base = devm_platform_ioremap_resource(pdev, 0); 687567e58cfSYong Wu if (IS_ERR(common->base)) 688567e58cfSYong Wu return PTR_ERR(common->base); 6893c8f4ad8SHonghui Zhang } 69047404757SYong Wu 69147404757SYong Wu /* link its smi-common if this is smi-sub-common */ 69247404757SYong Wu if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) { 69347404757SYong Wu ret = mtk_smi_device_link_common(dev, &common->smi_common_dev); 69447404757SYong Wu if (ret < 0) 69547404757SYong Wu return ret; 69647404757SYong Wu } 69747404757SYong Wu 698cc8bbe1aSYong Wu pm_runtime_enable(dev); 699cc8bbe1aSYong Wu platform_set_drvdata(pdev, common); 700cc8bbe1aSYong Wu return 0; 701cc8bbe1aSYong Wu } 702cc8bbe1aSYong Wu 703cc8bbe1aSYong Wu static int mtk_smi_common_remove(struct platform_device *pdev) 704cc8bbe1aSYong Wu { 70547404757SYong Wu struct mtk_smi *common = dev_get_drvdata(&pdev->dev); 70647404757SYong Wu 70747404757SYong Wu if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 70847404757SYong Wu device_link_remove(&pdev->dev, common->smi_common_dev); 709cc8bbe1aSYong Wu pm_runtime_disable(&pdev->dev); 710cc8bbe1aSYong Wu return 0; 711cc8bbe1aSYong Wu } 712cc8bbe1aSYong Wu 7134f0a1a1aSYong Wu static int __maybe_unused mtk_smi_common_resume(struct device *dev) 7144f0a1a1aSYong Wu { 7154f0a1a1aSYong Wu struct mtk_smi *common = dev_get_drvdata(dev); 716431e9cabSYong Wu const struct mtk_smi_reg_pair *init = common->plat->init; 717431e9cabSYong Wu u32 bus_sel = common->plat->bus_sel; /* default is 0 */ 718431e9cabSYong Wu int ret, i; 7194f0a1a1aSYong Wu 7200e14917cSYong Wu ret = clk_bulk_prepare_enable(common->clk_num, common->clks); 7210e14917cSYong Wu if (ret) 7224f0a1a1aSYong Wu return ret; 723567e58cfSYong Wu 724431e9cabSYong Wu if (common->plat->type != MTK_SMI_GEN2) 725431e9cabSYong Wu return 0; 726431e9cabSYong Wu 727431e9cabSYong Wu for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++) 728431e9cabSYong Wu writel_relaxed(init[i].value, common->base + init[i].offset); 729431e9cabSYong Wu 730567e58cfSYong Wu writel(bus_sel, common->base + SMI_BUS_SEL); 7314f0a1a1aSYong Wu return 0; 7324f0a1a1aSYong Wu } 7334f0a1a1aSYong Wu 7344f0a1a1aSYong Wu static int __maybe_unused mtk_smi_common_suspend(struct device *dev) 7354f0a1a1aSYong Wu { 7364f0a1a1aSYong Wu struct mtk_smi *common = dev_get_drvdata(dev); 7374f0a1a1aSYong Wu 7380e14917cSYong Wu clk_bulk_disable_unprepare(common->clk_num, common->clks); 7394f0a1a1aSYong Wu return 0; 7404f0a1a1aSYong Wu } 7414f0a1a1aSYong Wu 7424f0a1a1aSYong Wu static const struct dev_pm_ops smi_common_pm_ops = { 7434f0a1a1aSYong Wu SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL) 744fb03082aSYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 745fb03082aSYong Wu pm_runtime_force_resume) 7464f0a1a1aSYong Wu }; 7474f0a1a1aSYong Wu 748cc8bbe1aSYong Wu static struct platform_driver mtk_smi_common_driver = { 749cc8bbe1aSYong Wu .probe = mtk_smi_common_probe, 750cc8bbe1aSYong Wu .remove = mtk_smi_common_remove, 751cc8bbe1aSYong Wu .driver = { 752cc8bbe1aSYong Wu .name = "mtk-smi-common", 753cc8bbe1aSYong Wu .of_match_table = mtk_smi_common_of_ids, 7544f0a1a1aSYong Wu .pm = &smi_common_pm_ops, 755cc8bbe1aSYong Wu } 756cc8bbe1aSYong Wu }; 757cc8bbe1aSYong Wu 75818212031SYong Wu static struct platform_driver * const smidrivers[] = { 75918212031SYong Wu &mtk_smi_common_driver, 76018212031SYong Wu &mtk_smi_larb_driver, 76118212031SYong Wu }; 76218212031SYong Wu 763cc8bbe1aSYong Wu static int __init mtk_smi_init(void) 764cc8bbe1aSYong Wu { 76518212031SYong Wu return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 766cc8bbe1aSYong Wu } 7674f608d38SYong Wu module_init(mtk_smi_init); 76850fc8d92SYong Wu 76950fc8d92SYong Wu static void __exit mtk_smi_exit(void) 77050fc8d92SYong Wu { 77150fc8d92SYong Wu platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 77250fc8d92SYong Wu } 77350fc8d92SYong Wu module_exit(mtk_smi_exit); 77450fc8d92SYong Wu 77550fc8d92SYong Wu MODULE_DESCRIPTION("MediaTek SMI driver"); 77650fc8d92SYong Wu MODULE_LICENSE("GPL v2"); 777