11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2cc8bbe1aSYong Wu /* 3cc8bbe1aSYong Wu * Copyright (c) 2015-2016 MediaTek Inc. 4cc8bbe1aSYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 5cc8bbe1aSYong Wu */ 6cc8bbe1aSYong Wu #include <linux/clk.h> 7cc8bbe1aSYong Wu #include <linux/component.h> 8cc8bbe1aSYong Wu #include <linux/device.h> 9cc8bbe1aSYong Wu #include <linux/err.h> 10cc8bbe1aSYong Wu #include <linux/io.h> 114f608d38SYong Wu #include <linux/module.h> 12cc8bbe1aSYong Wu #include <linux/of.h> 13cc8bbe1aSYong Wu #include <linux/of_platform.h> 14cc8bbe1aSYong Wu #include <linux/platform_device.h> 15cc8bbe1aSYong Wu #include <linux/pm_runtime.h> 16cc8bbe1aSYong Wu #include <soc/mediatek/smi.h> 173c8f4ad8SHonghui Zhang #include <dt-bindings/memory/mt2701-larb-port.h> 18cc8bbe1aSYong Wu 19e6dec923SYong Wu /* mt8173 */ 20cc8bbe1aSYong Wu #define SMI_LARB_MMU_EN 0xf00 21e6dec923SYong Wu 22e6dec923SYong Wu /* mt2701 */ 233c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_BASE 0x5c0 243c8f4ad8SHonghui Zhang 253c8f4ad8SHonghui Zhang /* every register control 8 port, register offset 0x4 */ 263c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2) 273c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_ADDR(id) \ 283c8f4ad8SHonghui Zhang (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id)) 293c8f4ad8SHonghui Zhang 303c8f4ad8SHonghui Zhang /* 313c8f4ad8SHonghui Zhang * every port have 4 bit to control, bit[port + 3] control virtual or physical, 323c8f4ad8SHonghui Zhang * bit[port + 2 : port + 1] control the domain, bit[port] control the security 333c8f4ad8SHonghui Zhang * or non-security. 343c8f4ad8SHonghui Zhang */ 353c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2))) 363c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3) 373c8f4ad8SHonghui Zhang /* mt2701 domain should be set to 3 */ 383c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) 393c8f4ad8SHonghui Zhang 40e6dec923SYong Wu /* mt2712 */ 41e6dec923SYong Wu #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) 42e6dec923SYong Wu #define F_MMU_EN BIT(0) 43e6dec923SYong Wu 44567e58cfSYong Wu /* SMI COMMON */ 45567e58cfSYong Wu #define SMI_BUS_SEL 0x220 46567e58cfSYong Wu #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) 47567e58cfSYong Wu /* All are MMU0 defaultly. Only specialize mmu1 here. */ 48567e58cfSYong Wu #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) 49567e58cfSYong Wu 5042d42c76SYong Wu enum mtk_smi_gen { 5142d42c76SYong Wu MTK_SMI_GEN1, 5242d42c76SYong Wu MTK_SMI_GEN2 5342d42c76SYong Wu }; 5442d42c76SYong Wu 5542d42c76SYong Wu struct mtk_smi_common_plat { 5642d42c76SYong Wu enum mtk_smi_gen gen; 5764fea74aSYong Wu bool has_gals; 58567e58cfSYong Wu u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ 5942d42c76SYong Wu }; 6042d42c76SYong Wu 613c8f4ad8SHonghui Zhang struct mtk_smi_larb_gen { 623c8f4ad8SHonghui Zhang int port_in_larb[MTK_LARB_NR_MAX + 1]; 633aa5a6c2SKrzysztof Kozlowski void (*config_port)(struct device *dev); 642e9b0908SYong Wu unsigned int larb_direct_to_common_mask; 6564fea74aSYong Wu bool has_gals; 663c8f4ad8SHonghui Zhang }; 67cc8bbe1aSYong Wu 68cc8bbe1aSYong Wu struct mtk_smi { 69cc8bbe1aSYong Wu struct device *dev; 70cc8bbe1aSYong Wu struct clk *clk_apb, *clk_smi; 7164fea74aSYong Wu struct clk *clk_gals0, *clk_gals1; 723c8f4ad8SHonghui Zhang struct clk *clk_async; /*only needed by mt2701*/ 73567e58cfSYong Wu union { 74567e58cfSYong Wu void __iomem *smi_ao_base; /* only for gen1 */ 75567e58cfSYong Wu void __iomem *base; /* only for gen2 */ 76567e58cfSYong Wu }; 7742d42c76SYong Wu const struct mtk_smi_common_plat *plat; 78cc8bbe1aSYong Wu }; 79cc8bbe1aSYong Wu 80cc8bbe1aSYong Wu struct mtk_smi_larb { /* larb: local arbiter */ 81cc8bbe1aSYong Wu struct mtk_smi smi; 82cc8bbe1aSYong Wu void __iomem *base; 83cc8bbe1aSYong Wu struct device *smi_common_dev; 843c8f4ad8SHonghui Zhang const struct mtk_smi_larb_gen *larb_gen; 853c8f4ad8SHonghui Zhang int larbid; 86cc8bbe1aSYong Wu u32 *mmu; 87cc8bbe1aSYong Wu }; 88cc8bbe1aSYong Wu 894f0a1a1aSYong Wu static int mtk_smi_clk_enable(const struct mtk_smi *smi) 90cc8bbe1aSYong Wu { 91cc8bbe1aSYong Wu int ret; 92cc8bbe1aSYong Wu 93cc8bbe1aSYong Wu ret = clk_prepare_enable(smi->clk_apb); 94cc8bbe1aSYong Wu if (ret) 954f0a1a1aSYong Wu return ret; 96cc8bbe1aSYong Wu 97cc8bbe1aSYong Wu ret = clk_prepare_enable(smi->clk_smi); 98cc8bbe1aSYong Wu if (ret) 99cc8bbe1aSYong Wu goto err_disable_apb; 100cc8bbe1aSYong Wu 10164fea74aSYong Wu ret = clk_prepare_enable(smi->clk_gals0); 10264fea74aSYong Wu if (ret) 10364fea74aSYong Wu goto err_disable_smi; 10464fea74aSYong Wu 10564fea74aSYong Wu ret = clk_prepare_enable(smi->clk_gals1); 10664fea74aSYong Wu if (ret) 10764fea74aSYong Wu goto err_disable_gals0; 10864fea74aSYong Wu 109cc8bbe1aSYong Wu return 0; 110cc8bbe1aSYong Wu 11164fea74aSYong Wu err_disable_gals0: 11264fea74aSYong Wu clk_disable_unprepare(smi->clk_gals0); 11364fea74aSYong Wu err_disable_smi: 11464fea74aSYong Wu clk_disable_unprepare(smi->clk_smi); 115cc8bbe1aSYong Wu err_disable_apb: 116cc8bbe1aSYong Wu clk_disable_unprepare(smi->clk_apb); 117cc8bbe1aSYong Wu return ret; 118cc8bbe1aSYong Wu } 119cc8bbe1aSYong Wu 1204f0a1a1aSYong Wu static void mtk_smi_clk_disable(const struct mtk_smi *smi) 121cc8bbe1aSYong Wu { 12264fea74aSYong Wu clk_disable_unprepare(smi->clk_gals1); 12364fea74aSYong Wu clk_disable_unprepare(smi->clk_gals0); 124cc8bbe1aSYong Wu clk_disable_unprepare(smi->clk_smi); 125cc8bbe1aSYong Wu clk_disable_unprepare(smi->clk_apb); 126cc8bbe1aSYong Wu } 127cc8bbe1aSYong Wu 128cc8bbe1aSYong Wu int mtk_smi_larb_get(struct device *larbdev) 129cc8bbe1aSYong Wu { 1304f0a1a1aSYong Wu int ret = pm_runtime_get_sync(larbdev); 131cc8bbe1aSYong Wu 1324f0a1a1aSYong Wu return (ret < 0) ? ret : 0; 133cc8bbe1aSYong Wu } 134cb1b5dffSPhilipp Zabel EXPORT_SYMBOL_GPL(mtk_smi_larb_get); 135cc8bbe1aSYong Wu 136cc8bbe1aSYong Wu void mtk_smi_larb_put(struct device *larbdev) 137cc8bbe1aSYong Wu { 1384f0a1a1aSYong Wu pm_runtime_put_sync(larbdev); 139cc8bbe1aSYong Wu } 140cb1b5dffSPhilipp Zabel EXPORT_SYMBOL_GPL(mtk_smi_larb_put); 141cc8bbe1aSYong Wu 142cc8bbe1aSYong Wu static int 143cc8bbe1aSYong Wu mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) 144cc8bbe1aSYong Wu { 145cc8bbe1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 1461ee9feb2SYong Wu struct mtk_smi_larb_iommu *larb_mmu = data; 147cc8bbe1aSYong Wu unsigned int i; 148cc8bbe1aSYong Wu 149ec2da07cSYong Wu for (i = 0; i < MTK_LARB_NR_MAX; i++) { 1501ee9feb2SYong Wu if (dev == larb_mmu[i].dev) { 151ec2da07cSYong Wu larb->larbid = i; 1521ee9feb2SYong Wu larb->mmu = &larb_mmu[i].mmu; 153cc8bbe1aSYong Wu return 0; 154cc8bbe1aSYong Wu } 155cc8bbe1aSYong Wu } 156cc8bbe1aSYong Wu return -ENODEV; 157cc8bbe1aSYong Wu } 158cc8bbe1aSYong Wu 1592e9b0908SYong Wu static void mtk_smi_larb_config_port_gen2_general(struct device *dev) 160e6dec923SYong Wu { 161e6dec923SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 162e6dec923SYong Wu u32 reg; 163e6dec923SYong Wu int i; 164e6dec923SYong Wu 1652e9b0908SYong Wu if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) 166e6dec923SYong Wu return; 167e6dec923SYong Wu 168e6dec923SYong Wu for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { 169e6dec923SYong Wu reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); 170e6dec923SYong Wu reg |= F_MMU_EN; 171e6dec923SYong Wu writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); 172e6dec923SYong Wu } 173e6dec923SYong Wu } 174e6dec923SYong Wu 175e6dec923SYong Wu static void mtk_smi_larb_config_port_mt8173(struct device *dev) 1763c8f4ad8SHonghui Zhang { 1773c8f4ad8SHonghui Zhang struct mtk_smi_larb *larb = dev_get_drvdata(dev); 1783c8f4ad8SHonghui Zhang 1793c8f4ad8SHonghui Zhang writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN); 1803c8f4ad8SHonghui Zhang } 1813c8f4ad8SHonghui Zhang 1823c8f4ad8SHonghui Zhang static void mtk_smi_larb_config_port_gen1(struct device *dev) 1833c8f4ad8SHonghui Zhang { 1843c8f4ad8SHonghui Zhang struct mtk_smi_larb *larb = dev_get_drvdata(dev); 1853c8f4ad8SHonghui Zhang const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 1863c8f4ad8SHonghui Zhang struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); 1873c8f4ad8SHonghui Zhang int i, m4u_port_id, larb_port_num; 1883c8f4ad8SHonghui Zhang u32 sec_con_val, reg_val; 1893c8f4ad8SHonghui Zhang 1903c8f4ad8SHonghui Zhang m4u_port_id = larb_gen->port_in_larb[larb->larbid]; 1913c8f4ad8SHonghui Zhang larb_port_num = larb_gen->port_in_larb[larb->larbid + 1] 1923c8f4ad8SHonghui Zhang - larb_gen->port_in_larb[larb->larbid]; 1933c8f4ad8SHonghui Zhang 1943c8f4ad8SHonghui Zhang for (i = 0; i < larb_port_num; i++, m4u_port_id++) { 1953c8f4ad8SHonghui Zhang if (*larb->mmu & BIT(i)) { 1963c8f4ad8SHonghui Zhang /* bit[port + 3] controls the virtual or physical */ 1973c8f4ad8SHonghui Zhang sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id); 1983c8f4ad8SHonghui Zhang } else { 1993c8f4ad8SHonghui Zhang /* do not need to enable m4u for this port */ 2003c8f4ad8SHonghui Zhang continue; 2013c8f4ad8SHonghui Zhang } 2023c8f4ad8SHonghui Zhang reg_val = readl(common->smi_ao_base 2033c8f4ad8SHonghui Zhang + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 2043c8f4ad8SHonghui Zhang reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); 2053c8f4ad8SHonghui Zhang reg_val |= sec_con_val; 2063c8f4ad8SHonghui Zhang reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); 2073c8f4ad8SHonghui Zhang writel(reg_val, 2083c8f4ad8SHonghui Zhang common->smi_ao_base 2093c8f4ad8SHonghui Zhang + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 2103c8f4ad8SHonghui Zhang } 2113c8f4ad8SHonghui Zhang } 2123c8f4ad8SHonghui Zhang 213cc8bbe1aSYong Wu static void 214cc8bbe1aSYong Wu mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) 215cc8bbe1aSYong Wu { 216cc8bbe1aSYong Wu /* Do nothing as the iommu is always enabled. */ 217cc8bbe1aSYong Wu } 218cc8bbe1aSYong Wu 219cc8bbe1aSYong Wu static const struct component_ops mtk_smi_larb_component_ops = { 220cc8bbe1aSYong Wu .bind = mtk_smi_larb_bind, 221cc8bbe1aSYong Wu .unbind = mtk_smi_larb_unbind, 222cc8bbe1aSYong Wu }; 223cc8bbe1aSYong Wu 2243c8f4ad8SHonghui Zhang static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { 2253c8f4ad8SHonghui Zhang /* mt8173 do not need the port in larb */ 226e6dec923SYong Wu .config_port = mtk_smi_larb_config_port_mt8173, 2273c8f4ad8SHonghui Zhang }; 2283c8f4ad8SHonghui Zhang 2293c8f4ad8SHonghui Zhang static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { 2303c8f4ad8SHonghui Zhang .port_in_larb = { 2313c8f4ad8SHonghui Zhang LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 2323c8f4ad8SHonghui Zhang LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 2333c8f4ad8SHonghui Zhang }, 2343c8f4ad8SHonghui Zhang .config_port = mtk_smi_larb_config_port_gen1, 2353c8f4ad8SHonghui Zhang }; 2363c8f4ad8SHonghui Zhang 237e6dec923SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { 2382e9b0908SYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 2392e9b0908SYong Wu .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ 240e6dec923SYong Wu }; 241e6dec923SYong Wu 242907ba6a1SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { 243907ba6a1SYong Wu .has_gals = true, 244907ba6a1SYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 245907ba6a1SYong Wu .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), 246907ba6a1SYong Wu /* IPU0 | IPU1 | CCU */ 247907ba6a1SYong Wu }; 248907ba6a1SYong Wu 2493c8f4ad8SHonghui Zhang static const struct of_device_id mtk_smi_larb_of_ids[] = { 2503c8f4ad8SHonghui Zhang { 2513c8f4ad8SHonghui Zhang .compatible = "mediatek,mt8173-smi-larb", 2523c8f4ad8SHonghui Zhang .data = &mtk_smi_larb_mt8173 2533c8f4ad8SHonghui Zhang }, 2543c8f4ad8SHonghui Zhang { 2553c8f4ad8SHonghui Zhang .compatible = "mediatek,mt2701-smi-larb", 2563c8f4ad8SHonghui Zhang .data = &mtk_smi_larb_mt2701 2573c8f4ad8SHonghui Zhang }, 258e6dec923SYong Wu { 259e6dec923SYong Wu .compatible = "mediatek,mt2712-smi-larb", 260e6dec923SYong Wu .data = &mtk_smi_larb_mt2712 261e6dec923SYong Wu }, 262907ba6a1SYong Wu { 263907ba6a1SYong Wu .compatible = "mediatek,mt8183-smi-larb", 264907ba6a1SYong Wu .data = &mtk_smi_larb_mt8183 265907ba6a1SYong Wu }, 2663c8f4ad8SHonghui Zhang {} 2673c8f4ad8SHonghui Zhang }; 2683c8f4ad8SHonghui Zhang 269cc8bbe1aSYong Wu static int mtk_smi_larb_probe(struct platform_device *pdev) 270cc8bbe1aSYong Wu { 271cc8bbe1aSYong Wu struct mtk_smi_larb *larb; 272cc8bbe1aSYong Wu struct resource *res; 273cc8bbe1aSYong Wu struct device *dev = &pdev->dev; 274cc8bbe1aSYong Wu struct device_node *smi_node; 275cc8bbe1aSYong Wu struct platform_device *smi_pdev; 276cc8bbe1aSYong Wu 277cc8bbe1aSYong Wu larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); 278cc8bbe1aSYong Wu if (!larb) 279cc8bbe1aSYong Wu return -ENOMEM; 280cc8bbe1aSYong Wu 28175487860SHonghui Zhang larb->larb_gen = of_device_get_match_data(dev); 282cc8bbe1aSYong Wu res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 283cc8bbe1aSYong Wu larb->base = devm_ioremap_resource(dev, res); 284cc8bbe1aSYong Wu if (IS_ERR(larb->base)) 285cc8bbe1aSYong Wu return PTR_ERR(larb->base); 286cc8bbe1aSYong Wu 287cc8bbe1aSYong Wu larb->smi.clk_apb = devm_clk_get(dev, "apb"); 288cc8bbe1aSYong Wu if (IS_ERR(larb->smi.clk_apb)) 289cc8bbe1aSYong Wu return PTR_ERR(larb->smi.clk_apb); 290cc8bbe1aSYong Wu 291cc8bbe1aSYong Wu larb->smi.clk_smi = devm_clk_get(dev, "smi"); 292cc8bbe1aSYong Wu if (IS_ERR(larb->smi.clk_smi)) 293cc8bbe1aSYong Wu return PTR_ERR(larb->smi.clk_smi); 29464fea74aSYong Wu 29564fea74aSYong Wu if (larb->larb_gen->has_gals) { 29664fea74aSYong Wu /* The larbs may still haven't gals even if the SoC support.*/ 29764fea74aSYong Wu larb->smi.clk_gals0 = devm_clk_get(dev, "gals"); 29864fea74aSYong Wu if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT) 29964fea74aSYong Wu larb->smi.clk_gals0 = NULL; 30064fea74aSYong Wu else if (IS_ERR(larb->smi.clk_gals0)) 30164fea74aSYong Wu return PTR_ERR(larb->smi.clk_gals0); 30264fea74aSYong Wu } 303cc8bbe1aSYong Wu larb->smi.dev = dev; 304cc8bbe1aSYong Wu 305cc8bbe1aSYong Wu smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); 306cc8bbe1aSYong Wu if (!smi_node) 307cc8bbe1aSYong Wu return -EINVAL; 308cc8bbe1aSYong Wu 309cc8bbe1aSYong Wu smi_pdev = of_find_device_by_node(smi_node); 310cc8bbe1aSYong Wu of_node_put(smi_node); 311cc8bbe1aSYong Wu if (smi_pdev) { 3124f608d38SYong Wu if (!platform_get_drvdata(smi_pdev)) 3134f608d38SYong Wu return -EPROBE_DEFER; 314cc8bbe1aSYong Wu larb->smi_common_dev = &smi_pdev->dev; 315cc8bbe1aSYong Wu } else { 316cc8bbe1aSYong Wu dev_err(dev, "Failed to get the smi_common device\n"); 317cc8bbe1aSYong Wu return -EINVAL; 318cc8bbe1aSYong Wu } 319cc8bbe1aSYong Wu 320cc8bbe1aSYong Wu pm_runtime_enable(dev); 321cc8bbe1aSYong Wu platform_set_drvdata(pdev, larb); 322cc8bbe1aSYong Wu return component_add(dev, &mtk_smi_larb_component_ops); 323cc8bbe1aSYong Wu } 324cc8bbe1aSYong Wu 325cc8bbe1aSYong Wu static int mtk_smi_larb_remove(struct platform_device *pdev) 326cc8bbe1aSYong Wu { 327cc8bbe1aSYong Wu pm_runtime_disable(&pdev->dev); 328cc8bbe1aSYong Wu component_del(&pdev->dev, &mtk_smi_larb_component_ops); 329cc8bbe1aSYong Wu return 0; 330cc8bbe1aSYong Wu } 331cc8bbe1aSYong Wu 3324f0a1a1aSYong Wu static int __maybe_unused mtk_smi_larb_resume(struct device *dev) 3334f0a1a1aSYong Wu { 3344f0a1a1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 3354f0a1a1aSYong Wu const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 3364f0a1a1aSYong Wu int ret; 3374f0a1a1aSYong Wu 3384f0a1a1aSYong Wu /* Power on smi-common. */ 3394f0a1a1aSYong Wu ret = pm_runtime_get_sync(larb->smi_common_dev); 3404f0a1a1aSYong Wu if (ret < 0) { 3414f0a1a1aSYong Wu dev_err(dev, "Failed to pm get for smi-common(%d).\n", ret); 3424f0a1a1aSYong Wu return ret; 3434f0a1a1aSYong Wu } 3444f0a1a1aSYong Wu 3454f0a1a1aSYong Wu ret = mtk_smi_clk_enable(&larb->smi); 3464f0a1a1aSYong Wu if (ret < 0) { 3474f0a1a1aSYong Wu dev_err(dev, "Failed to enable clock(%d).\n", ret); 3484f0a1a1aSYong Wu pm_runtime_put_sync(larb->smi_common_dev); 3494f0a1a1aSYong Wu return ret; 3504f0a1a1aSYong Wu } 3514f0a1a1aSYong Wu 3524f0a1a1aSYong Wu /* Configure the basic setting for this larb */ 3534f0a1a1aSYong Wu larb_gen->config_port(dev); 3544f0a1a1aSYong Wu 3554f0a1a1aSYong Wu return 0; 3564f0a1a1aSYong Wu } 3574f0a1a1aSYong Wu 3584f0a1a1aSYong Wu static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) 3594f0a1a1aSYong Wu { 3604f0a1a1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 3614f0a1a1aSYong Wu 3624f0a1a1aSYong Wu mtk_smi_clk_disable(&larb->smi); 3634f0a1a1aSYong Wu pm_runtime_put_sync(larb->smi_common_dev); 3644f0a1a1aSYong Wu return 0; 3654f0a1a1aSYong Wu } 3664f0a1a1aSYong Wu 3674f0a1a1aSYong Wu static const struct dev_pm_ops smi_larb_pm_ops = { 3684f0a1a1aSYong Wu SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL) 369fb03082aSYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 370fb03082aSYong Wu pm_runtime_force_resume) 3714f0a1a1aSYong Wu }; 3724f0a1a1aSYong Wu 373cc8bbe1aSYong Wu static struct platform_driver mtk_smi_larb_driver = { 374cc8bbe1aSYong Wu .probe = mtk_smi_larb_probe, 375cc8bbe1aSYong Wu .remove = mtk_smi_larb_remove, 376cc8bbe1aSYong Wu .driver = { 377cc8bbe1aSYong Wu .name = "mtk-smi-larb", 378cc8bbe1aSYong Wu .of_match_table = mtk_smi_larb_of_ids, 3794f0a1a1aSYong Wu .pm = &smi_larb_pm_ops, 380cc8bbe1aSYong Wu } 381cc8bbe1aSYong Wu }; 382cc8bbe1aSYong Wu 38342d42c76SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_gen1 = { 38442d42c76SYong Wu .gen = MTK_SMI_GEN1, 38542d42c76SYong Wu }; 38642d42c76SYong Wu 38742d42c76SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { 38842d42c76SYong Wu .gen = MTK_SMI_GEN2, 38942d42c76SYong Wu }; 39042d42c76SYong Wu 391907ba6a1SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { 392907ba6a1SYong Wu .gen = MTK_SMI_GEN2, 393907ba6a1SYong Wu .has_gals = true, 394567e58cfSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 395567e58cfSYong Wu F_MMU1_LARB(7), 396907ba6a1SYong Wu }; 397907ba6a1SYong Wu 3983c8f4ad8SHonghui Zhang static const struct of_device_id mtk_smi_common_of_ids[] = { 3993c8f4ad8SHonghui Zhang { 4003c8f4ad8SHonghui Zhang .compatible = "mediatek,mt8173-smi-common", 40142d42c76SYong Wu .data = &mtk_smi_common_gen2, 4023c8f4ad8SHonghui Zhang }, 4033c8f4ad8SHonghui Zhang { 4043c8f4ad8SHonghui Zhang .compatible = "mediatek,mt2701-smi-common", 40542d42c76SYong Wu .data = &mtk_smi_common_gen1, 4063c8f4ad8SHonghui Zhang }, 407e6dec923SYong Wu { 408e6dec923SYong Wu .compatible = "mediatek,mt2712-smi-common", 40942d42c76SYong Wu .data = &mtk_smi_common_gen2, 410e6dec923SYong Wu }, 411907ba6a1SYong Wu { 412907ba6a1SYong Wu .compatible = "mediatek,mt8183-smi-common", 413907ba6a1SYong Wu .data = &mtk_smi_common_mt8183, 414907ba6a1SYong Wu }, 4153c8f4ad8SHonghui Zhang {} 4163c8f4ad8SHonghui Zhang }; 4173c8f4ad8SHonghui Zhang 418cc8bbe1aSYong Wu static int mtk_smi_common_probe(struct platform_device *pdev) 419cc8bbe1aSYong Wu { 420cc8bbe1aSYong Wu struct device *dev = &pdev->dev; 421cc8bbe1aSYong Wu struct mtk_smi *common; 4223c8f4ad8SHonghui Zhang struct resource *res; 42346cc815dSArvind Yadav int ret; 424cc8bbe1aSYong Wu 425cc8bbe1aSYong Wu common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); 426cc8bbe1aSYong Wu if (!common) 427cc8bbe1aSYong Wu return -ENOMEM; 428cc8bbe1aSYong Wu common->dev = dev; 42942d42c76SYong Wu common->plat = of_device_get_match_data(dev); 430cc8bbe1aSYong Wu 431cc8bbe1aSYong Wu common->clk_apb = devm_clk_get(dev, "apb"); 432cc8bbe1aSYong Wu if (IS_ERR(common->clk_apb)) 433cc8bbe1aSYong Wu return PTR_ERR(common->clk_apb); 434cc8bbe1aSYong Wu 435cc8bbe1aSYong Wu common->clk_smi = devm_clk_get(dev, "smi"); 436cc8bbe1aSYong Wu if (IS_ERR(common->clk_smi)) 437cc8bbe1aSYong Wu return PTR_ERR(common->clk_smi); 438cc8bbe1aSYong Wu 43964fea74aSYong Wu if (common->plat->has_gals) { 44064fea74aSYong Wu common->clk_gals0 = devm_clk_get(dev, "gals0"); 44164fea74aSYong Wu if (IS_ERR(common->clk_gals0)) 44264fea74aSYong Wu return PTR_ERR(common->clk_gals0); 44364fea74aSYong Wu 44464fea74aSYong Wu common->clk_gals1 = devm_clk_get(dev, "gals1"); 44564fea74aSYong Wu if (IS_ERR(common->clk_gals1)) 44664fea74aSYong Wu return PTR_ERR(common->clk_gals1); 44764fea74aSYong Wu } 44864fea74aSYong Wu 4493c8f4ad8SHonghui Zhang /* 4503c8f4ad8SHonghui Zhang * for mtk smi gen 1, we need to get the ao(always on) base to config 4513c8f4ad8SHonghui Zhang * m4u port, and we need to enable the aync clock for transform the smi 4523c8f4ad8SHonghui Zhang * clock into emi clock domain, but for mtk smi gen2, there's no smi ao 4533c8f4ad8SHonghui Zhang * base. 4543c8f4ad8SHonghui Zhang */ 45542d42c76SYong Wu if (common->plat->gen == MTK_SMI_GEN1) { 4563c8f4ad8SHonghui Zhang res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4573c8f4ad8SHonghui Zhang common->smi_ao_base = devm_ioremap_resource(dev, res); 4583c8f4ad8SHonghui Zhang if (IS_ERR(common->smi_ao_base)) 4593c8f4ad8SHonghui Zhang return PTR_ERR(common->smi_ao_base); 4603c8f4ad8SHonghui Zhang 4613c8f4ad8SHonghui Zhang common->clk_async = devm_clk_get(dev, "async"); 4623c8f4ad8SHonghui Zhang if (IS_ERR(common->clk_async)) 4633c8f4ad8SHonghui Zhang return PTR_ERR(common->clk_async); 4643c8f4ad8SHonghui Zhang 46546cc815dSArvind Yadav ret = clk_prepare_enable(common->clk_async); 46646cc815dSArvind Yadav if (ret) 46746cc815dSArvind Yadav return ret; 468567e58cfSYong Wu } else { 469567e58cfSYong Wu res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 470567e58cfSYong Wu common->base = devm_ioremap_resource(dev, res); 471567e58cfSYong Wu if (IS_ERR(common->base)) 472567e58cfSYong Wu return PTR_ERR(common->base); 4733c8f4ad8SHonghui Zhang } 474cc8bbe1aSYong Wu pm_runtime_enable(dev); 475cc8bbe1aSYong Wu platform_set_drvdata(pdev, common); 476cc8bbe1aSYong Wu return 0; 477cc8bbe1aSYong Wu } 478cc8bbe1aSYong Wu 479cc8bbe1aSYong Wu static int mtk_smi_common_remove(struct platform_device *pdev) 480cc8bbe1aSYong Wu { 481cc8bbe1aSYong Wu pm_runtime_disable(&pdev->dev); 482cc8bbe1aSYong Wu return 0; 483cc8bbe1aSYong Wu } 484cc8bbe1aSYong Wu 4854f0a1a1aSYong Wu static int __maybe_unused mtk_smi_common_resume(struct device *dev) 4864f0a1a1aSYong Wu { 4874f0a1a1aSYong Wu struct mtk_smi *common = dev_get_drvdata(dev); 488567e58cfSYong Wu u32 bus_sel = common->plat->bus_sel; 4894f0a1a1aSYong Wu int ret; 4904f0a1a1aSYong Wu 4914f0a1a1aSYong Wu ret = mtk_smi_clk_enable(common); 4924f0a1a1aSYong Wu if (ret) { 4934f0a1a1aSYong Wu dev_err(common->dev, "Failed to enable clock(%d).\n", ret); 4944f0a1a1aSYong Wu return ret; 4954f0a1a1aSYong Wu } 496567e58cfSYong Wu 497567e58cfSYong Wu if (common->plat->gen == MTK_SMI_GEN2 && bus_sel) 498567e58cfSYong Wu writel(bus_sel, common->base + SMI_BUS_SEL); 4994f0a1a1aSYong Wu return 0; 5004f0a1a1aSYong Wu } 5014f0a1a1aSYong Wu 5024f0a1a1aSYong Wu static int __maybe_unused mtk_smi_common_suspend(struct device *dev) 5034f0a1a1aSYong Wu { 5044f0a1a1aSYong Wu struct mtk_smi *common = dev_get_drvdata(dev); 5054f0a1a1aSYong Wu 5064f0a1a1aSYong Wu mtk_smi_clk_disable(common); 5074f0a1a1aSYong Wu return 0; 5084f0a1a1aSYong Wu } 5094f0a1a1aSYong Wu 5104f0a1a1aSYong Wu static const struct dev_pm_ops smi_common_pm_ops = { 5114f0a1a1aSYong Wu SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL) 512fb03082aSYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 513fb03082aSYong Wu pm_runtime_force_resume) 5144f0a1a1aSYong Wu }; 5154f0a1a1aSYong Wu 516cc8bbe1aSYong Wu static struct platform_driver mtk_smi_common_driver = { 517cc8bbe1aSYong Wu .probe = mtk_smi_common_probe, 518cc8bbe1aSYong Wu .remove = mtk_smi_common_remove, 519cc8bbe1aSYong Wu .driver = { 520cc8bbe1aSYong Wu .name = "mtk-smi-common", 521cc8bbe1aSYong Wu .of_match_table = mtk_smi_common_of_ids, 5224f0a1a1aSYong Wu .pm = &smi_common_pm_ops, 523cc8bbe1aSYong Wu } 524cc8bbe1aSYong Wu }; 525cc8bbe1aSYong Wu 526cc8bbe1aSYong Wu static int __init mtk_smi_init(void) 527cc8bbe1aSYong Wu { 528cc8bbe1aSYong Wu int ret; 529cc8bbe1aSYong Wu 530cc8bbe1aSYong Wu ret = platform_driver_register(&mtk_smi_common_driver); 531cc8bbe1aSYong Wu if (ret != 0) { 532cc8bbe1aSYong Wu pr_err("Failed to register SMI driver\n"); 533cc8bbe1aSYong Wu return ret; 534cc8bbe1aSYong Wu } 535cc8bbe1aSYong Wu 536cc8bbe1aSYong Wu ret = platform_driver_register(&mtk_smi_larb_driver); 537cc8bbe1aSYong Wu if (ret != 0) { 538cc8bbe1aSYong Wu pr_err("Failed to register SMI-LARB driver\n"); 539cc8bbe1aSYong Wu goto err_unreg_smi; 540cc8bbe1aSYong Wu } 541cc8bbe1aSYong Wu return ret; 542cc8bbe1aSYong Wu 543cc8bbe1aSYong Wu err_unreg_smi: 544cc8bbe1aSYong Wu platform_driver_unregister(&mtk_smi_common_driver); 545cc8bbe1aSYong Wu return ret; 546cc8bbe1aSYong Wu } 5473c8f4ad8SHonghui Zhang 5484f608d38SYong Wu module_init(mtk_smi_init); 549