11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2cc8bbe1aSYong Wu /* 3cc8bbe1aSYong Wu * Copyright (c) 2015-2016 MediaTek Inc. 4cc8bbe1aSYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 5cc8bbe1aSYong Wu */ 6cc8bbe1aSYong Wu #include <linux/clk.h> 7cc8bbe1aSYong Wu #include <linux/component.h> 8cc8bbe1aSYong Wu #include <linux/device.h> 9cc8bbe1aSYong Wu #include <linux/err.h> 10cc8bbe1aSYong Wu #include <linux/io.h> 114f608d38SYong Wu #include <linux/module.h> 12cc8bbe1aSYong Wu #include <linux/of.h> 13cc8bbe1aSYong Wu #include <linux/of_platform.h> 14cc8bbe1aSYong Wu #include <linux/platform_device.h> 15cc8bbe1aSYong Wu #include <linux/pm_runtime.h> 16cc8bbe1aSYong Wu #include <soc/mediatek/smi.h> 173c8f4ad8SHonghui Zhang #include <dt-bindings/memory/mt2701-larb-port.h> 1866a28915SYong Wu #include <dt-bindings/memory/mtk-memory-port.h> 19cc8bbe1aSYong Wu 20534e0ad2SYong Wu /* SMI COMMON */ 21534e0ad2SYong Wu #define SMI_BUS_SEL 0x220 22534e0ad2SYong Wu #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) 23534e0ad2SYong Wu /* All are MMU0 defaultly. Only specialize mmu1 here. */ 24534e0ad2SYong Wu #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) 25e6dec923SYong Wu 26534e0ad2SYong Wu /* SMI LARB */ 27a8529f3bSFabien Parent 28534e0ad2SYong Wu /* Below are about mmu enable registers, they are different in SoCs */ 29534e0ad2SYong Wu /* gen1: mt2701 */ 303c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_BASE 0x5c0 313c8f4ad8SHonghui Zhang 323c8f4ad8SHonghui Zhang /* every register control 8 port, register offset 0x4 */ 333c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2) 343c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_ADDR(id) \ 353c8f4ad8SHonghui Zhang (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id)) 363c8f4ad8SHonghui Zhang 373c8f4ad8SHonghui Zhang /* 383c8f4ad8SHonghui Zhang * every port have 4 bit to control, bit[port + 3] control virtual or physical, 393c8f4ad8SHonghui Zhang * bit[port + 2 : port + 1] control the domain, bit[port] control the security 403c8f4ad8SHonghui Zhang * or non-security. 413c8f4ad8SHonghui Zhang */ 423c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2))) 433c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3) 443c8f4ad8SHonghui Zhang /* mt2701 domain should be set to 3 */ 453c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) 463c8f4ad8SHonghui Zhang 47534e0ad2SYong Wu /* gen2: */ 48534e0ad2SYong Wu /* mt8167 */ 49534e0ad2SYong Wu #define MT8167_SMI_LARB_MMU_EN 0xfc0 50534e0ad2SYong Wu 51534e0ad2SYong Wu /* mt8173 */ 52534e0ad2SYong Wu #define MT8173_SMI_LARB_MMU_EN 0xf00 53534e0ad2SYong Wu 54534e0ad2SYong Wu /* general */ 55e6dec923SYong Wu #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) 56e6dec923SYong Wu #define F_MMU_EN BIT(0) 578d2c749eSYong Wu #define BANK_SEL(id) ({ \ 588d2c749eSYong Wu u32 _id = (id) & 0x3; \ 598d2c749eSYong Wu (_id << 8 | _id << 10 | _id << 12 | _id << 14); \ 608d2c749eSYong Wu }) 61e6dec923SYong Wu 62a5c18986SYong Wu enum mtk_smi_type { 6342d42c76SYong Wu MTK_SMI_GEN1, 6442d42c76SYong Wu MTK_SMI_GEN2 6542d42c76SYong Wu }; 6642d42c76SYong Wu 670e14917cSYong Wu #define MTK_SMI_CLK_NR_MAX 4 680e14917cSYong Wu 690e14917cSYong Wu /* larbs: Require apb/smi clocks while gals is optional. */ 700e14917cSYong Wu static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"}; 710e14917cSYong Wu #define MTK_SMI_LARB_REQ_CLK_NR 2 720e14917cSYong Wu #define MTK_SMI_LARB_OPT_CLK_NR 1 730e14917cSYong Wu 740e14917cSYong Wu /* 750e14917cSYong Wu * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required. 760e14917cSYong Wu */ 770e14917cSYong Wu static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"}; 780e14917cSYong Wu #define MTK_SMI_COM_REQ_CLK_NR 2 790e14917cSYong Wu #define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX 800e14917cSYong Wu 8142d42c76SYong Wu struct mtk_smi_common_plat { 82a5c18986SYong Wu enum mtk_smi_type type; 8364fea74aSYong Wu bool has_gals; 84567e58cfSYong Wu u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ 8542d42c76SYong Wu }; 8642d42c76SYong Wu 873c8f4ad8SHonghui Zhang struct mtk_smi_larb_gen { 883c8f4ad8SHonghui Zhang int port_in_larb[MTK_LARB_NR_MAX + 1]; 893aa5a6c2SKrzysztof Kozlowski void (*config_port)(struct device *dev); 902e9b0908SYong Wu unsigned int larb_direct_to_common_mask; 913c8f4ad8SHonghui Zhang }; 92cc8bbe1aSYong Wu 93cc8bbe1aSYong Wu struct mtk_smi { 94cc8bbe1aSYong Wu struct device *dev; 950e14917cSYong Wu unsigned int clk_num; 960e14917cSYong Wu struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX]; 973c8f4ad8SHonghui Zhang struct clk *clk_async; /*only needed by mt2701*/ 98567e58cfSYong Wu union { 99567e58cfSYong Wu void __iomem *smi_ao_base; /* only for gen1 */ 100567e58cfSYong Wu void __iomem *base; /* only for gen2 */ 101567e58cfSYong Wu }; 10242d42c76SYong Wu const struct mtk_smi_common_plat *plat; 103cc8bbe1aSYong Wu }; 104cc8bbe1aSYong Wu 105cc8bbe1aSYong Wu struct mtk_smi_larb { /* larb: local arbiter */ 106cc8bbe1aSYong Wu struct mtk_smi smi; 107cc8bbe1aSYong Wu void __iomem *base; 108cc8bbe1aSYong Wu struct device *smi_common_dev; 1093c8f4ad8SHonghui Zhang const struct mtk_smi_larb_gen *larb_gen; 1103c8f4ad8SHonghui Zhang int larbid; 111cc8bbe1aSYong Wu u32 *mmu; 1128d2c749eSYong Wu unsigned char *bank; 113cc8bbe1aSYong Wu }; 114cc8bbe1aSYong Wu 115cc8bbe1aSYong Wu int mtk_smi_larb_get(struct device *larbdev) 116cc8bbe1aSYong Wu { 117a2d522ffSZhang Qilong int ret = pm_runtime_resume_and_get(larbdev); 118cc8bbe1aSYong Wu 1194f0a1a1aSYong Wu return (ret < 0) ? ret : 0; 120cc8bbe1aSYong Wu } 121cb1b5dffSPhilipp Zabel EXPORT_SYMBOL_GPL(mtk_smi_larb_get); 122cc8bbe1aSYong Wu 123cc8bbe1aSYong Wu void mtk_smi_larb_put(struct device *larbdev) 124cc8bbe1aSYong Wu { 1254f0a1a1aSYong Wu pm_runtime_put_sync(larbdev); 126cc8bbe1aSYong Wu } 127cb1b5dffSPhilipp Zabel EXPORT_SYMBOL_GPL(mtk_smi_larb_put); 128cc8bbe1aSYong Wu 129cc8bbe1aSYong Wu static int 130cc8bbe1aSYong Wu mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) 131cc8bbe1aSYong Wu { 132cc8bbe1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 1331ee9feb2SYong Wu struct mtk_smi_larb_iommu *larb_mmu = data; 134cc8bbe1aSYong Wu unsigned int i; 135cc8bbe1aSYong Wu 136ec2da07cSYong Wu for (i = 0; i < MTK_LARB_NR_MAX; i++) { 1371ee9feb2SYong Wu if (dev == larb_mmu[i].dev) { 138ec2da07cSYong Wu larb->larbid = i; 1391ee9feb2SYong Wu larb->mmu = &larb_mmu[i].mmu; 1408d2c749eSYong Wu larb->bank = larb_mmu[i].bank; 141cc8bbe1aSYong Wu return 0; 142cc8bbe1aSYong Wu } 143cc8bbe1aSYong Wu } 144cc8bbe1aSYong Wu return -ENODEV; 145cc8bbe1aSYong Wu } 146cc8bbe1aSYong Wu 147534e0ad2SYong Wu static void 148534e0ad2SYong Wu mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) 149e6dec923SYong Wu { 150534e0ad2SYong Wu /* Do nothing as the iommu is always enabled. */ 151e6dec923SYong Wu } 152e6dec923SYong Wu 153534e0ad2SYong Wu static const struct component_ops mtk_smi_larb_component_ops = { 154534e0ad2SYong Wu .bind = mtk_smi_larb_bind, 155534e0ad2SYong Wu .unbind = mtk_smi_larb_unbind, 156534e0ad2SYong Wu }; 157a8529f3bSFabien Parent 1583c8f4ad8SHonghui Zhang static void mtk_smi_larb_config_port_gen1(struct device *dev) 1593c8f4ad8SHonghui Zhang { 1603c8f4ad8SHonghui Zhang struct mtk_smi_larb *larb = dev_get_drvdata(dev); 1613c8f4ad8SHonghui Zhang const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 1623c8f4ad8SHonghui Zhang struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); 1633c8f4ad8SHonghui Zhang int i, m4u_port_id, larb_port_num; 1643c8f4ad8SHonghui Zhang u32 sec_con_val, reg_val; 1653c8f4ad8SHonghui Zhang 1663c8f4ad8SHonghui Zhang m4u_port_id = larb_gen->port_in_larb[larb->larbid]; 1673c8f4ad8SHonghui Zhang larb_port_num = larb_gen->port_in_larb[larb->larbid + 1] 1683c8f4ad8SHonghui Zhang - larb_gen->port_in_larb[larb->larbid]; 1693c8f4ad8SHonghui Zhang 1703c8f4ad8SHonghui Zhang for (i = 0; i < larb_port_num; i++, m4u_port_id++) { 1713c8f4ad8SHonghui Zhang if (*larb->mmu & BIT(i)) { 1723c8f4ad8SHonghui Zhang /* bit[port + 3] controls the virtual or physical */ 1733c8f4ad8SHonghui Zhang sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id); 1743c8f4ad8SHonghui Zhang } else { 1753c8f4ad8SHonghui Zhang /* do not need to enable m4u for this port */ 1763c8f4ad8SHonghui Zhang continue; 1773c8f4ad8SHonghui Zhang } 1783c8f4ad8SHonghui Zhang reg_val = readl(common->smi_ao_base 1793c8f4ad8SHonghui Zhang + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 1803c8f4ad8SHonghui Zhang reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); 1813c8f4ad8SHonghui Zhang reg_val |= sec_con_val; 1823c8f4ad8SHonghui Zhang reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); 1833c8f4ad8SHonghui Zhang writel(reg_val, 1843c8f4ad8SHonghui Zhang common->smi_ao_base 1853c8f4ad8SHonghui Zhang + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 1863c8f4ad8SHonghui Zhang } 1873c8f4ad8SHonghui Zhang } 1883c8f4ad8SHonghui Zhang 189534e0ad2SYong Wu static void mtk_smi_larb_config_port_mt8167(struct device *dev) 190cc8bbe1aSYong Wu { 191534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 192534e0ad2SYong Wu 193534e0ad2SYong Wu writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); 194cc8bbe1aSYong Wu } 195cc8bbe1aSYong Wu 196534e0ad2SYong Wu static void mtk_smi_larb_config_port_mt8173(struct device *dev) 197534e0ad2SYong Wu { 198534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 199cc8bbe1aSYong Wu 200534e0ad2SYong Wu writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN); 201534e0ad2SYong Wu } 2023c8f4ad8SHonghui Zhang 203534e0ad2SYong Wu static void mtk_smi_larb_config_port_gen2_general(struct device *dev) 204534e0ad2SYong Wu { 205534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 206534e0ad2SYong Wu u32 reg; 207534e0ad2SYong Wu int i; 208534e0ad2SYong Wu 209534e0ad2SYong Wu if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) 210534e0ad2SYong Wu return; 211534e0ad2SYong Wu 212534e0ad2SYong Wu for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { 213534e0ad2SYong Wu reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); 214534e0ad2SYong Wu reg |= F_MMU_EN; 215534e0ad2SYong Wu reg |= BANK_SEL(larb->bank[i]); 216534e0ad2SYong Wu writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); 217534e0ad2SYong Wu } 218534e0ad2SYong Wu } 219a8529f3bSFabien Parent 2203c8f4ad8SHonghui Zhang static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { 2213c8f4ad8SHonghui Zhang .port_in_larb = { 2223c8f4ad8SHonghui Zhang LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 2233c8f4ad8SHonghui Zhang LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 2243c8f4ad8SHonghui Zhang }, 2253c8f4ad8SHonghui Zhang .config_port = mtk_smi_larb_config_port_gen1, 2263c8f4ad8SHonghui Zhang }; 2273c8f4ad8SHonghui Zhang 228e6dec923SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { 2292e9b0908SYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 2302e9b0908SYong Wu .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ 231e6dec923SYong Wu }; 232e6dec923SYong Wu 233fc492f33SMing-Fan Chen static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { 234fc492f33SMing-Fan Chen .config_port = mtk_smi_larb_config_port_gen2_general, 235fc492f33SMing-Fan Chen .larb_direct_to_common_mask = 236fc492f33SMing-Fan Chen BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), 237fc492f33SMing-Fan Chen /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ 238fc492f33SMing-Fan Chen }; 239fc492f33SMing-Fan Chen 240534e0ad2SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = { 241534e0ad2SYong Wu /* mt8167 do not need the port in larb */ 242534e0ad2SYong Wu .config_port = mtk_smi_larb_config_port_mt8167, 243534e0ad2SYong Wu }; 244534e0ad2SYong Wu 245534e0ad2SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { 246534e0ad2SYong Wu /* mt8173 do not need the port in larb */ 247534e0ad2SYong Wu .config_port = mtk_smi_larb_config_port_mt8173, 248534e0ad2SYong Wu }; 249534e0ad2SYong Wu 250907ba6a1SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { 251907ba6a1SYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 252907ba6a1SYong Wu .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), 253907ba6a1SYong Wu /* IPU0 | IPU1 | CCU */ 254907ba6a1SYong Wu }; 255907ba6a1SYong Wu 25602c02ddcSYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { 25702c02ddcSYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 25802c02ddcSYong Wu }; 25902c02ddcSYong Wu 2603c8f4ad8SHonghui Zhang static const struct of_device_id mtk_smi_larb_of_ids[] = { 261534e0ad2SYong Wu {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701}, 262534e0ad2SYong Wu {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712}, 263534e0ad2SYong Wu {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779}, 264534e0ad2SYong Wu {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167}, 265534e0ad2SYong Wu {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173}, 266534e0ad2SYong Wu {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, 267534e0ad2SYong Wu {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, 2683c8f4ad8SHonghui Zhang {} 2693c8f4ad8SHonghui Zhang }; 2703c8f4ad8SHonghui Zhang 2710e14917cSYong Wu static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi, 2720e14917cSYong Wu const char * const clks[], 2730e14917cSYong Wu unsigned int clk_nr_required, 2740e14917cSYong Wu unsigned int clk_nr_optional) 2750e14917cSYong Wu { 2760e14917cSYong Wu int i, ret; 2770e14917cSYong Wu 2780e14917cSYong Wu for (i = 0; i < clk_nr_required; i++) 2790e14917cSYong Wu smi->clks[i].id = clks[i]; 2800e14917cSYong Wu ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks); 2810e14917cSYong Wu if (ret) 2820e14917cSYong Wu return ret; 2830e14917cSYong Wu 2840e14917cSYong Wu for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++) 2850e14917cSYong Wu smi->clks[i].id = clks[i]; 2860e14917cSYong Wu ret = devm_clk_bulk_get_optional(dev, clk_nr_optional, 2870e14917cSYong Wu smi->clks + clk_nr_required); 2880e14917cSYong Wu smi->clk_num = clk_nr_required + clk_nr_optional; 2890e14917cSYong Wu return ret; 2900e14917cSYong Wu } 2910e14917cSYong Wu 292cc8bbe1aSYong Wu static int mtk_smi_larb_probe(struct platform_device *pdev) 293cc8bbe1aSYong Wu { 294cc8bbe1aSYong Wu struct mtk_smi_larb *larb; 295cc8bbe1aSYong Wu struct resource *res; 296cc8bbe1aSYong Wu struct device *dev = &pdev->dev; 297cc8bbe1aSYong Wu struct device_node *smi_node; 298cc8bbe1aSYong Wu struct platform_device *smi_pdev; 2996ce2c05bSYong Wu struct device_link *link; 3000e14917cSYong Wu int ret; 301cc8bbe1aSYong Wu 302cc8bbe1aSYong Wu larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); 303cc8bbe1aSYong Wu if (!larb) 304cc8bbe1aSYong Wu return -ENOMEM; 305cc8bbe1aSYong Wu 30675487860SHonghui Zhang larb->larb_gen = of_device_get_match_data(dev); 307cc8bbe1aSYong Wu res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 308cc8bbe1aSYong Wu larb->base = devm_ioremap_resource(dev, res); 309cc8bbe1aSYong Wu if (IS_ERR(larb->base)) 310cc8bbe1aSYong Wu return PTR_ERR(larb->base); 311cc8bbe1aSYong Wu 3120e14917cSYong Wu ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks, 3130e14917cSYong Wu MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR); 3140e14917cSYong Wu if (ret) 3150e14917cSYong Wu return ret; 316cc8bbe1aSYong Wu 317cc8bbe1aSYong Wu larb->smi.dev = dev; 318cc8bbe1aSYong Wu smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); 319cc8bbe1aSYong Wu if (!smi_node) 320cc8bbe1aSYong Wu return -EINVAL; 321cc8bbe1aSYong Wu 322cc8bbe1aSYong Wu smi_pdev = of_find_device_by_node(smi_node); 323cc8bbe1aSYong Wu of_node_put(smi_node); 324cc8bbe1aSYong Wu if (smi_pdev) { 3254f608d38SYong Wu if (!platform_get_drvdata(smi_pdev)) 3264f608d38SYong Wu return -EPROBE_DEFER; 327cc8bbe1aSYong Wu larb->smi_common_dev = &smi_pdev->dev; 3286ce2c05bSYong Wu link = device_link_add(dev, larb->smi_common_dev, 3296ce2c05bSYong Wu DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 3306ce2c05bSYong Wu if (!link) { 3316ce2c05bSYong Wu dev_err(dev, "Unable to link smi-common dev\n"); 3326ce2c05bSYong Wu return -ENODEV; 3336ce2c05bSYong Wu } 334cc8bbe1aSYong Wu } else { 335cc8bbe1aSYong Wu dev_err(dev, "Failed to get the smi_common device\n"); 336cc8bbe1aSYong Wu return -EINVAL; 337cc8bbe1aSYong Wu } 338cc8bbe1aSYong Wu 339cc8bbe1aSYong Wu pm_runtime_enable(dev); 340cc8bbe1aSYong Wu platform_set_drvdata(pdev, larb); 341*30b869e7SYong Wu ret = component_add(dev, &mtk_smi_larb_component_ops); 342*30b869e7SYong Wu if (ret) 343*30b869e7SYong Wu goto err_pm_disable; 344*30b869e7SYong Wu return 0; 345*30b869e7SYong Wu 346*30b869e7SYong Wu err_pm_disable: 347*30b869e7SYong Wu pm_runtime_disable(dev); 348*30b869e7SYong Wu device_link_remove(dev, larb->smi_common_dev); 349*30b869e7SYong Wu return ret; 350cc8bbe1aSYong Wu } 351cc8bbe1aSYong Wu 352cc8bbe1aSYong Wu static int mtk_smi_larb_remove(struct platform_device *pdev) 353cc8bbe1aSYong Wu { 3546ce2c05bSYong Wu struct mtk_smi_larb *larb = platform_get_drvdata(pdev); 3556ce2c05bSYong Wu 3566ce2c05bSYong Wu device_link_remove(&pdev->dev, larb->smi_common_dev); 357cc8bbe1aSYong Wu pm_runtime_disable(&pdev->dev); 358cc8bbe1aSYong Wu component_del(&pdev->dev, &mtk_smi_larb_component_ops); 359cc8bbe1aSYong Wu return 0; 360cc8bbe1aSYong Wu } 361cc8bbe1aSYong Wu 3624f0a1a1aSYong Wu static int __maybe_unused mtk_smi_larb_resume(struct device *dev) 3634f0a1a1aSYong Wu { 3644f0a1a1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 3654f0a1a1aSYong Wu const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 3664f0a1a1aSYong Wu int ret; 3674f0a1a1aSYong Wu 3680e14917cSYong Wu ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks); 3690e14917cSYong Wu if (ret < 0) 3704f0a1a1aSYong Wu return ret; 3714f0a1a1aSYong Wu 3724f0a1a1aSYong Wu /* Configure the basic setting for this larb */ 3734f0a1a1aSYong Wu larb_gen->config_port(dev); 3744f0a1a1aSYong Wu 3754f0a1a1aSYong Wu return 0; 3764f0a1a1aSYong Wu } 3774f0a1a1aSYong Wu 3784f0a1a1aSYong Wu static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) 3794f0a1a1aSYong Wu { 3804f0a1a1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 3814f0a1a1aSYong Wu 3820e14917cSYong Wu clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks); 3834f0a1a1aSYong Wu return 0; 3844f0a1a1aSYong Wu } 3854f0a1a1aSYong Wu 3864f0a1a1aSYong Wu static const struct dev_pm_ops smi_larb_pm_ops = { 3874f0a1a1aSYong Wu SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL) 388fb03082aSYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 389fb03082aSYong Wu pm_runtime_force_resume) 3904f0a1a1aSYong Wu }; 3914f0a1a1aSYong Wu 392cc8bbe1aSYong Wu static struct platform_driver mtk_smi_larb_driver = { 393cc8bbe1aSYong Wu .probe = mtk_smi_larb_probe, 394cc8bbe1aSYong Wu .remove = mtk_smi_larb_remove, 395cc8bbe1aSYong Wu .driver = { 396cc8bbe1aSYong Wu .name = "mtk-smi-larb", 397cc8bbe1aSYong Wu .of_match_table = mtk_smi_larb_of_ids, 3984f0a1a1aSYong Wu .pm = &smi_larb_pm_ops, 399cc8bbe1aSYong Wu } 400cc8bbe1aSYong Wu }; 401cc8bbe1aSYong Wu 40242d42c76SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_gen1 = { 403a5c18986SYong Wu .type = MTK_SMI_GEN1, 40442d42c76SYong Wu }; 40542d42c76SYong Wu 40642d42c76SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { 407a5c18986SYong Wu .type = MTK_SMI_GEN2, 40842d42c76SYong Wu }; 40942d42c76SYong Wu 410fc492f33SMing-Fan Chen static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { 411a5c18986SYong Wu .type = MTK_SMI_GEN2, 412fc492f33SMing-Fan Chen .has_gals = true, 413fc492f33SMing-Fan Chen .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | 414fc492f33SMing-Fan Chen F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), 415fc492f33SMing-Fan Chen }; 416fc492f33SMing-Fan Chen 417907ba6a1SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { 418a5c18986SYong Wu .type = MTK_SMI_GEN2, 419907ba6a1SYong Wu .has_gals = true, 420567e58cfSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 421567e58cfSYong Wu F_MMU1_LARB(7), 422907ba6a1SYong Wu }; 423907ba6a1SYong Wu 42402c02ddcSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { 425a5c18986SYong Wu .type = MTK_SMI_GEN2, 42602c02ddcSYong Wu .has_gals = true, 42702c02ddcSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 42802c02ddcSYong Wu F_MMU1_LARB(6), 42902c02ddcSYong Wu }; 43002c02ddcSYong Wu 4313c8f4ad8SHonghui Zhang static const struct of_device_id mtk_smi_common_of_ids[] = { 432534e0ad2SYong Wu {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1}, 433534e0ad2SYong Wu {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2}, 434534e0ad2SYong Wu {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779}, 435534e0ad2SYong Wu {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2}, 436534e0ad2SYong Wu {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2}, 437534e0ad2SYong Wu {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183}, 438534e0ad2SYong Wu {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, 4393c8f4ad8SHonghui Zhang {} 4403c8f4ad8SHonghui Zhang }; 4413c8f4ad8SHonghui Zhang 442cc8bbe1aSYong Wu static int mtk_smi_common_probe(struct platform_device *pdev) 443cc8bbe1aSYong Wu { 444cc8bbe1aSYong Wu struct device *dev = &pdev->dev; 445cc8bbe1aSYong Wu struct mtk_smi *common; 4463c8f4ad8SHonghui Zhang struct resource *res; 4470e14917cSYong Wu int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR; 448cc8bbe1aSYong Wu 449cc8bbe1aSYong Wu common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); 450cc8bbe1aSYong Wu if (!common) 451cc8bbe1aSYong Wu return -ENOMEM; 452cc8bbe1aSYong Wu common->dev = dev; 45342d42c76SYong Wu common->plat = of_device_get_match_data(dev); 454cc8bbe1aSYong Wu 4550e14917cSYong Wu if (common->plat->has_gals) 4560e14917cSYong Wu clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR; 4570e14917cSYong Wu ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0); 4580e14917cSYong Wu if (ret) 4590e14917cSYong Wu return ret; 46064fea74aSYong Wu 4613c8f4ad8SHonghui Zhang /* 4623c8f4ad8SHonghui Zhang * for mtk smi gen 1, we need to get the ao(always on) base to config 4633c8f4ad8SHonghui Zhang * m4u port, and we need to enable the aync clock for transform the smi 4643c8f4ad8SHonghui Zhang * clock into emi clock domain, but for mtk smi gen2, there's no smi ao 4653c8f4ad8SHonghui Zhang * base. 4663c8f4ad8SHonghui Zhang */ 467a5c18986SYong Wu if (common->plat->type == MTK_SMI_GEN1) { 4683c8f4ad8SHonghui Zhang res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4693c8f4ad8SHonghui Zhang common->smi_ao_base = devm_ioremap_resource(dev, res); 4703c8f4ad8SHonghui Zhang if (IS_ERR(common->smi_ao_base)) 4713c8f4ad8SHonghui Zhang return PTR_ERR(common->smi_ao_base); 4723c8f4ad8SHonghui Zhang 4733c8f4ad8SHonghui Zhang common->clk_async = devm_clk_get(dev, "async"); 4743c8f4ad8SHonghui Zhang if (IS_ERR(common->clk_async)) 4753c8f4ad8SHonghui Zhang return PTR_ERR(common->clk_async); 4763c8f4ad8SHonghui Zhang 47746cc815dSArvind Yadav ret = clk_prepare_enable(common->clk_async); 47846cc815dSArvind Yadav if (ret) 47946cc815dSArvind Yadav return ret; 480567e58cfSYong Wu } else { 481567e58cfSYong Wu res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 482567e58cfSYong Wu common->base = devm_ioremap_resource(dev, res); 483567e58cfSYong Wu if (IS_ERR(common->base)) 484567e58cfSYong Wu return PTR_ERR(common->base); 4853c8f4ad8SHonghui Zhang } 486cc8bbe1aSYong Wu pm_runtime_enable(dev); 487cc8bbe1aSYong Wu platform_set_drvdata(pdev, common); 488cc8bbe1aSYong Wu return 0; 489cc8bbe1aSYong Wu } 490cc8bbe1aSYong Wu 491cc8bbe1aSYong Wu static int mtk_smi_common_remove(struct platform_device *pdev) 492cc8bbe1aSYong Wu { 493cc8bbe1aSYong Wu pm_runtime_disable(&pdev->dev); 494cc8bbe1aSYong Wu return 0; 495cc8bbe1aSYong Wu } 496cc8bbe1aSYong Wu 4974f0a1a1aSYong Wu static int __maybe_unused mtk_smi_common_resume(struct device *dev) 4984f0a1a1aSYong Wu { 4994f0a1a1aSYong Wu struct mtk_smi *common = dev_get_drvdata(dev); 500567e58cfSYong Wu u32 bus_sel = common->plat->bus_sel; 5014f0a1a1aSYong Wu int ret; 5024f0a1a1aSYong Wu 5030e14917cSYong Wu ret = clk_bulk_prepare_enable(common->clk_num, common->clks); 5040e14917cSYong Wu if (ret) 5054f0a1a1aSYong Wu return ret; 506567e58cfSYong Wu 507a5c18986SYong Wu if (common->plat->type == MTK_SMI_GEN2 && bus_sel) 508567e58cfSYong Wu writel(bus_sel, common->base + SMI_BUS_SEL); 5094f0a1a1aSYong Wu return 0; 5104f0a1a1aSYong Wu } 5114f0a1a1aSYong Wu 5124f0a1a1aSYong Wu static int __maybe_unused mtk_smi_common_suspend(struct device *dev) 5134f0a1a1aSYong Wu { 5144f0a1a1aSYong Wu struct mtk_smi *common = dev_get_drvdata(dev); 5154f0a1a1aSYong Wu 5160e14917cSYong Wu clk_bulk_disable_unprepare(common->clk_num, common->clks); 5174f0a1a1aSYong Wu return 0; 5184f0a1a1aSYong Wu } 5194f0a1a1aSYong Wu 5204f0a1a1aSYong Wu static const struct dev_pm_ops smi_common_pm_ops = { 5214f0a1a1aSYong Wu SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL) 522fb03082aSYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 523fb03082aSYong Wu pm_runtime_force_resume) 5244f0a1a1aSYong Wu }; 5254f0a1a1aSYong Wu 526cc8bbe1aSYong Wu static struct platform_driver mtk_smi_common_driver = { 527cc8bbe1aSYong Wu .probe = mtk_smi_common_probe, 528cc8bbe1aSYong Wu .remove = mtk_smi_common_remove, 529cc8bbe1aSYong Wu .driver = { 530cc8bbe1aSYong Wu .name = "mtk-smi-common", 531cc8bbe1aSYong Wu .of_match_table = mtk_smi_common_of_ids, 5324f0a1a1aSYong Wu .pm = &smi_common_pm_ops, 533cc8bbe1aSYong Wu } 534cc8bbe1aSYong Wu }; 535cc8bbe1aSYong Wu 53618212031SYong Wu static struct platform_driver * const smidrivers[] = { 53718212031SYong Wu &mtk_smi_common_driver, 53818212031SYong Wu &mtk_smi_larb_driver, 53918212031SYong Wu }; 54018212031SYong Wu 541cc8bbe1aSYong Wu static int __init mtk_smi_init(void) 542cc8bbe1aSYong Wu { 54318212031SYong Wu return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 544cc8bbe1aSYong Wu } 5454f608d38SYong Wu module_init(mtk_smi_init); 54650fc8d92SYong Wu 54750fc8d92SYong Wu static void __exit mtk_smi_exit(void) 54850fc8d92SYong Wu { 54950fc8d92SYong Wu platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 55050fc8d92SYong Wu } 55150fc8d92SYong Wu module_exit(mtk_smi_exit); 55250fc8d92SYong Wu 55350fc8d92SYong Wu MODULE_DESCRIPTION("MediaTek SMI driver"); 55450fc8d92SYong Wu MODULE_LICENSE("GPL v2"); 555