11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2cc8bbe1aSYong Wu /* 3cc8bbe1aSYong Wu * Copyright (c) 2015-2016 MediaTek Inc. 4cc8bbe1aSYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 5cc8bbe1aSYong Wu */ 6cc8bbe1aSYong Wu #include <linux/clk.h> 7cc8bbe1aSYong Wu #include <linux/component.h> 8cc8bbe1aSYong Wu #include <linux/device.h> 9cc8bbe1aSYong Wu #include <linux/err.h> 10cc8bbe1aSYong Wu #include <linux/io.h> 114f608d38SYong Wu #include <linux/module.h> 12cc8bbe1aSYong Wu #include <linux/of.h> 13cc8bbe1aSYong Wu #include <linux/of_platform.h> 14cc8bbe1aSYong Wu #include <linux/platform_device.h> 15cc8bbe1aSYong Wu #include <linux/pm_runtime.h> 16cc8bbe1aSYong Wu #include <soc/mediatek/smi.h> 173c8f4ad8SHonghui Zhang #include <dt-bindings/memory/mt2701-larb-port.h> 18cc8bbe1aSYong Wu 19e6dec923SYong Wu /* mt8173 */ 20cc8bbe1aSYong Wu #define SMI_LARB_MMU_EN 0xf00 21e6dec923SYong Wu 22a8529f3bSFabien Parent /* mt8167 */ 23a8529f3bSFabien Parent #define MT8167_SMI_LARB_MMU_EN 0xfc0 24a8529f3bSFabien Parent 25e6dec923SYong Wu /* mt2701 */ 263c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_BASE 0x5c0 273c8f4ad8SHonghui Zhang 283c8f4ad8SHonghui Zhang /* every register control 8 port, register offset 0x4 */ 293c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2) 303c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_ADDR(id) \ 313c8f4ad8SHonghui Zhang (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id)) 323c8f4ad8SHonghui Zhang 333c8f4ad8SHonghui Zhang /* 343c8f4ad8SHonghui Zhang * every port have 4 bit to control, bit[port + 3] control virtual or physical, 353c8f4ad8SHonghui Zhang * bit[port + 2 : port + 1] control the domain, bit[port] control the security 363c8f4ad8SHonghui Zhang * or non-security. 373c8f4ad8SHonghui Zhang */ 383c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2))) 393c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3) 403c8f4ad8SHonghui Zhang /* mt2701 domain should be set to 3 */ 413c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) 423c8f4ad8SHonghui Zhang 43e6dec923SYong Wu /* mt2712 */ 44e6dec923SYong Wu #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) 45e6dec923SYong Wu #define F_MMU_EN BIT(0) 46e6dec923SYong Wu 47567e58cfSYong Wu /* SMI COMMON */ 48567e58cfSYong Wu #define SMI_BUS_SEL 0x220 49567e58cfSYong Wu #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) 50567e58cfSYong Wu /* All are MMU0 defaultly. Only specialize mmu1 here. */ 51567e58cfSYong Wu #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) 52567e58cfSYong Wu 5342d42c76SYong Wu enum mtk_smi_gen { 5442d42c76SYong Wu MTK_SMI_GEN1, 5542d42c76SYong Wu MTK_SMI_GEN2 5642d42c76SYong Wu }; 5742d42c76SYong Wu 5842d42c76SYong Wu struct mtk_smi_common_plat { 5942d42c76SYong Wu enum mtk_smi_gen gen; 6064fea74aSYong Wu bool has_gals; 61567e58cfSYong Wu u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ 6242d42c76SYong Wu }; 6342d42c76SYong Wu 643c8f4ad8SHonghui Zhang struct mtk_smi_larb_gen { 653c8f4ad8SHonghui Zhang int port_in_larb[MTK_LARB_NR_MAX + 1]; 663aa5a6c2SKrzysztof Kozlowski void (*config_port)(struct device *dev); 672e9b0908SYong Wu unsigned int larb_direct_to_common_mask; 6864fea74aSYong Wu bool has_gals; 693c8f4ad8SHonghui Zhang }; 70cc8bbe1aSYong Wu 71cc8bbe1aSYong Wu struct mtk_smi { 72cc8bbe1aSYong Wu struct device *dev; 73cc8bbe1aSYong Wu struct clk *clk_apb, *clk_smi; 7464fea74aSYong Wu struct clk *clk_gals0, *clk_gals1; 753c8f4ad8SHonghui Zhang struct clk *clk_async; /*only needed by mt2701*/ 76567e58cfSYong Wu union { 77567e58cfSYong Wu void __iomem *smi_ao_base; /* only for gen1 */ 78567e58cfSYong Wu void __iomem *base; /* only for gen2 */ 79567e58cfSYong Wu }; 8042d42c76SYong Wu const struct mtk_smi_common_plat *plat; 81cc8bbe1aSYong Wu }; 82cc8bbe1aSYong Wu 83cc8bbe1aSYong Wu struct mtk_smi_larb { /* larb: local arbiter */ 84cc8bbe1aSYong Wu struct mtk_smi smi; 85cc8bbe1aSYong Wu void __iomem *base; 86cc8bbe1aSYong Wu struct device *smi_common_dev; 873c8f4ad8SHonghui Zhang const struct mtk_smi_larb_gen *larb_gen; 883c8f4ad8SHonghui Zhang int larbid; 89cc8bbe1aSYong Wu u32 *mmu; 90cc8bbe1aSYong Wu }; 91cc8bbe1aSYong Wu 924f0a1a1aSYong Wu static int mtk_smi_clk_enable(const struct mtk_smi *smi) 93cc8bbe1aSYong Wu { 94cc8bbe1aSYong Wu int ret; 95cc8bbe1aSYong Wu 96cc8bbe1aSYong Wu ret = clk_prepare_enable(smi->clk_apb); 97cc8bbe1aSYong Wu if (ret) 984f0a1a1aSYong Wu return ret; 99cc8bbe1aSYong Wu 100cc8bbe1aSYong Wu ret = clk_prepare_enable(smi->clk_smi); 101cc8bbe1aSYong Wu if (ret) 102cc8bbe1aSYong Wu goto err_disable_apb; 103cc8bbe1aSYong Wu 10464fea74aSYong Wu ret = clk_prepare_enable(smi->clk_gals0); 10564fea74aSYong Wu if (ret) 10664fea74aSYong Wu goto err_disable_smi; 10764fea74aSYong Wu 10864fea74aSYong Wu ret = clk_prepare_enable(smi->clk_gals1); 10964fea74aSYong Wu if (ret) 11064fea74aSYong Wu goto err_disable_gals0; 11164fea74aSYong Wu 112cc8bbe1aSYong Wu return 0; 113cc8bbe1aSYong Wu 11464fea74aSYong Wu err_disable_gals0: 11564fea74aSYong Wu clk_disable_unprepare(smi->clk_gals0); 11664fea74aSYong Wu err_disable_smi: 11764fea74aSYong Wu clk_disable_unprepare(smi->clk_smi); 118cc8bbe1aSYong Wu err_disable_apb: 119cc8bbe1aSYong Wu clk_disable_unprepare(smi->clk_apb); 120cc8bbe1aSYong Wu return ret; 121cc8bbe1aSYong Wu } 122cc8bbe1aSYong Wu 1234f0a1a1aSYong Wu static void mtk_smi_clk_disable(const struct mtk_smi *smi) 124cc8bbe1aSYong Wu { 12564fea74aSYong Wu clk_disable_unprepare(smi->clk_gals1); 12664fea74aSYong Wu clk_disable_unprepare(smi->clk_gals0); 127cc8bbe1aSYong Wu clk_disable_unprepare(smi->clk_smi); 128cc8bbe1aSYong Wu clk_disable_unprepare(smi->clk_apb); 129cc8bbe1aSYong Wu } 130cc8bbe1aSYong Wu 131cc8bbe1aSYong Wu int mtk_smi_larb_get(struct device *larbdev) 132cc8bbe1aSYong Wu { 133a2d522ffSZhang Qilong int ret = pm_runtime_resume_and_get(larbdev); 134cc8bbe1aSYong Wu 1354f0a1a1aSYong Wu return (ret < 0) ? ret : 0; 136cc8bbe1aSYong Wu } 137cb1b5dffSPhilipp Zabel EXPORT_SYMBOL_GPL(mtk_smi_larb_get); 138cc8bbe1aSYong Wu 139cc8bbe1aSYong Wu void mtk_smi_larb_put(struct device *larbdev) 140cc8bbe1aSYong Wu { 1414f0a1a1aSYong Wu pm_runtime_put_sync(larbdev); 142cc8bbe1aSYong Wu } 143cb1b5dffSPhilipp Zabel EXPORT_SYMBOL_GPL(mtk_smi_larb_put); 144cc8bbe1aSYong Wu 145cc8bbe1aSYong Wu static int 146cc8bbe1aSYong Wu mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) 147cc8bbe1aSYong Wu { 148cc8bbe1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 1491ee9feb2SYong Wu struct mtk_smi_larb_iommu *larb_mmu = data; 150cc8bbe1aSYong Wu unsigned int i; 151cc8bbe1aSYong Wu 152ec2da07cSYong Wu for (i = 0; i < MTK_LARB_NR_MAX; i++) { 1531ee9feb2SYong Wu if (dev == larb_mmu[i].dev) { 154ec2da07cSYong Wu larb->larbid = i; 1551ee9feb2SYong Wu larb->mmu = &larb_mmu[i].mmu; 156cc8bbe1aSYong Wu return 0; 157cc8bbe1aSYong Wu } 158cc8bbe1aSYong Wu } 159cc8bbe1aSYong Wu return -ENODEV; 160cc8bbe1aSYong Wu } 161cc8bbe1aSYong Wu 1622e9b0908SYong Wu static void mtk_smi_larb_config_port_gen2_general(struct device *dev) 163e6dec923SYong Wu { 164e6dec923SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 165e6dec923SYong Wu u32 reg; 166e6dec923SYong Wu int i; 167e6dec923SYong Wu 1682e9b0908SYong Wu if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) 169e6dec923SYong Wu return; 170e6dec923SYong Wu 171e6dec923SYong Wu for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { 172e6dec923SYong Wu reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); 173e6dec923SYong Wu reg |= F_MMU_EN; 174e6dec923SYong Wu writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); 175e6dec923SYong Wu } 176e6dec923SYong Wu } 177e6dec923SYong Wu 178e6dec923SYong Wu static void mtk_smi_larb_config_port_mt8173(struct device *dev) 1793c8f4ad8SHonghui Zhang { 1803c8f4ad8SHonghui Zhang struct mtk_smi_larb *larb = dev_get_drvdata(dev); 1813c8f4ad8SHonghui Zhang 1823c8f4ad8SHonghui Zhang writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN); 1833c8f4ad8SHonghui Zhang } 1843c8f4ad8SHonghui Zhang 185a8529f3bSFabien Parent static void mtk_smi_larb_config_port_mt8167(struct device *dev) 186a8529f3bSFabien Parent { 187a8529f3bSFabien Parent struct mtk_smi_larb *larb = dev_get_drvdata(dev); 188a8529f3bSFabien Parent 189a8529f3bSFabien Parent writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); 190a8529f3bSFabien Parent } 191a8529f3bSFabien Parent 1923c8f4ad8SHonghui Zhang static void mtk_smi_larb_config_port_gen1(struct device *dev) 1933c8f4ad8SHonghui Zhang { 1943c8f4ad8SHonghui Zhang struct mtk_smi_larb *larb = dev_get_drvdata(dev); 1953c8f4ad8SHonghui Zhang const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 1963c8f4ad8SHonghui Zhang struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); 1973c8f4ad8SHonghui Zhang int i, m4u_port_id, larb_port_num; 1983c8f4ad8SHonghui Zhang u32 sec_con_val, reg_val; 1993c8f4ad8SHonghui Zhang 2003c8f4ad8SHonghui Zhang m4u_port_id = larb_gen->port_in_larb[larb->larbid]; 2013c8f4ad8SHonghui Zhang larb_port_num = larb_gen->port_in_larb[larb->larbid + 1] 2023c8f4ad8SHonghui Zhang - larb_gen->port_in_larb[larb->larbid]; 2033c8f4ad8SHonghui Zhang 2043c8f4ad8SHonghui Zhang for (i = 0; i < larb_port_num; i++, m4u_port_id++) { 2053c8f4ad8SHonghui Zhang if (*larb->mmu & BIT(i)) { 2063c8f4ad8SHonghui Zhang /* bit[port + 3] controls the virtual or physical */ 2073c8f4ad8SHonghui Zhang sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id); 2083c8f4ad8SHonghui Zhang } else { 2093c8f4ad8SHonghui Zhang /* do not need to enable m4u for this port */ 2103c8f4ad8SHonghui Zhang continue; 2113c8f4ad8SHonghui Zhang } 2123c8f4ad8SHonghui Zhang reg_val = readl(common->smi_ao_base 2133c8f4ad8SHonghui Zhang + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 2143c8f4ad8SHonghui Zhang reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); 2153c8f4ad8SHonghui Zhang reg_val |= sec_con_val; 2163c8f4ad8SHonghui Zhang reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); 2173c8f4ad8SHonghui Zhang writel(reg_val, 2183c8f4ad8SHonghui Zhang common->smi_ao_base 2193c8f4ad8SHonghui Zhang + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 2203c8f4ad8SHonghui Zhang } 2213c8f4ad8SHonghui Zhang } 2223c8f4ad8SHonghui Zhang 223cc8bbe1aSYong Wu static void 224cc8bbe1aSYong Wu mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) 225cc8bbe1aSYong Wu { 226cc8bbe1aSYong Wu /* Do nothing as the iommu is always enabled. */ 227cc8bbe1aSYong Wu } 228cc8bbe1aSYong Wu 229cc8bbe1aSYong Wu static const struct component_ops mtk_smi_larb_component_ops = { 230cc8bbe1aSYong Wu .bind = mtk_smi_larb_bind, 231cc8bbe1aSYong Wu .unbind = mtk_smi_larb_unbind, 232cc8bbe1aSYong Wu }; 233cc8bbe1aSYong Wu 2343c8f4ad8SHonghui Zhang static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { 2353c8f4ad8SHonghui Zhang /* mt8173 do not need the port in larb */ 236e6dec923SYong Wu .config_port = mtk_smi_larb_config_port_mt8173, 2373c8f4ad8SHonghui Zhang }; 2383c8f4ad8SHonghui Zhang 239a8529f3bSFabien Parent static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = { 240a8529f3bSFabien Parent /* mt8167 do not need the port in larb */ 241a8529f3bSFabien Parent .config_port = mtk_smi_larb_config_port_mt8167, 242a8529f3bSFabien Parent }; 243a8529f3bSFabien Parent 2443c8f4ad8SHonghui Zhang static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { 2453c8f4ad8SHonghui Zhang .port_in_larb = { 2463c8f4ad8SHonghui Zhang LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 2473c8f4ad8SHonghui Zhang LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 2483c8f4ad8SHonghui Zhang }, 2493c8f4ad8SHonghui Zhang .config_port = mtk_smi_larb_config_port_gen1, 2503c8f4ad8SHonghui Zhang }; 2513c8f4ad8SHonghui Zhang 252e6dec923SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { 2532e9b0908SYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 2542e9b0908SYong Wu .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ 255e6dec923SYong Wu }; 256e6dec923SYong Wu 257fc492f33SMing-Fan Chen static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { 258fc492f33SMing-Fan Chen .config_port = mtk_smi_larb_config_port_gen2_general, 259fc492f33SMing-Fan Chen .larb_direct_to_common_mask = 260fc492f33SMing-Fan Chen BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), 261fc492f33SMing-Fan Chen /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ 262fc492f33SMing-Fan Chen }; 263fc492f33SMing-Fan Chen 264907ba6a1SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { 265907ba6a1SYong Wu .has_gals = true, 266907ba6a1SYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 267907ba6a1SYong Wu .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), 268907ba6a1SYong Wu /* IPU0 | IPU1 | CCU */ 269907ba6a1SYong Wu }; 270907ba6a1SYong Wu 27102c02ddcSYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { 27202c02ddcSYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 27302c02ddcSYong Wu }; 27402c02ddcSYong Wu 2753c8f4ad8SHonghui Zhang static const struct of_device_id mtk_smi_larb_of_ids[] = { 2763c8f4ad8SHonghui Zhang { 277a8529f3bSFabien Parent .compatible = "mediatek,mt8167-smi-larb", 278a8529f3bSFabien Parent .data = &mtk_smi_larb_mt8167 279a8529f3bSFabien Parent }, 280a8529f3bSFabien Parent { 2813c8f4ad8SHonghui Zhang .compatible = "mediatek,mt8173-smi-larb", 2823c8f4ad8SHonghui Zhang .data = &mtk_smi_larb_mt8173 2833c8f4ad8SHonghui Zhang }, 2843c8f4ad8SHonghui Zhang { 2853c8f4ad8SHonghui Zhang .compatible = "mediatek,mt2701-smi-larb", 2863c8f4ad8SHonghui Zhang .data = &mtk_smi_larb_mt2701 2873c8f4ad8SHonghui Zhang }, 288e6dec923SYong Wu { 289e6dec923SYong Wu .compatible = "mediatek,mt2712-smi-larb", 290e6dec923SYong Wu .data = &mtk_smi_larb_mt2712 291e6dec923SYong Wu }, 292907ba6a1SYong Wu { 293fc492f33SMing-Fan Chen .compatible = "mediatek,mt6779-smi-larb", 294fc492f33SMing-Fan Chen .data = &mtk_smi_larb_mt6779 295fc492f33SMing-Fan Chen }, 296fc492f33SMing-Fan Chen { 297907ba6a1SYong Wu .compatible = "mediatek,mt8183-smi-larb", 298907ba6a1SYong Wu .data = &mtk_smi_larb_mt8183 299907ba6a1SYong Wu }, 30002c02ddcSYong Wu { 30102c02ddcSYong Wu .compatible = "mediatek,mt8192-smi-larb", 30202c02ddcSYong Wu .data = &mtk_smi_larb_mt8192 30302c02ddcSYong Wu }, 3043c8f4ad8SHonghui Zhang {} 3053c8f4ad8SHonghui Zhang }; 3063c8f4ad8SHonghui Zhang 307cc8bbe1aSYong Wu static int mtk_smi_larb_probe(struct platform_device *pdev) 308cc8bbe1aSYong Wu { 309cc8bbe1aSYong Wu struct mtk_smi_larb *larb; 310cc8bbe1aSYong Wu struct resource *res; 311cc8bbe1aSYong Wu struct device *dev = &pdev->dev; 312cc8bbe1aSYong Wu struct device_node *smi_node; 313cc8bbe1aSYong Wu struct platform_device *smi_pdev; 314cc8bbe1aSYong Wu 315cc8bbe1aSYong Wu larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); 316cc8bbe1aSYong Wu if (!larb) 317cc8bbe1aSYong Wu return -ENOMEM; 318cc8bbe1aSYong Wu 31975487860SHonghui Zhang larb->larb_gen = of_device_get_match_data(dev); 320cc8bbe1aSYong Wu res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 321cc8bbe1aSYong Wu larb->base = devm_ioremap_resource(dev, res); 322cc8bbe1aSYong Wu if (IS_ERR(larb->base)) 323cc8bbe1aSYong Wu return PTR_ERR(larb->base); 324cc8bbe1aSYong Wu 325cc8bbe1aSYong Wu larb->smi.clk_apb = devm_clk_get(dev, "apb"); 326cc8bbe1aSYong Wu if (IS_ERR(larb->smi.clk_apb)) 327cc8bbe1aSYong Wu return PTR_ERR(larb->smi.clk_apb); 328cc8bbe1aSYong Wu 329cc8bbe1aSYong Wu larb->smi.clk_smi = devm_clk_get(dev, "smi"); 330cc8bbe1aSYong Wu if (IS_ERR(larb->smi.clk_smi)) 331cc8bbe1aSYong Wu return PTR_ERR(larb->smi.clk_smi); 33264fea74aSYong Wu 33364fea74aSYong Wu if (larb->larb_gen->has_gals) { 33464fea74aSYong Wu /* The larbs may still haven't gals even if the SoC support.*/ 33564fea74aSYong Wu larb->smi.clk_gals0 = devm_clk_get(dev, "gals"); 33664fea74aSYong Wu if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT) 33764fea74aSYong Wu larb->smi.clk_gals0 = NULL; 33864fea74aSYong Wu else if (IS_ERR(larb->smi.clk_gals0)) 33964fea74aSYong Wu return PTR_ERR(larb->smi.clk_gals0); 34064fea74aSYong Wu } 341cc8bbe1aSYong Wu larb->smi.dev = dev; 342cc8bbe1aSYong Wu 343cc8bbe1aSYong Wu smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); 344cc8bbe1aSYong Wu if (!smi_node) 345cc8bbe1aSYong Wu return -EINVAL; 346cc8bbe1aSYong Wu 347cc8bbe1aSYong Wu smi_pdev = of_find_device_by_node(smi_node); 348cc8bbe1aSYong Wu of_node_put(smi_node); 349cc8bbe1aSYong Wu if (smi_pdev) { 3504f608d38SYong Wu if (!platform_get_drvdata(smi_pdev)) 3514f608d38SYong Wu return -EPROBE_DEFER; 352cc8bbe1aSYong Wu larb->smi_common_dev = &smi_pdev->dev; 353cc8bbe1aSYong Wu } else { 354cc8bbe1aSYong Wu dev_err(dev, "Failed to get the smi_common device\n"); 355cc8bbe1aSYong Wu return -EINVAL; 356cc8bbe1aSYong Wu } 357cc8bbe1aSYong Wu 358cc8bbe1aSYong Wu pm_runtime_enable(dev); 359cc8bbe1aSYong Wu platform_set_drvdata(pdev, larb); 360cc8bbe1aSYong Wu return component_add(dev, &mtk_smi_larb_component_ops); 361cc8bbe1aSYong Wu } 362cc8bbe1aSYong Wu 363cc8bbe1aSYong Wu static int mtk_smi_larb_remove(struct platform_device *pdev) 364cc8bbe1aSYong Wu { 365cc8bbe1aSYong Wu pm_runtime_disable(&pdev->dev); 366cc8bbe1aSYong Wu component_del(&pdev->dev, &mtk_smi_larb_component_ops); 367cc8bbe1aSYong Wu return 0; 368cc8bbe1aSYong Wu } 369cc8bbe1aSYong Wu 3704f0a1a1aSYong Wu static int __maybe_unused mtk_smi_larb_resume(struct device *dev) 3714f0a1a1aSYong Wu { 3724f0a1a1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 3734f0a1a1aSYong Wu const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 3744f0a1a1aSYong Wu int ret; 3754f0a1a1aSYong Wu 3764f0a1a1aSYong Wu /* Power on smi-common. */ 377a2d522ffSZhang Qilong ret = pm_runtime_resume_and_get(larb->smi_common_dev); 3784f0a1a1aSYong Wu if (ret < 0) { 3794f0a1a1aSYong Wu dev_err(dev, "Failed to pm get for smi-common(%d).\n", ret); 3804f0a1a1aSYong Wu return ret; 3814f0a1a1aSYong Wu } 3824f0a1a1aSYong Wu 3834f0a1a1aSYong Wu ret = mtk_smi_clk_enable(&larb->smi); 3844f0a1a1aSYong Wu if (ret < 0) { 3854f0a1a1aSYong Wu dev_err(dev, "Failed to enable clock(%d).\n", ret); 3864f0a1a1aSYong Wu pm_runtime_put_sync(larb->smi_common_dev); 3874f0a1a1aSYong Wu return ret; 3884f0a1a1aSYong Wu } 3894f0a1a1aSYong Wu 3904f0a1a1aSYong Wu /* Configure the basic setting for this larb */ 3914f0a1a1aSYong Wu larb_gen->config_port(dev); 3924f0a1a1aSYong Wu 3934f0a1a1aSYong Wu return 0; 3944f0a1a1aSYong Wu } 3954f0a1a1aSYong Wu 3964f0a1a1aSYong Wu static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) 3974f0a1a1aSYong Wu { 3984f0a1a1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 3994f0a1a1aSYong Wu 4004f0a1a1aSYong Wu mtk_smi_clk_disable(&larb->smi); 4014f0a1a1aSYong Wu pm_runtime_put_sync(larb->smi_common_dev); 4024f0a1a1aSYong Wu return 0; 4034f0a1a1aSYong Wu } 4044f0a1a1aSYong Wu 4054f0a1a1aSYong Wu static const struct dev_pm_ops smi_larb_pm_ops = { 4064f0a1a1aSYong Wu SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL) 407fb03082aSYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 408fb03082aSYong Wu pm_runtime_force_resume) 4094f0a1a1aSYong Wu }; 4104f0a1a1aSYong Wu 411cc8bbe1aSYong Wu static struct platform_driver mtk_smi_larb_driver = { 412cc8bbe1aSYong Wu .probe = mtk_smi_larb_probe, 413cc8bbe1aSYong Wu .remove = mtk_smi_larb_remove, 414cc8bbe1aSYong Wu .driver = { 415cc8bbe1aSYong Wu .name = "mtk-smi-larb", 416cc8bbe1aSYong Wu .of_match_table = mtk_smi_larb_of_ids, 4174f0a1a1aSYong Wu .pm = &smi_larb_pm_ops, 418cc8bbe1aSYong Wu } 419cc8bbe1aSYong Wu }; 420cc8bbe1aSYong Wu 42142d42c76SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_gen1 = { 42242d42c76SYong Wu .gen = MTK_SMI_GEN1, 42342d42c76SYong Wu }; 42442d42c76SYong Wu 42542d42c76SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { 42642d42c76SYong Wu .gen = MTK_SMI_GEN2, 42742d42c76SYong Wu }; 42842d42c76SYong Wu 429fc492f33SMing-Fan Chen static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { 430fc492f33SMing-Fan Chen .gen = MTK_SMI_GEN2, 431fc492f33SMing-Fan Chen .has_gals = true, 432fc492f33SMing-Fan Chen .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | 433fc492f33SMing-Fan Chen F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), 434fc492f33SMing-Fan Chen }; 435fc492f33SMing-Fan Chen 436907ba6a1SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { 437907ba6a1SYong Wu .gen = MTK_SMI_GEN2, 438907ba6a1SYong Wu .has_gals = true, 439567e58cfSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 440567e58cfSYong Wu F_MMU1_LARB(7), 441907ba6a1SYong Wu }; 442907ba6a1SYong Wu 44302c02ddcSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { 44402c02ddcSYong Wu .gen = MTK_SMI_GEN2, 44502c02ddcSYong Wu .has_gals = true, 44602c02ddcSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 44702c02ddcSYong Wu F_MMU1_LARB(6), 44802c02ddcSYong Wu }; 44902c02ddcSYong Wu 4503c8f4ad8SHonghui Zhang static const struct of_device_id mtk_smi_common_of_ids[] = { 4513c8f4ad8SHonghui Zhang { 4523c8f4ad8SHonghui Zhang .compatible = "mediatek,mt8173-smi-common", 45342d42c76SYong Wu .data = &mtk_smi_common_gen2, 4543c8f4ad8SHonghui Zhang }, 4553c8f4ad8SHonghui Zhang { 456a8529f3bSFabien Parent .compatible = "mediatek,mt8167-smi-common", 457a8529f3bSFabien Parent .data = &mtk_smi_common_gen2, 458a8529f3bSFabien Parent }, 459a8529f3bSFabien Parent { 4603c8f4ad8SHonghui Zhang .compatible = "mediatek,mt2701-smi-common", 46142d42c76SYong Wu .data = &mtk_smi_common_gen1, 4623c8f4ad8SHonghui Zhang }, 463e6dec923SYong Wu { 464e6dec923SYong Wu .compatible = "mediatek,mt2712-smi-common", 46542d42c76SYong Wu .data = &mtk_smi_common_gen2, 466e6dec923SYong Wu }, 467907ba6a1SYong Wu { 468fc492f33SMing-Fan Chen .compatible = "mediatek,mt6779-smi-common", 469fc492f33SMing-Fan Chen .data = &mtk_smi_common_mt6779, 470fc492f33SMing-Fan Chen }, 471fc492f33SMing-Fan Chen { 472907ba6a1SYong Wu .compatible = "mediatek,mt8183-smi-common", 473907ba6a1SYong Wu .data = &mtk_smi_common_mt8183, 474907ba6a1SYong Wu }, 47502c02ddcSYong Wu { 47602c02ddcSYong Wu .compatible = "mediatek,mt8192-smi-common", 47702c02ddcSYong Wu .data = &mtk_smi_common_mt8192, 47802c02ddcSYong Wu }, 4793c8f4ad8SHonghui Zhang {} 4803c8f4ad8SHonghui Zhang }; 4813c8f4ad8SHonghui Zhang 482cc8bbe1aSYong Wu static int mtk_smi_common_probe(struct platform_device *pdev) 483cc8bbe1aSYong Wu { 484cc8bbe1aSYong Wu struct device *dev = &pdev->dev; 485cc8bbe1aSYong Wu struct mtk_smi *common; 4863c8f4ad8SHonghui Zhang struct resource *res; 48746cc815dSArvind Yadav int ret; 488cc8bbe1aSYong Wu 489cc8bbe1aSYong Wu common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); 490cc8bbe1aSYong Wu if (!common) 491cc8bbe1aSYong Wu return -ENOMEM; 492cc8bbe1aSYong Wu common->dev = dev; 49342d42c76SYong Wu common->plat = of_device_get_match_data(dev); 494cc8bbe1aSYong Wu 495cc8bbe1aSYong Wu common->clk_apb = devm_clk_get(dev, "apb"); 496cc8bbe1aSYong Wu if (IS_ERR(common->clk_apb)) 497cc8bbe1aSYong Wu return PTR_ERR(common->clk_apb); 498cc8bbe1aSYong Wu 499cc8bbe1aSYong Wu common->clk_smi = devm_clk_get(dev, "smi"); 500cc8bbe1aSYong Wu if (IS_ERR(common->clk_smi)) 501cc8bbe1aSYong Wu return PTR_ERR(common->clk_smi); 502cc8bbe1aSYong Wu 50364fea74aSYong Wu if (common->plat->has_gals) { 50464fea74aSYong Wu common->clk_gals0 = devm_clk_get(dev, "gals0"); 50564fea74aSYong Wu if (IS_ERR(common->clk_gals0)) 50664fea74aSYong Wu return PTR_ERR(common->clk_gals0); 50764fea74aSYong Wu 50864fea74aSYong Wu common->clk_gals1 = devm_clk_get(dev, "gals1"); 50964fea74aSYong Wu if (IS_ERR(common->clk_gals1)) 51064fea74aSYong Wu return PTR_ERR(common->clk_gals1); 51164fea74aSYong Wu } 51264fea74aSYong Wu 5133c8f4ad8SHonghui Zhang /* 5143c8f4ad8SHonghui Zhang * for mtk smi gen 1, we need to get the ao(always on) base to config 5153c8f4ad8SHonghui Zhang * m4u port, and we need to enable the aync clock for transform the smi 5163c8f4ad8SHonghui Zhang * clock into emi clock domain, but for mtk smi gen2, there's no smi ao 5173c8f4ad8SHonghui Zhang * base. 5183c8f4ad8SHonghui Zhang */ 51942d42c76SYong Wu if (common->plat->gen == MTK_SMI_GEN1) { 5203c8f4ad8SHonghui Zhang res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 5213c8f4ad8SHonghui Zhang common->smi_ao_base = devm_ioremap_resource(dev, res); 5223c8f4ad8SHonghui Zhang if (IS_ERR(common->smi_ao_base)) 5233c8f4ad8SHonghui Zhang return PTR_ERR(common->smi_ao_base); 5243c8f4ad8SHonghui Zhang 5253c8f4ad8SHonghui Zhang common->clk_async = devm_clk_get(dev, "async"); 5263c8f4ad8SHonghui Zhang if (IS_ERR(common->clk_async)) 5273c8f4ad8SHonghui Zhang return PTR_ERR(common->clk_async); 5283c8f4ad8SHonghui Zhang 52946cc815dSArvind Yadav ret = clk_prepare_enable(common->clk_async); 53046cc815dSArvind Yadav if (ret) 53146cc815dSArvind Yadav return ret; 532567e58cfSYong Wu } else { 533567e58cfSYong Wu res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 534567e58cfSYong Wu common->base = devm_ioremap_resource(dev, res); 535567e58cfSYong Wu if (IS_ERR(common->base)) 536567e58cfSYong Wu return PTR_ERR(common->base); 5373c8f4ad8SHonghui Zhang } 538cc8bbe1aSYong Wu pm_runtime_enable(dev); 539cc8bbe1aSYong Wu platform_set_drvdata(pdev, common); 540cc8bbe1aSYong Wu return 0; 541cc8bbe1aSYong Wu } 542cc8bbe1aSYong Wu 543cc8bbe1aSYong Wu static int mtk_smi_common_remove(struct platform_device *pdev) 544cc8bbe1aSYong Wu { 545cc8bbe1aSYong Wu pm_runtime_disable(&pdev->dev); 546cc8bbe1aSYong Wu return 0; 547cc8bbe1aSYong Wu } 548cc8bbe1aSYong Wu 5494f0a1a1aSYong Wu static int __maybe_unused mtk_smi_common_resume(struct device *dev) 5504f0a1a1aSYong Wu { 5514f0a1a1aSYong Wu struct mtk_smi *common = dev_get_drvdata(dev); 552567e58cfSYong Wu u32 bus_sel = common->plat->bus_sel; 5534f0a1a1aSYong Wu int ret; 5544f0a1a1aSYong Wu 5554f0a1a1aSYong Wu ret = mtk_smi_clk_enable(common); 5564f0a1a1aSYong Wu if (ret) { 5574f0a1a1aSYong Wu dev_err(common->dev, "Failed to enable clock(%d).\n", ret); 5584f0a1a1aSYong Wu return ret; 5594f0a1a1aSYong Wu } 560567e58cfSYong Wu 561567e58cfSYong Wu if (common->plat->gen == MTK_SMI_GEN2 && bus_sel) 562567e58cfSYong Wu writel(bus_sel, common->base + SMI_BUS_SEL); 5634f0a1a1aSYong Wu return 0; 5644f0a1a1aSYong Wu } 5654f0a1a1aSYong Wu 5664f0a1a1aSYong Wu static int __maybe_unused mtk_smi_common_suspend(struct device *dev) 5674f0a1a1aSYong Wu { 5684f0a1a1aSYong Wu struct mtk_smi *common = dev_get_drvdata(dev); 5694f0a1a1aSYong Wu 5704f0a1a1aSYong Wu mtk_smi_clk_disable(common); 5714f0a1a1aSYong Wu return 0; 5724f0a1a1aSYong Wu } 5734f0a1a1aSYong Wu 5744f0a1a1aSYong Wu static const struct dev_pm_ops smi_common_pm_ops = { 5754f0a1a1aSYong Wu SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL) 576fb03082aSYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 577fb03082aSYong Wu pm_runtime_force_resume) 5784f0a1a1aSYong Wu }; 5794f0a1a1aSYong Wu 580cc8bbe1aSYong Wu static struct platform_driver mtk_smi_common_driver = { 581cc8bbe1aSYong Wu .probe = mtk_smi_common_probe, 582cc8bbe1aSYong Wu .remove = mtk_smi_common_remove, 583cc8bbe1aSYong Wu .driver = { 584cc8bbe1aSYong Wu .name = "mtk-smi-common", 585cc8bbe1aSYong Wu .of_match_table = mtk_smi_common_of_ids, 5864f0a1a1aSYong Wu .pm = &smi_common_pm_ops, 587cc8bbe1aSYong Wu } 588cc8bbe1aSYong Wu }; 589cc8bbe1aSYong Wu 590*18212031SYong Wu static struct platform_driver * const smidrivers[] = { 591*18212031SYong Wu &mtk_smi_common_driver, 592*18212031SYong Wu &mtk_smi_larb_driver, 593*18212031SYong Wu }; 594*18212031SYong Wu 595cc8bbe1aSYong Wu static int __init mtk_smi_init(void) 596cc8bbe1aSYong Wu { 597*18212031SYong Wu return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 598cc8bbe1aSYong Wu } 5994f608d38SYong Wu module_init(mtk_smi_init); 600