11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2cc8bbe1aSYong Wu /* 3cc8bbe1aSYong Wu * Copyright (c) 2015-2016 MediaTek Inc. 4cc8bbe1aSYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 5cc8bbe1aSYong Wu */ 6cc8bbe1aSYong Wu #include <linux/clk.h> 7cc8bbe1aSYong Wu #include <linux/component.h> 8cc8bbe1aSYong Wu #include <linux/device.h> 9cc8bbe1aSYong Wu #include <linux/err.h> 10cc8bbe1aSYong Wu #include <linux/io.h> 118956500eSYong Wu #include <linux/iopoll.h> 124f608d38SYong Wu #include <linux/module.h> 13cc8bbe1aSYong Wu #include <linux/of.h> 14cc8bbe1aSYong Wu #include <linux/of_platform.h> 15cc8bbe1aSYong Wu #include <linux/platform_device.h> 16cc8bbe1aSYong Wu #include <linux/pm_runtime.h> 17cc8bbe1aSYong Wu #include <soc/mediatek/smi.h> 183c8f4ad8SHonghui Zhang #include <dt-bindings/memory/mt2701-larb-port.h> 1966a28915SYong Wu #include <dt-bindings/memory/mtk-memory-port.h> 20cc8bbe1aSYong Wu 21534e0ad2SYong Wu /* SMI COMMON */ 22431e9cabSYong Wu #define SMI_L1LEN 0x100 23431e9cabSYong Wu 24534e0ad2SYong Wu #define SMI_BUS_SEL 0x220 25534e0ad2SYong Wu #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) 26534e0ad2SYong Wu /* All are MMU0 defaultly. Only specialize mmu1 here. */ 27534e0ad2SYong Wu #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) 28e6dec923SYong Wu 29431e9cabSYong Wu #define SMI_M4U_TH 0x234 30431e9cabSYong Wu #define SMI_FIFO_TH1 0x238 31431e9cabSYong Wu #define SMI_FIFO_TH2 0x23c 32431e9cabSYong Wu #define SMI_DCM 0x300 33431e9cabSYong Wu #define SMI_DUMMY 0x444 34431e9cabSYong Wu 35534e0ad2SYong Wu /* SMI LARB */ 368956500eSYong Wu #define SMI_LARB_SLP_CON 0xc 378956500eSYong Wu #define SLP_PROT_EN BIT(0) 388956500eSYong Wu #define SLP_PROT_RDY BIT(16) 398956500eSYong Wu 40fe6dd2a4SYong Wu #define SMI_LARB_CMD_THRT_CON 0x24 41fe6dd2a4SYong Wu #define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4) 42fe6dd2a4SYong Wu #define SMI_LARB_THRT_RD_NU_LMT (5 << 4) 43fe6dd2a4SYong Wu 44fe6dd2a4SYong Wu #define SMI_LARB_SW_FLAG 0x40 45fe6dd2a4SYong Wu #define SMI_LARB_SW_FLAG_1 0x1 46fe6dd2a4SYong Wu 47fe6dd2a4SYong Wu #define SMI_LARB_OSTDL_PORT 0x200 48fe6dd2a4SYong Wu #define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2)) 49a8529f3bSFabien Parent 50534e0ad2SYong Wu /* Below are about mmu enable registers, they are different in SoCs */ 51534e0ad2SYong Wu /* gen1: mt2701 */ 523c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_BASE 0x5c0 533c8f4ad8SHonghui Zhang 543c8f4ad8SHonghui Zhang /* every register control 8 port, register offset 0x4 */ 553c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2) 563c8f4ad8SHonghui Zhang #define REG_SMI_SECUR_CON_ADDR(id) \ 573c8f4ad8SHonghui Zhang (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id)) 583c8f4ad8SHonghui Zhang 593c8f4ad8SHonghui Zhang /* 603c8f4ad8SHonghui Zhang * every port have 4 bit to control, bit[port + 3] control virtual or physical, 613c8f4ad8SHonghui Zhang * bit[port + 2 : port + 1] control the domain, bit[port] control the security 623c8f4ad8SHonghui Zhang * or non-security. 633c8f4ad8SHonghui Zhang */ 643c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2))) 653c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3) 663c8f4ad8SHonghui Zhang /* mt2701 domain should be set to 3 */ 673c8f4ad8SHonghui Zhang #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) 683c8f4ad8SHonghui Zhang 69534e0ad2SYong Wu /* gen2: */ 70534e0ad2SYong Wu /* mt8167 */ 71534e0ad2SYong Wu #define MT8167_SMI_LARB_MMU_EN 0xfc0 72534e0ad2SYong Wu 73534e0ad2SYong Wu /* mt8173 */ 74534e0ad2SYong Wu #define MT8173_SMI_LARB_MMU_EN 0xf00 75534e0ad2SYong Wu 76534e0ad2SYong Wu /* general */ 77e6dec923SYong Wu #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) 78e6dec923SYong Wu #define F_MMU_EN BIT(0) 798d2c749eSYong Wu #define BANK_SEL(id) ({ \ 808d2c749eSYong Wu u32 _id = (id) & 0x3; \ 818d2c749eSYong Wu (_id << 8 | _id << 10 | _id << 12 | _id << 14); \ 828d2c749eSYong Wu }) 83e6dec923SYong Wu 84431e9cabSYong Wu #define SMI_COMMON_INIT_REGS_NR 6 85fe6dd2a4SYong Wu #define SMI_LARB_PORT_NR_MAX 32 86fe6dd2a4SYong Wu 87fe6dd2a4SYong Wu #define MTK_SMI_FLAG_THRT_UPDATE BIT(0) 88fe6dd2a4SYong Wu #define MTK_SMI_FLAG_SW_FLAG BIT(1) 898956500eSYong Wu #define MTK_SMI_FLAG_SLEEP_CTL BIT(2) 90fe6dd2a4SYong Wu #define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x))) 91431e9cabSYong Wu 92431e9cabSYong Wu struct mtk_smi_reg_pair { 93431e9cabSYong Wu unsigned int offset; 94431e9cabSYong Wu u32 value; 95431e9cabSYong Wu }; 96431e9cabSYong Wu 97a5c18986SYong Wu enum mtk_smi_type { 9842d42c76SYong Wu MTK_SMI_GEN1, 9947404757SYong Wu MTK_SMI_GEN2, /* gen2 smi common */ 10047404757SYong Wu MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */ 10142d42c76SYong Wu }; 10242d42c76SYong Wu 1030e14917cSYong Wu /* larbs: Require apb/smi clocks while gals is optional. */ 1040e14917cSYong Wu static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"}; 1050e14917cSYong Wu #define MTK_SMI_LARB_REQ_CLK_NR 2 1060e14917cSYong Wu #define MTK_SMI_LARB_OPT_CLK_NR 1 1070e14917cSYong Wu 1080e14917cSYong Wu /* 1090e14917cSYong Wu * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required. 1103e4f74e0SYong Wu * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required. 1110e14917cSYong Wu */ 1120e14917cSYong Wu static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"}; 113205e1776SAngeloGioacchino Del Regno #define MTK_SMI_CLK_NR_MAX ARRAY_SIZE(mtk_smi_common_clks) 1140e14917cSYong Wu #define MTK_SMI_COM_REQ_CLK_NR 2 1150e14917cSYong Wu #define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX 1163e4f74e0SYong Wu #define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3 1170e14917cSYong Wu 11842d42c76SYong Wu struct mtk_smi_common_plat { 119a5c18986SYong Wu enum mtk_smi_type type; 12064fea74aSYong Wu bool has_gals; 121567e58cfSYong Wu u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ 122431e9cabSYong Wu 123431e9cabSYong Wu const struct mtk_smi_reg_pair *init; 12442d42c76SYong Wu }; 12542d42c76SYong Wu 1263c8f4ad8SHonghui Zhang struct mtk_smi_larb_gen { 1273c8f4ad8SHonghui Zhang int port_in_larb[MTK_LARB_NR_MAX + 1]; 1283aa5a6c2SKrzysztof Kozlowski void (*config_port)(struct device *dev); 1292e9b0908SYong Wu unsigned int larb_direct_to_common_mask; 130fe6dd2a4SYong Wu unsigned int flags_general; 131fe6dd2a4SYong Wu const u8 (*ostd)[SMI_LARB_PORT_NR_MAX]; 1323c8f4ad8SHonghui Zhang }; 133cc8bbe1aSYong Wu 134cc8bbe1aSYong Wu struct mtk_smi { 135cc8bbe1aSYong Wu struct device *dev; 1360e14917cSYong Wu unsigned int clk_num; 1370e14917cSYong Wu struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX]; 1383c8f4ad8SHonghui Zhang struct clk *clk_async; /*only needed by mt2701*/ 139567e58cfSYong Wu union { 140567e58cfSYong Wu void __iomem *smi_ao_base; /* only for gen1 */ 141567e58cfSYong Wu void __iomem *base; /* only for gen2 */ 142567e58cfSYong Wu }; 14347404757SYong Wu struct device *smi_common_dev; /* for sub common */ 14442d42c76SYong Wu const struct mtk_smi_common_plat *plat; 145cc8bbe1aSYong Wu }; 146cc8bbe1aSYong Wu 147cc8bbe1aSYong Wu struct mtk_smi_larb { /* larb: local arbiter */ 148cc8bbe1aSYong Wu struct mtk_smi smi; 149cc8bbe1aSYong Wu void __iomem *base; 15047404757SYong Wu struct device *smi_common_dev; /* common or sub-common dev */ 1513c8f4ad8SHonghui Zhang const struct mtk_smi_larb_gen *larb_gen; 1523c8f4ad8SHonghui Zhang int larbid; 153cc8bbe1aSYong Wu u32 *mmu; 1548d2c749eSYong Wu unsigned char *bank; 155cc8bbe1aSYong Wu }; 156cc8bbe1aSYong Wu 157cc8bbe1aSYong Wu static int 158cc8bbe1aSYong Wu mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) 159cc8bbe1aSYong Wu { 160cc8bbe1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 1611ee9feb2SYong Wu struct mtk_smi_larb_iommu *larb_mmu = data; 162cc8bbe1aSYong Wu unsigned int i; 163cc8bbe1aSYong Wu 164ec2da07cSYong Wu for (i = 0; i < MTK_LARB_NR_MAX; i++) { 1651ee9feb2SYong Wu if (dev == larb_mmu[i].dev) { 166ec2da07cSYong Wu larb->larbid = i; 1671ee9feb2SYong Wu larb->mmu = &larb_mmu[i].mmu; 1688d2c749eSYong Wu larb->bank = larb_mmu[i].bank; 169cc8bbe1aSYong Wu return 0; 170cc8bbe1aSYong Wu } 171cc8bbe1aSYong Wu } 172cc8bbe1aSYong Wu return -ENODEV; 173cc8bbe1aSYong Wu } 174cc8bbe1aSYong Wu 175534e0ad2SYong Wu static void 176534e0ad2SYong Wu mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) 177e6dec923SYong Wu { 178534e0ad2SYong Wu /* Do nothing as the iommu is always enabled. */ 179e6dec923SYong Wu } 180e6dec923SYong Wu 181534e0ad2SYong Wu static const struct component_ops mtk_smi_larb_component_ops = { 182534e0ad2SYong Wu .bind = mtk_smi_larb_bind, 183534e0ad2SYong Wu .unbind = mtk_smi_larb_unbind, 184534e0ad2SYong Wu }; 185a8529f3bSFabien Parent 1863c8f4ad8SHonghui Zhang static void mtk_smi_larb_config_port_gen1(struct device *dev) 1873c8f4ad8SHonghui Zhang { 1883c8f4ad8SHonghui Zhang struct mtk_smi_larb *larb = dev_get_drvdata(dev); 1893c8f4ad8SHonghui Zhang const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 1903c8f4ad8SHonghui Zhang struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); 1913c8f4ad8SHonghui Zhang int i, m4u_port_id, larb_port_num; 1923c8f4ad8SHonghui Zhang u32 sec_con_val, reg_val; 1933c8f4ad8SHonghui Zhang 1943c8f4ad8SHonghui Zhang m4u_port_id = larb_gen->port_in_larb[larb->larbid]; 1953c8f4ad8SHonghui Zhang larb_port_num = larb_gen->port_in_larb[larb->larbid + 1] 1963c8f4ad8SHonghui Zhang - larb_gen->port_in_larb[larb->larbid]; 1973c8f4ad8SHonghui Zhang 1983c8f4ad8SHonghui Zhang for (i = 0; i < larb_port_num; i++, m4u_port_id++) { 1993c8f4ad8SHonghui Zhang if (*larb->mmu & BIT(i)) { 2003c8f4ad8SHonghui Zhang /* bit[port + 3] controls the virtual or physical */ 2013c8f4ad8SHonghui Zhang sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id); 2023c8f4ad8SHonghui Zhang } else { 2033c8f4ad8SHonghui Zhang /* do not need to enable m4u for this port */ 2043c8f4ad8SHonghui Zhang continue; 2053c8f4ad8SHonghui Zhang } 2063c8f4ad8SHonghui Zhang reg_val = readl(common->smi_ao_base 2073c8f4ad8SHonghui Zhang + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 2083c8f4ad8SHonghui Zhang reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); 2093c8f4ad8SHonghui Zhang reg_val |= sec_con_val; 2103c8f4ad8SHonghui Zhang reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); 2113c8f4ad8SHonghui Zhang writel(reg_val, 2123c8f4ad8SHonghui Zhang common->smi_ao_base 2133c8f4ad8SHonghui Zhang + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 2143c8f4ad8SHonghui Zhang } 2153c8f4ad8SHonghui Zhang } 2163c8f4ad8SHonghui Zhang 217534e0ad2SYong Wu static void mtk_smi_larb_config_port_mt8167(struct device *dev) 218cc8bbe1aSYong Wu { 219534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 220534e0ad2SYong Wu 221534e0ad2SYong Wu writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); 222cc8bbe1aSYong Wu } 223cc8bbe1aSYong Wu 224534e0ad2SYong Wu static void mtk_smi_larb_config_port_mt8173(struct device *dev) 225534e0ad2SYong Wu { 226534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 227cc8bbe1aSYong Wu 228534e0ad2SYong Wu writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN); 229534e0ad2SYong Wu } 2303c8f4ad8SHonghui Zhang 231534e0ad2SYong Wu static void mtk_smi_larb_config_port_gen2_general(struct device *dev) 232534e0ad2SYong Wu { 233534e0ad2SYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 234fe6dd2a4SYong Wu u32 reg, flags_general = larb->larb_gen->flags_general; 235383a44aeSYong Wu const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL; 236534e0ad2SYong Wu int i; 237534e0ad2SYong Wu 238534e0ad2SYong Wu if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) 239534e0ad2SYong Wu return; 240534e0ad2SYong Wu 241fe6dd2a4SYong Wu if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) { 242fe6dd2a4SYong Wu reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON); 243fe6dd2a4SYong Wu reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK; 244fe6dd2a4SYong Wu reg |= SMI_LARB_THRT_RD_NU_LMT; 245fe6dd2a4SYong Wu writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON); 246fe6dd2a4SYong Wu } 247fe6dd2a4SYong Wu 248fe6dd2a4SYong Wu if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG)) 249fe6dd2a4SYong Wu writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); 250fe6dd2a4SYong Wu 251fe6dd2a4SYong Wu for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) 252fe6dd2a4SYong Wu writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); 253fe6dd2a4SYong Wu 254534e0ad2SYong Wu for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { 255534e0ad2SYong Wu reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); 256534e0ad2SYong Wu reg |= F_MMU_EN; 257534e0ad2SYong Wu reg |= BANK_SEL(larb->bank[i]); 258534e0ad2SYong Wu writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); 259534e0ad2SYong Wu } 260534e0ad2SYong Wu } 261a8529f3bSFabien Parent 262fe6dd2a4SYong Wu static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = { 263fe6dd2a4SYong Wu [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */ 264fe6dd2a4SYong Wu [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */ 265fe6dd2a4SYong Wu [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, /* ... */ 266fe6dd2a4SYong Wu [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,}, 267fe6dd2a4SYong Wu [4] = {0x06, 0x01, 0x17, 0x06, 0x0a,}, 268fe6dd2a4SYong Wu [5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,}, 269fe6dd2a4SYong Wu [6] = {0x06, 0x01, 0x06, 0x0a,}, 270fe6dd2a4SYong Wu [7] = {0x0c, 0x0c, 0x12,}, 271fe6dd2a4SYong Wu [8] = {0x0c, 0x0c, 0x12,}, 272fe6dd2a4SYong Wu [9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a, 273fe6dd2a4SYong Wu 0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,}, 274fe6dd2a4SYong Wu [10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10, 275fe6dd2a4SYong Wu 0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d, 276fe6dd2a4SYong Wu 0x0d, 0x06, 0x10, 0x10,}, 277fe6dd2a4SYong Wu [11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,}, 278fe6dd2a4SYong Wu [12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,}, 279fe6dd2a4SYong Wu [13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,}, 280fe6dd2a4SYong Wu [14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01, 281fe6dd2a4SYong Wu 0x01, 0x02, 0x02, 0x08, 0x02,}, 282fe6dd2a4SYong Wu [15] = {}, 283fe6dd2a4SYong Wu [16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a, 284fe6dd2a4SYong Wu 0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,}, 285fe6dd2a4SYong Wu [17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 286fe6dd2a4SYong Wu [18] = {0x12, 0x06, 0x12, 0x06,}, 287fe6dd2a4SYong Wu [19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 288fe6dd2a4SYong Wu 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 289fe6dd2a4SYong Wu 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 290fe6dd2a4SYong Wu [20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 291fe6dd2a4SYong Wu 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 292fe6dd2a4SYong Wu 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 293fe6dd2a4SYong Wu [21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 294fe6dd2a4SYong Wu [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 295fe6dd2a4SYong Wu [23] = {0x18, 0x01,}, 296fe6dd2a4SYong Wu [24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01, 297fe6dd2a4SYong Wu 0x01, 0x01,}, 298fe6dd2a4SYong Wu [25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 299fe6dd2a4SYong Wu 0x02, 0x01,}, 300fe6dd2a4SYong Wu [26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 301fe6dd2a4SYong Wu 0x02, 0x01,}, 302fe6dd2a4SYong Wu [27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 303fe6dd2a4SYong Wu 0x02, 0x01,}, 304fe6dd2a4SYong Wu [28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 305fe6dd2a4SYong Wu }; 306fe6dd2a4SYong Wu 3073c8f4ad8SHonghui Zhang static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { 3083c8f4ad8SHonghui Zhang .port_in_larb = { 3093c8f4ad8SHonghui Zhang LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 3103c8f4ad8SHonghui Zhang LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 3113c8f4ad8SHonghui Zhang }, 3123c8f4ad8SHonghui Zhang .config_port = mtk_smi_larb_config_port_gen1, 3133c8f4ad8SHonghui Zhang }; 3143c8f4ad8SHonghui Zhang 315e6dec923SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { 3162e9b0908SYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 3172e9b0908SYong Wu .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ 318e6dec923SYong Wu }; 319e6dec923SYong Wu 320fc492f33SMing-Fan Chen static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { 321fc492f33SMing-Fan Chen .config_port = mtk_smi_larb_config_port_gen2_general, 322fc492f33SMing-Fan Chen .larb_direct_to_common_mask = 323fc492f33SMing-Fan Chen BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), 324fc492f33SMing-Fan Chen /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ 325fc492f33SMing-Fan Chen }; 326fc492f33SMing-Fan Chen 327534e0ad2SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = { 328534e0ad2SYong Wu /* mt8167 do not need the port in larb */ 329534e0ad2SYong Wu .config_port = mtk_smi_larb_config_port_mt8167, 330534e0ad2SYong Wu }; 331534e0ad2SYong Wu 332534e0ad2SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { 333534e0ad2SYong Wu /* mt8173 do not need the port in larb */ 334534e0ad2SYong Wu .config_port = mtk_smi_larb_config_port_mt8173, 335534e0ad2SYong Wu }; 336534e0ad2SYong Wu 337907ba6a1SYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { 338907ba6a1SYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 339907ba6a1SYong Wu .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), 340907ba6a1SYong Wu /* IPU0 | IPU1 | CCU */ 341907ba6a1SYong Wu }; 342907ba6a1SYong Wu 34386a010bfSYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = { 34486a010bfSYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 34586a010bfSYong Wu .flags_general = MTK_SMI_FLAG_SLEEP_CTL, 34686a010bfSYong Wu }; 34786a010bfSYong Wu 34802c02ddcSYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { 34902c02ddcSYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 35002c02ddcSYong Wu }; 35102c02ddcSYong Wu 352cc4f9dcdSYong Wu static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = { 353cc4f9dcdSYong Wu .config_port = mtk_smi_larb_config_port_gen2_general, 35412fbfd66SAngeloGioacchino Del Regno .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG | 35512fbfd66SAngeloGioacchino Del Regno MTK_SMI_FLAG_SLEEP_CTL, 356fe6dd2a4SYong Wu .ostd = mtk_smi_larb_mt8195_ostd, 357cc4f9dcdSYong Wu }; 358cc4f9dcdSYong Wu 3593c8f4ad8SHonghui Zhang static const struct of_device_id mtk_smi_larb_of_ids[] = { 360534e0ad2SYong Wu {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701}, 361534e0ad2SYong Wu {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712}, 362534e0ad2SYong Wu {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779}, 363534e0ad2SYong Wu {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167}, 364534e0ad2SYong Wu {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173}, 365534e0ad2SYong Wu {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, 36686a010bfSYong Wu {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186}, 367534e0ad2SYong Wu {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, 368cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195}, 3693c8f4ad8SHonghui Zhang {} 3703c8f4ad8SHonghui Zhang }; 3713c8f4ad8SHonghui Zhang 3728956500eSYong Wu static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb) 3738956500eSYong Wu { 3748956500eSYong Wu int ret; 3758956500eSYong Wu u32 tmp; 3768956500eSYong Wu 3778956500eSYong Wu writel_relaxed(SLP_PROT_EN, larb->base + SMI_LARB_SLP_CON); 3788956500eSYong Wu ret = readl_poll_timeout_atomic(larb->base + SMI_LARB_SLP_CON, 3798956500eSYong Wu tmp, !!(tmp & SLP_PROT_RDY), 10, 1000); 3808956500eSYong Wu if (ret) { 3818956500eSYong Wu /* TODO: Reset this larb if it fails here. */ 3828956500eSYong Wu dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp); 3838956500eSYong Wu } 3848956500eSYong Wu return ret; 3858956500eSYong Wu } 3868956500eSYong Wu 3878956500eSYong Wu static void mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb *larb) 3888956500eSYong Wu { 3898956500eSYong Wu writel_relaxed(0, larb->base + SMI_LARB_SLP_CON); 3908956500eSYong Wu } 3918956500eSYong Wu 39247404757SYong Wu static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev) 39347404757SYong Wu { 39447404757SYong Wu struct platform_device *smi_com_pdev; 39547404757SYong Wu struct device_node *smi_com_node; 39647404757SYong Wu struct device *smi_com_dev; 39747404757SYong Wu struct device_link *link; 39847404757SYong Wu 39947404757SYong Wu smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); 40047404757SYong Wu if (!smi_com_node) 40147404757SYong Wu return -EINVAL; 40247404757SYong Wu 40347404757SYong Wu smi_com_pdev = of_find_device_by_node(smi_com_node); 40447404757SYong Wu of_node_put(smi_com_node); 40547404757SYong Wu if (smi_com_pdev) { 40647404757SYong Wu /* smi common is the supplier, Make sure it is ready before */ 407*038ae37cSMiaoqian Lin if (!platform_get_drvdata(smi_com_pdev)) { 408*038ae37cSMiaoqian Lin put_device(&smi_com_pdev->dev); 40947404757SYong Wu return -EPROBE_DEFER; 410*038ae37cSMiaoqian Lin } 41147404757SYong Wu smi_com_dev = &smi_com_pdev->dev; 41247404757SYong Wu link = device_link_add(dev, smi_com_dev, 41347404757SYong Wu DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 41447404757SYong Wu if (!link) { 41547404757SYong Wu dev_err(dev, "Unable to link smi-common dev\n"); 416*038ae37cSMiaoqian Lin put_device(&smi_com_pdev->dev); 41747404757SYong Wu return -ENODEV; 41847404757SYong Wu } 41947404757SYong Wu *com_dev = smi_com_dev; 42047404757SYong Wu } else { 42147404757SYong Wu dev_err(dev, "Failed to get the smi_common device\n"); 42247404757SYong Wu return -EINVAL; 42347404757SYong Wu } 42447404757SYong Wu return 0; 42547404757SYong Wu } 42647404757SYong Wu 4270e14917cSYong Wu static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi, 4280e14917cSYong Wu const char * const clks[], 4290e14917cSYong Wu unsigned int clk_nr_required, 4300e14917cSYong Wu unsigned int clk_nr_optional) 4310e14917cSYong Wu { 4320e14917cSYong Wu int i, ret; 4330e14917cSYong Wu 4340e14917cSYong Wu for (i = 0; i < clk_nr_required; i++) 4350e14917cSYong Wu smi->clks[i].id = clks[i]; 4360e14917cSYong Wu ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks); 4370e14917cSYong Wu if (ret) 4380e14917cSYong Wu return ret; 4390e14917cSYong Wu 4400e14917cSYong Wu for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++) 4410e14917cSYong Wu smi->clks[i].id = clks[i]; 4420e14917cSYong Wu ret = devm_clk_bulk_get_optional(dev, clk_nr_optional, 4430e14917cSYong Wu smi->clks + clk_nr_required); 4440e14917cSYong Wu smi->clk_num = clk_nr_required + clk_nr_optional; 4450e14917cSYong Wu return ret; 4460e14917cSYong Wu } 4470e14917cSYong Wu 448cc8bbe1aSYong Wu static int mtk_smi_larb_probe(struct platform_device *pdev) 449cc8bbe1aSYong Wu { 450cc8bbe1aSYong Wu struct mtk_smi_larb *larb; 451cc8bbe1aSYong Wu struct device *dev = &pdev->dev; 4520e14917cSYong Wu int ret; 453cc8bbe1aSYong Wu 454cc8bbe1aSYong Wu larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); 455cc8bbe1aSYong Wu if (!larb) 456cc8bbe1aSYong Wu return -ENOMEM; 457cc8bbe1aSYong Wu 45875487860SHonghui Zhang larb->larb_gen = of_device_get_match_data(dev); 459912fea8bSYong Wu larb->base = devm_platform_ioremap_resource(pdev, 0); 460cc8bbe1aSYong Wu if (IS_ERR(larb->base)) 461cc8bbe1aSYong Wu return PTR_ERR(larb->base); 462cc8bbe1aSYong Wu 4630e14917cSYong Wu ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks, 4640e14917cSYong Wu MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR); 4650e14917cSYong Wu if (ret) 4660e14917cSYong Wu return ret; 467cc8bbe1aSYong Wu 468cc8bbe1aSYong Wu larb->smi.dev = dev; 469cc8bbe1aSYong Wu 47047404757SYong Wu ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev); 47147404757SYong Wu if (ret < 0) 47247404757SYong Wu return ret; 473cc8bbe1aSYong Wu 474cc8bbe1aSYong Wu pm_runtime_enable(dev); 475cc8bbe1aSYong Wu platform_set_drvdata(pdev, larb); 47630b869e7SYong Wu ret = component_add(dev, &mtk_smi_larb_component_ops); 47730b869e7SYong Wu if (ret) 47830b869e7SYong Wu goto err_pm_disable; 47930b869e7SYong Wu return 0; 48030b869e7SYong Wu 48130b869e7SYong Wu err_pm_disable: 48230b869e7SYong Wu pm_runtime_disable(dev); 48330b869e7SYong Wu device_link_remove(dev, larb->smi_common_dev); 48430b869e7SYong Wu return ret; 485cc8bbe1aSYong Wu } 486cc8bbe1aSYong Wu 487cc8bbe1aSYong Wu static int mtk_smi_larb_remove(struct platform_device *pdev) 488cc8bbe1aSYong Wu { 4896ce2c05bSYong Wu struct mtk_smi_larb *larb = platform_get_drvdata(pdev); 4906ce2c05bSYong Wu 4916ce2c05bSYong Wu device_link_remove(&pdev->dev, larb->smi_common_dev); 492cc8bbe1aSYong Wu pm_runtime_disable(&pdev->dev); 493cc8bbe1aSYong Wu component_del(&pdev->dev, &mtk_smi_larb_component_ops); 494cc8bbe1aSYong Wu return 0; 495cc8bbe1aSYong Wu } 496cc8bbe1aSYong Wu 4974f0a1a1aSYong Wu static int __maybe_unused mtk_smi_larb_resume(struct device *dev) 4984f0a1a1aSYong Wu { 4994f0a1a1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 5004f0a1a1aSYong Wu const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 5014f0a1a1aSYong Wu int ret; 5024f0a1a1aSYong Wu 5030e14917cSYong Wu ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks); 504a6945f45SYong Wu if (ret) 5054f0a1a1aSYong Wu return ret; 5064f0a1a1aSYong Wu 5078956500eSYong Wu if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) 5088956500eSYong Wu mtk_smi_larb_sleep_ctrl_disable(larb); 5098956500eSYong Wu 5104f0a1a1aSYong Wu /* Configure the basic setting for this larb */ 5114f0a1a1aSYong Wu larb_gen->config_port(dev); 5124f0a1a1aSYong Wu 5134f0a1a1aSYong Wu return 0; 5144f0a1a1aSYong Wu } 5154f0a1a1aSYong Wu 5164f0a1a1aSYong Wu static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) 5174f0a1a1aSYong Wu { 5184f0a1a1aSYong Wu struct mtk_smi_larb *larb = dev_get_drvdata(dev); 5198956500eSYong Wu int ret; 5208956500eSYong Wu 5218956500eSYong Wu if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) { 5228956500eSYong Wu ret = mtk_smi_larb_sleep_ctrl_enable(larb); 5238956500eSYong Wu if (ret) 5248956500eSYong Wu return ret; 5258956500eSYong Wu } 5264f0a1a1aSYong Wu 5270e14917cSYong Wu clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks); 5284f0a1a1aSYong Wu return 0; 5294f0a1a1aSYong Wu } 5304f0a1a1aSYong Wu 5314f0a1a1aSYong Wu static const struct dev_pm_ops smi_larb_pm_ops = { 5324f0a1a1aSYong Wu SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL) 533fb03082aSYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 534fb03082aSYong Wu pm_runtime_force_resume) 5354f0a1a1aSYong Wu }; 5364f0a1a1aSYong Wu 537cc8bbe1aSYong Wu static struct platform_driver mtk_smi_larb_driver = { 538cc8bbe1aSYong Wu .probe = mtk_smi_larb_probe, 539cc8bbe1aSYong Wu .remove = mtk_smi_larb_remove, 540cc8bbe1aSYong Wu .driver = { 541cc8bbe1aSYong Wu .name = "mtk-smi-larb", 542cc8bbe1aSYong Wu .of_match_table = mtk_smi_larb_of_ids, 5434f0a1a1aSYong Wu .pm = &smi_larb_pm_ops, 544cc8bbe1aSYong Wu } 545cc8bbe1aSYong Wu }; 546cc8bbe1aSYong Wu 547431e9cabSYong Wu static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = { 548431e9cabSYong Wu {SMI_L1LEN, 0xb}, 549431e9cabSYong Wu {SMI_M4U_TH, 0xe100e10}, 550431e9cabSYong Wu {SMI_FIFO_TH1, 0x506090a}, 551431e9cabSYong Wu {SMI_FIFO_TH2, 0x506090a}, 552431e9cabSYong Wu {SMI_DCM, 0x4f1}, 553431e9cabSYong Wu {SMI_DUMMY, 0x1}, 554431e9cabSYong Wu }; 555431e9cabSYong Wu 55642d42c76SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_gen1 = { 557a5c18986SYong Wu .type = MTK_SMI_GEN1, 55842d42c76SYong Wu }; 55942d42c76SYong Wu 56042d42c76SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { 561a5c18986SYong Wu .type = MTK_SMI_GEN2, 56242d42c76SYong Wu }; 56342d42c76SYong Wu 564fc492f33SMing-Fan Chen static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { 565a5c18986SYong Wu .type = MTK_SMI_GEN2, 566fc492f33SMing-Fan Chen .has_gals = true, 567fc492f33SMing-Fan Chen .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | 568fc492f33SMing-Fan Chen F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), 569fc492f33SMing-Fan Chen }; 570fc492f33SMing-Fan Chen 571907ba6a1SYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { 572a5c18986SYong Wu .type = MTK_SMI_GEN2, 573907ba6a1SYong Wu .has_gals = true, 574567e58cfSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 575567e58cfSYong Wu F_MMU1_LARB(7), 576907ba6a1SYong Wu }; 577907ba6a1SYong Wu 57886a010bfSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = { 57986a010bfSYong Wu .type = MTK_SMI_GEN2, 58086a010bfSYong Wu .has_gals = true, 58186a010bfSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7), 58286a010bfSYong Wu }; 58386a010bfSYong Wu 58402c02ddcSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { 585a5c18986SYong Wu .type = MTK_SMI_GEN2, 58602c02ddcSYong Wu .has_gals = true, 58702c02ddcSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 58802c02ddcSYong Wu F_MMU1_LARB(6), 58902c02ddcSYong Wu }; 59002c02ddcSYong Wu 591cc4f9dcdSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = { 592cc4f9dcdSYong Wu .type = MTK_SMI_GEN2, 593cc4f9dcdSYong Wu .has_gals = true, 594cc4f9dcdSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) | 595cc4f9dcdSYong Wu F_MMU1_LARB(7), 596431e9cabSYong Wu .init = mtk_smi_common_mt8195_init, 597cc4f9dcdSYong Wu }; 598cc4f9dcdSYong Wu 599cc4f9dcdSYong Wu static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = { 600cc4f9dcdSYong Wu .type = MTK_SMI_GEN2, 601cc4f9dcdSYong Wu .has_gals = true, 602cc4f9dcdSYong Wu .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7), 603431e9cabSYong Wu .init = mtk_smi_common_mt8195_init, 604cc4f9dcdSYong Wu }; 605cc4f9dcdSYong Wu 606cc4f9dcdSYong Wu static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = { 607cc4f9dcdSYong Wu .type = MTK_SMI_GEN2_SUB_COMM, 608cc4f9dcdSYong Wu .has_gals = true, 609cc4f9dcdSYong Wu }; 610cc4f9dcdSYong Wu 6113c8f4ad8SHonghui Zhang static const struct of_device_id mtk_smi_common_of_ids[] = { 612534e0ad2SYong Wu {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1}, 613534e0ad2SYong Wu {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2}, 614534e0ad2SYong Wu {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779}, 615534e0ad2SYong Wu {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2}, 616534e0ad2SYong Wu {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2}, 617534e0ad2SYong Wu {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183}, 61886a010bfSYong Wu {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186}, 619534e0ad2SYong Wu {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, 620cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, 621cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, 622cc4f9dcdSYong Wu {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195}, 6233c8f4ad8SHonghui Zhang {} 6243c8f4ad8SHonghui Zhang }; 6253c8f4ad8SHonghui Zhang 626cc8bbe1aSYong Wu static int mtk_smi_common_probe(struct platform_device *pdev) 627cc8bbe1aSYong Wu { 628cc8bbe1aSYong Wu struct device *dev = &pdev->dev; 629cc8bbe1aSYong Wu struct mtk_smi *common; 6300e14917cSYong Wu int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR; 631cc8bbe1aSYong Wu 632cc8bbe1aSYong Wu common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); 633cc8bbe1aSYong Wu if (!common) 634cc8bbe1aSYong Wu return -ENOMEM; 635cc8bbe1aSYong Wu common->dev = dev; 63642d42c76SYong Wu common->plat = of_device_get_match_data(dev); 637cc8bbe1aSYong Wu 6383e4f74e0SYong Wu if (common->plat->has_gals) { 6393e4f74e0SYong Wu if (common->plat->type == MTK_SMI_GEN2) 6400e14917cSYong Wu clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR; 6413e4f74e0SYong Wu else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 6423e4f74e0SYong Wu clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR; 6433e4f74e0SYong Wu } 6440e14917cSYong Wu ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0); 6450e14917cSYong Wu if (ret) 6460e14917cSYong Wu return ret; 64764fea74aSYong Wu 6483c8f4ad8SHonghui Zhang /* 6493c8f4ad8SHonghui Zhang * for mtk smi gen 1, we need to get the ao(always on) base to config 6503c8f4ad8SHonghui Zhang * m4u port, and we need to enable the aync clock for transform the smi 6513c8f4ad8SHonghui Zhang * clock into emi clock domain, but for mtk smi gen2, there's no smi ao 6523c8f4ad8SHonghui Zhang * base. 6533c8f4ad8SHonghui Zhang */ 654a5c18986SYong Wu if (common->plat->type == MTK_SMI_GEN1) { 655912fea8bSYong Wu common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0); 6563c8f4ad8SHonghui Zhang if (IS_ERR(common->smi_ao_base)) 6573c8f4ad8SHonghui Zhang return PTR_ERR(common->smi_ao_base); 6583c8f4ad8SHonghui Zhang 6593c8f4ad8SHonghui Zhang common->clk_async = devm_clk_get(dev, "async"); 6603c8f4ad8SHonghui Zhang if (IS_ERR(common->clk_async)) 6613c8f4ad8SHonghui Zhang return PTR_ERR(common->clk_async); 6623c8f4ad8SHonghui Zhang 66346cc815dSArvind Yadav ret = clk_prepare_enable(common->clk_async); 66446cc815dSArvind Yadav if (ret) 66546cc815dSArvind Yadav return ret; 666567e58cfSYong Wu } else { 667912fea8bSYong Wu common->base = devm_platform_ioremap_resource(pdev, 0); 668567e58cfSYong Wu if (IS_ERR(common->base)) 669567e58cfSYong Wu return PTR_ERR(common->base); 6703c8f4ad8SHonghui Zhang } 67147404757SYong Wu 67247404757SYong Wu /* link its smi-common if this is smi-sub-common */ 67347404757SYong Wu if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) { 67447404757SYong Wu ret = mtk_smi_device_link_common(dev, &common->smi_common_dev); 67547404757SYong Wu if (ret < 0) 67647404757SYong Wu return ret; 67747404757SYong Wu } 67847404757SYong Wu 679cc8bbe1aSYong Wu pm_runtime_enable(dev); 680cc8bbe1aSYong Wu platform_set_drvdata(pdev, common); 681cc8bbe1aSYong Wu return 0; 682cc8bbe1aSYong Wu } 683cc8bbe1aSYong Wu 684cc8bbe1aSYong Wu static int mtk_smi_common_remove(struct platform_device *pdev) 685cc8bbe1aSYong Wu { 68647404757SYong Wu struct mtk_smi *common = dev_get_drvdata(&pdev->dev); 68747404757SYong Wu 68847404757SYong Wu if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 68947404757SYong Wu device_link_remove(&pdev->dev, common->smi_common_dev); 690cc8bbe1aSYong Wu pm_runtime_disable(&pdev->dev); 691cc8bbe1aSYong Wu return 0; 692cc8bbe1aSYong Wu } 693cc8bbe1aSYong Wu 6944f0a1a1aSYong Wu static int __maybe_unused mtk_smi_common_resume(struct device *dev) 6954f0a1a1aSYong Wu { 6964f0a1a1aSYong Wu struct mtk_smi *common = dev_get_drvdata(dev); 697431e9cabSYong Wu const struct mtk_smi_reg_pair *init = common->plat->init; 698431e9cabSYong Wu u32 bus_sel = common->plat->bus_sel; /* default is 0 */ 699431e9cabSYong Wu int ret, i; 7004f0a1a1aSYong Wu 7010e14917cSYong Wu ret = clk_bulk_prepare_enable(common->clk_num, common->clks); 7020e14917cSYong Wu if (ret) 7034f0a1a1aSYong Wu return ret; 704567e58cfSYong Wu 705431e9cabSYong Wu if (common->plat->type != MTK_SMI_GEN2) 706431e9cabSYong Wu return 0; 707431e9cabSYong Wu 708431e9cabSYong Wu for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++) 709431e9cabSYong Wu writel_relaxed(init[i].value, common->base + init[i].offset); 710431e9cabSYong Wu 711567e58cfSYong Wu writel(bus_sel, common->base + SMI_BUS_SEL); 7124f0a1a1aSYong Wu return 0; 7134f0a1a1aSYong Wu } 7144f0a1a1aSYong Wu 7154f0a1a1aSYong Wu static int __maybe_unused mtk_smi_common_suspend(struct device *dev) 7164f0a1a1aSYong Wu { 7174f0a1a1aSYong Wu struct mtk_smi *common = dev_get_drvdata(dev); 7184f0a1a1aSYong Wu 7190e14917cSYong Wu clk_bulk_disable_unprepare(common->clk_num, common->clks); 7204f0a1a1aSYong Wu return 0; 7214f0a1a1aSYong Wu } 7224f0a1a1aSYong Wu 7234f0a1a1aSYong Wu static const struct dev_pm_ops smi_common_pm_ops = { 7244f0a1a1aSYong Wu SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL) 725fb03082aSYong Wu SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 726fb03082aSYong Wu pm_runtime_force_resume) 7274f0a1a1aSYong Wu }; 7284f0a1a1aSYong Wu 729cc8bbe1aSYong Wu static struct platform_driver mtk_smi_common_driver = { 730cc8bbe1aSYong Wu .probe = mtk_smi_common_probe, 731cc8bbe1aSYong Wu .remove = mtk_smi_common_remove, 732cc8bbe1aSYong Wu .driver = { 733cc8bbe1aSYong Wu .name = "mtk-smi-common", 734cc8bbe1aSYong Wu .of_match_table = mtk_smi_common_of_ids, 7354f0a1a1aSYong Wu .pm = &smi_common_pm_ops, 736cc8bbe1aSYong Wu } 737cc8bbe1aSYong Wu }; 738cc8bbe1aSYong Wu 73918212031SYong Wu static struct platform_driver * const smidrivers[] = { 74018212031SYong Wu &mtk_smi_common_driver, 74118212031SYong Wu &mtk_smi_larb_driver, 74218212031SYong Wu }; 74318212031SYong Wu 744cc8bbe1aSYong Wu static int __init mtk_smi_init(void) 745cc8bbe1aSYong Wu { 74618212031SYong Wu return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 747cc8bbe1aSYong Wu } 7484f608d38SYong Wu module_init(mtk_smi_init); 74950fc8d92SYong Wu 75050fc8d92SYong Wu static void __exit mtk_smi_exit(void) 75150fc8d92SYong Wu { 75250fc8d92SYong Wu platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 75350fc8d92SYong Wu } 75450fc8d92SYong Wu module_exit(mtk_smi_exit); 75550fc8d92SYong Wu 75650fc8d92SYong Wu MODULE_DESCRIPTION("MediaTek SMI driver"); 75750fc8d92SYong Wu MODULE_LICENSE("GPL v2"); 758