1 /* 2 * JZ4780 NAND/external memory controller (NEMC) 3 * 4 * Copyright (c) 2015 Imagination Technologies 5 * Author: Alex Smith <alex@alex-smith.me.uk> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published 9 * by the Free Software Foundation. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/init.h> 14 #include <linux/math64.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_device.h> 18 #include <linux/of_platform.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/spinlock.h> 22 23 #include <linux/jz4780-nemc.h> 24 25 #define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4)) 26 #define NEMC_NFCSR 0x50 27 28 #define NEMC_SMCR_SMT BIT(0) 29 #define NEMC_SMCR_BW_SHIFT 6 30 #define NEMC_SMCR_BW_MASK (0x3 << NEMC_SMCR_BW_SHIFT) 31 #define NEMC_SMCR_BW_8 (0 << 6) 32 #define NEMC_SMCR_TAS_SHIFT 8 33 #define NEMC_SMCR_TAS_MASK (0xf << NEMC_SMCR_TAS_SHIFT) 34 #define NEMC_SMCR_TAH_SHIFT 12 35 #define NEMC_SMCR_TAH_MASK (0xf << NEMC_SMCR_TAH_SHIFT) 36 #define NEMC_SMCR_TBP_SHIFT 16 37 #define NEMC_SMCR_TBP_MASK (0xf << NEMC_SMCR_TBP_SHIFT) 38 #define NEMC_SMCR_TAW_SHIFT 20 39 #define NEMC_SMCR_TAW_MASK (0xf << NEMC_SMCR_TAW_SHIFT) 40 #define NEMC_SMCR_TSTRV_SHIFT 24 41 #define NEMC_SMCR_TSTRV_MASK (0x3f << NEMC_SMCR_TSTRV_SHIFT) 42 43 #define NEMC_NFCSR_NFEn(n) BIT(((n) - 1) << 1) 44 #define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1) 45 #define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1) 46 47 struct jz_soc_info { 48 u8 tas_tah_cycles_max; 49 }; 50 51 struct jz4780_nemc { 52 spinlock_t lock; 53 struct device *dev; 54 const struct jz_soc_info *soc_info; 55 void __iomem *base; 56 struct clk *clk; 57 uint32_t clk_period; 58 unsigned long banks_present; 59 }; 60 61 /** 62 * jz4780_nemc_num_banks() - count the number of banks referenced by a device 63 * @dev: device to count banks for, must be a child of the NEMC. 64 * 65 * Return: The number of unique NEMC banks referred to by the specified NEMC 66 * child device. Unique here means that a device that references the same bank 67 * multiple times in the its "reg" property will only count once. 68 */ 69 unsigned int jz4780_nemc_num_banks(struct device *dev) 70 { 71 const __be32 *prop; 72 unsigned int bank, count = 0; 73 unsigned long referenced = 0; 74 int i = 0; 75 76 while ((prop = of_get_address(dev->of_node, i++, NULL, NULL))) { 77 bank = of_read_number(prop, 1); 78 if (!(referenced & BIT(bank))) { 79 referenced |= BIT(bank); 80 count++; 81 } 82 } 83 84 return count; 85 } 86 EXPORT_SYMBOL(jz4780_nemc_num_banks); 87 88 /** 89 * jz4780_nemc_set_type() - set the type of device connected to a bank 90 * @dev: child device of the NEMC. 91 * @bank: bank number to configure. 92 * @type: type of device connected to the bank. 93 */ 94 void jz4780_nemc_set_type(struct device *dev, unsigned int bank, 95 enum jz4780_nemc_bank_type type) 96 { 97 struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent); 98 uint32_t nfcsr; 99 100 nfcsr = readl(nemc->base + NEMC_NFCSR); 101 102 /* TODO: Support toggle NAND devices. */ 103 switch (type) { 104 case JZ4780_NEMC_BANK_SRAM: 105 nfcsr &= ~(NEMC_NFCSR_TNFEn(bank) | NEMC_NFCSR_NFEn(bank)); 106 break; 107 case JZ4780_NEMC_BANK_NAND: 108 nfcsr &= ~NEMC_NFCSR_TNFEn(bank); 109 nfcsr |= NEMC_NFCSR_NFEn(bank); 110 break; 111 } 112 113 writel(nfcsr, nemc->base + NEMC_NFCSR); 114 } 115 EXPORT_SYMBOL(jz4780_nemc_set_type); 116 117 /** 118 * jz4780_nemc_assert() - (de-)assert a NAND device's chip enable pin 119 * @dev: child device of the NEMC. 120 * @bank: bank number of device. 121 * @assert: whether the chip enable pin should be asserted. 122 * 123 * (De-)asserts the chip enable pin for the NAND device connected to the 124 * specified bank. 125 */ 126 void jz4780_nemc_assert(struct device *dev, unsigned int bank, bool assert) 127 { 128 struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent); 129 uint32_t nfcsr; 130 131 nfcsr = readl(nemc->base + NEMC_NFCSR); 132 133 if (assert) 134 nfcsr |= NEMC_NFCSR_NFCEn(bank); 135 else 136 nfcsr &= ~NEMC_NFCSR_NFCEn(bank); 137 138 writel(nfcsr, nemc->base + NEMC_NFCSR); 139 } 140 EXPORT_SYMBOL(jz4780_nemc_assert); 141 142 static uint32_t jz4780_nemc_clk_period(struct jz4780_nemc *nemc) 143 { 144 unsigned long rate; 145 146 rate = clk_get_rate(nemc->clk); 147 if (!rate) 148 return 0; 149 150 /* Return in picoseconds. */ 151 return div64_ul(1000000000000ull, rate); 152 } 153 154 static uint32_t jz4780_nemc_ns_to_cycles(struct jz4780_nemc *nemc, uint32_t ns) 155 { 156 return ((ns * 1000) + nemc->clk_period - 1) / nemc->clk_period; 157 } 158 159 static bool jz4780_nemc_configure_bank(struct jz4780_nemc *nemc, 160 unsigned int bank, 161 struct device_node *node) 162 { 163 uint32_t smcr, val, cycles; 164 165 /* 166 * Conversion of tBP and tAW cycle counts to values supported by the 167 * hardware (round up to the next supported value). 168 */ 169 static const u8 convert_tBP_tAW[] = { 170 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 171 172 /* 11 - 12 -> 12 cycles */ 173 11, 11, 174 175 /* 13 - 15 -> 15 cycles */ 176 12, 12, 12, 177 178 /* 16 - 20 -> 20 cycles */ 179 13, 13, 13, 13, 13, 180 181 /* 21 - 25 -> 25 cycles */ 182 14, 14, 14, 14, 14, 183 184 /* 26 - 31 -> 31 cycles */ 185 15, 15, 15, 15, 15, 15 186 }; 187 188 smcr = readl(nemc->base + NEMC_SMCRn(bank)); 189 smcr &= ~NEMC_SMCR_SMT; 190 191 if (!of_property_read_u32(node, "ingenic,nemc-bus-width", &val)) { 192 smcr &= ~NEMC_SMCR_BW_MASK; 193 switch (val) { 194 case 8: 195 smcr |= NEMC_SMCR_BW_8; 196 break; 197 default: 198 /* 199 * Earlier SoCs support a 16 bit bus width (the 4780 200 * does not), until those are properly supported, error. 201 */ 202 dev_err(nemc->dev, "unsupported bus width: %u\n", val); 203 return false; 204 } 205 } 206 207 if (of_property_read_u32(node, "ingenic,nemc-tAS", &val) == 0) { 208 smcr &= ~NEMC_SMCR_TAS_MASK; 209 cycles = jz4780_nemc_ns_to_cycles(nemc, val); 210 if (cycles > nemc->soc_info->tas_tah_cycles_max) { 211 dev_err(nemc->dev, "tAS %u is too high (%u cycles)\n", 212 val, cycles); 213 return false; 214 } 215 216 smcr |= cycles << NEMC_SMCR_TAS_SHIFT; 217 } 218 219 if (of_property_read_u32(node, "ingenic,nemc-tAH", &val) == 0) { 220 smcr &= ~NEMC_SMCR_TAH_MASK; 221 cycles = jz4780_nemc_ns_to_cycles(nemc, val); 222 if (cycles > nemc->soc_info->tas_tah_cycles_max) { 223 dev_err(nemc->dev, "tAH %u is too high (%u cycles)\n", 224 val, cycles); 225 return false; 226 } 227 228 smcr |= cycles << NEMC_SMCR_TAH_SHIFT; 229 } 230 231 if (of_property_read_u32(node, "ingenic,nemc-tBP", &val) == 0) { 232 smcr &= ~NEMC_SMCR_TBP_MASK; 233 cycles = jz4780_nemc_ns_to_cycles(nemc, val); 234 if (cycles > 31) { 235 dev_err(nemc->dev, "tBP %u is too high (%u cycles)\n", 236 val, cycles); 237 return false; 238 } 239 240 smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TBP_SHIFT; 241 } 242 243 if (of_property_read_u32(node, "ingenic,nemc-tAW", &val) == 0) { 244 smcr &= ~NEMC_SMCR_TAW_MASK; 245 cycles = jz4780_nemc_ns_to_cycles(nemc, val); 246 if (cycles > 31) { 247 dev_err(nemc->dev, "tAW %u is too high (%u cycles)\n", 248 val, cycles); 249 return false; 250 } 251 252 smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TAW_SHIFT; 253 } 254 255 if (of_property_read_u32(node, "ingenic,nemc-tSTRV", &val) == 0) { 256 smcr &= ~NEMC_SMCR_TSTRV_MASK; 257 cycles = jz4780_nemc_ns_to_cycles(nemc, val); 258 if (cycles > 63) { 259 dev_err(nemc->dev, "tSTRV %u is too high (%u cycles)\n", 260 val, cycles); 261 return false; 262 } 263 264 smcr |= cycles << NEMC_SMCR_TSTRV_SHIFT; 265 } 266 267 writel(smcr, nemc->base + NEMC_SMCRn(bank)); 268 return true; 269 } 270 271 static int jz4780_nemc_probe(struct platform_device *pdev) 272 { 273 struct device *dev = &pdev->dev; 274 struct jz4780_nemc *nemc; 275 struct resource *res; 276 struct device_node *child; 277 const __be32 *prop; 278 unsigned int bank; 279 unsigned long referenced; 280 int i, ret; 281 282 nemc = devm_kzalloc(dev, sizeof(*nemc), GFP_KERNEL); 283 if (!nemc) 284 return -ENOMEM; 285 286 nemc->soc_info = device_get_match_data(dev); 287 if (!nemc->soc_info) 288 return -EINVAL; 289 290 spin_lock_init(&nemc->lock); 291 nemc->dev = dev; 292 293 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 294 nemc->base = devm_ioremap_resource(dev, res); 295 if (IS_ERR(nemc->base)) { 296 dev_err(dev, "failed to get I/O memory\n"); 297 return PTR_ERR(nemc->base); 298 } 299 300 writel(0, nemc->base + NEMC_NFCSR); 301 302 nemc->clk = devm_clk_get(dev, NULL); 303 if (IS_ERR(nemc->clk)) { 304 dev_err(dev, "failed to get clock\n"); 305 return PTR_ERR(nemc->clk); 306 } 307 308 ret = clk_prepare_enable(nemc->clk); 309 if (ret) { 310 dev_err(dev, "failed to enable clock: %d\n", ret); 311 return ret; 312 } 313 314 nemc->clk_period = jz4780_nemc_clk_period(nemc); 315 if (!nemc->clk_period) { 316 dev_err(dev, "failed to calculate clock period\n"); 317 clk_disable_unprepare(nemc->clk); 318 return -EINVAL; 319 } 320 321 /* 322 * Iterate over child devices, check that they do not conflict with 323 * each other, and register child devices for them. If a child device 324 * has invalid properties, it is ignored and no platform device is 325 * registered for it. 326 */ 327 for_each_child_of_node(nemc->dev->of_node, child) { 328 referenced = 0; 329 i = 0; 330 while ((prop = of_get_address(child, i++, NULL, NULL))) { 331 bank = of_read_number(prop, 1); 332 if (bank < 1 || bank >= JZ4780_NEMC_NUM_BANKS) { 333 dev_err(nemc->dev, 334 "%pOF requests invalid bank %u\n", 335 child, bank); 336 337 /* Will continue the outer loop below. */ 338 referenced = 0; 339 break; 340 } 341 342 referenced |= BIT(bank); 343 } 344 345 if (!referenced) { 346 dev_err(nemc->dev, "%pOF has no addresses\n", 347 child); 348 continue; 349 } else if (nemc->banks_present & referenced) { 350 dev_err(nemc->dev, "%pOF conflicts with another node\n", 351 child); 352 continue; 353 } 354 355 /* Configure bank parameters. */ 356 for_each_set_bit(bank, &referenced, JZ4780_NEMC_NUM_BANKS) { 357 if (!jz4780_nemc_configure_bank(nemc, bank, child)) { 358 referenced = 0; 359 break; 360 } 361 } 362 363 if (referenced) { 364 if (of_platform_device_create(child, NULL, nemc->dev)) 365 nemc->banks_present |= referenced; 366 } 367 } 368 369 platform_set_drvdata(pdev, nemc); 370 dev_info(dev, "JZ4780 NEMC initialised\n"); 371 return 0; 372 } 373 374 static int jz4780_nemc_remove(struct platform_device *pdev) 375 { 376 struct jz4780_nemc *nemc = platform_get_drvdata(pdev); 377 378 clk_disable_unprepare(nemc->clk); 379 return 0; 380 } 381 382 static const struct jz_soc_info jz4740_soc_info = { 383 .tas_tah_cycles_max = 7, 384 }; 385 386 static const struct jz_soc_info jz4780_soc_info = { 387 .tas_tah_cycles_max = 15, 388 }; 389 390 static const struct of_device_id jz4780_nemc_dt_match[] = { 391 { .compatible = "ingenic,jz4740-nemc", .data = &jz4740_soc_info, }, 392 { .compatible = "ingenic,jz4780-nemc", .data = &jz4780_soc_info, }, 393 {}, 394 }; 395 396 static struct platform_driver jz4780_nemc_driver = { 397 .probe = jz4780_nemc_probe, 398 .remove = jz4780_nemc_remove, 399 .driver = { 400 .name = "jz4780-nemc", 401 .of_match_table = of_match_ptr(jz4780_nemc_dt_match), 402 }, 403 }; 404 405 static int __init jz4780_nemc_init(void) 406 { 407 return platform_driver_register(&jz4780_nemc_driver); 408 } 409 subsys_initcall(jz4780_nemc_init); 410