1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * JZ4780 NAND/external memory controller (NEMC) 4 * 5 * Copyright (c) 2015 Imagination Technologies 6 * Author: Alex Smith <alex@alex-smith.me.uk> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/init.h> 11 #include <linux/math64.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/of_device.h> 15 #include <linux/of_platform.h> 16 #include <linux/platform_device.h> 17 #include <linux/slab.h> 18 #include <linux/spinlock.h> 19 20 #include <linux/jz4780-nemc.h> 21 22 #define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4)) 23 #define NEMC_NFCSR 0x50 24 25 #define NEMC_SMCR_SMT BIT(0) 26 #define NEMC_SMCR_BW_SHIFT 6 27 #define NEMC_SMCR_BW_MASK (0x3 << NEMC_SMCR_BW_SHIFT) 28 #define NEMC_SMCR_BW_8 (0 << 6) 29 #define NEMC_SMCR_TAS_SHIFT 8 30 #define NEMC_SMCR_TAS_MASK (0xf << NEMC_SMCR_TAS_SHIFT) 31 #define NEMC_SMCR_TAH_SHIFT 12 32 #define NEMC_SMCR_TAH_MASK (0xf << NEMC_SMCR_TAH_SHIFT) 33 #define NEMC_SMCR_TBP_SHIFT 16 34 #define NEMC_SMCR_TBP_MASK (0xf << NEMC_SMCR_TBP_SHIFT) 35 #define NEMC_SMCR_TAW_SHIFT 20 36 #define NEMC_SMCR_TAW_MASK (0xf << NEMC_SMCR_TAW_SHIFT) 37 #define NEMC_SMCR_TSTRV_SHIFT 24 38 #define NEMC_SMCR_TSTRV_MASK (0x3f << NEMC_SMCR_TSTRV_SHIFT) 39 40 #define NEMC_NFCSR_NFEn(n) BIT(((n) - 1) << 1) 41 #define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1) 42 #define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1) 43 44 struct jz4780_nemc { 45 spinlock_t lock; 46 struct device *dev; 47 void __iomem *base; 48 struct clk *clk; 49 uint32_t clk_period; 50 unsigned long banks_present; 51 }; 52 53 /** 54 * jz4780_nemc_num_banks() - count the number of banks referenced by a device 55 * @dev: device to count banks for, must be a child of the NEMC. 56 * 57 * Return: The number of unique NEMC banks referred to by the specified NEMC 58 * child device. Unique here means that a device that references the same bank 59 * multiple times in the its "reg" property will only count once. 60 */ 61 unsigned int jz4780_nemc_num_banks(struct device *dev) 62 { 63 const __be32 *prop; 64 unsigned int bank, count = 0; 65 unsigned long referenced = 0; 66 int i = 0; 67 68 while ((prop = of_get_address(dev->of_node, i++, NULL, NULL))) { 69 bank = of_read_number(prop, 1); 70 if (!(referenced & BIT(bank))) { 71 referenced |= BIT(bank); 72 count++; 73 } 74 } 75 76 return count; 77 } 78 EXPORT_SYMBOL(jz4780_nemc_num_banks); 79 80 /** 81 * jz4780_nemc_set_type() - set the type of device connected to a bank 82 * @dev: child device of the NEMC. 83 * @bank: bank number to configure. 84 * @type: type of device connected to the bank. 85 */ 86 void jz4780_nemc_set_type(struct device *dev, unsigned int bank, 87 enum jz4780_nemc_bank_type type) 88 { 89 struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent); 90 uint32_t nfcsr; 91 92 nfcsr = readl(nemc->base + NEMC_NFCSR); 93 94 /* TODO: Support toggle NAND devices. */ 95 switch (type) { 96 case JZ4780_NEMC_BANK_SRAM: 97 nfcsr &= ~(NEMC_NFCSR_TNFEn(bank) | NEMC_NFCSR_NFEn(bank)); 98 break; 99 case JZ4780_NEMC_BANK_NAND: 100 nfcsr &= ~NEMC_NFCSR_TNFEn(bank); 101 nfcsr |= NEMC_NFCSR_NFEn(bank); 102 break; 103 } 104 105 writel(nfcsr, nemc->base + NEMC_NFCSR); 106 } 107 EXPORT_SYMBOL(jz4780_nemc_set_type); 108 109 /** 110 * jz4780_nemc_assert() - (de-)assert a NAND device's chip enable pin 111 * @dev: child device of the NEMC. 112 * @bank: bank number of device. 113 * @assert: whether the chip enable pin should be asserted. 114 * 115 * (De-)asserts the chip enable pin for the NAND device connected to the 116 * specified bank. 117 */ 118 void jz4780_nemc_assert(struct device *dev, unsigned int bank, bool assert) 119 { 120 struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent); 121 uint32_t nfcsr; 122 123 nfcsr = readl(nemc->base + NEMC_NFCSR); 124 125 if (assert) 126 nfcsr |= NEMC_NFCSR_NFCEn(bank); 127 else 128 nfcsr &= ~NEMC_NFCSR_NFCEn(bank); 129 130 writel(nfcsr, nemc->base + NEMC_NFCSR); 131 } 132 EXPORT_SYMBOL(jz4780_nemc_assert); 133 134 static uint32_t jz4780_nemc_clk_period(struct jz4780_nemc *nemc) 135 { 136 unsigned long rate; 137 138 rate = clk_get_rate(nemc->clk); 139 if (!rate) 140 return 0; 141 142 /* Return in picoseconds. */ 143 return div64_ul(1000000000000ull, rate); 144 } 145 146 static uint32_t jz4780_nemc_ns_to_cycles(struct jz4780_nemc *nemc, uint32_t ns) 147 { 148 return ((ns * 1000) + nemc->clk_period - 1) / nemc->clk_period; 149 } 150 151 static bool jz4780_nemc_configure_bank(struct jz4780_nemc *nemc, 152 unsigned int bank, 153 struct device_node *node) 154 { 155 uint32_t smcr, val, cycles; 156 157 /* 158 * Conversion of tBP and tAW cycle counts to values supported by the 159 * hardware (round up to the next supported value). 160 */ 161 static const uint32_t convert_tBP_tAW[] = { 162 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 163 164 /* 11 - 12 -> 12 cycles */ 165 11, 11, 166 167 /* 13 - 15 -> 15 cycles */ 168 12, 12, 12, 169 170 /* 16 - 20 -> 20 cycles */ 171 13, 13, 13, 13, 13, 172 173 /* 21 - 25 -> 25 cycles */ 174 14, 14, 14, 14, 14, 175 176 /* 26 - 31 -> 31 cycles */ 177 15, 15, 15, 15, 15, 15 178 }; 179 180 smcr = readl(nemc->base + NEMC_SMCRn(bank)); 181 smcr &= ~NEMC_SMCR_SMT; 182 183 if (!of_property_read_u32(node, "ingenic,nemc-bus-width", &val)) { 184 smcr &= ~NEMC_SMCR_BW_MASK; 185 switch (val) { 186 case 8: 187 smcr |= NEMC_SMCR_BW_8; 188 break; 189 default: 190 /* 191 * Earlier SoCs support a 16 bit bus width (the 4780 192 * does not), until those are properly supported, error. 193 */ 194 dev_err(nemc->dev, "unsupported bus width: %u\n", val); 195 return false; 196 } 197 } 198 199 if (of_property_read_u32(node, "ingenic,nemc-tAS", &val) == 0) { 200 smcr &= ~NEMC_SMCR_TAS_MASK; 201 cycles = jz4780_nemc_ns_to_cycles(nemc, val); 202 if (cycles > 15) { 203 dev_err(nemc->dev, "tAS %u is too high (%u cycles)\n", 204 val, cycles); 205 return false; 206 } 207 208 smcr |= cycles << NEMC_SMCR_TAS_SHIFT; 209 } 210 211 if (of_property_read_u32(node, "ingenic,nemc-tAH", &val) == 0) { 212 smcr &= ~NEMC_SMCR_TAH_MASK; 213 cycles = jz4780_nemc_ns_to_cycles(nemc, val); 214 if (cycles > 15) { 215 dev_err(nemc->dev, "tAH %u is too high (%u cycles)\n", 216 val, cycles); 217 return false; 218 } 219 220 smcr |= cycles << NEMC_SMCR_TAH_SHIFT; 221 } 222 223 if (of_property_read_u32(node, "ingenic,nemc-tBP", &val) == 0) { 224 smcr &= ~NEMC_SMCR_TBP_MASK; 225 cycles = jz4780_nemc_ns_to_cycles(nemc, val); 226 if (cycles > 31) { 227 dev_err(nemc->dev, "tBP %u is too high (%u cycles)\n", 228 val, cycles); 229 return false; 230 } 231 232 smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TBP_SHIFT; 233 } 234 235 if (of_property_read_u32(node, "ingenic,nemc-tAW", &val) == 0) { 236 smcr &= ~NEMC_SMCR_TAW_MASK; 237 cycles = jz4780_nemc_ns_to_cycles(nemc, val); 238 if (cycles > 31) { 239 dev_err(nemc->dev, "tAW %u is too high (%u cycles)\n", 240 val, cycles); 241 return false; 242 } 243 244 smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TAW_SHIFT; 245 } 246 247 if (of_property_read_u32(node, "ingenic,nemc-tSTRV", &val) == 0) { 248 smcr &= ~NEMC_SMCR_TSTRV_MASK; 249 cycles = jz4780_nemc_ns_to_cycles(nemc, val); 250 if (cycles > 63) { 251 dev_err(nemc->dev, "tSTRV %u is too high (%u cycles)\n", 252 val, cycles); 253 return false; 254 } 255 256 smcr |= cycles << NEMC_SMCR_TSTRV_SHIFT; 257 } 258 259 writel(smcr, nemc->base + NEMC_SMCRn(bank)); 260 return true; 261 } 262 263 static int jz4780_nemc_probe(struct platform_device *pdev) 264 { 265 struct device *dev = &pdev->dev; 266 struct jz4780_nemc *nemc; 267 struct resource *res; 268 struct device_node *child; 269 const __be32 *prop; 270 unsigned int bank; 271 unsigned long referenced; 272 int i, ret; 273 274 nemc = devm_kzalloc(dev, sizeof(*nemc), GFP_KERNEL); 275 if (!nemc) 276 return -ENOMEM; 277 278 spin_lock_init(&nemc->lock); 279 nemc->dev = dev; 280 281 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 282 nemc->base = devm_ioremap_resource(dev, res); 283 if (IS_ERR(nemc->base)) { 284 dev_err(dev, "failed to get I/O memory\n"); 285 return PTR_ERR(nemc->base); 286 } 287 288 writel(0, nemc->base + NEMC_NFCSR); 289 290 nemc->clk = devm_clk_get(dev, NULL); 291 if (IS_ERR(nemc->clk)) { 292 dev_err(dev, "failed to get clock\n"); 293 return PTR_ERR(nemc->clk); 294 } 295 296 ret = clk_prepare_enable(nemc->clk); 297 if (ret) { 298 dev_err(dev, "failed to enable clock: %d\n", ret); 299 return ret; 300 } 301 302 nemc->clk_period = jz4780_nemc_clk_period(nemc); 303 if (!nemc->clk_period) { 304 dev_err(dev, "failed to calculate clock period\n"); 305 clk_disable_unprepare(nemc->clk); 306 return -EINVAL; 307 } 308 309 /* 310 * Iterate over child devices, check that they do not conflict with 311 * each other, and register child devices for them. If a child device 312 * has invalid properties, it is ignored and no platform device is 313 * registered for it. 314 */ 315 for_each_child_of_node(nemc->dev->of_node, child) { 316 referenced = 0; 317 i = 0; 318 while ((prop = of_get_address(child, i++, NULL, NULL))) { 319 bank = of_read_number(prop, 1); 320 if (bank < 1 || bank >= JZ4780_NEMC_NUM_BANKS) { 321 dev_err(nemc->dev, 322 "%pOF requests invalid bank %u\n", 323 child, bank); 324 325 /* Will continue the outer loop below. */ 326 referenced = 0; 327 break; 328 } 329 330 referenced |= BIT(bank); 331 } 332 333 if (!referenced) { 334 dev_err(nemc->dev, "%pOF has no addresses\n", 335 child); 336 continue; 337 } else if (nemc->banks_present & referenced) { 338 dev_err(nemc->dev, "%pOF conflicts with another node\n", 339 child); 340 continue; 341 } 342 343 /* Configure bank parameters. */ 344 for_each_set_bit(bank, &referenced, JZ4780_NEMC_NUM_BANKS) { 345 if (!jz4780_nemc_configure_bank(nemc, bank, child)) { 346 referenced = 0; 347 break; 348 } 349 } 350 351 if (referenced) { 352 if (of_platform_device_create(child, NULL, nemc->dev)) 353 nemc->banks_present |= referenced; 354 } 355 } 356 357 platform_set_drvdata(pdev, nemc); 358 dev_info(dev, "JZ4780 NEMC initialised\n"); 359 return 0; 360 } 361 362 static int jz4780_nemc_remove(struct platform_device *pdev) 363 { 364 struct jz4780_nemc *nemc = platform_get_drvdata(pdev); 365 366 clk_disable_unprepare(nemc->clk); 367 return 0; 368 } 369 370 static const struct of_device_id jz4780_nemc_dt_match[] = { 371 { .compatible = "ingenic,jz4780-nemc" }, 372 {}, 373 }; 374 375 static struct platform_driver jz4780_nemc_driver = { 376 .probe = jz4780_nemc_probe, 377 .remove = jz4780_nemc_remove, 378 .driver = { 379 .name = "jz4780-nemc", 380 .of_match_table = of_match_ptr(jz4780_nemc_dt_match), 381 }, 382 }; 383 384 static int __init jz4780_nemc_init(void) 385 { 386 return platform_driver_register(&jz4780_nemc_driver); 387 } 388 subsys_initcall(jz4780_nemc_init); 389