1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Definitions for DDR memories based on JEDEC specs 4 * 5 * Copyright (C) 2012 Texas Instruments, Inc. 6 * 7 * Aneesh V <aneesh@ti.com> 8 */ 9 #ifndef __JEDEC_DDR_H 10 #define __JEDEC_DDR_H 11 12 #include <linux/types.h> 13 14 /* DDR Densities */ 15 #define DDR_DENSITY_64Mb 1 16 #define DDR_DENSITY_128Mb 2 17 #define DDR_DENSITY_256Mb 3 18 #define DDR_DENSITY_512Mb 4 19 #define DDR_DENSITY_1Gb 5 20 #define DDR_DENSITY_2Gb 6 21 #define DDR_DENSITY_4Gb 7 22 #define DDR_DENSITY_8Gb 8 23 #define DDR_DENSITY_16Gb 9 24 #define DDR_DENSITY_32Gb 10 25 26 /* DDR type */ 27 #define DDR_TYPE_DDR2 1 28 #define DDR_TYPE_DDR3 2 29 #define DDR_TYPE_LPDDR2_S4 3 30 #define DDR_TYPE_LPDDR2_S2 4 31 #define DDR_TYPE_LPDDR2_NVM 5 32 #define DDR_TYPE_LPDDR3 6 33 34 /* DDR IO width */ 35 #define DDR_IO_WIDTH_4 1 36 #define DDR_IO_WIDTH_8 2 37 #define DDR_IO_WIDTH_16 3 38 #define DDR_IO_WIDTH_32 4 39 40 /* Number of Row bits */ 41 #define R9 9 42 #define R10 10 43 #define R11 11 44 #define R12 12 45 #define R13 13 46 #define R14 14 47 #define R15 15 48 #define R16 16 49 50 /* Number of Column bits */ 51 #define C7 7 52 #define C8 8 53 #define C9 9 54 #define C10 10 55 #define C11 11 56 #define C12 12 57 58 /* Number of Banks */ 59 #define B1 0 60 #define B2 1 61 #define B4 2 62 #define B8 3 63 64 /* Refresh rate in nano-seconds */ 65 #define T_REFI_15_6 15600 66 #define T_REFI_7_8 7800 67 #define T_REFI_3_9 3900 68 69 /* tRFC values */ 70 #define T_RFC_90 90000 71 #define T_RFC_110 110000 72 #define T_RFC_130 130000 73 #define T_RFC_160 160000 74 #define T_RFC_210 210000 75 #define T_RFC_300 300000 76 #define T_RFC_350 350000 77 78 /* Mode register numbers */ 79 #define DDR_MR0 0 80 #define DDR_MR1 1 81 #define DDR_MR2 2 82 #define DDR_MR3 3 83 #define DDR_MR4 4 84 #define DDR_MR5 5 85 #define DDR_MR6 6 86 #define DDR_MR7 7 87 #define DDR_MR8 8 88 #define DDR_MR9 9 89 #define DDR_MR10 10 90 #define DDR_MR11 11 91 #define DDR_MR16 16 92 #define DDR_MR17 17 93 #define DDR_MR18 18 94 95 /* 96 * LPDDR2 related defines 97 */ 98 99 /* MR4 register fields */ 100 #define MR4_SDRAM_REF_RATE_SHIFT 0 101 #define MR4_SDRAM_REF_RATE_MASK 7 102 #define MR4_TUF_SHIFT 7 103 #define MR4_TUF_MASK (1 << 7) 104 105 /* MR4 SDRAM Refresh Rate field values */ 106 #define SDRAM_TEMP_NOMINAL 0x3 107 #define SDRAM_TEMP_RESERVED_4 0x4 108 #define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5 109 #define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6 110 #define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7 111 112 #define NUM_DDR_ADDR_TABLE_ENTRIES 11 113 #define NUM_DDR_TIMING_TABLE_ENTRIES 4 114 115 /* Structure for DDR addressing info from the JEDEC spec */ 116 struct lpddr2_addressing { 117 u32 num_banks; 118 u32 tREFI_ns; 119 u32 tRFCab_ps; 120 }; 121 122 /* 123 * Structure for timings from the LPDDR2 datasheet 124 * All parameters are in pico seconds(ps) unless explicitly indicated 125 * with a suffix like tRAS_max_ns below 126 */ 127 struct lpddr2_timings { 128 u32 max_freq; 129 u32 min_freq; 130 u32 tRPab; 131 u32 tRCD; 132 u32 tWR; 133 u32 tRAS_min; 134 u32 tRRD; 135 u32 tWTR; 136 u32 tXP; 137 u32 tRTP; 138 u32 tCKESR; 139 u32 tDQSCK_max; 140 u32 tDQSCK_max_derated; 141 u32 tFAW; 142 u32 tZQCS; 143 u32 tZQCL; 144 u32 tZQinit; 145 u32 tRAS_max_ns; 146 }; 147 148 /* 149 * Min value for some parameters in terms of number of tCK cycles(nCK) 150 * Please set to zero parameters that are not valid for a given memory 151 * type 152 */ 153 struct lpddr2_min_tck { 154 u32 tRPab; 155 u32 tRCD; 156 u32 tWR; 157 u32 tRASmin; 158 u32 tRRD; 159 u32 tWTR; 160 u32 tXP; 161 u32 tRTP; 162 u32 tCKE; 163 u32 tCKESR; 164 u32 tFAW; 165 }; 166 167 extern const struct lpddr2_addressing 168 lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES]; 169 extern const struct lpddr2_timings 170 lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES]; 171 extern const struct lpddr2_min_tck lpddr2_jedec_min_tck; 172 173 /* 174 * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields. 175 * All parameters are in pico seconds(ps) excluding max_freq, min_freq which 176 * are in Hz. 177 */ 178 struct lpddr3_timings { 179 u32 max_freq; 180 u32 min_freq; 181 u32 tRFC; 182 u32 tRRD; 183 u32 tRPab; 184 u32 tRPpb; 185 u32 tRCD; 186 u32 tRC; 187 u32 tRAS; 188 u32 tWTR; 189 u32 tWR; 190 u32 tRTP; 191 u32 tW2W_C2C; 192 u32 tR2R_C2C; 193 u32 tWL; 194 u32 tDQSCK; 195 u32 tRL; 196 u32 tFAW; 197 u32 tXSR; 198 u32 tXP; 199 u32 tCKE; 200 u32 tCKESR; 201 u32 tMRD; 202 }; 203 204 /* 205 * Min value for some parameters in terms of number of tCK cycles(nCK) 206 * Please set to zero parameters that are not valid for a given memory 207 * type 208 */ 209 struct lpddr3_min_tck { 210 u32 tRFC; 211 u32 tRRD; 212 u32 tRPab; 213 u32 tRPpb; 214 u32 tRCD; 215 u32 tRC; 216 u32 tRAS; 217 u32 tWTR; 218 u32 tWR; 219 u32 tRTP; 220 u32 tW2W_C2C; 221 u32 tR2R_C2C; 222 u32 tWL; 223 u32 tDQSCK; 224 u32 tRL; 225 u32 tFAW; 226 u32 tXSR; 227 u32 tXP; 228 u32 tCKE; 229 u32 tCKESR; 230 u32 tMRD; 231 }; 232 233 #endif /* __JEDEC_DDR_H */ 234