1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Definitions for DDR memories based on JEDEC specs 4 * 5 * Copyright (C) 2012 Texas Instruments, Inc. 6 * 7 * Aneesh V <aneesh@ti.com> 8 */ 9 #ifndef __JEDEC_DDR_H 10 #define __JEDEC_DDR_H 11 12 #include <linux/types.h> 13 14 /* DDR Densities */ 15 #define DDR_DENSITY_64Mb 1 16 #define DDR_DENSITY_128Mb 2 17 #define DDR_DENSITY_256Mb 3 18 #define DDR_DENSITY_512Mb 4 19 #define DDR_DENSITY_1Gb 5 20 #define DDR_DENSITY_2Gb 6 21 #define DDR_DENSITY_4Gb 7 22 #define DDR_DENSITY_8Gb 8 23 #define DDR_DENSITY_16Gb 9 24 #define DDR_DENSITY_32Gb 10 25 26 /* DDR type */ 27 #define DDR_TYPE_DDR2 1 28 #define DDR_TYPE_DDR3 2 29 #define DDR_TYPE_LPDDR2_S4 3 30 #define DDR_TYPE_LPDDR2_S2 4 31 #define DDR_TYPE_LPDDR2_NVM 5 32 #define DDR_TYPE_LPDDR3 6 33 34 /* DDR IO width */ 35 #define DDR_IO_WIDTH_4 1 36 #define DDR_IO_WIDTH_8 2 37 #define DDR_IO_WIDTH_16 3 38 #define DDR_IO_WIDTH_32 4 39 40 /* Number of Row bits */ 41 #define R9 9 42 #define R10 10 43 #define R11 11 44 #define R12 12 45 #define R13 13 46 #define R14 14 47 #define R15 15 48 #define R16 16 49 50 /* Number of Column bits */ 51 #define C7 7 52 #define C8 8 53 #define C9 9 54 #define C10 10 55 #define C11 11 56 #define C12 12 57 58 /* Number of Banks */ 59 #define B1 0 60 #define B2 1 61 #define B4 2 62 #define B8 3 63 64 /* Refresh rate in nano-seconds */ 65 #define T_REFI_15_6 15600 66 #define T_REFI_7_8 7800 67 #define T_REFI_3_9 3900 68 69 /* tRFC values */ 70 #define T_RFC_90 90000 71 #define T_RFC_110 110000 72 #define T_RFC_130 130000 73 #define T_RFC_160 160000 74 #define T_RFC_210 210000 75 #define T_RFC_300 300000 76 #define T_RFC_350 350000 77 78 /* Mode register numbers */ 79 #define DDR_MR0 0 80 #define DDR_MR1 1 81 #define DDR_MR2 2 82 #define DDR_MR3 3 83 #define DDR_MR4 4 84 #define DDR_MR5 5 85 #define DDR_MR6 6 86 #define DDR_MR7 7 87 #define DDR_MR8 8 88 #define DDR_MR9 9 89 #define DDR_MR10 10 90 #define DDR_MR11 11 91 #define DDR_MR16 16 92 #define DDR_MR17 17 93 #define DDR_MR18 18 94 95 /* 96 * LPDDR2 related defines 97 */ 98 99 /* MR4 register fields */ 100 #define MR4_SDRAM_REF_RATE_SHIFT 0 101 #define MR4_SDRAM_REF_RATE_MASK 7 102 #define MR4_TUF_SHIFT 7 103 #define MR4_TUF_MASK (1 << 7) 104 105 /* MR4 SDRAM Refresh Rate field values */ 106 #define SDRAM_TEMP_NOMINAL 0x3 107 #define SDRAM_TEMP_RESERVED_4 0x4 108 #define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5 109 #define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6 110 #define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7 111 112 #define NUM_DDR_ADDR_TABLE_ENTRIES 11 113 #define NUM_DDR_TIMING_TABLE_ENTRIES 4 114 115 #define LPDDR2_MANID_SAMSUNG 1 116 #define LPDDR2_MANID_QIMONDA 2 117 #define LPDDR2_MANID_ELPIDA 3 118 #define LPDDR2_MANID_ETRON 4 119 #define LPDDR2_MANID_NANYA 5 120 #define LPDDR2_MANID_HYNIX 6 121 #define LPDDR2_MANID_MOSEL 7 122 #define LPDDR2_MANID_WINBOND 8 123 #define LPDDR2_MANID_ESMT 9 124 #define LPDDR2_MANID_SPANSION 11 125 #define LPDDR2_MANID_SST 12 126 #define LPDDR2_MANID_ZMOS 13 127 #define LPDDR2_MANID_INTEL 14 128 #define LPDDR2_MANID_NUMONYX 254 129 #define LPDDR2_MANID_MICRON 255 130 131 #define LPDDR2_TYPE_S4 0 132 #define LPDDR2_TYPE_S2 1 133 #define LPDDR2_TYPE_NVM 2 134 135 /* Structure for DDR addressing info from the JEDEC spec */ 136 struct lpddr2_addressing { 137 u32 num_banks; 138 u32 tREFI_ns; 139 u32 tRFCab_ps; 140 }; 141 142 /* 143 * Structure for timings from the LPDDR2 datasheet 144 * All parameters are in pico seconds(ps) unless explicitly indicated 145 * with a suffix like tRAS_max_ns below 146 */ 147 struct lpddr2_timings { 148 u32 max_freq; 149 u32 min_freq; 150 u32 tRPab; 151 u32 tRCD; 152 u32 tWR; 153 u32 tRAS_min; 154 u32 tRRD; 155 u32 tWTR; 156 u32 tXP; 157 u32 tRTP; 158 u32 tCKESR; 159 u32 tDQSCK_max; 160 u32 tDQSCK_max_derated; 161 u32 tFAW; 162 u32 tZQCS; 163 u32 tZQCL; 164 u32 tZQinit; 165 u32 tRAS_max_ns; 166 }; 167 168 /* 169 * Min value for some parameters in terms of number of tCK cycles(nCK) 170 * Please set to zero parameters that are not valid for a given memory 171 * type 172 */ 173 struct lpddr2_min_tck { 174 u32 tRPab; 175 u32 tRCD; 176 u32 tWR; 177 u32 tRASmin; 178 u32 tRRD; 179 u32 tWTR; 180 u32 tXP; 181 u32 tRTP; 182 u32 tCKE; 183 u32 tCKESR; 184 u32 tFAW; 185 }; 186 187 extern const struct lpddr2_addressing 188 lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES]; 189 extern const struct lpddr2_timings 190 lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES]; 191 extern const struct lpddr2_min_tck lpddr2_jedec_min_tck; 192 193 /* Structure of MR8 */ 194 union lpddr2_basic_config4 { 195 u32 value; 196 197 struct { 198 unsigned int arch_type : 2; 199 unsigned int density : 4; 200 unsigned int io_width : 2; 201 } __packed; 202 }; 203 204 /* 205 * Structure for information about LPDDR2 chip. All parameters are 206 * matching raw values of standard mode register bitfields or set to 207 * -ENOENT if info unavailable. 208 */ 209 struct lpddr2_info { 210 int arch_type; 211 int density; 212 int io_width; 213 int manufacturer_id; 214 int revision_id1; 215 int revision_id2; 216 }; 217 218 const char *lpddr2_jedec_manufacturer(unsigned int manufacturer_id); 219 220 /* 221 * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields. 222 * All parameters are in pico seconds(ps) excluding max_freq, min_freq which 223 * are in Hz. 224 */ 225 struct lpddr3_timings { 226 u32 max_freq; 227 u32 min_freq; 228 u32 tRFC; 229 u32 tRRD; 230 u32 tRPab; 231 u32 tRPpb; 232 u32 tRCD; 233 u32 tRC; 234 u32 tRAS; 235 u32 tWTR; 236 u32 tWR; 237 u32 tRTP; 238 u32 tW2W_C2C; 239 u32 tR2R_C2C; 240 u32 tWL; 241 u32 tDQSCK; 242 u32 tRL; 243 u32 tFAW; 244 u32 tXSR; 245 u32 tXP; 246 u32 tCKE; 247 u32 tCKESR; 248 u32 tMRD; 249 }; 250 251 /* 252 * Min value for some parameters in terms of number of tCK cycles(nCK) 253 * Please set to zero parameters that are not valid for a given memory 254 * type 255 */ 256 struct lpddr3_min_tck { 257 u32 tRFC; 258 u32 tRRD; 259 u32 tRPab; 260 u32 tRPpb; 261 u32 tRCD; 262 u32 tRC; 263 u32 tRAS; 264 u32 tWTR; 265 u32 tWR; 266 u32 tRTP; 267 u32 tW2W_C2C; 268 u32 tR2R_C2C; 269 u32 tWL; 270 u32 tDQSCK; 271 u32 tRL; 272 u32 tFAW; 273 u32 tXSR; 274 u32 tXP; 275 u32 tCKE; 276 u32 tCKESR; 277 u32 tMRD; 278 }; 279 280 #endif /* __JEDEC_DDR_H */ 281