1 /* 2 * TI AM33XX EMIF PM Assembly Offsets 3 * 4 * Copyright (C) 2016-2017 Texas Instruments Inc. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 #include <linux/ti-emif-sram.h> 16 17 int main(void) 18 { 19 DEFINE(EMIF_SDCFG_VAL_OFFSET, 20 offsetof(struct emif_regs_amx3, emif_sdcfg_val)); 21 DEFINE(EMIF_TIMING1_VAL_OFFSET, 22 offsetof(struct emif_regs_amx3, emif_timing1_val)); 23 DEFINE(EMIF_TIMING2_VAL_OFFSET, 24 offsetof(struct emif_regs_amx3, emif_timing2_val)); 25 DEFINE(EMIF_TIMING3_VAL_OFFSET, 26 offsetof(struct emif_regs_amx3, emif_timing3_val)); 27 DEFINE(EMIF_REF_CTRL_VAL_OFFSET, 28 offsetof(struct emif_regs_amx3, emif_ref_ctrl_val)); 29 DEFINE(EMIF_ZQCFG_VAL_OFFSET, 30 offsetof(struct emif_regs_amx3, emif_zqcfg_val)); 31 DEFINE(EMIF_PMCR_VAL_OFFSET, 32 offsetof(struct emif_regs_amx3, emif_pmcr_val)); 33 DEFINE(EMIF_PMCR_SHDW_VAL_OFFSET, 34 offsetof(struct emif_regs_amx3, emif_pmcr_shdw_val)); 35 DEFINE(EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET, 36 offsetof(struct emif_regs_amx3, emif_rd_wr_level_ramp_ctrl)); 37 DEFINE(EMIF_RD_WR_EXEC_THRESH_OFFSET, 38 offsetof(struct emif_regs_amx3, emif_rd_wr_exec_thresh)); 39 DEFINE(EMIF_COS_CONFIG_OFFSET, 40 offsetof(struct emif_regs_amx3, emif_cos_config)); 41 DEFINE(EMIF_PRIORITY_TO_COS_MAPPING_OFFSET, 42 offsetof(struct emif_regs_amx3, emif_priority_to_cos_mapping)); 43 DEFINE(EMIF_CONNECT_ID_SERV_1_MAP_OFFSET, 44 offsetof(struct emif_regs_amx3, emif_connect_id_serv_1_map)); 45 DEFINE(EMIF_CONNECT_ID_SERV_2_MAP_OFFSET, 46 offsetof(struct emif_regs_amx3, emif_connect_id_serv_2_map)); 47 DEFINE(EMIF_OCP_CONFIG_VAL_OFFSET, 48 offsetof(struct emif_regs_amx3, emif_ocp_config_val)); 49 DEFINE(EMIF_LPDDR2_NVM_TIM_OFFSET, 50 offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim)); 51 DEFINE(EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET, 52 offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim_shdw)); 53 DEFINE(EMIF_DLL_CALIB_CTRL_VAL_OFFSET, 54 offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val)); 55 DEFINE(EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET, 56 offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val_shdw)); 57 DEFINE(EMIF_DDR_PHY_CTLR_1_OFFSET, 58 offsetof(struct emif_regs_amx3, emif_ddr_phy_ctlr_1)); 59 DEFINE(EMIF_EXT_PHY_CTRL_VALS_OFFSET, 60 offsetof(struct emif_regs_amx3, emif_ext_phy_ctrl_vals)); 61 DEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3)); 62 63 BLANK(); 64 65 DEFINE(EMIF_PM_BASE_ADDR_VIRT_OFFSET, 66 offsetof(struct ti_emif_pm_data, ti_emif_base_addr_virt)); 67 DEFINE(EMIF_PM_BASE_ADDR_PHYS_OFFSET, 68 offsetof(struct ti_emif_pm_data, ti_emif_base_addr_phys)); 69 DEFINE(EMIF_PM_CONFIG_OFFSET, 70 offsetof(struct ti_emif_pm_data, ti_emif_sram_config)); 71 DEFINE(EMIF_PM_REGS_VIRT_OFFSET, 72 offsetof(struct ti_emif_pm_data, regs_virt)); 73 DEFINE(EMIF_PM_REGS_PHYS_OFFSET, 74 offsetof(struct ti_emif_pm_data, regs_phys)); 75 DEFINE(EMIF_PM_DATA_SIZE, sizeof(struct ti_emif_pm_data)); 76 77 BLANK(); 78 79 DEFINE(EMIF_PM_SAVE_CONTEXT_OFFSET, 80 offsetof(struct ti_emif_pm_functions, save_context)); 81 DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET, 82 offsetof(struct ti_emif_pm_functions, restore_context)); 83 DEFINE(EMIF_PM_ENTER_SR_OFFSET, 84 offsetof(struct ti_emif_pm_functions, enter_sr)); 85 DEFINE(EMIF_PM_EXIT_SR_OFFSET, 86 offsetof(struct ti_emif_pm_functions, exit_sr)); 87 DEFINE(EMIF_PM_ABORT_SR_OFFSET, 88 offsetof(struct ti_emif_pm_functions, abort_sr)); 89 DEFINE(EMIF_PM_FUNCTIONS_SIZE, sizeof(struct ti_emif_pm_functions)); 90 91 return 0; 92 } 93