1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Memory devices 4# 5 6menuconfig MEMORY 7 bool "Memory Controller drivers" 8 help 9 This option allows to enable specific memory controller drivers, 10 useful mostly on embedded systems. These could be controllers 11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features 12 vary from memory tuning and frequency scaling to enabling 13 access to attached peripherals through memory bus. 14 15if MEMORY 16 17config DDR 18 bool 19 help 20 Data from JEDEC specs for DDR SDRAM memories, 21 particularly the AC timing parameters and addressing 22 information. This data is useful for drivers handling 23 DDR SDRAM controllers. 24 25config ARM_PL172_MPMC 26 tristate "ARM PL172 MPMC driver" 27 depends on ARM_AMBA && OF 28 help 29 This selects the ARM PrimeCell PL172 MultiPort Memory Controller. 30 If you have an embedded system with an AMBA bus and a PL172 31 controller, say Y or M here. 32 33config ATMEL_SDRAMC 34 bool "Atmel (Multi-port DDR-)SDRAM Controller" 35 default y if ARCH_AT91 36 depends on ARCH_AT91 || COMPILE_TEST 37 depends on OF 38 help 39 This driver is for Atmel SDRAM Controller or Atmel Multi-port 40 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs. 41 Starting with the at91sam9g45, this controller supports SDR, DDR and 42 LP-DDR memories. 43 44config ATMEL_EBI 45 bool "Atmel EBI driver" 46 default y if ARCH_AT91 47 depends on ARCH_AT91 || COMPILE_TEST 48 depends on OF 49 select MFD_SYSCON 50 select MFD_ATMEL_SMC 51 help 52 Driver for Atmel EBI controller. 53 Used to configure the EBI (external bus interface) when the device- 54 tree is used. This bus supports NANDs, external ethernet controller, 55 SRAMs, ATA devices, etc. 56 57config BRCMSTB_DPFE 58 bool "Broadcom STB DPFE driver" if COMPILE_TEST 59 default y if ARCH_BRCMSTB 60 depends on ARCH_BRCMSTB || COMPILE_TEST 61 help 62 This driver provides access to the DPFE interface of Broadcom 63 STB SoCs. The firmware running on the DCPU inside the DDR PHY can 64 provide current information about the system's RAM, for instance 65 the DRAM refresh rate. This can be used as an indirect indicator 66 for the DRAM's temperature. Slower refresh rate means cooler RAM, 67 higher refresh rate means hotter RAM. 68 69config BT1_L2_CTL 70 bool "Baikal-T1 CM2 L2-RAM Cache Control Block" 71 depends on MIPS_BAIKAL_T1 || COMPILE_TEST 72 select MFD_SYSCON 73 help 74 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU 75 resides Coherency Manager v2 with embedded 1MB L2-cache. It's 76 possible to tune the L2 cache performance up by setting the data, 77 tags and way-select latencies of RAM access. This driver provides a 78 dt properties-based and sysfs interface for it. 79 80config TI_AEMIF 81 tristate "Texas Instruments AEMIF driver" 82 depends on ARCH_DAVINCI || ARCH_KEYSTONE || COMPILE_TEST 83 depends on OF 84 help 85 This driver is for the AEMIF module available in Texas Instruments 86 SoCs. AEMIF stands for Asynchronous External Memory Interface and 87 is intended to provide a glue-less interface to a variety of 88 asynchronuous memory devices like ASRAM, NOR and NAND memory. A total 89 of 256M bytes of any of these memories can be accessed at a given 90 time via four chip selects with 64M byte access per chip select. 91 92config TI_EMIF 93 tristate "Texas Instruments EMIF driver" 94 depends on ARCH_OMAP2PLUS || COMPILE_TEST 95 select DDR 96 help 97 This driver is for the EMIF module available in Texas Instruments 98 SoCs. EMIF is an SDRAM controller that, based on its revision, 99 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols. 100 This driver takes care of only LPDDR2 memories presently. The 101 functions of the driver includes re-configuring AC timing 102 parameters and other settings during frequency, voltage and 103 temperature changes 104 105config OMAP_GPMC 106 bool "Texas Instruments OMAP SoC GPMC driver" if COMPILE_TEST 107 select GPIOLIB 108 help 109 This driver is for the General Purpose Memory Controller (GPMC) 110 present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows 111 interfacing to a variety of asynchronous as well as synchronous 112 memory drives like NOR, NAND, OneNAND, SRAM. 113 114config OMAP_GPMC_DEBUG 115 bool "Enable GPMC debug output and skip reset of GPMC during init" 116 depends on OMAP_GPMC 117 help 118 Enables verbose debugging mostly to decode the bootloader provided 119 timings. To preserve the bootloader provided timings, the reset 120 of GPMC is skipped during init. Enable this during development to 121 configure devices connected to the GPMC bus. 122 123 NOTE: In addition to matching the register setup with the bootloader 124 you also need to match the GPMC FCLK frequency used by the 125 bootloader or else the GPMC timings won't be identical with the 126 bootloader timings. 127 128config TI_EMIF_SRAM 129 tristate "Texas Instruments EMIF SRAM driver" 130 depends on SOC_AM33XX || SOC_AM43XX || (ARM && COMPILE_TEST) 131 depends on SRAM 132 help 133 This driver is for the EMIF module available on Texas Instruments 134 AM33XX and AM43XX SoCs and is required for PM. Certain parts of 135 the EMIF PM code must run from on-chip SRAM late in the suspend 136 sequence so this driver provides several relocatable PM functions 137 for the SoC PM code to use. 138 139config MVEBU_DEVBUS 140 bool "Marvell EBU Device Bus Controller" 141 default y if PLAT_ORION 142 depends on PLAT_ORION || COMPILE_TEST 143 depends on OF 144 help 145 This driver is for the Device Bus controller available in some 146 Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and 147 Armada 370 and Armada XP. This controller allows to handle flash 148 devices such as NOR, NAND, SRAM, and FPGA. 149 150config FSL_CORENET_CF 151 tristate "Freescale CoreNet Error Reporting" 152 depends on FSL_SOC_BOOKE || COMPILE_TEST 153 help 154 Say Y for reporting of errors from the Freescale CoreNet 155 Coherency Fabric. Errors reported include accesses to 156 physical addresses that mapped by no local access window 157 (LAW) or an invalid LAW, as well as bad cache state that 158 represents a coherency violation. 159 160config FSL_IFC 161 bool "Freescale IFC driver" if COMPILE_TEST 162 depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A || COMPILE_TEST 163 depends on HAS_IOMEM 164 165config JZ4780_NEMC 166 bool "Ingenic JZ4780 SoC NEMC driver" 167 depends on MIPS || COMPILE_TEST 168 depends on HAS_IOMEM && OF 169 help 170 This driver is for the NAND/External Memory Controller (NEMC) in 171 the Ingenic JZ4780. This controller is used to handle external 172 memory devices such as NAND and SRAM. 173 174config MTK_SMI 175 bool "Mediatek SoC Memory Controller driver" if COMPILE_TEST 176 depends on ARCH_MEDIATEK || COMPILE_TEST 177 help 178 This driver is for the Memory Controller module in MediaTek SoCs, 179 mainly help enable/disable iommu and control the power domain and 180 clocks for each local arbiter. 181 182config DA8XX_DDRCTL 183 bool "Texas Instruments da8xx DDR2/mDDR driver" 184 depends on ARCH_DAVINCI_DA8XX || COMPILE_TEST 185 help 186 This driver is for the DDR2/mDDR Memory Controller present on 187 Texas Instruments da8xx SoCs. It's used to tweak various memory 188 controller configuration options. 189 190config PL353_SMC 191 tristate "ARM PL35X Static Memory Controller(SMC) driver" 192 default y if ARM 193 depends on ARM 194 depends on ARM_AMBA || COMPILE_TEST 195 help 196 This driver is for the ARM PL351/PL353 Static Memory 197 Controller(SMC) module. 198 199config RENESAS_RPCIF 200 tristate "Renesas RPC-IF driver" 201 depends on ARCH_RENESAS || COMPILE_TEST 202 select REGMAP_MMIO 203 help 204 This supports Renesas R-Car Gen3 RPC-IF which provides either SPI 205 host or HyperFlash. You'll have to select individual components 206 under the corresponding menu. 207 208config STM32_FMC2_EBI 209 tristate "Support for FMC2 External Bus Interface on STM32MP SoCs" 210 depends on MACH_STM32MP157 || COMPILE_TEST 211 select MFD_SYSCON 212 help 213 Select this option to enable the STM32 FMC2 External Bus Interface 214 controller. This driver configures the transactions with external 215 devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on 216 SOCs containing the FMC2 External Bus Interface. 217 218source "drivers/memory/samsung/Kconfig" 219source "drivers/memory/tegra/Kconfig" 220 221endif 222