1# 2# Memory devices 3# 4 5menuconfig MEMORY 6 bool "Memory Controller drivers" 7 8if MEMORY 9 10config ATMEL_SDRAMC 11 bool "Atmel (Multi-port DDR-)SDRAM Controller" 12 default y 13 depends on ARCH_AT91 && OF 14 help 15 This driver is for Atmel SDRAM Controller or Atmel Multi-port 16 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs. 17 Starting with the at91sam9g45, this controller supports SDR, DDR and 18 LP-DDR memories. 19 20config TI_AEMIF 21 tristate "Texas Instruments AEMIF driver" 22 depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF 23 help 24 This driver is for the AEMIF module available in Texas Instruments 25 SoCs. AEMIF stands for Asynchronous External Memory Interface and 26 is intended to provide a glue-less interface to a variety of 27 asynchronuous memory devices like ASRAM, NOR and NAND memory. A total 28 of 256M bytes of any of these memories can be accessed at a given 29 time via four chip selects with 64M byte access per chip select. 30 31config TI_EMIF 32 tristate "Texas Instruments EMIF driver" 33 depends on ARCH_OMAP2PLUS 34 select DDR 35 help 36 This driver is for the EMIF module available in Texas Instruments 37 SoCs. EMIF is an SDRAM controller that, based on its revision, 38 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols. 39 This driver takes care of only LPDDR2 memories presently. The 40 functions of the driver includes re-configuring AC timing 41 parameters and other settings during frequency, voltage and 42 temperature changes 43 44config OMAP_GPMC 45 bool 46 help 47 This driver is for the General Purpose Memory Controller (GPMC) 48 present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows 49 interfacing to a variety of asynchronous as well as synchronous 50 memory drives like NOR, NAND, OneNAND, SRAM. 51 52config OMAP_GPMC_DEBUG 53 bool 54 depends on OMAP_GPMC 55 help 56 Enables verbose debugging mostly to decode the bootloader provided 57 timings. Enable this during development to configure devices 58 connected to the GPMC bus. 59 60config MVEBU_DEVBUS 61 bool "Marvell EBU Device Bus Controller" 62 default y 63 depends on PLAT_ORION && OF 64 help 65 This driver is for the Device Bus controller available in some 66 Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and 67 Armada 370 and Armada XP. This controller allows to handle flash 68 devices such as NOR, NAND, SRAM, and FPGA. 69 70config TEGRA20_MC 71 bool "Tegra20 Memory Controller(MC) driver" 72 default y 73 depends on ARCH_TEGRA_2x_SOC 74 help 75 This driver is for the Memory Controller(MC) module available 76 in Tegra20 SoCs, mainly for a address translation fault 77 analysis, especially for IOMMU/GART(Graphics Address 78 Relocation Table) module. 79 80config FSL_CORENET_CF 81 tristate "Freescale CoreNet Error Reporting" 82 depends on FSL_SOC_BOOKE 83 help 84 Say Y for reporting of errors from the Freescale CoreNet 85 Coherency Fabric. Errors reported include accesses to 86 physical addresses that mapped by no local access window 87 (LAW) or an invalid LAW, as well as bad cache state that 88 represents a coherency violation. 89 90config FSL_IFC 91 bool 92 depends on FSL_SOC 93 94config JZ4780_NEMC 95 bool "Ingenic JZ4780 SoC NEMC driver" 96 default y 97 depends on MACH_JZ4780 98 help 99 This driver is for the NAND/External Memory Controller (NEMC) in 100 the Ingenic JZ4780. This controller is used to handle external 101 memory devices such as NAND and SRAM. 102 103source "drivers/memory/tegra/Kconfig" 104 105endif 106