xref: /openbmc/linux/drivers/memory/Kconfig (revision b34e08d5)
1#
2# Memory devices
3#
4
5menuconfig MEMORY
6	bool "Memory Controller drivers"
7
8if MEMORY
9
10config TI_AEMIF
11	tristate "Texas Instruments AEMIF driver"
12	depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF
13	help
14	  This driver is for the AEMIF module available in Texas Instruments
15	  SoCs. AEMIF stands for Asynchronous External Memory Interface and
16	  is intended to provide a glue-less interface to a variety of
17	  asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
18	  of 256M bytes of any of these memories can be accessed at a given
19	  time via four chip selects with 64M byte access per chip select.
20
21config TI_EMIF
22	tristate "Texas Instruments EMIF driver"
23	depends on ARCH_OMAP2PLUS
24	select DDR
25	help
26	  This driver is for the EMIF module available in Texas Instruments
27	  SoCs. EMIF is an SDRAM controller that, based on its revision,
28	  supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
29	  This driver takes care of only LPDDR2 memories presently. The
30	  functions of the driver includes re-configuring AC timing
31	  parameters and other settings during frequency, voltage and
32	  temperature changes
33
34config MVEBU_DEVBUS
35	bool "Marvell EBU Device Bus Controller"
36	default y
37	depends on PLAT_ORION && OF
38	help
39	  This driver is for the Device Bus controller available in some
40	  Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
41	  Armada 370 and Armada XP. This controller allows to handle flash
42	  devices such as NOR, NAND, SRAM, and FPGA.
43
44config TEGRA20_MC
45	bool "Tegra20 Memory Controller(MC) driver"
46	default y
47	depends on ARCH_TEGRA_2x_SOC
48	help
49	  This driver is for the Memory Controller(MC) module available
50	  in Tegra20 SoCs, mainly for a address translation fault
51	  analysis, especially for IOMMU/GART(Graphics Address
52	  Relocation Table) module.
53
54config TEGRA30_MC
55	bool "Tegra30 Memory Controller(MC) driver"
56	default y
57	depends on ARCH_TEGRA_3x_SOC
58	help
59	  This driver is for the Memory Controller(MC) module available
60	  in Tegra30 SoCs, mainly for a address translation fault
61	  analysis, especially for IOMMU/SMMU(System Memory Management
62	  Unit) module.
63
64config FSL_IFC
65	bool
66	depends on FSL_SOC
67
68endif
69