xref: /openbmc/linux/drivers/memory/Kconfig (revision 904ffa81)
1# SPDX-License-Identifier: GPL-2.0-only
2#
3# Memory devices
4#
5
6menuconfig MEMORY
7	bool "Memory Controller drivers"
8	help
9	  This option allows to enable specific memory controller drivers,
10	  useful mostly on embedded systems.  These could be controllers
11	  for DRAM (SDR, DDR), ROM, SRAM and others.  The drivers features
12	  vary from memory tuning and frequency scaling to enabling
13	  access to attached peripherals through memory bus.
14
15if MEMORY
16
17config DDR
18	bool
19	help
20	  Data from JEDEC specs for DDR SDRAM memories,
21	  particularly the AC timing parameters and addressing
22	  information. This data is useful for drivers handling
23	  DDR SDRAM controllers.
24
25config ARM_PL172_MPMC
26	tristate "ARM PL172 MPMC driver"
27	depends on ARM_AMBA && OF
28	help
29	  This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
30	  If you have an embedded system with an AMBA bus and a PL172
31	  controller, say Y or M here.
32
33config ATMEL_SDRAMC
34	bool "Atmel (Multi-port DDR-)SDRAM Controller"
35	default y
36	depends on ARCH_AT91 && OF
37	help
38	  This driver is for Atmel SDRAM Controller or Atmel Multi-port
39	  DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
40	  Starting with the at91sam9g45, this controller supports SDR, DDR and
41	  LP-DDR memories.
42
43config ATMEL_EBI
44	bool "Atmel EBI driver"
45	default y
46	depends on ARCH_AT91 && OF
47	select MFD_SYSCON
48	select MFD_ATMEL_SMC
49	help
50	  Driver for Atmel EBI controller.
51	  Used to configure the EBI (external bus interface) when the device-
52	  tree is used. This bus supports NANDs, external ethernet controller,
53	  SRAMs, ATA devices, etc.
54
55config BRCMSTB_DPFE
56	bool "Broadcom STB DPFE driver" if COMPILE_TEST
57	default y if ARCH_BRCMSTB
58	depends on ARCH_BRCMSTB || COMPILE_TEST
59	help
60	  This driver provides access to the DPFE interface of Broadcom
61	  STB SoCs. The firmware running on the DCPU inside the DDR PHY can
62	  provide current information about the system's RAM, for instance
63	  the DRAM refresh rate. This can be used as an indirect indicator
64	  for the DRAM's temperature. Slower refresh rate means cooler RAM,
65	  higher refresh rate means hotter RAM.
66
67config BT1_L2_CTL
68	bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
69	depends on MIPS_BAIKAL_T1 || COMPILE_TEST
70	select MFD_SYSCON
71	help
72	  Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73	  resides Coherency Manager v2 with embedded 1MB L2-cache. It's
74	  possible to tune the L2 cache performance up by setting the data,
75	  tags and way-select latencies of RAM access. This driver provides a
76	  dt properties-based and sysfs interface for it.
77
78config TI_AEMIF
79	tristate "Texas Instruments AEMIF driver"
80	depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF
81	help
82	  This driver is for the AEMIF module available in Texas Instruments
83	  SoCs. AEMIF stands for Asynchronous External Memory Interface and
84	  is intended to provide a glue-less interface to a variety of
85	  asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
86	  of 256M bytes of any of these memories can be accessed at a given
87	  time via four chip selects with 64M byte access per chip select.
88
89config TI_EMIF
90	tristate "Texas Instruments EMIF driver"
91	depends on ARCH_OMAP2PLUS
92	select DDR
93	help
94	  This driver is for the EMIF module available in Texas Instruments
95	  SoCs. EMIF is an SDRAM controller that, based on its revision,
96	  supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
97	  This driver takes care of only LPDDR2 memories presently. The
98	  functions of the driver includes re-configuring AC timing
99	  parameters and other settings during frequency, voltage and
100	  temperature changes
101
102config OMAP_GPMC
103	bool
104	select GPIOLIB
105	help
106	  This driver is for the General Purpose Memory Controller (GPMC)
107	  present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows
108	  interfacing to a variety of asynchronous as well as synchronous
109	  memory drives like NOR, NAND, OneNAND, SRAM.
110
111config OMAP_GPMC_DEBUG
112	bool "Enable GPMC debug output and skip reset of GPMC during init"
113	depends on OMAP_GPMC
114	help
115	  Enables verbose debugging mostly to decode the bootloader provided
116	  timings. To preserve the bootloader provided timings, the reset
117	  of GPMC is skipped during init. Enable this during development to
118	  configure devices connected to the GPMC bus.
119
120	  NOTE: In addition to matching the register setup with the bootloader
121	  you also need to match the GPMC FCLK frequency used by the
122	  bootloader or else the GPMC timings won't be identical with the
123	  bootloader timings.
124
125config TI_EMIF_SRAM
126	tristate "Texas Instruments EMIF SRAM driver"
127	depends on (SOC_AM33XX || SOC_AM43XX) && SRAM
128	help
129	  This driver is for the EMIF module available on Texas Instruments
130	  AM33XX and AM43XX SoCs and is required for PM. Certain parts of
131	  the EMIF PM code must run from on-chip SRAM late in the suspend
132	  sequence so this driver provides several relocatable PM functions
133	  for the SoC PM code to use.
134
135config MVEBU_DEVBUS
136	bool "Marvell EBU Device Bus Controller"
137	default y
138	depends on PLAT_ORION && OF
139	help
140	  This driver is for the Device Bus controller available in some
141	  Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
142	  Armada 370 and Armada XP. This controller allows to handle flash
143	  devices such as NOR, NAND, SRAM, and FPGA.
144
145config FSL_CORENET_CF
146	tristate "Freescale CoreNet Error Reporting"
147	depends on FSL_SOC_BOOKE
148	help
149	  Say Y for reporting of errors from the Freescale CoreNet
150	  Coherency Fabric.  Errors reported include accesses to
151	  physical addresses that mapped by no local access window
152	  (LAW) or an invalid LAW, as well as bad cache state that
153	  represents a coherency violation.
154
155config FSL_IFC
156	bool
157	depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A || COMPILE_TEST
158	depends on HAS_IOMEM
159
160config JZ4780_NEMC
161	bool "Ingenic JZ4780 SoC NEMC driver"
162	depends on MIPS || COMPILE_TEST
163	depends on HAS_IOMEM && OF
164	help
165	  This driver is for the NAND/External Memory Controller (NEMC) in
166	  the Ingenic JZ4780. This controller is used to handle external
167	  memory devices such as NAND and SRAM.
168
169config MTK_SMI
170	bool
171	depends on ARCH_MEDIATEK || COMPILE_TEST
172	help
173	  This driver is for the Memory Controller module in MediaTek SoCs,
174	  mainly help enable/disable iommu and control the power domain and
175	  clocks for each local arbiter.
176
177config DA8XX_DDRCTL
178	bool "Texas Instruments da8xx DDR2/mDDR driver"
179	depends on ARCH_DAVINCI_DA8XX
180	help
181	  This driver is for the DDR2/mDDR Memory Controller present on
182	  Texas Instruments da8xx SoCs. It's used to tweak various memory
183	  controller configuration options.
184
185config PL353_SMC
186	tristate "ARM PL35X Static Memory Controller(SMC) driver"
187	default y
188	depends on ARM
189	depends on ARM_AMBA
190	help
191	  This driver is for the ARM PL351/PL353 Static Memory
192	  Controller(SMC) module.
193
194config RENESAS_RPCIF
195	tristate "Renesas RPC-IF driver"
196	depends on ARCH_RENESAS
197	select REGMAP_MMIO
198	help
199	  This supports Renesas R-Car Gen3 RPC-IF which provides either SPI
200	  host or HyperFlash. You'll have to select individual components
201	  under the corresponding menu.
202
203config STM32_FMC2_EBI
204	tristate "Support for FMC2 External Bus Interface on STM32MP SoCs"
205	depends on MACH_STM32MP157 || COMPILE_TEST
206	select MFD_SYSCON
207	help
208	  Select this option to enable the STM32 FMC2 External Bus Interface
209	  controller. This driver configures the transactions with external
210	  devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
211	  SOCs containing the FMC2 External Bus Interface.
212
213source "drivers/memory/samsung/Kconfig"
214source "drivers/memory/tegra/Kconfig"
215
216endif
217