1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Memory devices 4# 5 6menuconfig MEMORY 7 bool "Memory Controller drivers" 8 9if MEMORY 10 11config DDR 12 bool 13 help 14 Data from JEDEC specs for DDR SDRAM memories, 15 particularly the AC timing parameters and addressing 16 information. This data is useful for drivers handling 17 DDR SDRAM controllers. 18 19config ARM_PL172_MPMC 20 tristate "ARM PL172 MPMC driver" 21 depends on ARM_AMBA && OF 22 help 23 This selects the ARM PrimeCell PL172 MultiPort Memory Controller. 24 If you have an embedded system with an AMBA bus and a PL172 25 controller, say Y or M here. 26 27config ATMEL_SDRAMC 28 bool "Atmel (Multi-port DDR-)SDRAM Controller" 29 default y 30 depends on ARCH_AT91 && OF 31 help 32 This driver is for Atmel SDRAM Controller or Atmel Multi-port 33 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs. 34 Starting with the at91sam9g45, this controller supports SDR, DDR and 35 LP-DDR memories. 36 37config ATMEL_EBI 38 bool "Atmel EBI driver" 39 default y 40 depends on ARCH_AT91 && OF 41 select MFD_SYSCON 42 select MFD_ATMEL_SMC 43 help 44 Driver for Atmel EBI controller. 45 Used to configure the EBI (external bus interface) when the device- 46 tree is used. This bus supports NANDs, external ethernet controller, 47 SRAMs, ATA devices, etc. 48 49config BT1_L2_CTL 50 bool "Baikal-T1 CM2 L2-RAM Cache Control Block" 51 depends on MIPS_BAIKAL_T1 || COMPILE_TEST 52 select MFD_SYSCON 53 help 54 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU 55 resides Coherency Manager v2 with embedded 1MB L2-cache. It's 56 possible to tune the L2 cache performance up by setting the data, 57 tags and way-select latencies of RAM access. This driver provides a 58 dt properties-based and sysfs interface for it. 59 60config TI_AEMIF 61 tristate "Texas Instruments AEMIF driver" 62 depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF 63 help 64 This driver is for the AEMIF module available in Texas Instruments 65 SoCs. AEMIF stands for Asynchronous External Memory Interface and 66 is intended to provide a glue-less interface to a variety of 67 asynchronuous memory devices like ASRAM, NOR and NAND memory. A total 68 of 256M bytes of any of these memories can be accessed at a given 69 time via four chip selects with 64M byte access per chip select. 70 71config TI_EMIF 72 tristate "Texas Instruments EMIF driver" 73 depends on ARCH_OMAP2PLUS 74 select DDR 75 help 76 This driver is for the EMIF module available in Texas Instruments 77 SoCs. EMIF is an SDRAM controller that, based on its revision, 78 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols. 79 This driver takes care of only LPDDR2 memories presently. The 80 functions of the driver includes re-configuring AC timing 81 parameters and other settings during frequency, voltage and 82 temperature changes 83 84config OMAP_GPMC 85 bool 86 select GPIOLIB 87 help 88 This driver is for the General Purpose Memory Controller (GPMC) 89 present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows 90 interfacing to a variety of asynchronous as well as synchronous 91 memory drives like NOR, NAND, OneNAND, SRAM. 92 93config OMAP_GPMC_DEBUG 94 bool "Enable GPMC debug output and skip reset of GPMC during init" 95 depends on OMAP_GPMC 96 help 97 Enables verbose debugging mostly to decode the bootloader provided 98 timings. To preserve the bootloader provided timings, the reset 99 of GPMC is skipped during init. Enable this during development to 100 configure devices connected to the GPMC bus. 101 102 NOTE: In addition to matching the register setup with the bootloader 103 you also need to match the GPMC FCLK frequency used by the 104 bootloader or else the GPMC timings won't be identical with the 105 bootloader timings. 106 107config TI_EMIF_SRAM 108 tristate "Texas Instruments EMIF SRAM driver" 109 depends on (SOC_AM33XX || SOC_AM43XX) && SRAM 110 help 111 This driver is for the EMIF module available on Texas Instruments 112 AM33XX and AM43XX SoCs and is required for PM. Certain parts of 113 the EMIF PM code must run from on-chip SRAM late in the suspend 114 sequence so this driver provides several relocatable PM functions 115 for the SoC PM code to use. 116 117config MVEBU_DEVBUS 118 bool "Marvell EBU Device Bus Controller" 119 default y 120 depends on PLAT_ORION && OF 121 help 122 This driver is for the Device Bus controller available in some 123 Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and 124 Armada 370 and Armada XP. This controller allows to handle flash 125 devices such as NOR, NAND, SRAM, and FPGA. 126 127config FSL_CORENET_CF 128 tristate "Freescale CoreNet Error Reporting" 129 depends on FSL_SOC_BOOKE 130 help 131 Say Y for reporting of errors from the Freescale CoreNet 132 Coherency Fabric. Errors reported include accesses to 133 physical addresses that mapped by no local access window 134 (LAW) or an invalid LAW, as well as bad cache state that 135 represents a coherency violation. 136 137config FSL_IFC 138 bool 139 depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A || COMPILE_TEST 140 depends on HAS_IOMEM 141 142config JZ4780_NEMC 143 bool "Ingenic JZ4780 SoC NEMC driver" 144 default y 145 depends on MIPS || COMPILE_TEST 146 depends on HAS_IOMEM && OF 147 help 148 This driver is for the NAND/External Memory Controller (NEMC) in 149 the Ingenic JZ4780. This controller is used to handle external 150 memory devices such as NAND and SRAM. 151 152config MTK_SMI 153 bool 154 depends on ARCH_MEDIATEK || COMPILE_TEST 155 help 156 This driver is for the Memory Controller module in MediaTek SoCs, 157 mainly help enable/disable iommu and control the power domain and 158 clocks for each local arbiter. 159 160config DA8XX_DDRCTL 161 bool "Texas Instruments da8xx DDR2/mDDR driver" 162 depends on ARCH_DAVINCI_DA8XX 163 help 164 This driver is for the DDR2/mDDR Memory Controller present on 165 Texas Instruments da8xx SoCs. It's used to tweak various memory 166 controller configuration options. 167 168config PL353_SMC 169 tristate "ARM PL35X Static Memory Controller(SMC) driver" 170 default y 171 depends on ARM 172 depends on ARM_AMBA 173 help 174 This driver is for the ARM PL351/PL353 Static Memory 175 Controller(SMC) module. 176 177config STM32_FMC2_EBI 178 tristate "Support for FMC2 External Bus Interface on STM32MP SoCs" 179 depends on MACH_STM32MP157 || COMPILE_TEST 180 select MFD_SYSCON 181 help 182 Select this option to enable the STM32 FMC2 External Bus Interface 183 controller. This driver configures the transactions with external 184 devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on 185 SOCs containing the FMC2 External Bus Interface. 186 187source "drivers/memory/samsung/Kconfig" 188source "drivers/memory/tegra/Kconfig" 189 190endif 191