1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Memory devices 4# 5 6menuconfig MEMORY 7 bool "Memory Controller drivers" 8 9if MEMORY 10 11config DDR 12 bool 13 help 14 Data from JEDEC specs for DDR SDRAM memories, 15 particularly the AC timing parameters and addressing 16 information. This data is useful for drivers handling 17 DDR SDRAM controllers. 18 19config ARM_PL172_MPMC 20 tristate "ARM PL172 MPMC driver" 21 depends on ARM_AMBA && OF 22 help 23 This selects the ARM PrimeCell PL172 MultiPort Memory Controller. 24 If you have an embedded system with an AMBA bus and a PL172 25 controller, say Y or M here. 26 27config ATMEL_SDRAMC 28 bool "Atmel (Multi-port DDR-)SDRAM Controller" 29 default y 30 depends on ARCH_AT91 && OF 31 help 32 This driver is for Atmel SDRAM Controller or Atmel Multi-port 33 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs. 34 Starting with the at91sam9g45, this controller supports SDR, DDR and 35 LP-DDR memories. 36 37config ATMEL_EBI 38 bool "Atmel EBI driver" 39 default y 40 depends on ARCH_AT91 && OF 41 select MFD_SYSCON 42 select MFD_ATMEL_SMC 43 help 44 Driver for Atmel EBI controller. 45 Used to configure the EBI (external bus interface) when the device- 46 tree is used. This bus supports NANDs, external ethernet controller, 47 SRAMs, ATA devices, etc. 48 49config TI_AEMIF 50 tristate "Texas Instruments AEMIF driver" 51 depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF 52 help 53 This driver is for the AEMIF module available in Texas Instruments 54 SoCs. AEMIF stands for Asynchronous External Memory Interface and 55 is intended to provide a glue-less interface to a variety of 56 asynchronuous memory devices like ASRAM, NOR and NAND memory. A total 57 of 256M bytes of any of these memories can be accessed at a given 58 time via four chip selects with 64M byte access per chip select. 59 60config TI_EMIF 61 tristate "Texas Instruments EMIF driver" 62 depends on ARCH_OMAP2PLUS 63 select DDR 64 help 65 This driver is for the EMIF module available in Texas Instruments 66 SoCs. EMIF is an SDRAM controller that, based on its revision, 67 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols. 68 This driver takes care of only LPDDR2 memories presently. The 69 functions of the driver includes re-configuring AC timing 70 parameters and other settings during frequency, voltage and 71 temperature changes 72 73config OMAP_GPMC 74 bool 75 select GPIOLIB 76 help 77 This driver is for the General Purpose Memory Controller (GPMC) 78 present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows 79 interfacing to a variety of asynchronous as well as synchronous 80 memory drives like NOR, NAND, OneNAND, SRAM. 81 82config OMAP_GPMC_DEBUG 83 bool "Enable GPMC debug output and skip reset of GPMC during init" 84 depends on OMAP_GPMC 85 help 86 Enables verbose debugging mostly to decode the bootloader provided 87 timings. To preserve the bootloader provided timings, the reset 88 of GPMC is skipped during init. Enable this during development to 89 configure devices connected to the GPMC bus. 90 91 NOTE: In addition to matching the register setup with the bootloader 92 you also need to match the GPMC FCLK frequency used by the 93 bootloader or else the GPMC timings won't be identical with the 94 bootloader timings. 95 96config TI_EMIF_SRAM 97 tristate "Texas Instruments EMIF SRAM driver" 98 depends on (SOC_AM33XX || SOC_AM43XX) && SRAM 99 help 100 This driver is for the EMIF module available on Texas Instruments 101 AM33XX and AM43XX SoCs and is required for PM. Certain parts of 102 the EMIF PM code must run from on-chip SRAM late in the suspend 103 sequence so this driver provides several relocatable PM functions 104 for the SoC PM code to use. 105 106config MVEBU_DEVBUS 107 bool "Marvell EBU Device Bus Controller" 108 default y 109 depends on PLAT_ORION && OF 110 help 111 This driver is for the Device Bus controller available in some 112 Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and 113 Armada 370 and Armada XP. This controller allows to handle flash 114 devices such as NOR, NAND, SRAM, and FPGA. 115 116config FSL_CORENET_CF 117 tristate "Freescale CoreNet Error Reporting" 118 depends on FSL_SOC_BOOKE 119 help 120 Say Y for reporting of errors from the Freescale CoreNet 121 Coherency Fabric. Errors reported include accesses to 122 physical addresses that mapped by no local access window 123 (LAW) or an invalid LAW, as well as bad cache state that 124 represents a coherency violation. 125 126config FSL_IFC 127 bool 128 depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A || COMPILE_TEST 129 depends on HAS_IOMEM 130 131config JZ4780_NEMC 132 bool "Ingenic JZ4780 SoC NEMC driver" 133 default y 134 depends on MIPS || COMPILE_TEST 135 depends on HAS_IOMEM && OF 136 help 137 This driver is for the NAND/External Memory Controller (NEMC) in 138 the Ingenic JZ4780. This controller is used to handle external 139 memory devices such as NAND and SRAM. 140 141config MTK_SMI 142 bool 143 depends on ARCH_MEDIATEK || COMPILE_TEST 144 help 145 This driver is for the Memory Controller module in MediaTek SoCs, 146 mainly help enable/disable iommu and control the power domain and 147 clocks for each local arbiter. 148 149config DA8XX_DDRCTL 150 bool "Texas Instruments da8xx DDR2/mDDR driver" 151 depends on ARCH_DAVINCI_DA8XX 152 help 153 This driver is for the DDR2/mDDR Memory Controller present on 154 Texas Instruments da8xx SoCs. It's used to tweak various memory 155 controller configuration options. 156 157config PL353_SMC 158 tristate "ARM PL35X Static Memory Controller(SMC) driver" 159 default y 160 depends on ARM 161 depends on ARM_AMBA 162 help 163 This driver is for the ARM PL351/PL353 Static Memory 164 Controller(SMC) module. 165 166source "drivers/memory/samsung/Kconfig" 167source "drivers/memory/tegra/Kconfig" 168 169endif 170