1 /* 2 * 3 * 4 * Copyright (C) 2005 Mike Isely <isely@pobox.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 #include <linux/errno.h> 18 #include <linux/string.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 #include <linux/firmware.h> 22 #include <linux/videodev2.h> 23 #include <media/v4l2-common.h> 24 #include <media/tuner.h> 25 #include "pvrusb2.h" 26 #include "pvrusb2-std.h" 27 #include "pvrusb2-util.h" 28 #include "pvrusb2-hdw.h" 29 #include "pvrusb2-i2c-core.h" 30 #include "pvrusb2-eeprom.h" 31 #include "pvrusb2-hdw-internal.h" 32 #include "pvrusb2-encoder.h" 33 #include "pvrusb2-debug.h" 34 #include "pvrusb2-fx2-cmd.h" 35 #include "pvrusb2-wm8775.h" 36 #include "pvrusb2-video-v4l.h" 37 #include "pvrusb2-cx2584x-v4l.h" 38 #include "pvrusb2-cs53l32a.h" 39 #include "pvrusb2-audio.h" 40 41 #define TV_MIN_FREQ 55250000L 42 #define TV_MAX_FREQ 850000000L 43 44 /* This defines a minimum interval that the decoder must remain quiet 45 before we are allowed to start it running. */ 46 #define TIME_MSEC_DECODER_WAIT 50 47 48 /* This defines a minimum interval that the decoder must be allowed to run 49 before we can safely begin using its streaming output. */ 50 #define TIME_MSEC_DECODER_STABILIZATION_WAIT 300 51 52 /* This defines a minimum interval that the encoder must remain quiet 53 before we are allowed to configure it. */ 54 #define TIME_MSEC_ENCODER_WAIT 50 55 56 /* This defines the minimum interval that the encoder must successfully run 57 before we consider that the encoder has run at least once since its 58 firmware has been loaded. This measurement is in important for cases 59 where we can't do something until we know that the encoder has been run 60 at least once. */ 61 #define TIME_MSEC_ENCODER_OK 250 62 63 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL}; 64 static DEFINE_MUTEX(pvr2_unit_mtx); 65 66 static int ctlchg; 67 static int procreload; 68 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 }; 69 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 }; 70 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 }; 71 static int init_pause_msec; 72 73 module_param(ctlchg, int, S_IRUGO|S_IWUSR); 74 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value"); 75 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR); 76 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay"); 77 module_param(procreload, int, S_IRUGO|S_IWUSR); 78 MODULE_PARM_DESC(procreload, 79 "Attempt init failure recovery with firmware reload"); 80 module_param_array(tuner, int, NULL, 0444); 81 MODULE_PARM_DESC(tuner,"specify installed tuner type"); 82 module_param_array(video_std, int, NULL, 0444); 83 MODULE_PARM_DESC(video_std,"specify initial video standard"); 84 module_param_array(tolerance, int, NULL, 0444); 85 MODULE_PARM_DESC(tolerance,"specify stream error tolerance"); 86 87 /* US Broadcast channel 3 (61.25 MHz), to help with testing */ 88 static int default_tv_freq = 61250000L; 89 /* 104.3 MHz, a usable FM station for my area */ 90 static int default_radio_freq = 104300000L; 91 92 module_param_named(tv_freq, default_tv_freq, int, 0444); 93 MODULE_PARM_DESC(tv_freq, "specify initial television frequency"); 94 module_param_named(radio_freq, default_radio_freq, int, 0444); 95 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency"); 96 97 #define PVR2_CTL_WRITE_ENDPOINT 0x01 98 #define PVR2_CTL_READ_ENDPOINT 0x81 99 100 #define PVR2_GPIO_IN 0x9008 101 #define PVR2_GPIO_OUT 0x900c 102 #define PVR2_GPIO_DIR 0x9020 103 104 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__) 105 106 #define PVR2_FIRMWARE_ENDPOINT 0x02 107 108 /* size of a firmware chunk */ 109 #define FIRMWARE_CHUNK_SIZE 0x2000 110 111 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *, 112 struct v4l2_subdev *); 113 114 static const pvr2_subdev_update_func pvr2_module_update_functions[] = { 115 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update, 116 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update, 117 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update, 118 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update, 119 [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update, 120 }; 121 122 static const char *module_names[] = { 123 [PVR2_CLIENT_ID_MSP3400] = "msp3400", 124 [PVR2_CLIENT_ID_CX25840] = "cx25840", 125 [PVR2_CLIENT_ID_SAA7115] = "saa7115", 126 [PVR2_CLIENT_ID_TUNER] = "tuner", 127 [PVR2_CLIENT_ID_DEMOD] = "tuner", 128 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a", 129 [PVR2_CLIENT_ID_WM8775] = "wm8775", 130 }; 131 132 133 static const unsigned char *module_i2c_addresses[] = { 134 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63", 135 [PVR2_CLIENT_ID_DEMOD] = "\x43", 136 [PVR2_CLIENT_ID_MSP3400] = "\x40", 137 [PVR2_CLIENT_ID_SAA7115] = "\x21", 138 [PVR2_CLIENT_ID_WM8775] = "\x1b", 139 [PVR2_CLIENT_ID_CX25840] = "\x44", 140 [PVR2_CLIENT_ID_CS53L32A] = "\x11", 141 }; 142 143 144 static const char *ir_scheme_names[] = { 145 [PVR2_IR_SCHEME_NONE] = "none", 146 [PVR2_IR_SCHEME_29XXX] = "29xxx", 147 [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)", 148 [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)", 149 [PVR2_IR_SCHEME_ZILOG] = "Zilog", 150 }; 151 152 153 /* Define the list of additional controls we'll dynamically construct based 154 on query of the cx2341x module. */ 155 struct pvr2_mpeg_ids { 156 const char *strid; 157 int id; 158 }; 159 static const struct pvr2_mpeg_ids mpeg_ids[] = { 160 { 161 .strid = "audio_layer", 162 .id = V4L2_CID_MPEG_AUDIO_ENCODING, 163 },{ 164 .strid = "audio_bitrate", 165 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE, 166 },{ 167 /* Already using audio_mode elsewhere :-( */ 168 .strid = "mpeg_audio_mode", 169 .id = V4L2_CID_MPEG_AUDIO_MODE, 170 },{ 171 .strid = "mpeg_audio_mode_extension", 172 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION, 173 },{ 174 .strid = "audio_emphasis", 175 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS, 176 },{ 177 .strid = "audio_crc", 178 .id = V4L2_CID_MPEG_AUDIO_CRC, 179 },{ 180 .strid = "video_aspect", 181 .id = V4L2_CID_MPEG_VIDEO_ASPECT, 182 },{ 183 .strid = "video_b_frames", 184 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES, 185 },{ 186 .strid = "video_gop_size", 187 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE, 188 },{ 189 .strid = "video_gop_closure", 190 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE, 191 },{ 192 .strid = "video_bitrate_mode", 193 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE, 194 },{ 195 .strid = "video_bitrate", 196 .id = V4L2_CID_MPEG_VIDEO_BITRATE, 197 },{ 198 .strid = "video_bitrate_peak", 199 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK, 200 },{ 201 .strid = "video_temporal_decimation", 202 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION, 203 },{ 204 .strid = "stream_type", 205 .id = V4L2_CID_MPEG_STREAM_TYPE, 206 },{ 207 .strid = "video_spatial_filter_mode", 208 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE, 209 },{ 210 .strid = "video_spatial_filter", 211 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER, 212 },{ 213 .strid = "video_luma_spatial_filter_type", 214 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE, 215 },{ 216 .strid = "video_chroma_spatial_filter_type", 217 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE, 218 },{ 219 .strid = "video_temporal_filter_mode", 220 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE, 221 },{ 222 .strid = "video_temporal_filter", 223 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER, 224 },{ 225 .strid = "video_median_filter_type", 226 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE, 227 },{ 228 .strid = "video_luma_median_filter_top", 229 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP, 230 },{ 231 .strid = "video_luma_median_filter_bottom", 232 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM, 233 },{ 234 .strid = "video_chroma_median_filter_top", 235 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP, 236 },{ 237 .strid = "video_chroma_median_filter_bottom", 238 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM, 239 } 240 }; 241 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids) 242 243 244 static const char *control_values_srate[] = { 245 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz", 246 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz", 247 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz", 248 }; 249 250 251 252 static const char *control_values_input[] = { 253 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/ 254 [PVR2_CVAL_INPUT_DTV] = "dtv", 255 [PVR2_CVAL_INPUT_RADIO] = "radio", 256 [PVR2_CVAL_INPUT_SVIDEO] = "s-video", 257 [PVR2_CVAL_INPUT_COMPOSITE] = "composite", 258 }; 259 260 261 static const char *control_values_audiomode[] = { 262 [V4L2_TUNER_MODE_MONO] = "Mono", 263 [V4L2_TUNER_MODE_STEREO] = "Stereo", 264 [V4L2_TUNER_MODE_LANG1] = "Lang1", 265 [V4L2_TUNER_MODE_LANG2] = "Lang2", 266 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2", 267 }; 268 269 270 static const char *control_values_hsm[] = { 271 [PVR2_CVAL_HSM_FAIL] = "Fail", 272 [PVR2_CVAL_HSM_HIGH] = "High", 273 [PVR2_CVAL_HSM_FULL] = "Full", 274 }; 275 276 277 static const char *pvr2_state_names[] = { 278 [PVR2_STATE_NONE] = "none", 279 [PVR2_STATE_DEAD] = "dead", 280 [PVR2_STATE_COLD] = "cold", 281 [PVR2_STATE_WARM] = "warm", 282 [PVR2_STATE_ERROR] = "error", 283 [PVR2_STATE_READY] = "ready", 284 [PVR2_STATE_RUN] = "run", 285 }; 286 287 288 struct pvr2_fx2cmd_descdef { 289 unsigned char id; 290 unsigned char *desc; 291 }; 292 293 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = { 294 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"}, 295 {FX2CMD_MEM_READ_DWORD, "read encoder dword"}, 296 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"}, 297 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"}, 298 {FX2CMD_REG_WRITE, "write encoder register"}, 299 {FX2CMD_REG_READ, "read encoder register"}, 300 {FX2CMD_MEMSEL, "encoder memsel"}, 301 {FX2CMD_I2C_WRITE, "i2c write"}, 302 {FX2CMD_I2C_READ, "i2c read"}, 303 {FX2CMD_GET_USB_SPEED, "get USB speed"}, 304 {FX2CMD_STREAMING_ON, "stream on"}, 305 {FX2CMD_STREAMING_OFF, "stream off"}, 306 {FX2CMD_FWPOST1, "fwpost1"}, 307 {FX2CMD_POWER_OFF, "power off"}, 308 {FX2CMD_POWER_ON, "power on"}, 309 {FX2CMD_DEEP_RESET, "deep reset"}, 310 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"}, 311 {FX2CMD_GET_IR_CODE, "get IR code"}, 312 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"}, 313 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"}, 314 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"}, 315 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"}, 316 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"}, 317 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"}, 318 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"}, 319 }; 320 321 322 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v); 323 static void pvr2_hdw_state_sched(struct pvr2_hdw *); 324 static int pvr2_hdw_state_eval(struct pvr2_hdw *); 325 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long); 326 static void pvr2_hdw_worker_poll(struct work_struct *work); 327 static int pvr2_hdw_wait(struct pvr2_hdw *,int state); 328 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *); 329 static void pvr2_hdw_state_log_state(struct pvr2_hdw *); 330 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl); 331 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw); 332 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw); 333 static void pvr2_hdw_quiescent_timeout(struct timer_list *); 334 static void pvr2_hdw_decoder_stabilization_timeout(struct timer_list *); 335 static void pvr2_hdw_encoder_wait_timeout(struct timer_list *); 336 static void pvr2_hdw_encoder_run_timeout(struct timer_list *); 337 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32); 338 static int pvr2_send_request_ex(struct pvr2_hdw *hdw, 339 unsigned int timeout,int probe_fl, 340 void *write_data,unsigned int write_len, 341 void *read_data,unsigned int read_len); 342 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw); 343 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw); 344 345 static void trace_stbit(const char *name,int val) 346 { 347 pvr2_trace(PVR2_TRACE_STBITS, 348 "State bit %s <-- %s", 349 name,(val ? "true" : "false")); 350 } 351 352 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp) 353 { 354 struct pvr2_hdw *hdw = cptr->hdw; 355 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) { 356 *vp = hdw->freqTable[hdw->freqProgSlot-1]; 357 } else { 358 *vp = 0; 359 } 360 return 0; 361 } 362 363 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v) 364 { 365 struct pvr2_hdw *hdw = cptr->hdw; 366 unsigned int slotId = hdw->freqProgSlot; 367 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) { 368 hdw->freqTable[slotId-1] = v; 369 /* Handle side effects correctly - if we're tuned to this 370 slot, then forgot the slot id relation since the stored 371 frequency has been changed. */ 372 if (hdw->freqSelector) { 373 if (hdw->freqSlotRadio == slotId) { 374 hdw->freqSlotRadio = 0; 375 } 376 } else { 377 if (hdw->freqSlotTelevision == slotId) { 378 hdw->freqSlotTelevision = 0; 379 } 380 } 381 } 382 return 0; 383 } 384 385 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp) 386 { 387 *vp = cptr->hdw->freqProgSlot; 388 return 0; 389 } 390 391 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v) 392 { 393 struct pvr2_hdw *hdw = cptr->hdw; 394 if ((v >= 0) && (v <= FREQTABLE_SIZE)) { 395 hdw->freqProgSlot = v; 396 } 397 return 0; 398 } 399 400 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp) 401 { 402 struct pvr2_hdw *hdw = cptr->hdw; 403 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision; 404 return 0; 405 } 406 407 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId) 408 { 409 unsigned freq = 0; 410 struct pvr2_hdw *hdw = cptr->hdw; 411 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0; 412 if (slotId > 0) { 413 freq = hdw->freqTable[slotId-1]; 414 if (!freq) return 0; 415 pvr2_hdw_set_cur_freq(hdw,freq); 416 } 417 if (hdw->freqSelector) { 418 hdw->freqSlotRadio = slotId; 419 } else { 420 hdw->freqSlotTelevision = slotId; 421 } 422 return 0; 423 } 424 425 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp) 426 { 427 *vp = pvr2_hdw_get_cur_freq(cptr->hdw); 428 return 0; 429 } 430 431 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr) 432 { 433 return cptr->hdw->freqDirty != 0; 434 } 435 436 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr) 437 { 438 cptr->hdw->freqDirty = 0; 439 } 440 441 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v) 442 { 443 pvr2_hdw_set_cur_freq(cptr->hdw,v); 444 return 0; 445 } 446 447 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left) 448 { 449 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 450 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 451 if (stat != 0) { 452 return stat; 453 } 454 *left = cap->bounds.left; 455 return 0; 456 } 457 458 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left) 459 { 460 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 461 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 462 if (stat != 0) { 463 return stat; 464 } 465 *left = cap->bounds.left; 466 if (cap->bounds.width > cptr->hdw->cropw_val) { 467 *left += cap->bounds.width - cptr->hdw->cropw_val; 468 } 469 return 0; 470 } 471 472 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top) 473 { 474 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 475 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 476 if (stat != 0) { 477 return stat; 478 } 479 *top = cap->bounds.top; 480 return 0; 481 } 482 483 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top) 484 { 485 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 486 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 487 if (stat != 0) { 488 return stat; 489 } 490 *top = cap->bounds.top; 491 if (cap->bounds.height > cptr->hdw->croph_val) { 492 *top += cap->bounds.height - cptr->hdw->croph_val; 493 } 494 return 0; 495 } 496 497 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width) 498 { 499 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 500 int stat, bleftend, cleft; 501 502 stat = pvr2_hdw_check_cropcap(cptr->hdw); 503 if (stat != 0) { 504 return stat; 505 } 506 bleftend = cap->bounds.left+cap->bounds.width; 507 cleft = cptr->hdw->cropl_val; 508 509 *width = cleft < bleftend ? bleftend-cleft : 0; 510 return 0; 511 } 512 513 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height) 514 { 515 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 516 int stat, btopend, ctop; 517 518 stat = pvr2_hdw_check_cropcap(cptr->hdw); 519 if (stat != 0) { 520 return stat; 521 } 522 btopend = cap->bounds.top+cap->bounds.height; 523 ctop = cptr->hdw->cropt_val; 524 525 *height = ctop < btopend ? btopend-ctop : 0; 526 return 0; 527 } 528 529 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val) 530 { 531 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 532 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 533 if (stat != 0) { 534 return stat; 535 } 536 *val = cap->bounds.left; 537 return 0; 538 } 539 540 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val) 541 { 542 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 543 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 544 if (stat != 0) { 545 return stat; 546 } 547 *val = cap->bounds.top; 548 return 0; 549 } 550 551 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val) 552 { 553 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 554 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 555 if (stat != 0) { 556 return stat; 557 } 558 *val = cap->bounds.width; 559 return 0; 560 } 561 562 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val) 563 { 564 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 565 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 566 if (stat != 0) { 567 return stat; 568 } 569 *val = cap->bounds.height; 570 return 0; 571 } 572 573 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val) 574 { 575 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 576 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 577 if (stat != 0) { 578 return stat; 579 } 580 *val = cap->defrect.left; 581 return 0; 582 } 583 584 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val) 585 { 586 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 587 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 588 if (stat != 0) { 589 return stat; 590 } 591 *val = cap->defrect.top; 592 return 0; 593 } 594 595 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val) 596 { 597 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 598 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 599 if (stat != 0) { 600 return stat; 601 } 602 *val = cap->defrect.width; 603 return 0; 604 } 605 606 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val) 607 { 608 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 609 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 610 if (stat != 0) { 611 return stat; 612 } 613 *val = cap->defrect.height; 614 return 0; 615 } 616 617 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val) 618 { 619 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 620 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 621 if (stat != 0) { 622 return stat; 623 } 624 *val = cap->pixelaspect.numerator; 625 return 0; 626 } 627 628 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val) 629 { 630 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 631 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 632 if (stat != 0) { 633 return stat; 634 } 635 *val = cap->pixelaspect.denominator; 636 return 0; 637 } 638 639 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp) 640 { 641 /* Actual maximum depends on the video standard in effect. */ 642 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) { 643 *vp = 480; 644 } else { 645 *vp = 576; 646 } 647 return 0; 648 } 649 650 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp) 651 { 652 /* Actual minimum depends on device digitizer type. */ 653 if (cptr->hdw->hdw_desc->flag_has_cx25840) { 654 *vp = 75; 655 } else { 656 *vp = 17; 657 } 658 return 0; 659 } 660 661 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp) 662 { 663 *vp = cptr->hdw->input_val; 664 return 0; 665 } 666 667 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v) 668 { 669 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0; 670 } 671 672 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v) 673 { 674 return pvr2_hdw_set_input(cptr->hdw,v); 675 } 676 677 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr) 678 { 679 return cptr->hdw->input_dirty != 0; 680 } 681 682 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr) 683 { 684 cptr->hdw->input_dirty = 0; 685 } 686 687 688 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp) 689 { 690 unsigned long fv; 691 struct pvr2_hdw *hdw = cptr->hdw; 692 if (hdw->tuner_signal_stale) { 693 pvr2_hdw_status_poll(hdw); 694 } 695 fv = hdw->tuner_signal_info.rangehigh; 696 if (!fv) { 697 /* Safety fallback */ 698 *vp = TV_MAX_FREQ; 699 return 0; 700 } 701 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) { 702 fv = (fv * 125) / 2; 703 } else { 704 fv = fv * 62500; 705 } 706 *vp = fv; 707 return 0; 708 } 709 710 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp) 711 { 712 unsigned long fv; 713 struct pvr2_hdw *hdw = cptr->hdw; 714 if (hdw->tuner_signal_stale) { 715 pvr2_hdw_status_poll(hdw); 716 } 717 fv = hdw->tuner_signal_info.rangelow; 718 if (!fv) { 719 /* Safety fallback */ 720 *vp = TV_MIN_FREQ; 721 return 0; 722 } 723 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) { 724 fv = (fv * 125) / 2; 725 } else { 726 fv = fv * 62500; 727 } 728 *vp = fv; 729 return 0; 730 } 731 732 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr) 733 { 734 return cptr->hdw->enc_stale != 0; 735 } 736 737 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr) 738 { 739 cptr->hdw->enc_stale = 0; 740 cptr->hdw->enc_unsafe_stale = 0; 741 } 742 743 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp) 744 { 745 int ret; 746 struct v4l2_ext_controls cs; 747 struct v4l2_ext_control c1; 748 memset(&cs,0,sizeof(cs)); 749 memset(&c1,0,sizeof(c1)); 750 cs.controls = &c1; 751 cs.count = 1; 752 c1.id = cptr->info->v4l_id; 753 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs, 754 VIDIOC_G_EXT_CTRLS); 755 if (ret) return ret; 756 *vp = c1.value; 757 return 0; 758 } 759 760 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v) 761 { 762 int ret; 763 struct pvr2_hdw *hdw = cptr->hdw; 764 struct v4l2_ext_controls cs; 765 struct v4l2_ext_control c1; 766 memset(&cs,0,sizeof(cs)); 767 memset(&c1,0,sizeof(c1)); 768 cs.controls = &c1; 769 cs.count = 1; 770 c1.id = cptr->info->v4l_id; 771 c1.value = v; 772 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state, 773 hdw->state_encoder_run, &cs, 774 VIDIOC_S_EXT_CTRLS); 775 if (ret == -EBUSY) { 776 /* Oops. cx2341x is telling us it's not safe to change 777 this control while we're capturing. Make a note of this 778 fact so that the pipeline will be stopped the next time 779 controls are committed. Then go on ahead and store this 780 change anyway. */ 781 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state, 782 0, &cs, 783 VIDIOC_S_EXT_CTRLS); 784 if (!ret) hdw->enc_unsafe_stale = !0; 785 } 786 if (ret) return ret; 787 hdw->enc_stale = !0; 788 return 0; 789 } 790 791 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr) 792 { 793 struct v4l2_queryctrl qctrl; 794 struct pvr2_ctl_info *info; 795 qctrl.id = cptr->info->v4l_id; 796 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl); 797 /* Strip out the const so we can adjust a function pointer. It's 798 OK to do this here because we know this is a dynamically created 799 control, so the underlying storage for the info pointer is (a) 800 private to us, and (b) not in read-only storage. Either we do 801 this or we significantly complicate the underlying control 802 implementation. */ 803 info = (struct pvr2_ctl_info *)(cptr->info); 804 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) { 805 if (info->set_value) { 806 info->set_value = NULL; 807 } 808 } else { 809 if (!(info->set_value)) { 810 info->set_value = ctrl_cx2341x_set; 811 } 812 } 813 return qctrl.flags; 814 } 815 816 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp) 817 { 818 *vp = cptr->hdw->state_pipeline_req; 819 return 0; 820 } 821 822 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp) 823 { 824 *vp = cptr->hdw->master_state; 825 return 0; 826 } 827 828 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp) 829 { 830 int result = pvr2_hdw_is_hsm(cptr->hdw); 831 *vp = PVR2_CVAL_HSM_FULL; 832 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL; 833 if (result) *vp = PVR2_CVAL_HSM_HIGH; 834 return 0; 835 } 836 837 static int ctrl_stddetect_get(struct pvr2_ctrl *cptr, int *vp) 838 { 839 *vp = pvr2_hdw_get_detected_std(cptr->hdw); 840 return 0; 841 } 842 843 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp) 844 { 845 *vp = cptr->hdw->std_mask_avail; 846 return 0; 847 } 848 849 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v) 850 { 851 struct pvr2_hdw *hdw = cptr->hdw; 852 v4l2_std_id ns; 853 ns = hdw->std_mask_avail; 854 ns = (ns & ~m) | (v & m); 855 if (ns == hdw->std_mask_avail) return 0; 856 hdw->std_mask_avail = ns; 857 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail; 858 return 0; 859 } 860 861 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val, 862 char *bufPtr,unsigned int bufSize, 863 unsigned int *len) 864 { 865 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val); 866 return 0; 867 } 868 869 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr, 870 const char *bufPtr,unsigned int bufSize, 871 int *mskp,int *valp) 872 { 873 int ret; 874 v4l2_std_id id; 875 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize); 876 if (ret < 0) return ret; 877 if (mskp) *mskp = id; 878 if (valp) *valp = id; 879 return 0; 880 } 881 882 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp) 883 { 884 *vp = cptr->hdw->std_mask_cur; 885 return 0; 886 } 887 888 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v) 889 { 890 struct pvr2_hdw *hdw = cptr->hdw; 891 v4l2_std_id ns; 892 ns = hdw->std_mask_cur; 893 ns = (ns & ~m) | (v & m); 894 if (ns == hdw->std_mask_cur) return 0; 895 hdw->std_mask_cur = ns; 896 hdw->std_dirty = !0; 897 return 0; 898 } 899 900 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr) 901 { 902 return cptr->hdw->std_dirty != 0; 903 } 904 905 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr) 906 { 907 cptr->hdw->std_dirty = 0; 908 } 909 910 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp) 911 { 912 struct pvr2_hdw *hdw = cptr->hdw; 913 pvr2_hdw_status_poll(hdw); 914 *vp = hdw->tuner_signal_info.signal; 915 return 0; 916 } 917 918 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp) 919 { 920 int val = 0; 921 unsigned int subchan; 922 struct pvr2_hdw *hdw = cptr->hdw; 923 pvr2_hdw_status_poll(hdw); 924 subchan = hdw->tuner_signal_info.rxsubchans; 925 if (subchan & V4L2_TUNER_SUB_MONO) { 926 val |= (1 << V4L2_TUNER_MODE_MONO); 927 } 928 if (subchan & V4L2_TUNER_SUB_STEREO) { 929 val |= (1 << V4L2_TUNER_MODE_STEREO); 930 } 931 if (subchan & V4L2_TUNER_SUB_LANG1) { 932 val |= (1 << V4L2_TUNER_MODE_LANG1); 933 } 934 if (subchan & V4L2_TUNER_SUB_LANG2) { 935 val |= (1 << V4L2_TUNER_MODE_LANG2); 936 } 937 *vp = val; 938 return 0; 939 } 940 941 942 #define DEFINT(vmin,vmax) \ 943 .type = pvr2_ctl_int, \ 944 .def.type_int.min_value = vmin, \ 945 .def.type_int.max_value = vmax 946 947 #define DEFENUM(tab) \ 948 .type = pvr2_ctl_enum, \ 949 .def.type_enum.count = ARRAY_SIZE(tab), \ 950 .def.type_enum.value_names = tab 951 952 #define DEFBOOL \ 953 .type = pvr2_ctl_bool 954 955 #define DEFMASK(msk,tab) \ 956 .type = pvr2_ctl_bitmask, \ 957 .def.type_bitmask.valid_bits = msk, \ 958 .def.type_bitmask.bit_names = tab 959 960 #define DEFREF(vname) \ 961 .set_value = ctrl_set_##vname, \ 962 .get_value = ctrl_get_##vname, \ 963 .is_dirty = ctrl_isdirty_##vname, \ 964 .clear_dirty = ctrl_cleardirty_##vname 965 966 967 #define VCREATE_FUNCS(vname) \ 968 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \ 969 {*vp = cptr->hdw->vname##_val; return 0;} \ 970 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \ 971 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \ 972 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \ 973 {return cptr->hdw->vname##_dirty != 0;} \ 974 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \ 975 {cptr->hdw->vname##_dirty = 0;} 976 977 VCREATE_FUNCS(brightness) 978 VCREATE_FUNCS(contrast) 979 VCREATE_FUNCS(saturation) 980 VCREATE_FUNCS(hue) 981 VCREATE_FUNCS(volume) 982 VCREATE_FUNCS(balance) 983 VCREATE_FUNCS(bass) 984 VCREATE_FUNCS(treble) 985 VCREATE_FUNCS(mute) 986 VCREATE_FUNCS(cropl) 987 VCREATE_FUNCS(cropt) 988 VCREATE_FUNCS(cropw) 989 VCREATE_FUNCS(croph) 990 VCREATE_FUNCS(audiomode) 991 VCREATE_FUNCS(res_hor) 992 VCREATE_FUNCS(res_ver) 993 VCREATE_FUNCS(srate) 994 995 /* Table definition of all controls which can be manipulated */ 996 static const struct pvr2_ctl_info control_defs[] = { 997 { 998 .v4l_id = V4L2_CID_BRIGHTNESS, 999 .desc = "Brightness", 1000 .name = "brightness", 1001 .default_value = 128, 1002 DEFREF(brightness), 1003 DEFINT(0,255), 1004 },{ 1005 .v4l_id = V4L2_CID_CONTRAST, 1006 .desc = "Contrast", 1007 .name = "contrast", 1008 .default_value = 68, 1009 DEFREF(contrast), 1010 DEFINT(0,127), 1011 },{ 1012 .v4l_id = V4L2_CID_SATURATION, 1013 .desc = "Saturation", 1014 .name = "saturation", 1015 .default_value = 64, 1016 DEFREF(saturation), 1017 DEFINT(0,127), 1018 },{ 1019 .v4l_id = V4L2_CID_HUE, 1020 .desc = "Hue", 1021 .name = "hue", 1022 .default_value = 0, 1023 DEFREF(hue), 1024 DEFINT(-128,127), 1025 },{ 1026 .v4l_id = V4L2_CID_AUDIO_VOLUME, 1027 .desc = "Volume", 1028 .name = "volume", 1029 .default_value = 62000, 1030 DEFREF(volume), 1031 DEFINT(0,65535), 1032 },{ 1033 .v4l_id = V4L2_CID_AUDIO_BALANCE, 1034 .desc = "Balance", 1035 .name = "balance", 1036 .default_value = 0, 1037 DEFREF(balance), 1038 DEFINT(-32768,32767), 1039 },{ 1040 .v4l_id = V4L2_CID_AUDIO_BASS, 1041 .desc = "Bass", 1042 .name = "bass", 1043 .default_value = 0, 1044 DEFREF(bass), 1045 DEFINT(-32768,32767), 1046 },{ 1047 .v4l_id = V4L2_CID_AUDIO_TREBLE, 1048 .desc = "Treble", 1049 .name = "treble", 1050 .default_value = 0, 1051 DEFREF(treble), 1052 DEFINT(-32768,32767), 1053 },{ 1054 .v4l_id = V4L2_CID_AUDIO_MUTE, 1055 .desc = "Mute", 1056 .name = "mute", 1057 .default_value = 0, 1058 DEFREF(mute), 1059 DEFBOOL, 1060 }, { 1061 .desc = "Capture crop left margin", 1062 .name = "crop_left", 1063 .internal_id = PVR2_CID_CROPL, 1064 .default_value = 0, 1065 DEFREF(cropl), 1066 DEFINT(-129, 340), 1067 .get_min_value = ctrl_cropl_min_get, 1068 .get_max_value = ctrl_cropl_max_get, 1069 .get_def_value = ctrl_get_cropcapdl, 1070 }, { 1071 .desc = "Capture crop top margin", 1072 .name = "crop_top", 1073 .internal_id = PVR2_CID_CROPT, 1074 .default_value = 0, 1075 DEFREF(cropt), 1076 DEFINT(-35, 544), 1077 .get_min_value = ctrl_cropt_min_get, 1078 .get_max_value = ctrl_cropt_max_get, 1079 .get_def_value = ctrl_get_cropcapdt, 1080 }, { 1081 .desc = "Capture crop width", 1082 .name = "crop_width", 1083 .internal_id = PVR2_CID_CROPW, 1084 .default_value = 720, 1085 DEFREF(cropw), 1086 DEFINT(0, 864), 1087 .get_max_value = ctrl_cropw_max_get, 1088 .get_def_value = ctrl_get_cropcapdw, 1089 }, { 1090 .desc = "Capture crop height", 1091 .name = "crop_height", 1092 .internal_id = PVR2_CID_CROPH, 1093 .default_value = 480, 1094 DEFREF(croph), 1095 DEFINT(0, 576), 1096 .get_max_value = ctrl_croph_max_get, 1097 .get_def_value = ctrl_get_cropcapdh, 1098 }, { 1099 .desc = "Capture capability pixel aspect numerator", 1100 .name = "cropcap_pixel_numerator", 1101 .internal_id = PVR2_CID_CROPCAPPAN, 1102 .get_value = ctrl_get_cropcappan, 1103 }, { 1104 .desc = "Capture capability pixel aspect denominator", 1105 .name = "cropcap_pixel_denominator", 1106 .internal_id = PVR2_CID_CROPCAPPAD, 1107 .get_value = ctrl_get_cropcappad, 1108 }, { 1109 .desc = "Capture capability bounds top", 1110 .name = "cropcap_bounds_top", 1111 .internal_id = PVR2_CID_CROPCAPBT, 1112 .get_value = ctrl_get_cropcapbt, 1113 }, { 1114 .desc = "Capture capability bounds left", 1115 .name = "cropcap_bounds_left", 1116 .internal_id = PVR2_CID_CROPCAPBL, 1117 .get_value = ctrl_get_cropcapbl, 1118 }, { 1119 .desc = "Capture capability bounds width", 1120 .name = "cropcap_bounds_width", 1121 .internal_id = PVR2_CID_CROPCAPBW, 1122 .get_value = ctrl_get_cropcapbw, 1123 }, { 1124 .desc = "Capture capability bounds height", 1125 .name = "cropcap_bounds_height", 1126 .internal_id = PVR2_CID_CROPCAPBH, 1127 .get_value = ctrl_get_cropcapbh, 1128 },{ 1129 .desc = "Video Source", 1130 .name = "input", 1131 .internal_id = PVR2_CID_INPUT, 1132 .default_value = PVR2_CVAL_INPUT_TV, 1133 .check_value = ctrl_check_input, 1134 DEFREF(input), 1135 DEFENUM(control_values_input), 1136 },{ 1137 .desc = "Audio Mode", 1138 .name = "audio_mode", 1139 .internal_id = PVR2_CID_AUDIOMODE, 1140 .default_value = V4L2_TUNER_MODE_STEREO, 1141 DEFREF(audiomode), 1142 DEFENUM(control_values_audiomode), 1143 },{ 1144 .desc = "Horizontal capture resolution", 1145 .name = "resolution_hor", 1146 .internal_id = PVR2_CID_HRES, 1147 .default_value = 720, 1148 DEFREF(res_hor), 1149 DEFINT(19,720), 1150 },{ 1151 .desc = "Vertical capture resolution", 1152 .name = "resolution_ver", 1153 .internal_id = PVR2_CID_VRES, 1154 .default_value = 480, 1155 DEFREF(res_ver), 1156 DEFINT(17,576), 1157 /* Hook in check for video standard and adjust maximum 1158 depending on the standard. */ 1159 .get_max_value = ctrl_vres_max_get, 1160 .get_min_value = ctrl_vres_min_get, 1161 },{ 1162 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ, 1163 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000, 1164 .desc = "Audio Sampling Frequency", 1165 .name = "srate", 1166 DEFREF(srate), 1167 DEFENUM(control_values_srate), 1168 },{ 1169 .desc = "Tuner Frequency (Hz)", 1170 .name = "frequency", 1171 .internal_id = PVR2_CID_FREQUENCY, 1172 .default_value = 0, 1173 .set_value = ctrl_freq_set, 1174 .get_value = ctrl_freq_get, 1175 .is_dirty = ctrl_freq_is_dirty, 1176 .clear_dirty = ctrl_freq_clear_dirty, 1177 DEFINT(0,0), 1178 /* Hook in check for input value (tv/radio) and adjust 1179 max/min values accordingly */ 1180 .get_max_value = ctrl_freq_max_get, 1181 .get_min_value = ctrl_freq_min_get, 1182 },{ 1183 .desc = "Channel", 1184 .name = "channel", 1185 .set_value = ctrl_channel_set, 1186 .get_value = ctrl_channel_get, 1187 DEFINT(0,FREQTABLE_SIZE), 1188 },{ 1189 .desc = "Channel Program Frequency", 1190 .name = "freq_table_value", 1191 .set_value = ctrl_channelfreq_set, 1192 .get_value = ctrl_channelfreq_get, 1193 DEFINT(0,0), 1194 /* Hook in check for input value (tv/radio) and adjust 1195 max/min values accordingly */ 1196 .get_max_value = ctrl_freq_max_get, 1197 .get_min_value = ctrl_freq_min_get, 1198 },{ 1199 .desc = "Channel Program ID", 1200 .name = "freq_table_channel", 1201 .set_value = ctrl_channelprog_set, 1202 .get_value = ctrl_channelprog_get, 1203 DEFINT(0,FREQTABLE_SIZE), 1204 },{ 1205 .desc = "Streaming Enabled", 1206 .name = "streaming_enabled", 1207 .get_value = ctrl_streamingenabled_get, 1208 DEFBOOL, 1209 },{ 1210 .desc = "USB Speed", 1211 .name = "usb_speed", 1212 .get_value = ctrl_hsm_get, 1213 DEFENUM(control_values_hsm), 1214 },{ 1215 .desc = "Master State", 1216 .name = "master_state", 1217 .get_value = ctrl_masterstate_get, 1218 DEFENUM(pvr2_state_names), 1219 },{ 1220 .desc = "Signal Present", 1221 .name = "signal_present", 1222 .get_value = ctrl_signal_get, 1223 DEFINT(0,65535), 1224 },{ 1225 .desc = "Audio Modes Present", 1226 .name = "audio_modes_present", 1227 .get_value = ctrl_audio_modes_present_get, 1228 /* For this type we "borrow" the V4L2_TUNER_MODE enum from 1229 v4l. Nothing outside of this module cares about this, 1230 but I reuse it in order to also reuse the 1231 control_values_audiomode string table. */ 1232 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)| 1233 (1 << V4L2_TUNER_MODE_STEREO)| 1234 (1 << V4L2_TUNER_MODE_LANG1)| 1235 (1 << V4L2_TUNER_MODE_LANG2)), 1236 control_values_audiomode), 1237 },{ 1238 .desc = "Video Standards Available Mask", 1239 .name = "video_standard_mask_available", 1240 .internal_id = PVR2_CID_STDAVAIL, 1241 .skip_init = !0, 1242 .get_value = ctrl_stdavail_get, 1243 .set_value = ctrl_stdavail_set, 1244 .val_to_sym = ctrl_std_val_to_sym, 1245 .sym_to_val = ctrl_std_sym_to_val, 1246 .type = pvr2_ctl_bitmask, 1247 },{ 1248 .desc = "Video Standards In Use Mask", 1249 .name = "video_standard_mask_active", 1250 .internal_id = PVR2_CID_STDCUR, 1251 .skip_init = !0, 1252 .get_value = ctrl_stdcur_get, 1253 .set_value = ctrl_stdcur_set, 1254 .is_dirty = ctrl_stdcur_is_dirty, 1255 .clear_dirty = ctrl_stdcur_clear_dirty, 1256 .val_to_sym = ctrl_std_val_to_sym, 1257 .sym_to_val = ctrl_std_sym_to_val, 1258 .type = pvr2_ctl_bitmask, 1259 },{ 1260 .desc = "Video Standards Detected Mask", 1261 .name = "video_standard_mask_detected", 1262 .internal_id = PVR2_CID_STDDETECT, 1263 .skip_init = !0, 1264 .get_value = ctrl_stddetect_get, 1265 .val_to_sym = ctrl_std_val_to_sym, 1266 .sym_to_val = ctrl_std_sym_to_val, 1267 .type = pvr2_ctl_bitmask, 1268 } 1269 }; 1270 1271 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs) 1272 1273 1274 const char *pvr2_config_get_name(enum pvr2_config cfg) 1275 { 1276 switch (cfg) { 1277 case pvr2_config_empty: return "empty"; 1278 case pvr2_config_mpeg: return "mpeg"; 1279 case pvr2_config_vbi: return "vbi"; 1280 case pvr2_config_pcm: return "pcm"; 1281 case pvr2_config_rawvideo: return "raw video"; 1282 } 1283 return "<unknown>"; 1284 } 1285 1286 1287 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw) 1288 { 1289 return hdw->usb_dev; 1290 } 1291 1292 1293 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw) 1294 { 1295 return hdw->serial_number; 1296 } 1297 1298 1299 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw) 1300 { 1301 return hdw->bus_info; 1302 } 1303 1304 1305 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw) 1306 { 1307 return hdw->identifier; 1308 } 1309 1310 1311 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw) 1312 { 1313 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio; 1314 } 1315 1316 /* Set the currently tuned frequency and account for all possible 1317 driver-core side effects of this action. */ 1318 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val) 1319 { 1320 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { 1321 if (hdw->freqSelector) { 1322 /* Swing over to radio frequency selection */ 1323 hdw->freqSelector = 0; 1324 hdw->freqDirty = !0; 1325 } 1326 if (hdw->freqValRadio != val) { 1327 hdw->freqValRadio = val; 1328 hdw->freqSlotRadio = 0; 1329 hdw->freqDirty = !0; 1330 } 1331 } else { 1332 if (!(hdw->freqSelector)) { 1333 /* Swing over to television frequency selection */ 1334 hdw->freqSelector = 1; 1335 hdw->freqDirty = !0; 1336 } 1337 if (hdw->freqValTelevision != val) { 1338 hdw->freqValTelevision = val; 1339 hdw->freqSlotTelevision = 0; 1340 hdw->freqDirty = !0; 1341 } 1342 } 1343 } 1344 1345 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw) 1346 { 1347 return hdw->unit_number; 1348 } 1349 1350 1351 /* Attempt to locate one of the given set of files. Messages are logged 1352 appropriate to what has been found. The return value will be 0 or 1353 greater on success (it will be the index of the file name found) and 1354 fw_entry will be filled in. Otherwise a negative error is returned on 1355 failure. If the return value is -ENOENT then no viable firmware file 1356 could be located. */ 1357 static int pvr2_locate_firmware(struct pvr2_hdw *hdw, 1358 const struct firmware **fw_entry, 1359 const char *fwtypename, 1360 unsigned int fwcount, 1361 const char *fwnames[]) 1362 { 1363 unsigned int idx; 1364 int ret = -EINVAL; 1365 for (idx = 0; idx < fwcount; idx++) { 1366 ret = request_firmware(fw_entry, 1367 fwnames[idx], 1368 &hdw->usb_dev->dev); 1369 if (!ret) { 1370 trace_firmware("Located %s firmware: %s; uploading...", 1371 fwtypename, 1372 fwnames[idx]); 1373 return idx; 1374 } 1375 if (ret == -ENOENT) continue; 1376 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1377 "request_firmware fatal error with code=%d",ret); 1378 return ret; 1379 } 1380 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1381 "***WARNING*** Device %s firmware seems to be missing.", 1382 fwtypename); 1383 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1384 "Did you install the pvrusb2 firmware files in their proper location?"); 1385 if (fwcount == 1) { 1386 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1387 "request_firmware unable to locate %s file %s", 1388 fwtypename,fwnames[0]); 1389 } else { 1390 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1391 "request_firmware unable to locate one of the following %s files:", 1392 fwtypename); 1393 for (idx = 0; idx < fwcount; idx++) { 1394 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1395 "request_firmware: Failed to find %s", 1396 fwnames[idx]); 1397 } 1398 } 1399 return ret; 1400 } 1401 1402 1403 /* 1404 * pvr2_upload_firmware1(). 1405 * 1406 * Send the 8051 firmware to the device. After the upload, arrange for 1407 * device to re-enumerate. 1408 * 1409 * NOTE : the pointer to the firmware data given by request_firmware() 1410 * is not suitable for an usb transaction. 1411 * 1412 */ 1413 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw) 1414 { 1415 const struct firmware *fw_entry = NULL; 1416 void *fw_ptr; 1417 unsigned int pipe; 1418 unsigned int fwsize; 1419 int ret; 1420 u16 address; 1421 1422 if (!hdw->hdw_desc->fx2_firmware.cnt) { 1423 hdw->fw1_state = FW1_STATE_OK; 1424 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1425 "Connected device type defines no firmware to upload; ignoring firmware"); 1426 return -ENOTTY; 1427 } 1428 1429 hdw->fw1_state = FW1_STATE_FAILED; // default result 1430 1431 trace_firmware("pvr2_upload_firmware1"); 1432 1433 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller", 1434 hdw->hdw_desc->fx2_firmware.cnt, 1435 hdw->hdw_desc->fx2_firmware.lst); 1436 if (ret < 0) { 1437 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING; 1438 return ret; 1439 } 1440 1441 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f)); 1442 1443 pipe = usb_sndctrlpipe(hdw->usb_dev, 0); 1444 fwsize = fw_entry->size; 1445 1446 if ((fwsize != 0x2000) && 1447 (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) { 1448 if (hdw->hdw_desc->flag_fx2_16kb) { 1449 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1450 "Wrong fx2 firmware size (expected 8192 or 16384, got %u)", 1451 fwsize); 1452 } else { 1453 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1454 "Wrong fx2 firmware size (expected 8192, got %u)", 1455 fwsize); 1456 } 1457 release_firmware(fw_entry); 1458 return -ENOMEM; 1459 } 1460 1461 fw_ptr = kmalloc(0x800, GFP_KERNEL); 1462 if (fw_ptr == NULL){ 1463 release_firmware(fw_entry); 1464 return -ENOMEM; 1465 } 1466 1467 /* We have to hold the CPU during firmware upload. */ 1468 pvr2_hdw_cpureset_assert(hdw,1); 1469 1470 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes 1471 chunk. */ 1472 1473 ret = 0; 1474 for (address = 0; address < fwsize; address += 0x800) { 1475 memcpy(fw_ptr, fw_entry->data + address, 0x800); 1476 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address, 1477 0, fw_ptr, 0x800, HZ); 1478 } 1479 1480 trace_firmware("Upload done, releasing device's CPU"); 1481 1482 /* Now release the CPU. It will disconnect and reconnect later. */ 1483 pvr2_hdw_cpureset_assert(hdw,0); 1484 1485 kfree(fw_ptr); 1486 release_firmware(fw_entry); 1487 1488 trace_firmware("Upload done (%d bytes sent)",ret); 1489 1490 /* We should have written fwsize bytes */ 1491 if (ret == fwsize) { 1492 hdw->fw1_state = FW1_STATE_RELOAD; 1493 return 0; 1494 } 1495 1496 return -EIO; 1497 } 1498 1499 1500 /* 1501 * pvr2_upload_firmware2() 1502 * 1503 * This uploads encoder firmware on endpoint 2. 1504 * 1505 */ 1506 1507 int pvr2_upload_firmware2(struct pvr2_hdw *hdw) 1508 { 1509 const struct firmware *fw_entry = NULL; 1510 void *fw_ptr; 1511 unsigned int pipe, fw_len, fw_done, bcnt, icnt; 1512 int actual_length; 1513 int ret = 0; 1514 int fwidx; 1515 static const char *fw_files[] = { 1516 CX2341X_FIRM_ENC_FILENAME, 1517 }; 1518 1519 if (hdw->hdw_desc->flag_skip_cx23416_firmware) { 1520 return 0; 1521 } 1522 1523 trace_firmware("pvr2_upload_firmware2"); 1524 1525 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder", 1526 ARRAY_SIZE(fw_files), fw_files); 1527 if (ret < 0) return ret; 1528 fwidx = ret; 1529 ret = 0; 1530 /* Since we're about to completely reinitialize the encoder, 1531 invalidate our cached copy of its configuration state. Next 1532 time we configure the encoder, then we'll fully configure it. */ 1533 hdw->enc_cur_valid = 0; 1534 1535 /* Encoder is about to be reset so note that as far as we're 1536 concerned now, the encoder has never been run. */ 1537 del_timer_sync(&hdw->encoder_run_timer); 1538 if (hdw->state_encoder_runok) { 1539 hdw->state_encoder_runok = 0; 1540 trace_stbit("state_encoder_runok",hdw->state_encoder_runok); 1541 } 1542 1543 /* First prepare firmware loading */ 1544 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/ 1545 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/ 1546 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/ 1547 ret |= pvr2_hdw_cmd_deep_reset(hdw); 1548 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/ 1549 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/ 1550 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/ 1551 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/ 1552 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/ 1553 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/ 1554 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/ 1555 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/ 1556 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/ 1557 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/ 1558 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/ 1559 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/ 1560 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1); 1561 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16)); 1562 1563 if (ret) { 1564 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1565 "firmware2 upload prep failed, ret=%d",ret); 1566 release_firmware(fw_entry); 1567 goto done; 1568 } 1569 1570 /* Now send firmware */ 1571 1572 fw_len = fw_entry->size; 1573 1574 if (fw_len % sizeof(u32)) { 1575 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1576 "size of %s firmware must be a multiple of %zu bytes", 1577 fw_files[fwidx],sizeof(u32)); 1578 release_firmware(fw_entry); 1579 ret = -EINVAL; 1580 goto done; 1581 } 1582 1583 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL); 1584 if (fw_ptr == NULL){ 1585 release_firmware(fw_entry); 1586 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1587 "failed to allocate memory for firmware2 upload"); 1588 ret = -ENOMEM; 1589 goto done; 1590 } 1591 1592 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT); 1593 1594 fw_done = 0; 1595 for (fw_done = 0; fw_done < fw_len;) { 1596 bcnt = fw_len - fw_done; 1597 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE; 1598 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt); 1599 /* Usbsnoop log shows that we must swap bytes... */ 1600 /* Some background info: The data being swapped here is a 1601 firmware image destined for the mpeg encoder chip that 1602 lives at the other end of a USB endpoint. The encoder 1603 chip always talks in 32 bit chunks and its storage is 1604 organized into 32 bit words. However from the file 1605 system to the encoder chip everything is purely a byte 1606 stream. The firmware file's contents are always 32 bit 1607 swapped from what the encoder expects. Thus the need 1608 always exists to swap the bytes regardless of the endian 1609 type of the host processor and therefore swab32() makes 1610 the most sense. */ 1611 for (icnt = 0; icnt < bcnt/4 ; icnt++) 1612 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]); 1613 1614 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt, 1615 &actual_length, HZ); 1616 ret |= (actual_length != bcnt); 1617 if (ret) break; 1618 fw_done += bcnt; 1619 } 1620 1621 trace_firmware("upload of %s : %i / %i ", 1622 fw_files[fwidx],fw_done,fw_len); 1623 1624 kfree(fw_ptr); 1625 release_firmware(fw_entry); 1626 1627 if (ret) { 1628 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1629 "firmware2 upload transfer failure"); 1630 goto done; 1631 } 1632 1633 /* Finish upload */ 1634 1635 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/ 1636 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/ 1637 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16)); 1638 1639 if (ret) { 1640 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1641 "firmware2 upload post-proc failure"); 1642 } 1643 1644 done: 1645 if (hdw->hdw_desc->signal_routing_scheme == 1646 PVR2_ROUTING_SCHEME_GOTVIEW) { 1647 /* Ensure that GPIO 11 is set to output for GOTVIEW 1648 hardware. */ 1649 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0); 1650 } 1651 return ret; 1652 } 1653 1654 1655 static const char *pvr2_get_state_name(unsigned int st) 1656 { 1657 if (st < ARRAY_SIZE(pvr2_state_names)) { 1658 return pvr2_state_names[st]; 1659 } 1660 return "???"; 1661 } 1662 1663 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl) 1664 { 1665 /* Even though we really only care about the video decoder chip at 1666 this point, we'll broadcast stream on/off to all sub-devices 1667 anyway, just in case somebody else wants to hear the 1668 command... */ 1669 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s", 1670 (enablefl ? "on" : "off")); 1671 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl); 1672 v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl); 1673 if (hdw->decoder_client_id) { 1674 /* We get here if the encoder has been noticed. Otherwise 1675 we'll issue a warning to the user (which should 1676 normally never happen). */ 1677 return 0; 1678 } 1679 if (!hdw->flag_decoder_missed) { 1680 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1681 "WARNING: No decoder present"); 1682 hdw->flag_decoder_missed = !0; 1683 trace_stbit("flag_decoder_missed", 1684 hdw->flag_decoder_missed); 1685 } 1686 return -EIO; 1687 } 1688 1689 1690 int pvr2_hdw_get_state(struct pvr2_hdw *hdw) 1691 { 1692 return hdw->master_state; 1693 } 1694 1695 1696 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw) 1697 { 1698 if (!hdw->flag_tripped) return 0; 1699 hdw->flag_tripped = 0; 1700 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1701 "Clearing driver error statuss"); 1702 return !0; 1703 } 1704 1705 1706 int pvr2_hdw_untrip(struct pvr2_hdw *hdw) 1707 { 1708 int fl; 1709 LOCK_TAKE(hdw->big_lock); do { 1710 fl = pvr2_hdw_untrip_unlocked(hdw); 1711 } while (0); LOCK_GIVE(hdw->big_lock); 1712 if (fl) pvr2_hdw_state_sched(hdw); 1713 return 0; 1714 } 1715 1716 1717 1718 1719 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw) 1720 { 1721 return hdw->state_pipeline_req != 0; 1722 } 1723 1724 1725 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag) 1726 { 1727 int ret,st; 1728 LOCK_TAKE(hdw->big_lock); do { 1729 pvr2_hdw_untrip_unlocked(hdw); 1730 if ((!enable_flag) != !(hdw->state_pipeline_req)) { 1731 hdw->state_pipeline_req = enable_flag != 0; 1732 pvr2_trace(PVR2_TRACE_START_STOP, 1733 "/*--TRACE_STREAM--*/ %s", 1734 enable_flag ? "enable" : "disable"); 1735 } 1736 pvr2_hdw_state_sched(hdw); 1737 } while (0); LOCK_GIVE(hdw->big_lock); 1738 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret; 1739 if (enable_flag) { 1740 while ((st = hdw->master_state) != PVR2_STATE_RUN) { 1741 if (st != PVR2_STATE_READY) return -EIO; 1742 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret; 1743 } 1744 } 1745 return 0; 1746 } 1747 1748 1749 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config) 1750 { 1751 int fl; 1752 LOCK_TAKE(hdw->big_lock); 1753 if ((fl = (hdw->desired_stream_type != config)) != 0) { 1754 hdw->desired_stream_type = config; 1755 hdw->state_pipeline_config = 0; 1756 trace_stbit("state_pipeline_config", 1757 hdw->state_pipeline_config); 1758 pvr2_hdw_state_sched(hdw); 1759 } 1760 LOCK_GIVE(hdw->big_lock); 1761 if (fl) return 0; 1762 return pvr2_hdw_wait(hdw,0); 1763 } 1764 1765 1766 static int get_default_tuner_type(struct pvr2_hdw *hdw) 1767 { 1768 int unit_number = hdw->unit_number; 1769 int tp = -1; 1770 if ((unit_number >= 0) && (unit_number < PVR_NUM)) { 1771 tp = tuner[unit_number]; 1772 } 1773 if (tp < 0) return -EINVAL; 1774 hdw->tuner_type = tp; 1775 hdw->tuner_updated = !0; 1776 return 0; 1777 } 1778 1779 1780 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw) 1781 { 1782 int unit_number = hdw->unit_number; 1783 int tp = 0; 1784 if ((unit_number >= 0) && (unit_number < PVR_NUM)) { 1785 tp = video_std[unit_number]; 1786 if (tp) return tp; 1787 } 1788 return 0; 1789 } 1790 1791 1792 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw) 1793 { 1794 int unit_number = hdw->unit_number; 1795 int tp = 0; 1796 if ((unit_number >= 0) && (unit_number < PVR_NUM)) { 1797 tp = tolerance[unit_number]; 1798 } 1799 return tp; 1800 } 1801 1802 1803 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw) 1804 { 1805 /* Try a harmless request to fetch the eeprom's address over 1806 endpoint 1. See what happens. Only the full FX2 image can 1807 respond to this. If this probe fails then likely the FX2 1808 firmware needs be loaded. */ 1809 int result; 1810 LOCK_TAKE(hdw->ctl_lock); do { 1811 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR; 1812 result = pvr2_send_request_ex(hdw,HZ*1,!0, 1813 hdw->cmd_buffer,1, 1814 hdw->cmd_buffer,1); 1815 if (result < 0) break; 1816 } while(0); LOCK_GIVE(hdw->ctl_lock); 1817 if (result) { 1818 pvr2_trace(PVR2_TRACE_INIT, 1819 "Probe of device endpoint 1 result status %d", 1820 result); 1821 } else { 1822 pvr2_trace(PVR2_TRACE_INIT, 1823 "Probe of device endpoint 1 succeeded"); 1824 } 1825 return result == 0; 1826 } 1827 1828 struct pvr2_std_hack { 1829 v4l2_std_id pat; /* Pattern to match */ 1830 v4l2_std_id msk; /* Which bits we care about */ 1831 v4l2_std_id std; /* What additional standards or default to set */ 1832 }; 1833 1834 /* This data structure labels specific combinations of standards from 1835 tveeprom that we'll try to recognize. If we recognize one, then assume 1836 a specified default standard to use. This is here because tveeprom only 1837 tells us about available standards not the intended default standard (if 1838 any) for the device in question. We guess the default based on what has 1839 been reported as available. Note that this is only for guessing a 1840 default - which can always be overridden explicitly - and if the user 1841 has otherwise named a default then that default will always be used in 1842 place of this table. */ 1843 static const struct pvr2_std_hack std_eeprom_maps[] = { 1844 { /* PAL(B/G) */ 1845 .pat = V4L2_STD_B|V4L2_STD_GH, 1846 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G, 1847 }, 1848 { /* NTSC(M) */ 1849 .pat = V4L2_STD_MN, 1850 .std = V4L2_STD_NTSC_M, 1851 }, 1852 { /* PAL(I) */ 1853 .pat = V4L2_STD_PAL_I, 1854 .std = V4L2_STD_PAL_I, 1855 }, 1856 { /* SECAM(L/L') */ 1857 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC, 1858 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC, 1859 }, 1860 { /* PAL(D/D1/K) */ 1861 .pat = V4L2_STD_DK, 1862 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K, 1863 }, 1864 }; 1865 1866 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw) 1867 { 1868 char buf[40]; 1869 unsigned int bcnt; 1870 v4l2_std_id std1,std2,std3; 1871 1872 std1 = get_default_standard(hdw); 1873 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask; 1874 1875 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom); 1876 pvr2_trace(PVR2_TRACE_STD, 1877 "Supported video standard(s) reported available in hardware: %.*s", 1878 bcnt,buf); 1879 1880 hdw->std_mask_avail = hdw->std_mask_eeprom; 1881 1882 std2 = (std1|std3) & ~hdw->std_mask_avail; 1883 if (std2) { 1884 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2); 1885 pvr2_trace(PVR2_TRACE_STD, 1886 "Expanding supported video standards to include: %.*s", 1887 bcnt,buf); 1888 hdw->std_mask_avail |= std2; 1889 } 1890 1891 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail; 1892 1893 if (std1) { 1894 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1); 1895 pvr2_trace(PVR2_TRACE_STD, 1896 "Initial video standard forced to %.*s", 1897 bcnt,buf); 1898 hdw->std_mask_cur = std1; 1899 hdw->std_dirty = !0; 1900 return; 1901 } 1902 if (std3) { 1903 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3); 1904 pvr2_trace(PVR2_TRACE_STD, 1905 "Initial video standard (determined by device type): %.*s", 1906 bcnt, buf); 1907 hdw->std_mask_cur = std3; 1908 hdw->std_dirty = !0; 1909 return; 1910 } 1911 1912 { 1913 unsigned int idx; 1914 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) { 1915 if (std_eeprom_maps[idx].msk ? 1916 ((std_eeprom_maps[idx].pat ^ 1917 hdw->std_mask_eeprom) & 1918 std_eeprom_maps[idx].msk) : 1919 (std_eeprom_maps[idx].pat != 1920 hdw->std_mask_eeprom)) continue; 1921 bcnt = pvr2_std_id_to_str(buf,sizeof(buf), 1922 std_eeprom_maps[idx].std); 1923 pvr2_trace(PVR2_TRACE_STD, 1924 "Initial video standard guessed as %.*s", 1925 bcnt,buf); 1926 hdw->std_mask_cur = std_eeprom_maps[idx].std; 1927 hdw->std_dirty = !0; 1928 return; 1929 } 1930 } 1931 1932 } 1933 1934 1935 static unsigned int pvr2_copy_i2c_addr_list( 1936 unsigned short *dst, const unsigned char *src, 1937 unsigned int dst_max) 1938 { 1939 unsigned int cnt = 0; 1940 if (!src) return 0; 1941 while (src[cnt] && (cnt + 1) < dst_max) { 1942 dst[cnt] = src[cnt]; 1943 cnt++; 1944 } 1945 dst[cnt] = I2C_CLIENT_END; 1946 return cnt; 1947 } 1948 1949 1950 static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw) 1951 { 1952 /* 1953 Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness 1954 for cx25840 causes that module to correctly set up its video 1955 scaling. This is really a problem in the cx25840 module itself, 1956 but we work around it here. The problem has not been seen in 1957 ivtv because there VBI is supported and set up. We don't do VBI 1958 here (at least not yet) and thus we never attempted to even set 1959 it up. 1960 */ 1961 struct v4l2_format fmt; 1962 if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) { 1963 /* We're not using a cx25840 so don't enable the hack */ 1964 return; 1965 } 1966 1967 pvr2_trace(PVR2_TRACE_INIT, 1968 "Module ID %u: Executing cx25840 VBI hack", 1969 hdw->decoder_client_id); 1970 memset(&fmt, 0, sizeof(fmt)); 1971 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE; 1972 fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525; 1973 fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525; 1974 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id, 1975 vbi, s_sliced_fmt, &fmt.fmt.sliced); 1976 } 1977 1978 1979 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw, 1980 const struct pvr2_device_client_desc *cd) 1981 { 1982 const char *fname; 1983 unsigned char mid; 1984 struct v4l2_subdev *sd; 1985 unsigned int i2ccnt; 1986 const unsigned char *p; 1987 /* Arbitrary count - max # i2c addresses we will probe */ 1988 unsigned short i2caddr[25]; 1989 1990 mid = cd->module_id; 1991 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL; 1992 if (!fname) { 1993 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1994 "Module ID %u for device %s has no name? The driver might have a configuration problem.", 1995 mid, 1996 hdw->hdw_desc->description); 1997 return -EINVAL; 1998 } 1999 pvr2_trace(PVR2_TRACE_INIT, 2000 "Module ID %u (%s) for device %s being loaded...", 2001 mid, fname, 2002 hdw->hdw_desc->description); 2003 2004 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list, 2005 ARRAY_SIZE(i2caddr)); 2006 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ? 2007 module_i2c_addresses[mid] : NULL) != NULL)) { 2008 /* Second chance: Try default i2c address list */ 2009 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p, 2010 ARRAY_SIZE(i2caddr)); 2011 if (i2ccnt) { 2012 pvr2_trace(PVR2_TRACE_INIT, 2013 "Module ID %u: Using default i2c address list", 2014 mid); 2015 } 2016 } 2017 2018 if (!i2ccnt) { 2019 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 2020 "Module ID %u (%s) for device %s: No i2c addresses. The driver might have a configuration problem.", 2021 mid, fname, hdw->hdw_desc->description); 2022 return -EINVAL; 2023 } 2024 2025 if (i2ccnt == 1) { 2026 pvr2_trace(PVR2_TRACE_INIT, 2027 "Module ID %u: Setting up with specified i2c address 0x%x", 2028 mid, i2caddr[0]); 2029 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap, 2030 fname, i2caddr[0], NULL); 2031 } else { 2032 pvr2_trace(PVR2_TRACE_INIT, 2033 "Module ID %u: Setting up with address probe list", 2034 mid); 2035 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap, 2036 fname, 0, i2caddr); 2037 } 2038 2039 if (!sd) { 2040 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 2041 "Module ID %u (%s) for device %s failed to load. Possible missing sub-device kernel module or initialization failure within module.", 2042 mid, fname, hdw->hdw_desc->description); 2043 return -EIO; 2044 } 2045 2046 /* Tag this sub-device instance with the module ID we know about. 2047 In other places we'll use that tag to determine if the instance 2048 requires special handling. */ 2049 sd->grp_id = mid; 2050 2051 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname); 2052 2053 2054 /* client-specific setup... */ 2055 switch (mid) { 2056 case PVR2_CLIENT_ID_CX25840: 2057 case PVR2_CLIENT_ID_SAA7115: 2058 hdw->decoder_client_id = mid; 2059 break; 2060 default: break; 2061 } 2062 2063 return 0; 2064 } 2065 2066 2067 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw) 2068 { 2069 unsigned int idx; 2070 const struct pvr2_string_table *cm; 2071 const struct pvr2_device_client_table *ct; 2072 int okFl = !0; 2073 2074 cm = &hdw->hdw_desc->client_modules; 2075 for (idx = 0; idx < cm->cnt; idx++) { 2076 request_module(cm->lst[idx]); 2077 } 2078 2079 ct = &hdw->hdw_desc->client_table; 2080 for (idx = 0; idx < ct->cnt; idx++) { 2081 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0; 2082 } 2083 if (!okFl) { 2084 hdw->flag_modulefail = !0; 2085 pvr2_hdw_render_useless(hdw); 2086 } 2087 } 2088 2089 2090 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw) 2091 { 2092 int ret; 2093 unsigned int idx; 2094 struct pvr2_ctrl *cptr; 2095 int reloadFl = 0; 2096 if (hdw->hdw_desc->fx2_firmware.cnt) { 2097 if (!reloadFl) { 2098 reloadFl = 2099 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints 2100 == 0); 2101 if (reloadFl) { 2102 pvr2_trace(PVR2_TRACE_INIT, 2103 "USB endpoint config looks strange; possibly firmware needs to be loaded"); 2104 } 2105 } 2106 if (!reloadFl) { 2107 reloadFl = !pvr2_hdw_check_firmware(hdw); 2108 if (reloadFl) { 2109 pvr2_trace(PVR2_TRACE_INIT, 2110 "Check for FX2 firmware failed; possibly firmware needs to be loaded"); 2111 } 2112 } 2113 if (reloadFl) { 2114 if (pvr2_upload_firmware1(hdw) != 0) { 2115 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 2116 "Failure uploading firmware1"); 2117 } 2118 return; 2119 } 2120 } 2121 hdw->fw1_state = FW1_STATE_OK; 2122 2123 if (!pvr2_hdw_dev_ok(hdw)) return; 2124 2125 hdw->force_dirty = !0; 2126 2127 if (!hdw->hdw_desc->flag_no_powerup) { 2128 pvr2_hdw_cmd_powerup(hdw); 2129 if (!pvr2_hdw_dev_ok(hdw)) return; 2130 } 2131 2132 /* Take the IR chip out of reset, if appropriate */ 2133 if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) { 2134 pvr2_issue_simple_cmd(hdw, 2135 FX2CMD_HCW_ZILOG_RESET | 2136 (1 << 8) | 2137 ((0) << 16)); 2138 } 2139 2140 // This step MUST happen after the earlier powerup step. 2141 pvr2_i2c_core_init(hdw); 2142 if (!pvr2_hdw_dev_ok(hdw)) return; 2143 2144 pvr2_hdw_load_modules(hdw); 2145 if (!pvr2_hdw_dev_ok(hdw)) return; 2146 2147 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw); 2148 2149 for (idx = 0; idx < CTRLDEF_COUNT; idx++) { 2150 cptr = hdw->controls + idx; 2151 if (cptr->info->skip_init) continue; 2152 if (!cptr->info->set_value) continue; 2153 cptr->info->set_value(cptr,~0,cptr->info->default_value); 2154 } 2155 2156 pvr2_hdw_cx25840_vbi_hack(hdw); 2157 2158 /* Set up special default values for the television and radio 2159 frequencies here. It's not really important what these defaults 2160 are, but I set them to something usable in the Chicago area just 2161 to make driver testing a little easier. */ 2162 2163 hdw->freqValTelevision = default_tv_freq; 2164 hdw->freqValRadio = default_radio_freq; 2165 2166 // Do not use pvr2_reset_ctl_endpoints() here. It is not 2167 // thread-safe against the normal pvr2_send_request() mechanism. 2168 // (We should make it thread safe). 2169 2170 if (hdw->hdw_desc->flag_has_hauppauge_rom) { 2171 ret = pvr2_hdw_get_eeprom_addr(hdw); 2172 if (!pvr2_hdw_dev_ok(hdw)) return; 2173 if (ret < 0) { 2174 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 2175 "Unable to determine location of eeprom, skipping"); 2176 } else { 2177 hdw->eeprom_addr = ret; 2178 pvr2_eeprom_analyze(hdw); 2179 if (!pvr2_hdw_dev_ok(hdw)) return; 2180 } 2181 } else { 2182 hdw->tuner_type = hdw->hdw_desc->default_tuner_type; 2183 hdw->tuner_updated = !0; 2184 hdw->std_mask_eeprom = V4L2_STD_ALL; 2185 } 2186 2187 if (hdw->serial_number) { 2188 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1, 2189 "sn-%lu", hdw->serial_number); 2190 } else if (hdw->unit_number >= 0) { 2191 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1, 2192 "unit-%c", 2193 hdw->unit_number + 'a'); 2194 } else { 2195 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1, 2196 "unit-??"); 2197 } 2198 hdw->identifier[idx] = 0; 2199 2200 pvr2_hdw_setup_std(hdw); 2201 2202 if (!get_default_tuner_type(hdw)) { 2203 pvr2_trace(PVR2_TRACE_INIT, 2204 "pvr2_hdw_setup: Tuner type overridden to %d", 2205 hdw->tuner_type); 2206 } 2207 2208 2209 if (!pvr2_hdw_dev_ok(hdw)) return; 2210 2211 if (hdw->hdw_desc->signal_routing_scheme == 2212 PVR2_ROUTING_SCHEME_GOTVIEW) { 2213 /* Ensure that GPIO 11 is set to output for GOTVIEW 2214 hardware. */ 2215 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0); 2216 } 2217 2218 pvr2_hdw_commit_setup(hdw); 2219 2220 hdw->vid_stream = pvr2_stream_create(); 2221 if (!pvr2_hdw_dev_ok(hdw)) return; 2222 pvr2_trace(PVR2_TRACE_INIT, 2223 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream); 2224 if (hdw->vid_stream) { 2225 idx = get_default_error_tolerance(hdw); 2226 if (idx) { 2227 pvr2_trace(PVR2_TRACE_INIT, 2228 "pvr2_hdw_setup: video stream %p setting tolerance %u", 2229 hdw->vid_stream,idx); 2230 } 2231 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev, 2232 PVR2_VID_ENDPOINT,idx); 2233 } 2234 2235 if (!pvr2_hdw_dev_ok(hdw)) return; 2236 2237 hdw->flag_init_ok = !0; 2238 2239 pvr2_hdw_state_sched(hdw); 2240 } 2241 2242 2243 /* Set up the structure and attempt to put the device into a usable state. 2244 This can be a time-consuming operation, which is why it is not done 2245 internally as part of the create() step. */ 2246 static void pvr2_hdw_setup(struct pvr2_hdw *hdw) 2247 { 2248 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw); 2249 do { 2250 pvr2_hdw_setup_low(hdw); 2251 pvr2_trace(PVR2_TRACE_INIT, 2252 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d", 2253 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok); 2254 if (pvr2_hdw_dev_ok(hdw)) { 2255 if (hdw->flag_init_ok) { 2256 pvr2_trace( 2257 PVR2_TRACE_INFO, 2258 "Device initialization completed successfully."); 2259 break; 2260 } 2261 if (hdw->fw1_state == FW1_STATE_RELOAD) { 2262 pvr2_trace( 2263 PVR2_TRACE_INFO, 2264 "Device microcontroller firmware (re)loaded; it should now reset and reconnect."); 2265 break; 2266 } 2267 pvr2_trace( 2268 PVR2_TRACE_ERROR_LEGS, 2269 "Device initialization was not successful."); 2270 if (hdw->fw1_state == FW1_STATE_MISSING) { 2271 pvr2_trace( 2272 PVR2_TRACE_ERROR_LEGS, 2273 "Giving up since device microcontroller firmware appears to be missing."); 2274 break; 2275 } 2276 } 2277 if (hdw->flag_modulefail) { 2278 pvr2_trace( 2279 PVR2_TRACE_ERROR_LEGS, 2280 "***WARNING*** pvrusb2 driver initialization failed due to the failure of one or more sub-device kernel modules."); 2281 pvr2_trace( 2282 PVR2_TRACE_ERROR_LEGS, 2283 "You need to resolve the failing condition before this driver can function. There should be some earlier messages giving more information about the problem."); 2284 break; 2285 } 2286 if (procreload) { 2287 pvr2_trace( 2288 PVR2_TRACE_ERROR_LEGS, 2289 "Attempting pvrusb2 recovery by reloading primary firmware."); 2290 pvr2_trace( 2291 PVR2_TRACE_ERROR_LEGS, 2292 "If this works, device should disconnect and reconnect in a sane state."); 2293 hdw->fw1_state = FW1_STATE_UNKNOWN; 2294 pvr2_upload_firmware1(hdw); 2295 } else { 2296 pvr2_trace( 2297 PVR2_TRACE_ERROR_LEGS, 2298 "***WARNING*** pvrusb2 device hardware appears to be jammed and I can't clear it."); 2299 pvr2_trace( 2300 PVR2_TRACE_ERROR_LEGS, 2301 "You might need to power cycle the pvrusb2 device in order to recover."); 2302 } 2303 } while (0); 2304 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw); 2305 } 2306 2307 2308 /* Perform second stage initialization. Set callback pointer first so that 2309 we can avoid a possible initialization race (if the kernel thread runs 2310 before the callback has been set). */ 2311 int pvr2_hdw_initialize(struct pvr2_hdw *hdw, 2312 void (*callback_func)(void *), 2313 void *callback_data) 2314 { 2315 LOCK_TAKE(hdw->big_lock); do { 2316 if (hdw->flag_disconnected) { 2317 /* Handle a race here: If we're already 2318 disconnected by this point, then give up. If we 2319 get past this then we'll remain connected for 2320 the duration of initialization since the entire 2321 initialization sequence is now protected by the 2322 big_lock. */ 2323 break; 2324 } 2325 hdw->state_data = callback_data; 2326 hdw->state_func = callback_func; 2327 pvr2_hdw_setup(hdw); 2328 } while (0); LOCK_GIVE(hdw->big_lock); 2329 return hdw->flag_init_ok; 2330 } 2331 2332 2333 /* Create, set up, and return a structure for interacting with the 2334 underlying hardware. */ 2335 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf, 2336 const struct usb_device_id *devid) 2337 { 2338 unsigned int idx,cnt1,cnt2,m; 2339 struct pvr2_hdw *hdw = NULL; 2340 int valid_std_mask; 2341 struct pvr2_ctrl *cptr; 2342 struct usb_device *usb_dev; 2343 const struct pvr2_device_desc *hdw_desc; 2344 __u8 ifnum; 2345 struct v4l2_queryctrl qctrl; 2346 struct pvr2_ctl_info *ciptr; 2347 2348 usb_dev = interface_to_usbdev(intf); 2349 2350 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info); 2351 2352 if (hdw_desc == NULL) { 2353 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create: No device description pointer, unable to continue."); 2354 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type, please contact Mike Isely <isely@pobox.com> to get it included in the driver\n"); 2355 goto fail; 2356 } 2357 2358 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL); 2359 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"", 2360 hdw,hdw_desc->description); 2361 pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s", 2362 hdw_desc->description); 2363 if (hdw_desc->flag_is_experimental) { 2364 pvr2_trace(PVR2_TRACE_INFO, "**********"); 2365 pvr2_trace(PVR2_TRACE_INFO, 2366 "WARNING: Support for this device (%s) is experimental.", 2367 hdw_desc->description); 2368 pvr2_trace(PVR2_TRACE_INFO, 2369 "Important functionality might not be entirely working."); 2370 pvr2_trace(PVR2_TRACE_INFO, 2371 "Please consider contacting the driver author to help with further stabilization of the driver."); 2372 pvr2_trace(PVR2_TRACE_INFO, "**********"); 2373 } 2374 if (!hdw) goto fail; 2375 2376 timer_setup(&hdw->quiescent_timer, pvr2_hdw_quiescent_timeout, 0); 2377 2378 timer_setup(&hdw->decoder_stabilization_timer, 2379 pvr2_hdw_decoder_stabilization_timeout, 0); 2380 2381 timer_setup(&hdw->encoder_wait_timer, pvr2_hdw_encoder_wait_timeout, 2382 0); 2383 2384 timer_setup(&hdw->encoder_run_timer, pvr2_hdw_encoder_run_timeout, 0); 2385 2386 hdw->master_state = PVR2_STATE_DEAD; 2387 2388 init_waitqueue_head(&hdw->state_wait_data); 2389 2390 hdw->tuner_signal_stale = !0; 2391 cx2341x_fill_defaults(&hdw->enc_ctl_state); 2392 2393 /* Calculate which inputs are OK */ 2394 m = 0; 2395 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV; 2396 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) { 2397 m |= 1 << PVR2_CVAL_INPUT_DTV; 2398 } 2399 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO; 2400 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE; 2401 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO; 2402 hdw->input_avail_mask = m; 2403 hdw->input_allowed_mask = hdw->input_avail_mask; 2404 2405 /* If not a hybrid device, pathway_state never changes. So 2406 initialize it here to what it should forever be. */ 2407 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) { 2408 hdw->pathway_state = PVR2_PATHWAY_ANALOG; 2409 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) { 2410 hdw->pathway_state = PVR2_PATHWAY_DIGITAL; 2411 } 2412 2413 hdw->control_cnt = CTRLDEF_COUNT; 2414 hdw->control_cnt += MPEGDEF_COUNT; 2415 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt, 2416 GFP_KERNEL); 2417 if (!hdw->controls) goto fail; 2418 hdw->hdw_desc = hdw_desc; 2419 hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme; 2420 for (idx = 0; idx < hdw->control_cnt; idx++) { 2421 cptr = hdw->controls + idx; 2422 cptr->hdw = hdw; 2423 } 2424 for (idx = 0; idx < 32; idx++) { 2425 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx]; 2426 } 2427 for (idx = 0; idx < CTRLDEF_COUNT; idx++) { 2428 cptr = hdw->controls + idx; 2429 cptr->info = control_defs+idx; 2430 } 2431 2432 /* Ensure that default input choice is a valid one. */ 2433 m = hdw->input_avail_mask; 2434 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) { 2435 if (!((1 << idx) & m)) continue; 2436 hdw->input_val = idx; 2437 break; 2438 } 2439 2440 /* Define and configure additional controls from cx2341x module. */ 2441 hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT, 2442 sizeof(*(hdw->mpeg_ctrl_info)), 2443 GFP_KERNEL); 2444 if (!hdw->mpeg_ctrl_info) goto fail; 2445 for (idx = 0; idx < MPEGDEF_COUNT; idx++) { 2446 cptr = hdw->controls + idx + CTRLDEF_COUNT; 2447 ciptr = &(hdw->mpeg_ctrl_info[idx].info); 2448 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc; 2449 ciptr->name = mpeg_ids[idx].strid; 2450 ciptr->v4l_id = mpeg_ids[idx].id; 2451 ciptr->skip_init = !0; 2452 ciptr->get_value = ctrl_cx2341x_get; 2453 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags; 2454 ciptr->is_dirty = ctrl_cx2341x_is_dirty; 2455 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty; 2456 qctrl.id = ciptr->v4l_id; 2457 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl); 2458 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) { 2459 ciptr->set_value = ctrl_cx2341x_set; 2460 } 2461 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name, 2462 PVR2_CTLD_INFO_DESC_SIZE); 2463 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0; 2464 ciptr->default_value = qctrl.default_value; 2465 switch (qctrl.type) { 2466 default: 2467 case V4L2_CTRL_TYPE_INTEGER: 2468 ciptr->type = pvr2_ctl_int; 2469 ciptr->def.type_int.min_value = qctrl.minimum; 2470 ciptr->def.type_int.max_value = qctrl.maximum; 2471 break; 2472 case V4L2_CTRL_TYPE_BOOLEAN: 2473 ciptr->type = pvr2_ctl_bool; 2474 break; 2475 case V4L2_CTRL_TYPE_MENU: 2476 ciptr->type = pvr2_ctl_enum; 2477 ciptr->def.type_enum.value_names = 2478 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state, 2479 ciptr->v4l_id); 2480 for (cnt1 = 0; 2481 ciptr->def.type_enum.value_names[cnt1] != NULL; 2482 cnt1++) { } 2483 ciptr->def.type_enum.count = cnt1; 2484 break; 2485 } 2486 cptr->info = ciptr; 2487 } 2488 2489 // Initialize control data regarding video standard masks 2490 valid_std_mask = pvr2_std_get_usable(); 2491 for (idx = 0; idx < 32; idx++) { 2492 if (!(valid_std_mask & (1 << idx))) continue; 2493 cnt1 = pvr2_std_id_to_str( 2494 hdw->std_mask_names[idx], 2495 sizeof(hdw->std_mask_names[idx])-1, 2496 1 << idx); 2497 hdw->std_mask_names[idx][cnt1] = 0; 2498 } 2499 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL); 2500 if (cptr) { 2501 memcpy(&hdw->std_info_avail,cptr->info, 2502 sizeof(hdw->std_info_avail)); 2503 cptr->info = &hdw->std_info_avail; 2504 hdw->std_info_avail.def.type_bitmask.bit_names = 2505 hdw->std_mask_ptrs; 2506 hdw->std_info_avail.def.type_bitmask.valid_bits = 2507 valid_std_mask; 2508 } 2509 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR); 2510 if (cptr) { 2511 memcpy(&hdw->std_info_cur,cptr->info, 2512 sizeof(hdw->std_info_cur)); 2513 cptr->info = &hdw->std_info_cur; 2514 hdw->std_info_cur.def.type_bitmask.bit_names = 2515 hdw->std_mask_ptrs; 2516 hdw->std_info_cur.def.type_bitmask.valid_bits = 2517 valid_std_mask; 2518 } 2519 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDDETECT); 2520 if (cptr) { 2521 memcpy(&hdw->std_info_detect,cptr->info, 2522 sizeof(hdw->std_info_detect)); 2523 cptr->info = &hdw->std_info_detect; 2524 hdw->std_info_detect.def.type_bitmask.bit_names = 2525 hdw->std_mask_ptrs; 2526 hdw->std_info_detect.def.type_bitmask.valid_bits = 2527 valid_std_mask; 2528 } 2529 2530 hdw->cropcap_stale = !0; 2531 hdw->eeprom_addr = -1; 2532 hdw->unit_number = -1; 2533 hdw->v4l_minor_number_video = -1; 2534 hdw->v4l_minor_number_vbi = -1; 2535 hdw->v4l_minor_number_radio = -1; 2536 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL); 2537 if (!hdw->ctl_write_buffer) goto fail; 2538 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL); 2539 if (!hdw->ctl_read_buffer) goto fail; 2540 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL); 2541 if (!hdw->ctl_write_urb) goto fail; 2542 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL); 2543 if (!hdw->ctl_read_urb) goto fail; 2544 2545 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) { 2546 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 2547 "Error registering with v4l core, giving up"); 2548 goto fail; 2549 } 2550 mutex_lock(&pvr2_unit_mtx); 2551 do { 2552 for (idx = 0; idx < PVR_NUM; idx++) { 2553 if (unit_pointers[idx]) continue; 2554 hdw->unit_number = idx; 2555 unit_pointers[idx] = hdw; 2556 break; 2557 } 2558 } while (0); 2559 mutex_unlock(&pvr2_unit_mtx); 2560 2561 cnt1 = 0; 2562 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2"); 2563 cnt1 += cnt2; 2564 if (hdw->unit_number >= 0) { 2565 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c", 2566 ('a' + hdw->unit_number)); 2567 cnt1 += cnt2; 2568 } 2569 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1; 2570 hdw->name[cnt1] = 0; 2571 2572 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll); 2573 2574 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s", 2575 hdw->unit_number,hdw->name); 2576 2577 hdw->tuner_type = -1; 2578 hdw->flag_ok = !0; 2579 2580 hdw->usb_intf = intf; 2581 hdw->usb_dev = usb_dev; 2582 2583 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info)); 2584 2585 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber; 2586 usb_set_interface(hdw->usb_dev,ifnum,0); 2587 2588 mutex_init(&hdw->ctl_lock_mutex); 2589 mutex_init(&hdw->big_lock_mutex); 2590 2591 return hdw; 2592 fail: 2593 if (hdw) { 2594 del_timer_sync(&hdw->quiescent_timer); 2595 del_timer_sync(&hdw->decoder_stabilization_timer); 2596 del_timer_sync(&hdw->encoder_run_timer); 2597 del_timer_sync(&hdw->encoder_wait_timer); 2598 flush_work(&hdw->workpoll); 2599 usb_free_urb(hdw->ctl_read_urb); 2600 usb_free_urb(hdw->ctl_write_urb); 2601 kfree(hdw->ctl_read_buffer); 2602 kfree(hdw->ctl_write_buffer); 2603 kfree(hdw->controls); 2604 kfree(hdw->mpeg_ctrl_info); 2605 kfree(hdw); 2606 } 2607 return NULL; 2608 } 2609 2610 2611 /* Remove _all_ associations between this driver and the underlying USB 2612 layer. */ 2613 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw) 2614 { 2615 if (hdw->flag_disconnected) return; 2616 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw); 2617 if (hdw->ctl_read_urb) { 2618 usb_kill_urb(hdw->ctl_read_urb); 2619 usb_free_urb(hdw->ctl_read_urb); 2620 hdw->ctl_read_urb = NULL; 2621 } 2622 if (hdw->ctl_write_urb) { 2623 usb_kill_urb(hdw->ctl_write_urb); 2624 usb_free_urb(hdw->ctl_write_urb); 2625 hdw->ctl_write_urb = NULL; 2626 } 2627 if (hdw->ctl_read_buffer) { 2628 kfree(hdw->ctl_read_buffer); 2629 hdw->ctl_read_buffer = NULL; 2630 } 2631 if (hdw->ctl_write_buffer) { 2632 kfree(hdw->ctl_write_buffer); 2633 hdw->ctl_write_buffer = NULL; 2634 } 2635 hdw->flag_disconnected = !0; 2636 /* If we don't do this, then there will be a dangling struct device 2637 reference to our disappearing device persisting inside the V4L 2638 core... */ 2639 v4l2_device_disconnect(&hdw->v4l2_dev); 2640 hdw->usb_dev = NULL; 2641 hdw->usb_intf = NULL; 2642 pvr2_hdw_render_useless(hdw); 2643 } 2644 2645 void pvr2_hdw_set_v4l2_dev(struct pvr2_hdw *hdw, struct video_device *vdev) 2646 { 2647 vdev->v4l2_dev = &hdw->v4l2_dev; 2648 } 2649 2650 /* Destroy hardware interaction structure */ 2651 void pvr2_hdw_destroy(struct pvr2_hdw *hdw) 2652 { 2653 if (!hdw) return; 2654 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw); 2655 flush_work(&hdw->workpoll); 2656 del_timer_sync(&hdw->quiescent_timer); 2657 del_timer_sync(&hdw->decoder_stabilization_timer); 2658 del_timer_sync(&hdw->encoder_run_timer); 2659 del_timer_sync(&hdw->encoder_wait_timer); 2660 if (hdw->fw_buffer) { 2661 kfree(hdw->fw_buffer); 2662 hdw->fw_buffer = NULL; 2663 } 2664 if (hdw->vid_stream) { 2665 pvr2_stream_destroy(hdw->vid_stream); 2666 hdw->vid_stream = NULL; 2667 } 2668 pvr2_i2c_core_done(hdw); 2669 v4l2_device_unregister(&hdw->v4l2_dev); 2670 pvr2_hdw_remove_usb_stuff(hdw); 2671 mutex_lock(&pvr2_unit_mtx); 2672 do { 2673 if ((hdw->unit_number >= 0) && 2674 (hdw->unit_number < PVR_NUM) && 2675 (unit_pointers[hdw->unit_number] == hdw)) { 2676 unit_pointers[hdw->unit_number] = NULL; 2677 } 2678 } while (0); 2679 mutex_unlock(&pvr2_unit_mtx); 2680 kfree(hdw->controls); 2681 kfree(hdw->mpeg_ctrl_info); 2682 kfree(hdw); 2683 } 2684 2685 2686 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw) 2687 { 2688 return (hdw && hdw->flag_ok); 2689 } 2690 2691 2692 /* Called when hardware has been unplugged */ 2693 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw) 2694 { 2695 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw); 2696 LOCK_TAKE(hdw->big_lock); 2697 LOCK_TAKE(hdw->ctl_lock); 2698 pvr2_hdw_remove_usb_stuff(hdw); 2699 LOCK_GIVE(hdw->ctl_lock); 2700 LOCK_GIVE(hdw->big_lock); 2701 } 2702 2703 2704 /* Get the number of defined controls */ 2705 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw) 2706 { 2707 return hdw->control_cnt; 2708 } 2709 2710 2711 /* Retrieve a control handle given its index (0..count-1) */ 2712 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw, 2713 unsigned int idx) 2714 { 2715 if (idx >= hdw->control_cnt) return NULL; 2716 return hdw->controls + idx; 2717 } 2718 2719 2720 /* Retrieve a control handle given its index (0..count-1) */ 2721 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw, 2722 unsigned int ctl_id) 2723 { 2724 struct pvr2_ctrl *cptr; 2725 unsigned int idx; 2726 int i; 2727 2728 /* This could be made a lot more efficient, but for now... */ 2729 for (idx = 0; idx < hdw->control_cnt; idx++) { 2730 cptr = hdw->controls + idx; 2731 i = cptr->info->internal_id; 2732 if (i && (i == ctl_id)) return cptr; 2733 } 2734 return NULL; 2735 } 2736 2737 2738 /* Given a V4L ID, retrieve the control structure associated with it. */ 2739 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id) 2740 { 2741 struct pvr2_ctrl *cptr; 2742 unsigned int idx; 2743 int i; 2744 2745 /* This could be made a lot more efficient, but for now... */ 2746 for (idx = 0; idx < hdw->control_cnt; idx++) { 2747 cptr = hdw->controls + idx; 2748 i = cptr->info->v4l_id; 2749 if (i && (i == ctl_id)) return cptr; 2750 } 2751 return NULL; 2752 } 2753 2754 2755 /* Given a V4L ID for its immediate predecessor, retrieve the control 2756 structure associated with it. */ 2757 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw, 2758 unsigned int ctl_id) 2759 { 2760 struct pvr2_ctrl *cptr,*cp2; 2761 unsigned int idx; 2762 int i; 2763 2764 /* This could be made a lot more efficient, but for now... */ 2765 cp2 = NULL; 2766 for (idx = 0; idx < hdw->control_cnt; idx++) { 2767 cptr = hdw->controls + idx; 2768 i = cptr->info->v4l_id; 2769 if (!i) continue; 2770 if (i <= ctl_id) continue; 2771 if (cp2 && (cp2->info->v4l_id < i)) continue; 2772 cp2 = cptr; 2773 } 2774 return cp2; 2775 return NULL; 2776 } 2777 2778 2779 static const char *get_ctrl_typename(enum pvr2_ctl_type tp) 2780 { 2781 switch (tp) { 2782 case pvr2_ctl_int: return "integer"; 2783 case pvr2_ctl_enum: return "enum"; 2784 case pvr2_ctl_bool: return "boolean"; 2785 case pvr2_ctl_bitmask: return "bitmask"; 2786 } 2787 return ""; 2788 } 2789 2790 2791 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id, 2792 const char *name, int val) 2793 { 2794 struct v4l2_control ctrl; 2795 struct v4l2_subdev *sd; 2796 2797 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val); 2798 memset(&ctrl, 0, sizeof(ctrl)); 2799 ctrl.id = id; 2800 ctrl.value = val; 2801 2802 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) 2803 v4l2_s_ctrl(NULL, sd->ctrl_handler, &ctrl); 2804 } 2805 2806 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \ 2807 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \ 2808 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \ 2809 } 2810 2811 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw) 2812 { 2813 v4l2_std_id std; 2814 std = (v4l2_std_id)hdw->std_mask_avail; 2815 v4l2_device_call_all(&hdw->v4l2_dev, 0, 2816 video, querystd, &std); 2817 return std; 2818 } 2819 2820 /* Execute whatever commands are required to update the state of all the 2821 sub-devices so that they match our current control values. */ 2822 static void pvr2_subdev_update(struct pvr2_hdw *hdw) 2823 { 2824 struct v4l2_subdev *sd; 2825 unsigned int id; 2826 pvr2_subdev_update_func fp; 2827 2828 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update..."); 2829 2830 if (hdw->tuner_updated || hdw->force_dirty) { 2831 struct tuner_setup setup; 2832 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)", 2833 hdw->tuner_type); 2834 if (((int)(hdw->tuner_type)) >= 0) { 2835 memset(&setup, 0, sizeof(setup)); 2836 setup.addr = ADDR_UNSET; 2837 setup.type = hdw->tuner_type; 2838 setup.mode_mask = T_RADIO | T_ANALOG_TV; 2839 v4l2_device_call_all(&hdw->v4l2_dev, 0, 2840 tuner, s_type_addr, &setup); 2841 } 2842 } 2843 2844 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) { 2845 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard"); 2846 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { 2847 v4l2_device_call_all(&hdw->v4l2_dev, 0, 2848 tuner, s_radio); 2849 } else { 2850 v4l2_std_id vs; 2851 vs = hdw->std_mask_cur; 2852 v4l2_device_call_all(&hdw->v4l2_dev, 0, 2853 video, s_std, vs); 2854 pvr2_hdw_cx25840_vbi_hack(hdw); 2855 } 2856 hdw->tuner_signal_stale = !0; 2857 hdw->cropcap_stale = !0; 2858 } 2859 2860 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness); 2861 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast); 2862 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation); 2863 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue); 2864 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute); 2865 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume); 2866 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance); 2867 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass); 2868 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble); 2869 2870 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) { 2871 struct v4l2_tuner vt; 2872 memset(&vt, 0, sizeof(vt)); 2873 vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ? 2874 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; 2875 vt.audmode = hdw->audiomode_val; 2876 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt); 2877 } 2878 2879 if (hdw->freqDirty || hdw->force_dirty) { 2880 unsigned long fv; 2881 struct v4l2_frequency freq; 2882 fv = pvr2_hdw_get_cur_freq(hdw); 2883 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv); 2884 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw); 2885 memset(&freq, 0, sizeof(freq)); 2886 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) { 2887 /* ((fv * 1000) / 62500) */ 2888 freq.frequency = (fv * 2) / 125; 2889 } else { 2890 freq.frequency = fv / 62500; 2891 } 2892 /* tuner-core currently doesn't seem to care about this, but 2893 let's set it anyway for completeness. */ 2894 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { 2895 freq.type = V4L2_TUNER_RADIO; 2896 } else { 2897 freq.type = V4L2_TUNER_ANALOG_TV; 2898 } 2899 freq.tuner = 0; 2900 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, 2901 s_frequency, &freq); 2902 } 2903 2904 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) { 2905 struct v4l2_subdev_format format = { 2906 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 2907 }; 2908 2909 format.format.width = hdw->res_hor_val; 2910 format.format.height = hdw->res_ver_val; 2911 format.format.code = MEDIA_BUS_FMT_FIXED; 2912 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)", 2913 format.format.width, format.format.height); 2914 v4l2_device_call_all(&hdw->v4l2_dev, 0, pad, set_fmt, 2915 NULL, &format); 2916 } 2917 2918 if (hdw->srate_dirty || hdw->force_dirty) { 2919 u32 val; 2920 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d", 2921 hdw->srate_val); 2922 switch (hdw->srate_val) { 2923 default: 2924 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000: 2925 val = 48000; 2926 break; 2927 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100: 2928 val = 44100; 2929 break; 2930 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000: 2931 val = 32000; 2932 break; 2933 } 2934 v4l2_device_call_all(&hdw->v4l2_dev, 0, 2935 audio, s_clock_freq, val); 2936 } 2937 2938 /* Unable to set crop parameters; there is apparently no equivalent 2939 for VIDIOC_S_CROP */ 2940 2941 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) { 2942 id = sd->grp_id; 2943 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue; 2944 fp = pvr2_module_update_functions[id]; 2945 if (!fp) continue; 2946 (*fp)(hdw, sd); 2947 } 2948 2949 if (hdw->tuner_signal_stale || hdw->cropcap_stale) { 2950 pvr2_hdw_status_poll(hdw); 2951 } 2952 } 2953 2954 2955 /* Figure out if we need to commit control changes. If so, mark internal 2956 state flags to indicate this fact and return true. Otherwise do nothing 2957 else and return false. */ 2958 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw) 2959 { 2960 unsigned int idx; 2961 struct pvr2_ctrl *cptr; 2962 int value; 2963 int commit_flag = hdw->force_dirty; 2964 char buf[100]; 2965 unsigned int bcnt,ccnt; 2966 2967 for (idx = 0; idx < hdw->control_cnt; idx++) { 2968 cptr = hdw->controls + idx; 2969 if (!cptr->info->is_dirty) continue; 2970 if (!cptr->info->is_dirty(cptr)) continue; 2971 commit_flag = !0; 2972 2973 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue; 2974 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ", 2975 cptr->info->name); 2976 value = 0; 2977 cptr->info->get_value(cptr,&value); 2978 pvr2_ctrl_value_to_sym_internal(cptr,~0,value, 2979 buf+bcnt, 2980 sizeof(buf)-bcnt,&ccnt); 2981 bcnt += ccnt; 2982 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>", 2983 get_ctrl_typename(cptr->info->type)); 2984 pvr2_trace(PVR2_TRACE_CTL, 2985 "/*--TRACE_COMMIT--*/ %.*s", 2986 bcnt,buf); 2987 } 2988 2989 if (!commit_flag) { 2990 /* Nothing has changed */ 2991 return 0; 2992 } 2993 2994 hdw->state_pipeline_config = 0; 2995 trace_stbit("state_pipeline_config",hdw->state_pipeline_config); 2996 pvr2_hdw_state_sched(hdw); 2997 2998 return !0; 2999 } 3000 3001 3002 /* Perform all operations needed to commit all control changes. This must 3003 be performed in synchronization with the pipeline state and is thus 3004 expected to be called as part of the driver's worker thread. Return 3005 true if commit successful, otherwise return false to indicate that 3006 commit isn't possible at this time. */ 3007 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw) 3008 { 3009 unsigned int idx; 3010 struct pvr2_ctrl *cptr; 3011 int disruptive_change; 3012 3013 if (hdw->input_dirty && hdw->state_pathway_ok && 3014 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ? 3015 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) != 3016 hdw->pathway_state)) { 3017 /* Change of mode being asked for... */ 3018 hdw->state_pathway_ok = 0; 3019 trace_stbit("state_pathway_ok", hdw->state_pathway_ok); 3020 } 3021 if (!hdw->state_pathway_ok) { 3022 /* Can't commit anything until pathway is ok. */ 3023 return 0; 3024 } 3025 3026 /* Handle some required side effects when the video standard is 3027 changed.... */ 3028 if (hdw->std_dirty) { 3029 int nvres; 3030 int gop_size; 3031 if (hdw->std_mask_cur & V4L2_STD_525_60) { 3032 nvres = 480; 3033 gop_size = 15; 3034 } else { 3035 nvres = 576; 3036 gop_size = 12; 3037 } 3038 /* Rewrite the vertical resolution to be appropriate to the 3039 video standard that has been selected. */ 3040 if (nvres != hdw->res_ver_val) { 3041 hdw->res_ver_val = nvres; 3042 hdw->res_ver_dirty = !0; 3043 } 3044 /* Rewrite the GOP size to be appropriate to the video 3045 standard that has been selected. */ 3046 if (gop_size != hdw->enc_ctl_state.video_gop_size) { 3047 struct v4l2_ext_controls cs; 3048 struct v4l2_ext_control c1; 3049 memset(&cs, 0, sizeof(cs)); 3050 memset(&c1, 0, sizeof(c1)); 3051 cs.controls = &c1; 3052 cs.count = 1; 3053 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE; 3054 c1.value = gop_size; 3055 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs, 3056 VIDIOC_S_EXT_CTRLS); 3057 } 3058 } 3059 3060 /* The broadcast decoder can only scale down, so if 3061 * res_*_dirty && crop window < output format ==> enlarge crop. 3062 * 3063 * The mpeg encoder receives fields of res_hor_val dots and 3064 * res_ver_val halflines. Limits: hor<=720, ver<=576. 3065 */ 3066 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) { 3067 hdw->cropw_val = hdw->res_hor_val; 3068 hdw->cropw_dirty = !0; 3069 } else if (hdw->cropw_dirty) { 3070 hdw->res_hor_dirty = !0; /* must rescale */ 3071 hdw->res_hor_val = min(720, hdw->cropw_val); 3072 } 3073 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) { 3074 hdw->croph_val = hdw->res_ver_val; 3075 hdw->croph_dirty = !0; 3076 } else if (hdw->croph_dirty) { 3077 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576; 3078 hdw->res_ver_dirty = !0; 3079 hdw->res_ver_val = min(nvres, hdw->croph_val); 3080 } 3081 3082 /* If any of the below has changed, then we can't do the update 3083 while the pipeline is running. Pipeline must be paused first 3084 and decoder -> encoder connection be made quiescent before we 3085 can proceed. */ 3086 disruptive_change = 3087 (hdw->std_dirty || 3088 hdw->enc_unsafe_stale || 3089 hdw->srate_dirty || 3090 hdw->res_ver_dirty || 3091 hdw->res_hor_dirty || 3092 hdw->cropw_dirty || 3093 hdw->croph_dirty || 3094 hdw->input_dirty || 3095 (hdw->active_stream_type != hdw->desired_stream_type)); 3096 if (disruptive_change && !hdw->state_pipeline_idle) { 3097 /* Pipeline is not idle; we can't proceed. Arrange to 3098 cause pipeline to stop so that we can try this again 3099 later.... */ 3100 hdw->state_pipeline_pause = !0; 3101 return 0; 3102 } 3103 3104 if (hdw->srate_dirty) { 3105 /* Write new sample rate into control structure since 3106 * the master copy is stale. We must track srate 3107 * separate from the mpeg control structure because 3108 * other logic also uses this value. */ 3109 struct v4l2_ext_controls cs; 3110 struct v4l2_ext_control c1; 3111 memset(&cs,0,sizeof(cs)); 3112 memset(&c1,0,sizeof(c1)); 3113 cs.controls = &c1; 3114 cs.count = 1; 3115 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ; 3116 c1.value = hdw->srate_val; 3117 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS); 3118 } 3119 3120 if (hdw->active_stream_type != hdw->desired_stream_type) { 3121 /* Handle any side effects of stream config here */ 3122 hdw->active_stream_type = hdw->desired_stream_type; 3123 } 3124 3125 if (hdw->hdw_desc->signal_routing_scheme == 3126 PVR2_ROUTING_SCHEME_GOTVIEW) { 3127 u32 b; 3128 /* Handle GOTVIEW audio switching */ 3129 pvr2_hdw_gpio_get_out(hdw,&b); 3130 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { 3131 /* Set GPIO 11 */ 3132 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0); 3133 } else { 3134 /* Clear GPIO 11 */ 3135 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0); 3136 } 3137 } 3138 3139 /* Check and update state for all sub-devices. */ 3140 pvr2_subdev_update(hdw); 3141 3142 hdw->tuner_updated = 0; 3143 hdw->force_dirty = 0; 3144 for (idx = 0; idx < hdw->control_cnt; idx++) { 3145 cptr = hdw->controls + idx; 3146 if (!cptr->info->clear_dirty) continue; 3147 cptr->info->clear_dirty(cptr); 3148 } 3149 3150 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) && 3151 hdw->state_encoder_run) { 3152 /* If encoder isn't running or it can't be touched, then 3153 this will get worked out later when we start the 3154 encoder. */ 3155 if (pvr2_encoder_adjust(hdw) < 0) return !0; 3156 } 3157 3158 hdw->state_pipeline_config = !0; 3159 /* Hardware state may have changed in a way to cause the cropping 3160 capabilities to have changed. So mark it stale, which will 3161 cause a later re-fetch. */ 3162 trace_stbit("state_pipeline_config",hdw->state_pipeline_config); 3163 return !0; 3164 } 3165 3166 3167 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw) 3168 { 3169 int fl; 3170 LOCK_TAKE(hdw->big_lock); 3171 fl = pvr2_hdw_commit_setup(hdw); 3172 LOCK_GIVE(hdw->big_lock); 3173 if (!fl) return 0; 3174 return pvr2_hdw_wait(hdw,0); 3175 } 3176 3177 3178 static void pvr2_hdw_worker_poll(struct work_struct *work) 3179 { 3180 int fl = 0; 3181 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll); 3182 LOCK_TAKE(hdw->big_lock); do { 3183 fl = pvr2_hdw_state_eval(hdw); 3184 } while (0); LOCK_GIVE(hdw->big_lock); 3185 if (fl && hdw->state_func) { 3186 hdw->state_func(hdw->state_data); 3187 } 3188 } 3189 3190 3191 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state) 3192 { 3193 return wait_event_interruptible( 3194 hdw->state_wait_data, 3195 (hdw->state_stale == 0) && 3196 (!state || (hdw->master_state != state))); 3197 } 3198 3199 3200 /* Return name for this driver instance */ 3201 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw) 3202 { 3203 return hdw->name; 3204 } 3205 3206 3207 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw) 3208 { 3209 return hdw->hdw_desc->description; 3210 } 3211 3212 3213 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw) 3214 { 3215 return hdw->hdw_desc->shortname; 3216 } 3217 3218 3219 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw) 3220 { 3221 int result; 3222 LOCK_TAKE(hdw->ctl_lock); do { 3223 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED; 3224 result = pvr2_send_request(hdw, 3225 hdw->cmd_buffer,1, 3226 hdw->cmd_buffer,1); 3227 if (result < 0) break; 3228 result = (hdw->cmd_buffer[0] != 0); 3229 } while(0); LOCK_GIVE(hdw->ctl_lock); 3230 return result; 3231 } 3232 3233 3234 /* Execute poll of tuner status */ 3235 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw) 3236 { 3237 LOCK_TAKE(hdw->big_lock); do { 3238 pvr2_hdw_status_poll(hdw); 3239 } while (0); LOCK_GIVE(hdw->big_lock); 3240 } 3241 3242 3243 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw) 3244 { 3245 if (!hdw->cropcap_stale) { 3246 return 0; 3247 } 3248 pvr2_hdw_status_poll(hdw); 3249 if (hdw->cropcap_stale) { 3250 return -EIO; 3251 } 3252 return 0; 3253 } 3254 3255 3256 /* Return information about cropping capabilities */ 3257 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp) 3258 { 3259 int stat = 0; 3260 LOCK_TAKE(hdw->big_lock); 3261 stat = pvr2_hdw_check_cropcap(hdw); 3262 if (!stat) { 3263 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info)); 3264 } 3265 LOCK_GIVE(hdw->big_lock); 3266 return stat; 3267 } 3268 3269 3270 /* Return information about the tuner */ 3271 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp) 3272 { 3273 LOCK_TAKE(hdw->big_lock); do { 3274 if (hdw->tuner_signal_stale) { 3275 pvr2_hdw_status_poll(hdw); 3276 } 3277 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner)); 3278 } while (0); LOCK_GIVE(hdw->big_lock); 3279 return 0; 3280 } 3281 3282 3283 /* Get handle to video output stream */ 3284 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp) 3285 { 3286 return hp->vid_stream; 3287 } 3288 3289 3290 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw) 3291 { 3292 int nr = pvr2_hdw_get_unit_number(hdw); 3293 LOCK_TAKE(hdw->big_lock); 3294 do { 3295 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr); 3296 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status); 3297 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:"); 3298 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2"); 3299 pvr2_hdw_state_log_state(hdw); 3300 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr); 3301 } while (0); 3302 LOCK_GIVE(hdw->big_lock); 3303 } 3304 3305 3306 /* Grab EEPROM contents, needed for direct method. */ 3307 #define EEPROM_SIZE 8192 3308 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__) 3309 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw) 3310 { 3311 struct i2c_msg msg[2]; 3312 u8 *eeprom; 3313 u8 iadd[2]; 3314 u8 addr; 3315 u16 eepromSize; 3316 unsigned int offs; 3317 int ret; 3318 int mode16 = 0; 3319 unsigned pcnt,tcnt; 3320 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL); 3321 if (!eeprom) { 3322 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3323 "Failed to allocate memory required to read eeprom"); 3324 return NULL; 3325 } 3326 3327 trace_eeprom("Value for eeprom addr from controller was 0x%x", 3328 hdw->eeprom_addr); 3329 addr = hdw->eeprom_addr; 3330 /* Seems that if the high bit is set, then the *real* eeprom 3331 address is shifted right now bit position (noticed this in 3332 newer PVR USB2 hardware) */ 3333 if (addr & 0x80) addr >>= 1; 3334 3335 /* FX2 documentation states that a 16bit-addressed eeprom is 3336 expected if the I2C address is an odd number (yeah, this is 3337 strange but it's what they do) */ 3338 mode16 = (addr & 1); 3339 eepromSize = (mode16 ? EEPROM_SIZE : 256); 3340 trace_eeprom("Examining %d byte eeprom at location 0x%x using %d bit addressing", 3341 eepromSize, addr, 3342 mode16 ? 16 : 8); 3343 3344 msg[0].addr = addr; 3345 msg[0].flags = 0; 3346 msg[0].len = mode16 ? 2 : 1; 3347 msg[0].buf = iadd; 3348 msg[1].addr = addr; 3349 msg[1].flags = I2C_M_RD; 3350 3351 /* We have to do the actual eeprom data fetch ourselves, because 3352 (1) we're only fetching part of the eeprom, and (2) if we were 3353 getting the whole thing our I2C driver can't grab it in one 3354 pass - which is what tveeprom is otherwise going to attempt */ 3355 memset(eeprom,0,EEPROM_SIZE); 3356 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) { 3357 pcnt = 16; 3358 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt; 3359 offs = tcnt + (eepromSize - EEPROM_SIZE); 3360 if (mode16) { 3361 iadd[0] = offs >> 8; 3362 iadd[1] = offs; 3363 } else { 3364 iadd[0] = offs; 3365 } 3366 msg[1].len = pcnt; 3367 msg[1].buf = eeprom+tcnt; 3368 if ((ret = i2c_transfer(&hdw->i2c_adap, 3369 msg,ARRAY_SIZE(msg))) != 2) { 3370 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3371 "eeprom fetch set offs err=%d",ret); 3372 kfree(eeprom); 3373 return NULL; 3374 } 3375 } 3376 return eeprom; 3377 } 3378 3379 3380 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, 3381 int mode, 3382 int enable_flag) 3383 { 3384 int ret; 3385 u16 address; 3386 unsigned int pipe; 3387 LOCK_TAKE(hdw->big_lock); do { 3388 if ((hdw->fw_buffer == NULL) == !enable_flag) break; 3389 3390 if (!enable_flag) { 3391 pvr2_trace(PVR2_TRACE_FIRMWARE, 3392 "Cleaning up after CPU firmware fetch"); 3393 kfree(hdw->fw_buffer); 3394 hdw->fw_buffer = NULL; 3395 hdw->fw_size = 0; 3396 if (hdw->fw_cpu_flag) { 3397 /* Now release the CPU. It will disconnect 3398 and reconnect later. */ 3399 pvr2_hdw_cpureset_assert(hdw,0); 3400 } 3401 break; 3402 } 3403 3404 hdw->fw_cpu_flag = (mode != 2); 3405 if (hdw->fw_cpu_flag) { 3406 hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000; 3407 pvr2_trace(PVR2_TRACE_FIRMWARE, 3408 "Preparing to suck out CPU firmware (size=%u)", 3409 hdw->fw_size); 3410 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL); 3411 if (!hdw->fw_buffer) { 3412 hdw->fw_size = 0; 3413 break; 3414 } 3415 3416 /* We have to hold the CPU during firmware upload. */ 3417 pvr2_hdw_cpureset_assert(hdw,1); 3418 3419 /* download the firmware from address 0000-1fff in 2048 3420 (=0x800) bytes chunk. */ 3421 3422 pvr2_trace(PVR2_TRACE_FIRMWARE, 3423 "Grabbing CPU firmware"); 3424 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0); 3425 for(address = 0; address < hdw->fw_size; 3426 address += 0x800) { 3427 ret = usb_control_msg(hdw->usb_dev,pipe, 3428 0xa0,0xc0, 3429 address,0, 3430 hdw->fw_buffer+address, 3431 0x800,HZ); 3432 if (ret < 0) break; 3433 } 3434 3435 pvr2_trace(PVR2_TRACE_FIRMWARE, 3436 "Done grabbing CPU firmware"); 3437 } else { 3438 pvr2_trace(PVR2_TRACE_FIRMWARE, 3439 "Sucking down EEPROM contents"); 3440 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw); 3441 if (!hdw->fw_buffer) { 3442 pvr2_trace(PVR2_TRACE_FIRMWARE, 3443 "EEPROM content suck failed."); 3444 break; 3445 } 3446 hdw->fw_size = EEPROM_SIZE; 3447 pvr2_trace(PVR2_TRACE_FIRMWARE, 3448 "Done sucking down EEPROM contents"); 3449 } 3450 3451 } while (0); LOCK_GIVE(hdw->big_lock); 3452 } 3453 3454 3455 /* Return true if we're in a mode for retrieval CPU firmware */ 3456 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw) 3457 { 3458 return hdw->fw_buffer != NULL; 3459 } 3460 3461 3462 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs, 3463 char *buf,unsigned int cnt) 3464 { 3465 int ret = -EINVAL; 3466 LOCK_TAKE(hdw->big_lock); do { 3467 if (!buf) break; 3468 if (!cnt) break; 3469 3470 if (!hdw->fw_buffer) { 3471 ret = -EIO; 3472 break; 3473 } 3474 3475 if (offs >= hdw->fw_size) { 3476 pvr2_trace(PVR2_TRACE_FIRMWARE, 3477 "Read firmware data offs=%d EOF", 3478 offs); 3479 ret = 0; 3480 break; 3481 } 3482 3483 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs; 3484 3485 memcpy(buf,hdw->fw_buffer+offs,cnt); 3486 3487 pvr2_trace(PVR2_TRACE_FIRMWARE, 3488 "Read firmware data offs=%d cnt=%d", 3489 offs,cnt); 3490 ret = cnt; 3491 } while (0); LOCK_GIVE(hdw->big_lock); 3492 3493 return ret; 3494 } 3495 3496 3497 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw, 3498 enum pvr2_v4l_type index) 3499 { 3500 switch (index) { 3501 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video; 3502 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi; 3503 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio; 3504 default: return -1; 3505 } 3506 } 3507 3508 3509 /* Store a v4l minor device number */ 3510 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw, 3511 enum pvr2_v4l_type index,int v) 3512 { 3513 switch (index) { 3514 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;break; 3515 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;break; 3516 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;break; 3517 default: break; 3518 } 3519 } 3520 3521 3522 static void pvr2_ctl_write_complete(struct urb *urb) 3523 { 3524 struct pvr2_hdw *hdw = urb->context; 3525 hdw->ctl_write_pend_flag = 0; 3526 if (hdw->ctl_read_pend_flag) return; 3527 complete(&hdw->ctl_done); 3528 } 3529 3530 3531 static void pvr2_ctl_read_complete(struct urb *urb) 3532 { 3533 struct pvr2_hdw *hdw = urb->context; 3534 hdw->ctl_read_pend_flag = 0; 3535 if (hdw->ctl_write_pend_flag) return; 3536 complete(&hdw->ctl_done); 3537 } 3538 3539 struct hdw_timer { 3540 struct timer_list timer; 3541 struct pvr2_hdw *hdw; 3542 }; 3543 3544 static void pvr2_ctl_timeout(struct timer_list *t) 3545 { 3546 struct hdw_timer *timer = from_timer(timer, t, timer); 3547 struct pvr2_hdw *hdw = timer->hdw; 3548 3549 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) { 3550 hdw->ctl_timeout_flag = !0; 3551 if (hdw->ctl_write_pend_flag) 3552 usb_unlink_urb(hdw->ctl_write_urb); 3553 if (hdw->ctl_read_pend_flag) 3554 usb_unlink_urb(hdw->ctl_read_urb); 3555 } 3556 } 3557 3558 3559 /* Issue a command and get a response from the device. This extended 3560 version includes a probe flag (which if set means that device errors 3561 should not be logged or treated as fatal) and a timeout in jiffies. 3562 This can be used to non-lethally probe the health of endpoint 1. */ 3563 static int pvr2_send_request_ex(struct pvr2_hdw *hdw, 3564 unsigned int timeout,int probe_fl, 3565 void *write_data,unsigned int write_len, 3566 void *read_data,unsigned int read_len) 3567 { 3568 unsigned int idx; 3569 int status = 0; 3570 struct hdw_timer timer = { 3571 .hdw = hdw, 3572 }; 3573 3574 if (!hdw->ctl_lock_held) { 3575 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3576 "Attempted to execute control transfer without lock!!"); 3577 return -EDEADLK; 3578 } 3579 if (!hdw->flag_ok && !probe_fl) { 3580 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3581 "Attempted to execute control transfer when device not ok"); 3582 return -EIO; 3583 } 3584 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) { 3585 if (!probe_fl) { 3586 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3587 "Attempted to execute control transfer when USB is disconnected"); 3588 } 3589 return -ENOTTY; 3590 } 3591 3592 /* Ensure that we have sane parameters */ 3593 if (!write_data) write_len = 0; 3594 if (!read_data) read_len = 0; 3595 if (write_len > PVR2_CTL_BUFFSIZE) { 3596 pvr2_trace( 3597 PVR2_TRACE_ERROR_LEGS, 3598 "Attempted to execute %d byte control-write transfer (limit=%d)", 3599 write_len,PVR2_CTL_BUFFSIZE); 3600 return -EINVAL; 3601 } 3602 if (read_len > PVR2_CTL_BUFFSIZE) { 3603 pvr2_trace( 3604 PVR2_TRACE_ERROR_LEGS, 3605 "Attempted to execute %d byte control-read transfer (limit=%d)", 3606 write_len,PVR2_CTL_BUFFSIZE); 3607 return -EINVAL; 3608 } 3609 if ((!write_len) && (!read_len)) { 3610 pvr2_trace( 3611 PVR2_TRACE_ERROR_LEGS, 3612 "Attempted to execute null control transfer?"); 3613 return -EINVAL; 3614 } 3615 3616 3617 hdw->cmd_debug_state = 1; 3618 if (write_len && write_data) 3619 hdw->cmd_debug_code = ((unsigned char *)write_data)[0]; 3620 else 3621 hdw->cmd_debug_code = 0; 3622 hdw->cmd_debug_write_len = write_len; 3623 hdw->cmd_debug_read_len = read_len; 3624 3625 /* Initialize common stuff */ 3626 init_completion(&hdw->ctl_done); 3627 hdw->ctl_timeout_flag = 0; 3628 hdw->ctl_write_pend_flag = 0; 3629 hdw->ctl_read_pend_flag = 0; 3630 timer_setup_on_stack(&timer.timer, pvr2_ctl_timeout, 0); 3631 timer.timer.expires = jiffies + timeout; 3632 3633 if (write_len && write_data) { 3634 hdw->cmd_debug_state = 2; 3635 /* Transfer write data to internal buffer */ 3636 for (idx = 0; idx < write_len; idx++) { 3637 hdw->ctl_write_buffer[idx] = 3638 ((unsigned char *)write_data)[idx]; 3639 } 3640 /* Initiate a write request */ 3641 usb_fill_bulk_urb(hdw->ctl_write_urb, 3642 hdw->usb_dev, 3643 usb_sndbulkpipe(hdw->usb_dev, 3644 PVR2_CTL_WRITE_ENDPOINT), 3645 hdw->ctl_write_buffer, 3646 write_len, 3647 pvr2_ctl_write_complete, 3648 hdw); 3649 hdw->ctl_write_urb->actual_length = 0; 3650 hdw->ctl_write_pend_flag = !0; 3651 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL); 3652 if (status < 0) { 3653 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3654 "Failed to submit write-control URB status=%d", 3655 status); 3656 hdw->ctl_write_pend_flag = 0; 3657 goto done; 3658 } 3659 } 3660 3661 if (read_len) { 3662 hdw->cmd_debug_state = 3; 3663 memset(hdw->ctl_read_buffer,0x43,read_len); 3664 /* Initiate a read request */ 3665 usb_fill_bulk_urb(hdw->ctl_read_urb, 3666 hdw->usb_dev, 3667 usb_rcvbulkpipe(hdw->usb_dev, 3668 PVR2_CTL_READ_ENDPOINT), 3669 hdw->ctl_read_buffer, 3670 read_len, 3671 pvr2_ctl_read_complete, 3672 hdw); 3673 hdw->ctl_read_urb->actual_length = 0; 3674 hdw->ctl_read_pend_flag = !0; 3675 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL); 3676 if (status < 0) { 3677 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3678 "Failed to submit read-control URB status=%d", 3679 status); 3680 hdw->ctl_read_pend_flag = 0; 3681 goto done; 3682 } 3683 } 3684 3685 /* Start timer */ 3686 add_timer(&timer.timer); 3687 3688 /* Now wait for all I/O to complete */ 3689 hdw->cmd_debug_state = 4; 3690 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) { 3691 wait_for_completion(&hdw->ctl_done); 3692 } 3693 hdw->cmd_debug_state = 5; 3694 3695 /* Stop timer */ 3696 del_timer_sync(&timer.timer); 3697 3698 hdw->cmd_debug_state = 6; 3699 status = 0; 3700 3701 if (hdw->ctl_timeout_flag) { 3702 status = -ETIMEDOUT; 3703 if (!probe_fl) { 3704 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3705 "Timed out control-write"); 3706 } 3707 goto done; 3708 } 3709 3710 if (write_len) { 3711 /* Validate results of write request */ 3712 if ((hdw->ctl_write_urb->status != 0) && 3713 (hdw->ctl_write_urb->status != -ENOENT) && 3714 (hdw->ctl_write_urb->status != -ESHUTDOWN) && 3715 (hdw->ctl_write_urb->status != -ECONNRESET)) { 3716 /* USB subsystem is reporting some kind of failure 3717 on the write */ 3718 status = hdw->ctl_write_urb->status; 3719 if (!probe_fl) { 3720 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3721 "control-write URB failure, status=%d", 3722 status); 3723 } 3724 goto done; 3725 } 3726 if (hdw->ctl_write_urb->actual_length < write_len) { 3727 /* Failed to write enough data */ 3728 status = -EIO; 3729 if (!probe_fl) { 3730 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3731 "control-write URB short, expected=%d got=%d", 3732 write_len, 3733 hdw->ctl_write_urb->actual_length); 3734 } 3735 goto done; 3736 } 3737 } 3738 if (read_len && read_data) { 3739 /* Validate results of read request */ 3740 if ((hdw->ctl_read_urb->status != 0) && 3741 (hdw->ctl_read_urb->status != -ENOENT) && 3742 (hdw->ctl_read_urb->status != -ESHUTDOWN) && 3743 (hdw->ctl_read_urb->status != -ECONNRESET)) { 3744 /* USB subsystem is reporting some kind of failure 3745 on the read */ 3746 status = hdw->ctl_read_urb->status; 3747 if (!probe_fl) { 3748 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3749 "control-read URB failure, status=%d", 3750 status); 3751 } 3752 goto done; 3753 } 3754 if (hdw->ctl_read_urb->actual_length < read_len) { 3755 /* Failed to read enough data */ 3756 status = -EIO; 3757 if (!probe_fl) { 3758 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3759 "control-read URB short, expected=%d got=%d", 3760 read_len, 3761 hdw->ctl_read_urb->actual_length); 3762 } 3763 goto done; 3764 } 3765 /* Transfer retrieved data out from internal buffer */ 3766 for (idx = 0; idx < read_len; idx++) { 3767 ((unsigned char *)read_data)[idx] = 3768 hdw->ctl_read_buffer[idx]; 3769 } 3770 } 3771 3772 done: 3773 3774 hdw->cmd_debug_state = 0; 3775 if ((status < 0) && (!probe_fl)) { 3776 pvr2_hdw_render_useless(hdw); 3777 } 3778 destroy_timer_on_stack(&timer.timer); 3779 3780 return status; 3781 } 3782 3783 3784 int pvr2_send_request(struct pvr2_hdw *hdw, 3785 void *write_data,unsigned int write_len, 3786 void *read_data,unsigned int read_len) 3787 { 3788 return pvr2_send_request_ex(hdw,HZ*4,0, 3789 write_data,write_len, 3790 read_data,read_len); 3791 } 3792 3793 3794 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode) 3795 { 3796 int ret; 3797 unsigned int cnt = 1; 3798 unsigned int args = 0; 3799 LOCK_TAKE(hdw->ctl_lock); 3800 hdw->cmd_buffer[0] = cmdcode & 0xffu; 3801 args = (cmdcode >> 8) & 0xffu; 3802 args = (args > 2) ? 2 : args; 3803 if (args) { 3804 cnt += args; 3805 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu; 3806 if (args > 1) { 3807 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu; 3808 } 3809 } 3810 if (pvrusb2_debug & PVR2_TRACE_INIT) { 3811 unsigned int idx; 3812 unsigned int ccnt,bcnt; 3813 char tbuf[50]; 3814 cmdcode &= 0xffu; 3815 bcnt = 0; 3816 ccnt = scnprintf(tbuf+bcnt, 3817 sizeof(tbuf)-bcnt, 3818 "Sending FX2 command 0x%x",cmdcode); 3819 bcnt += ccnt; 3820 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) { 3821 if (pvr2_fx2cmd_desc[idx].id == cmdcode) { 3822 ccnt = scnprintf(tbuf+bcnt, 3823 sizeof(tbuf)-bcnt, 3824 " \"%s\"", 3825 pvr2_fx2cmd_desc[idx].desc); 3826 bcnt += ccnt; 3827 break; 3828 } 3829 } 3830 if (args) { 3831 ccnt = scnprintf(tbuf+bcnt, 3832 sizeof(tbuf)-bcnt, 3833 " (%u",hdw->cmd_buffer[1]); 3834 bcnt += ccnt; 3835 if (args > 1) { 3836 ccnt = scnprintf(tbuf+bcnt, 3837 sizeof(tbuf)-bcnt, 3838 ",%u",hdw->cmd_buffer[2]); 3839 bcnt += ccnt; 3840 } 3841 ccnt = scnprintf(tbuf+bcnt, 3842 sizeof(tbuf)-bcnt, 3843 ")"); 3844 bcnt += ccnt; 3845 } 3846 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf); 3847 } 3848 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0); 3849 LOCK_GIVE(hdw->ctl_lock); 3850 return ret; 3851 } 3852 3853 3854 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data) 3855 { 3856 int ret; 3857 3858 LOCK_TAKE(hdw->ctl_lock); 3859 3860 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */ 3861 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data); 3862 hdw->cmd_buffer[5] = 0; 3863 hdw->cmd_buffer[6] = (reg >> 8) & 0xff; 3864 hdw->cmd_buffer[7] = reg & 0xff; 3865 3866 3867 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0); 3868 3869 LOCK_GIVE(hdw->ctl_lock); 3870 3871 return ret; 3872 } 3873 3874 3875 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data) 3876 { 3877 int ret = 0; 3878 3879 LOCK_TAKE(hdw->ctl_lock); 3880 3881 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */ 3882 hdw->cmd_buffer[1] = 0; 3883 hdw->cmd_buffer[2] = 0; 3884 hdw->cmd_buffer[3] = 0; 3885 hdw->cmd_buffer[4] = 0; 3886 hdw->cmd_buffer[5] = 0; 3887 hdw->cmd_buffer[6] = (reg >> 8) & 0xff; 3888 hdw->cmd_buffer[7] = reg & 0xff; 3889 3890 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4); 3891 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0); 3892 3893 LOCK_GIVE(hdw->ctl_lock); 3894 3895 return ret; 3896 } 3897 3898 3899 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw) 3900 { 3901 if (!hdw->flag_ok) return; 3902 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3903 "Device being rendered inoperable"); 3904 if (hdw->vid_stream) { 3905 pvr2_stream_setup(hdw->vid_stream,NULL,0,0); 3906 } 3907 hdw->flag_ok = 0; 3908 trace_stbit("flag_ok",hdw->flag_ok); 3909 pvr2_hdw_state_sched(hdw); 3910 } 3911 3912 3913 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw) 3914 { 3915 int ret; 3916 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset..."); 3917 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL); 3918 if (ret == 0) { 3919 ret = usb_reset_device(hdw->usb_dev); 3920 usb_unlock_device(hdw->usb_dev); 3921 } else { 3922 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3923 "Failed to lock USB device ret=%d",ret); 3924 } 3925 if (init_pause_msec) { 3926 pvr2_trace(PVR2_TRACE_INFO, 3927 "Waiting %u msec for hardware to settle", 3928 init_pause_msec); 3929 msleep(init_pause_msec); 3930 } 3931 3932 } 3933 3934 3935 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val) 3936 { 3937 char *da; 3938 unsigned int pipe; 3939 int ret; 3940 3941 if (!hdw->usb_dev) return; 3942 3943 da = kmalloc(16, GFP_KERNEL); 3944 3945 if (da == NULL) { 3946 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3947 "Unable to allocate memory to control CPU reset"); 3948 return; 3949 } 3950 3951 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val); 3952 3953 da[0] = val ? 0x01 : 0x00; 3954 3955 /* Write the CPUCS register on the 8051. The lsb of the register 3956 is the reset bit; a 1 asserts reset while a 0 clears it. */ 3957 pipe = usb_sndctrlpipe(hdw->usb_dev, 0); 3958 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ); 3959 if (ret < 0) { 3960 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3961 "cpureset_assert(%d) error=%d",val,ret); 3962 pvr2_hdw_render_useless(hdw); 3963 } 3964 3965 kfree(da); 3966 } 3967 3968 3969 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw) 3970 { 3971 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET); 3972 } 3973 3974 3975 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw) 3976 { 3977 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON); 3978 } 3979 3980 3981 3982 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw) 3983 { 3984 pvr2_trace(PVR2_TRACE_INIT, 3985 "Requesting decoder reset"); 3986 if (hdw->decoder_client_id) { 3987 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id, 3988 core, reset, 0); 3989 pvr2_hdw_cx25840_vbi_hack(hdw); 3990 return 0; 3991 } 3992 pvr2_trace(PVR2_TRACE_INIT, 3993 "Unable to reset decoder: nothing attached"); 3994 return -ENOTTY; 3995 } 3996 3997 3998 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff) 3999 { 4000 hdw->flag_ok = !0; 4001 return pvr2_issue_simple_cmd(hdw, 4002 FX2CMD_HCW_DEMOD_RESETIN | 4003 (1 << 8) | 4004 ((onoff ? 1 : 0) << 16)); 4005 } 4006 4007 4008 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff) 4009 { 4010 hdw->flag_ok = !0; 4011 return pvr2_issue_simple_cmd(hdw,(onoff ? 4012 FX2CMD_ONAIR_DTV_POWER_ON : 4013 FX2CMD_ONAIR_DTV_POWER_OFF)); 4014 } 4015 4016 4017 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw, 4018 int onoff) 4019 { 4020 return pvr2_issue_simple_cmd(hdw,(onoff ? 4021 FX2CMD_ONAIR_DTV_STREAMING_ON : 4022 FX2CMD_ONAIR_DTV_STREAMING_OFF)); 4023 } 4024 4025 4026 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl) 4027 { 4028 int cmode; 4029 /* Compare digital/analog desired setting with current setting. If 4030 they don't match, fix it... */ 4031 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG); 4032 if (cmode == hdw->pathway_state) { 4033 /* They match; nothing to do */ 4034 return; 4035 } 4036 4037 switch (hdw->hdw_desc->digital_control_scheme) { 4038 case PVR2_DIGITAL_SCHEME_HAUPPAUGE: 4039 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl); 4040 if (cmode == PVR2_PATHWAY_ANALOG) { 4041 /* If moving to analog mode, also force the decoder 4042 to reset. If no decoder is attached, then it's 4043 ok to ignore this because if/when the decoder 4044 attaches, it will reset itself at that time. */ 4045 pvr2_hdw_cmd_decoder_reset(hdw); 4046 } 4047 break; 4048 case PVR2_DIGITAL_SCHEME_ONAIR: 4049 /* Supposedly we should always have the power on whether in 4050 digital or analog mode. But for now do what appears to 4051 work... */ 4052 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl); 4053 break; 4054 default: break; 4055 } 4056 4057 pvr2_hdw_untrip_unlocked(hdw); 4058 hdw->pathway_state = cmode; 4059 } 4060 4061 4062 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff) 4063 { 4064 /* change some GPIO data 4065 * 4066 * note: bit d7 of dir appears to control the LED, 4067 * so we shut it off here. 4068 * 4069 */ 4070 if (onoff) { 4071 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481); 4072 } else { 4073 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401); 4074 } 4075 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000); 4076 } 4077 4078 4079 typedef void (*led_method_func)(struct pvr2_hdw *,int); 4080 4081 static led_method_func led_methods[] = { 4082 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge, 4083 }; 4084 4085 4086 /* Toggle LED */ 4087 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff) 4088 { 4089 unsigned int scheme_id; 4090 led_method_func fp; 4091 4092 if ((!onoff) == (!hdw->led_on)) return; 4093 4094 hdw->led_on = onoff != 0; 4095 4096 scheme_id = hdw->hdw_desc->led_scheme; 4097 if (scheme_id < ARRAY_SIZE(led_methods)) { 4098 fp = led_methods[scheme_id]; 4099 } else { 4100 fp = NULL; 4101 } 4102 4103 if (fp) (*fp)(hdw,onoff); 4104 } 4105 4106 4107 /* Stop / start video stream transport */ 4108 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl) 4109 { 4110 int ret; 4111 4112 /* If we're in analog mode, then just issue the usual analog 4113 command. */ 4114 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) { 4115 return pvr2_issue_simple_cmd(hdw, 4116 (runFl ? 4117 FX2CMD_STREAMING_ON : 4118 FX2CMD_STREAMING_OFF)); 4119 /*Note: Not reached */ 4120 } 4121 4122 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) { 4123 /* Whoops, we don't know what mode we're in... */ 4124 return -EINVAL; 4125 } 4126 4127 /* To get here we have to be in digital mode. The mechanism here 4128 is unfortunately different for different vendors. So we switch 4129 on the device's digital scheme attribute in order to figure out 4130 what to do. */ 4131 switch (hdw->hdw_desc->digital_control_scheme) { 4132 case PVR2_DIGITAL_SCHEME_HAUPPAUGE: 4133 return pvr2_issue_simple_cmd(hdw, 4134 (runFl ? 4135 FX2CMD_HCW_DTV_STREAMING_ON : 4136 FX2CMD_HCW_DTV_STREAMING_OFF)); 4137 case PVR2_DIGITAL_SCHEME_ONAIR: 4138 ret = pvr2_issue_simple_cmd(hdw, 4139 (runFl ? 4140 FX2CMD_STREAMING_ON : 4141 FX2CMD_STREAMING_OFF)); 4142 if (ret) return ret; 4143 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl); 4144 default: 4145 return -EINVAL; 4146 } 4147 } 4148 4149 4150 /* Evaluate whether or not state_pathway_ok can change */ 4151 static int state_eval_pathway_ok(struct pvr2_hdw *hdw) 4152 { 4153 if (hdw->state_pathway_ok) { 4154 /* Nothing to do if pathway is already ok */ 4155 return 0; 4156 } 4157 if (!hdw->state_pipeline_idle) { 4158 /* Not allowed to change anything if pipeline is not idle */ 4159 return 0; 4160 } 4161 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV); 4162 hdw->state_pathway_ok = !0; 4163 trace_stbit("state_pathway_ok",hdw->state_pathway_ok); 4164 return !0; 4165 } 4166 4167 4168 /* Evaluate whether or not state_encoder_ok can change */ 4169 static int state_eval_encoder_ok(struct pvr2_hdw *hdw) 4170 { 4171 if (hdw->state_encoder_ok) return 0; 4172 if (hdw->flag_tripped) return 0; 4173 if (hdw->state_encoder_run) return 0; 4174 if (hdw->state_encoder_config) return 0; 4175 if (hdw->state_decoder_run) return 0; 4176 if (hdw->state_usbstream_run) return 0; 4177 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) { 4178 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0; 4179 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) { 4180 return 0; 4181 } 4182 4183 if (pvr2_upload_firmware2(hdw) < 0) { 4184 hdw->flag_tripped = !0; 4185 trace_stbit("flag_tripped",hdw->flag_tripped); 4186 return !0; 4187 } 4188 hdw->state_encoder_ok = !0; 4189 trace_stbit("state_encoder_ok",hdw->state_encoder_ok); 4190 return !0; 4191 } 4192 4193 4194 /* Evaluate whether or not state_encoder_config can change */ 4195 static int state_eval_encoder_config(struct pvr2_hdw *hdw) 4196 { 4197 if (hdw->state_encoder_config) { 4198 if (hdw->state_encoder_ok) { 4199 if (hdw->state_pipeline_req && 4200 !hdw->state_pipeline_pause) return 0; 4201 } 4202 hdw->state_encoder_config = 0; 4203 hdw->state_encoder_waitok = 0; 4204 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok); 4205 /* paranoia - solve race if timer just completed */ 4206 del_timer_sync(&hdw->encoder_wait_timer); 4207 } else { 4208 if (!hdw->state_pathway_ok || 4209 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) || 4210 !hdw->state_encoder_ok || 4211 !hdw->state_pipeline_idle || 4212 hdw->state_pipeline_pause || 4213 !hdw->state_pipeline_req || 4214 !hdw->state_pipeline_config) { 4215 /* We must reset the enforced wait interval if 4216 anything has happened that might have disturbed 4217 the encoder. This should be a rare case. */ 4218 if (timer_pending(&hdw->encoder_wait_timer)) { 4219 del_timer_sync(&hdw->encoder_wait_timer); 4220 } 4221 if (hdw->state_encoder_waitok) { 4222 /* Must clear the state - therefore we did 4223 something to a state bit and must also 4224 return true. */ 4225 hdw->state_encoder_waitok = 0; 4226 trace_stbit("state_encoder_waitok", 4227 hdw->state_encoder_waitok); 4228 return !0; 4229 } 4230 return 0; 4231 } 4232 if (!hdw->state_encoder_waitok) { 4233 if (!timer_pending(&hdw->encoder_wait_timer)) { 4234 /* waitok flag wasn't set and timer isn't 4235 running. Check flag once more to avoid 4236 a race then start the timer. This is 4237 the point when we measure out a minimal 4238 quiet interval before doing something to 4239 the encoder. */ 4240 if (!hdw->state_encoder_waitok) { 4241 hdw->encoder_wait_timer.expires = 4242 jiffies + msecs_to_jiffies( 4243 TIME_MSEC_ENCODER_WAIT); 4244 add_timer(&hdw->encoder_wait_timer); 4245 } 4246 } 4247 /* We can't continue until we know we have been 4248 quiet for the interval measured by this 4249 timer. */ 4250 return 0; 4251 } 4252 pvr2_encoder_configure(hdw); 4253 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0; 4254 } 4255 trace_stbit("state_encoder_config",hdw->state_encoder_config); 4256 return !0; 4257 } 4258 4259 4260 /* Return true if the encoder should not be running. */ 4261 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw) 4262 { 4263 if (!hdw->state_encoder_ok) { 4264 /* Encoder isn't healthy at the moment, so stop it. */ 4265 return !0; 4266 } 4267 if (!hdw->state_pathway_ok) { 4268 /* Mode is not understood at the moment (i.e. it wants to 4269 change), so encoder must be stopped. */ 4270 return !0; 4271 } 4272 4273 switch (hdw->pathway_state) { 4274 case PVR2_PATHWAY_ANALOG: 4275 if (!hdw->state_decoder_run) { 4276 /* We're in analog mode and the decoder is not 4277 running; thus the encoder should be stopped as 4278 well. */ 4279 return !0; 4280 } 4281 break; 4282 case PVR2_PATHWAY_DIGITAL: 4283 if (hdw->state_encoder_runok) { 4284 /* This is a funny case. We're in digital mode so 4285 really the encoder should be stopped. However 4286 if it really is running, only kill it after 4287 runok has been set. This gives a chance for the 4288 onair quirk to function (encoder must run 4289 briefly first, at least once, before onair 4290 digital streaming can work). */ 4291 return !0; 4292 } 4293 break; 4294 default: 4295 /* Unknown mode; so encoder should be stopped. */ 4296 return !0; 4297 } 4298 4299 /* If we get here, we haven't found a reason to stop the 4300 encoder. */ 4301 return 0; 4302 } 4303 4304 4305 /* Return true if the encoder should be running. */ 4306 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw) 4307 { 4308 if (!hdw->state_encoder_ok) { 4309 /* Don't run the encoder if it isn't healthy... */ 4310 return 0; 4311 } 4312 if (!hdw->state_pathway_ok) { 4313 /* Don't run the encoder if we don't (yet) know what mode 4314 we need to be in... */ 4315 return 0; 4316 } 4317 4318 switch (hdw->pathway_state) { 4319 case PVR2_PATHWAY_ANALOG: 4320 if (hdw->state_decoder_run && hdw->state_decoder_ready) { 4321 /* In analog mode, if the decoder is running, then 4322 run the encoder. */ 4323 return !0; 4324 } 4325 break; 4326 case PVR2_PATHWAY_DIGITAL: 4327 if ((hdw->hdw_desc->digital_control_scheme == 4328 PVR2_DIGITAL_SCHEME_ONAIR) && 4329 !hdw->state_encoder_runok) { 4330 /* This is a quirk. OnAir hardware won't stream 4331 digital until the encoder has been run at least 4332 once, for a minimal period of time (empiricially 4333 measured to be 1/4 second). So if we're on 4334 OnAir hardware and the encoder has never been 4335 run at all, then start the encoder. Normal 4336 state machine logic in the driver will 4337 automatically handle the remaining bits. */ 4338 return !0; 4339 } 4340 break; 4341 default: 4342 /* For completeness (unknown mode; encoder won't run ever) */ 4343 break; 4344 } 4345 /* If we get here, then we haven't found any reason to run the 4346 encoder, so don't run it. */ 4347 return 0; 4348 } 4349 4350 4351 /* Evaluate whether or not state_encoder_run can change */ 4352 static int state_eval_encoder_run(struct pvr2_hdw *hdw) 4353 { 4354 if (hdw->state_encoder_run) { 4355 if (!state_check_disable_encoder_run(hdw)) return 0; 4356 if (hdw->state_encoder_ok) { 4357 del_timer_sync(&hdw->encoder_run_timer); 4358 if (pvr2_encoder_stop(hdw) < 0) return !0; 4359 } 4360 hdw->state_encoder_run = 0; 4361 } else { 4362 if (!state_check_enable_encoder_run(hdw)) return 0; 4363 if (pvr2_encoder_start(hdw) < 0) return !0; 4364 hdw->state_encoder_run = !0; 4365 if (!hdw->state_encoder_runok) { 4366 hdw->encoder_run_timer.expires = jiffies + 4367 msecs_to_jiffies(TIME_MSEC_ENCODER_OK); 4368 add_timer(&hdw->encoder_run_timer); 4369 } 4370 } 4371 trace_stbit("state_encoder_run",hdw->state_encoder_run); 4372 return !0; 4373 } 4374 4375 4376 /* Timeout function for quiescent timer. */ 4377 static void pvr2_hdw_quiescent_timeout(struct timer_list *t) 4378 { 4379 struct pvr2_hdw *hdw = from_timer(hdw, t, quiescent_timer); 4380 hdw->state_decoder_quiescent = !0; 4381 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent); 4382 hdw->state_stale = !0; 4383 schedule_work(&hdw->workpoll); 4384 } 4385 4386 4387 /* Timeout function for decoder stabilization timer. */ 4388 static void pvr2_hdw_decoder_stabilization_timeout(struct timer_list *t) 4389 { 4390 struct pvr2_hdw *hdw = from_timer(hdw, t, decoder_stabilization_timer); 4391 hdw->state_decoder_ready = !0; 4392 trace_stbit("state_decoder_ready", hdw->state_decoder_ready); 4393 hdw->state_stale = !0; 4394 schedule_work(&hdw->workpoll); 4395 } 4396 4397 4398 /* Timeout function for encoder wait timer. */ 4399 static void pvr2_hdw_encoder_wait_timeout(struct timer_list *t) 4400 { 4401 struct pvr2_hdw *hdw = from_timer(hdw, t, encoder_wait_timer); 4402 hdw->state_encoder_waitok = !0; 4403 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok); 4404 hdw->state_stale = !0; 4405 schedule_work(&hdw->workpoll); 4406 } 4407 4408 4409 /* Timeout function for encoder run timer. */ 4410 static void pvr2_hdw_encoder_run_timeout(struct timer_list *t) 4411 { 4412 struct pvr2_hdw *hdw = from_timer(hdw, t, encoder_run_timer); 4413 if (!hdw->state_encoder_runok) { 4414 hdw->state_encoder_runok = !0; 4415 trace_stbit("state_encoder_runok",hdw->state_encoder_runok); 4416 hdw->state_stale = !0; 4417 schedule_work(&hdw->workpoll); 4418 } 4419 } 4420 4421 4422 /* Evaluate whether or not state_decoder_run can change */ 4423 static int state_eval_decoder_run(struct pvr2_hdw *hdw) 4424 { 4425 if (hdw->state_decoder_run) { 4426 if (hdw->state_encoder_ok) { 4427 if (hdw->state_pipeline_req && 4428 !hdw->state_pipeline_pause && 4429 hdw->state_pathway_ok) return 0; 4430 } 4431 if (!hdw->flag_decoder_missed) { 4432 pvr2_decoder_enable(hdw,0); 4433 } 4434 hdw->state_decoder_quiescent = 0; 4435 hdw->state_decoder_run = 0; 4436 /* paranoia - solve race if timer(s) just completed */ 4437 del_timer_sync(&hdw->quiescent_timer); 4438 /* Kill the stabilization timer, in case we're killing the 4439 encoder before the previous stabilization interval has 4440 been properly timed. */ 4441 del_timer_sync(&hdw->decoder_stabilization_timer); 4442 hdw->state_decoder_ready = 0; 4443 } else { 4444 if (!hdw->state_decoder_quiescent) { 4445 if (!timer_pending(&hdw->quiescent_timer)) { 4446 /* We don't do something about the 4447 quiescent timer until right here because 4448 we also want to catch cases where the 4449 decoder was already not running (like 4450 after initialization) as opposed to 4451 knowing that we had just stopped it. 4452 The second flag check is here to cover a 4453 race - the timer could have run and set 4454 this flag just after the previous check 4455 but before we did the pending check. */ 4456 if (!hdw->state_decoder_quiescent) { 4457 hdw->quiescent_timer.expires = 4458 jiffies + msecs_to_jiffies( 4459 TIME_MSEC_DECODER_WAIT); 4460 add_timer(&hdw->quiescent_timer); 4461 } 4462 } 4463 /* Don't allow decoder to start again until it has 4464 been quiesced first. This little detail should 4465 hopefully further stabilize the encoder. */ 4466 return 0; 4467 } 4468 if (!hdw->state_pathway_ok || 4469 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) || 4470 !hdw->state_pipeline_req || 4471 hdw->state_pipeline_pause || 4472 !hdw->state_pipeline_config || 4473 !hdw->state_encoder_config || 4474 !hdw->state_encoder_ok) return 0; 4475 del_timer_sync(&hdw->quiescent_timer); 4476 if (hdw->flag_decoder_missed) return 0; 4477 if (pvr2_decoder_enable(hdw,!0) < 0) return 0; 4478 hdw->state_decoder_quiescent = 0; 4479 hdw->state_decoder_ready = 0; 4480 hdw->state_decoder_run = !0; 4481 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) { 4482 hdw->decoder_stabilization_timer.expires = 4483 jiffies + msecs_to_jiffies( 4484 TIME_MSEC_DECODER_STABILIZATION_WAIT); 4485 add_timer(&hdw->decoder_stabilization_timer); 4486 } else { 4487 hdw->state_decoder_ready = !0; 4488 } 4489 } 4490 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent); 4491 trace_stbit("state_decoder_run",hdw->state_decoder_run); 4492 trace_stbit("state_decoder_ready", hdw->state_decoder_ready); 4493 return !0; 4494 } 4495 4496 4497 /* Evaluate whether or not state_usbstream_run can change */ 4498 static int state_eval_usbstream_run(struct pvr2_hdw *hdw) 4499 { 4500 if (hdw->state_usbstream_run) { 4501 int fl = !0; 4502 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) { 4503 fl = (hdw->state_encoder_ok && 4504 hdw->state_encoder_run); 4505 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) && 4506 (hdw->hdw_desc->flag_digital_requires_cx23416)) { 4507 fl = hdw->state_encoder_ok; 4508 } 4509 if (fl && 4510 hdw->state_pipeline_req && 4511 !hdw->state_pipeline_pause && 4512 hdw->state_pathway_ok) { 4513 return 0; 4514 } 4515 pvr2_hdw_cmd_usbstream(hdw,0); 4516 hdw->state_usbstream_run = 0; 4517 } else { 4518 if (!hdw->state_pipeline_req || 4519 hdw->state_pipeline_pause || 4520 !hdw->state_pathway_ok) return 0; 4521 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) { 4522 if (!hdw->state_encoder_ok || 4523 !hdw->state_encoder_run) return 0; 4524 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) && 4525 (hdw->hdw_desc->flag_digital_requires_cx23416)) { 4526 if (!hdw->state_encoder_ok) return 0; 4527 if (hdw->state_encoder_run) return 0; 4528 if (hdw->hdw_desc->digital_control_scheme == 4529 PVR2_DIGITAL_SCHEME_ONAIR) { 4530 /* OnAir digital receivers won't stream 4531 unless the analog encoder has run first. 4532 Why? I have no idea. But don't even 4533 try until we know the analog side is 4534 known to have run. */ 4535 if (!hdw->state_encoder_runok) return 0; 4536 } 4537 } 4538 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0; 4539 hdw->state_usbstream_run = !0; 4540 } 4541 trace_stbit("state_usbstream_run",hdw->state_usbstream_run); 4542 return !0; 4543 } 4544 4545 4546 /* Attempt to configure pipeline, if needed */ 4547 static int state_eval_pipeline_config(struct pvr2_hdw *hdw) 4548 { 4549 if (hdw->state_pipeline_config || 4550 hdw->state_pipeline_pause) return 0; 4551 pvr2_hdw_commit_execute(hdw); 4552 return !0; 4553 } 4554 4555 4556 /* Update pipeline idle and pipeline pause tracking states based on other 4557 inputs. This must be called whenever the other relevant inputs have 4558 changed. */ 4559 static int state_update_pipeline_state(struct pvr2_hdw *hdw) 4560 { 4561 unsigned int st; 4562 int updatedFl = 0; 4563 /* Update pipeline state */ 4564 st = !(hdw->state_encoder_run || 4565 hdw->state_decoder_run || 4566 hdw->state_usbstream_run || 4567 (!hdw->state_decoder_quiescent)); 4568 if (!st != !hdw->state_pipeline_idle) { 4569 hdw->state_pipeline_idle = st; 4570 updatedFl = !0; 4571 } 4572 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) { 4573 hdw->state_pipeline_pause = 0; 4574 updatedFl = !0; 4575 } 4576 return updatedFl; 4577 } 4578 4579 4580 typedef int (*state_eval_func)(struct pvr2_hdw *); 4581 4582 /* Set of functions to be run to evaluate various states in the driver. */ 4583 static const state_eval_func eval_funcs[] = { 4584 state_eval_pathway_ok, 4585 state_eval_pipeline_config, 4586 state_eval_encoder_ok, 4587 state_eval_encoder_config, 4588 state_eval_decoder_run, 4589 state_eval_encoder_run, 4590 state_eval_usbstream_run, 4591 }; 4592 4593 4594 /* Process various states and return true if we did anything interesting. */ 4595 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw) 4596 { 4597 unsigned int i; 4598 int state_updated = 0; 4599 int check_flag; 4600 4601 if (!hdw->state_stale) return 0; 4602 if ((hdw->fw1_state != FW1_STATE_OK) || 4603 !hdw->flag_ok) { 4604 hdw->state_stale = 0; 4605 return !0; 4606 } 4607 /* This loop is the heart of the entire driver. It keeps trying to 4608 evaluate various bits of driver state until nothing changes for 4609 one full iteration. Each "bit of state" tracks some global 4610 aspect of the driver, e.g. whether decoder should run, if 4611 pipeline is configured, usb streaming is on, etc. We separately 4612 evaluate each of those questions based on other driver state to 4613 arrive at the correct running configuration. */ 4614 do { 4615 check_flag = 0; 4616 state_update_pipeline_state(hdw); 4617 /* Iterate over each bit of state */ 4618 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) { 4619 if ((*eval_funcs[i])(hdw)) { 4620 check_flag = !0; 4621 state_updated = !0; 4622 state_update_pipeline_state(hdw); 4623 } 4624 } 4625 } while (check_flag && hdw->flag_ok); 4626 hdw->state_stale = 0; 4627 trace_stbit("state_stale",hdw->state_stale); 4628 return state_updated; 4629 } 4630 4631 4632 static unsigned int print_input_mask(unsigned int msk, 4633 char *buf,unsigned int acnt) 4634 { 4635 unsigned int idx,ccnt; 4636 unsigned int tcnt = 0; 4637 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) { 4638 if (!((1 << idx) & msk)) continue; 4639 ccnt = scnprintf(buf+tcnt, 4640 acnt-tcnt, 4641 "%s%s", 4642 (tcnt ? ", " : ""), 4643 control_values_input[idx]); 4644 tcnt += ccnt; 4645 } 4646 return tcnt; 4647 } 4648 4649 4650 static const char *pvr2_pathway_state_name(int id) 4651 { 4652 switch (id) { 4653 case PVR2_PATHWAY_ANALOG: return "analog"; 4654 case PVR2_PATHWAY_DIGITAL: return "digital"; 4655 default: return "unknown"; 4656 } 4657 } 4658 4659 4660 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which, 4661 char *buf,unsigned int acnt) 4662 { 4663 switch (which) { 4664 case 0: 4665 return scnprintf( 4666 buf,acnt, 4667 "driver:%s%s%s%s%s <mode=%s>", 4668 (hdw->flag_ok ? " <ok>" : " <fail>"), 4669 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"), 4670 (hdw->flag_disconnected ? " <disconnected>" : 4671 " <connected>"), 4672 (hdw->flag_tripped ? " <tripped>" : ""), 4673 (hdw->flag_decoder_missed ? " <no decoder>" : ""), 4674 pvr2_pathway_state_name(hdw->pathway_state)); 4675 4676 case 1: 4677 return scnprintf( 4678 buf,acnt, 4679 "pipeline:%s%s%s%s", 4680 (hdw->state_pipeline_idle ? " <idle>" : ""), 4681 (hdw->state_pipeline_config ? 4682 " <configok>" : " <stale>"), 4683 (hdw->state_pipeline_req ? " <req>" : ""), 4684 (hdw->state_pipeline_pause ? " <pause>" : "")); 4685 case 2: 4686 return scnprintf( 4687 buf,acnt, 4688 "worker:%s%s%s%s%s%s%s", 4689 (hdw->state_decoder_run ? 4690 (hdw->state_decoder_ready ? 4691 "<decode:run>" : " <decode:start>") : 4692 (hdw->state_decoder_quiescent ? 4693 "" : " <decode:stop>")), 4694 (hdw->state_decoder_quiescent ? 4695 " <decode:quiescent>" : ""), 4696 (hdw->state_encoder_ok ? 4697 "" : " <encode:init>"), 4698 (hdw->state_encoder_run ? 4699 (hdw->state_encoder_runok ? 4700 " <encode:run>" : 4701 " <encode:firstrun>") : 4702 (hdw->state_encoder_runok ? 4703 " <encode:stop>" : 4704 " <encode:virgin>")), 4705 (hdw->state_encoder_config ? 4706 " <encode:configok>" : 4707 (hdw->state_encoder_waitok ? 4708 "" : " <encode:waitok>")), 4709 (hdw->state_usbstream_run ? 4710 " <usb:run>" : " <usb:stop>"), 4711 (hdw->state_pathway_ok ? 4712 " <pathway:ok>" : "")); 4713 case 3: 4714 return scnprintf( 4715 buf,acnt, 4716 "state: %s", 4717 pvr2_get_state_name(hdw->master_state)); 4718 case 4: { 4719 unsigned int tcnt = 0; 4720 unsigned int ccnt; 4721 4722 ccnt = scnprintf(buf, 4723 acnt, 4724 "Hardware supported inputs: "); 4725 tcnt += ccnt; 4726 tcnt += print_input_mask(hdw->input_avail_mask, 4727 buf+tcnt, 4728 acnt-tcnt); 4729 if (hdw->input_avail_mask != hdw->input_allowed_mask) { 4730 ccnt = scnprintf(buf+tcnt, 4731 acnt-tcnt, 4732 "; allowed inputs: "); 4733 tcnt += ccnt; 4734 tcnt += print_input_mask(hdw->input_allowed_mask, 4735 buf+tcnt, 4736 acnt-tcnt); 4737 } 4738 return tcnt; 4739 } 4740 case 5: { 4741 struct pvr2_stream_stats stats; 4742 if (!hdw->vid_stream) break; 4743 pvr2_stream_get_stats(hdw->vid_stream, 4744 &stats, 4745 0); 4746 return scnprintf( 4747 buf,acnt, 4748 "Bytes streamed=%u URBs: queued=%u idle=%u ready=%u processed=%u failed=%u", 4749 stats.bytes_processed, 4750 stats.buffers_in_queue, 4751 stats.buffers_in_idle, 4752 stats.buffers_in_ready, 4753 stats.buffers_processed, 4754 stats.buffers_failed); 4755 } 4756 case 6: { 4757 unsigned int id = hdw->ir_scheme_active; 4758 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id, 4759 (id >= ARRAY_SIZE(ir_scheme_names) ? 4760 "?" : ir_scheme_names[id])); 4761 } 4762 default: break; 4763 } 4764 return 0; 4765 } 4766 4767 4768 /* Generate report containing info about attached sub-devices and attached 4769 i2c clients, including an indication of which attached i2c clients are 4770 actually sub-devices. */ 4771 static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw, 4772 char *buf, unsigned int acnt) 4773 { 4774 struct v4l2_subdev *sd; 4775 unsigned int tcnt = 0; 4776 unsigned int ccnt; 4777 struct i2c_client *client; 4778 const char *p; 4779 unsigned int id; 4780 4781 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n"); 4782 tcnt += ccnt; 4783 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) { 4784 id = sd->grp_id; 4785 p = NULL; 4786 if (id < ARRAY_SIZE(module_names)) p = module_names[id]; 4787 if (p) { 4788 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p); 4789 tcnt += ccnt; 4790 } else { 4791 ccnt = scnprintf(buf + tcnt, acnt - tcnt, 4792 " (unknown id=%u):", id); 4793 tcnt += ccnt; 4794 } 4795 client = v4l2_get_subdevdata(sd); 4796 if (client) { 4797 ccnt = scnprintf(buf + tcnt, acnt - tcnt, 4798 " %s @ %02x\n", client->name, 4799 client->addr); 4800 tcnt += ccnt; 4801 } else { 4802 ccnt = scnprintf(buf + tcnt, acnt - tcnt, 4803 " no i2c client\n"); 4804 tcnt += ccnt; 4805 } 4806 } 4807 return tcnt; 4808 } 4809 4810 4811 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw, 4812 char *buf,unsigned int acnt) 4813 { 4814 unsigned int bcnt,ccnt,idx; 4815 bcnt = 0; 4816 LOCK_TAKE(hdw->big_lock); 4817 for (idx = 0; ; idx++) { 4818 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt); 4819 if (!ccnt) break; 4820 bcnt += ccnt; acnt -= ccnt; buf += ccnt; 4821 if (!acnt) break; 4822 buf[0] = '\n'; ccnt = 1; 4823 bcnt += ccnt; acnt -= ccnt; buf += ccnt; 4824 } 4825 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt); 4826 bcnt += ccnt; acnt -= ccnt; buf += ccnt; 4827 LOCK_GIVE(hdw->big_lock); 4828 return bcnt; 4829 } 4830 4831 4832 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw) 4833 { 4834 char buf[256]; 4835 unsigned int idx, ccnt; 4836 unsigned int lcnt, ucnt; 4837 4838 for (idx = 0; ; idx++) { 4839 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf)); 4840 if (!ccnt) break; 4841 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf); 4842 } 4843 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf)); 4844 if (ccnt >= sizeof(buf)) 4845 ccnt = sizeof(buf); 4846 4847 ucnt = 0; 4848 while (ucnt < ccnt) { 4849 lcnt = 0; 4850 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) { 4851 lcnt++; 4852 } 4853 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt); 4854 ucnt += lcnt + 1; 4855 } 4856 } 4857 4858 4859 /* Evaluate and update the driver's current state, taking various actions 4860 as appropriate for the update. */ 4861 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw) 4862 { 4863 unsigned int st; 4864 int state_updated = 0; 4865 int callback_flag = 0; 4866 int analog_mode; 4867 4868 pvr2_trace(PVR2_TRACE_STBITS, 4869 "Drive state check START"); 4870 if (pvrusb2_debug & PVR2_TRACE_STBITS) { 4871 pvr2_hdw_state_log_state(hdw); 4872 } 4873 4874 /* Process all state and get back over disposition */ 4875 state_updated = pvr2_hdw_state_update(hdw); 4876 4877 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL); 4878 4879 /* Update master state based upon all other states. */ 4880 if (!hdw->flag_ok) { 4881 st = PVR2_STATE_DEAD; 4882 } else if (hdw->fw1_state != FW1_STATE_OK) { 4883 st = PVR2_STATE_COLD; 4884 } else if ((analog_mode || 4885 hdw->hdw_desc->flag_digital_requires_cx23416) && 4886 !hdw->state_encoder_ok) { 4887 st = PVR2_STATE_WARM; 4888 } else if (hdw->flag_tripped || 4889 (analog_mode && hdw->flag_decoder_missed)) { 4890 st = PVR2_STATE_ERROR; 4891 } else if (hdw->state_usbstream_run && 4892 (!analog_mode || 4893 (hdw->state_encoder_run && hdw->state_decoder_run))) { 4894 st = PVR2_STATE_RUN; 4895 } else { 4896 st = PVR2_STATE_READY; 4897 } 4898 if (hdw->master_state != st) { 4899 pvr2_trace(PVR2_TRACE_STATE, 4900 "Device state change from %s to %s", 4901 pvr2_get_state_name(hdw->master_state), 4902 pvr2_get_state_name(st)); 4903 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN); 4904 hdw->master_state = st; 4905 state_updated = !0; 4906 callback_flag = !0; 4907 } 4908 if (state_updated) { 4909 /* Trigger anyone waiting on any state changes here. */ 4910 wake_up(&hdw->state_wait_data); 4911 } 4912 4913 if (pvrusb2_debug & PVR2_TRACE_STBITS) { 4914 pvr2_hdw_state_log_state(hdw); 4915 } 4916 pvr2_trace(PVR2_TRACE_STBITS, 4917 "Drive state check DONE callback=%d",callback_flag); 4918 4919 return callback_flag; 4920 } 4921 4922 4923 /* Cause kernel thread to check / update driver state */ 4924 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw) 4925 { 4926 if (hdw->state_stale) return; 4927 hdw->state_stale = !0; 4928 trace_stbit("state_stale",hdw->state_stale); 4929 schedule_work(&hdw->workpoll); 4930 } 4931 4932 4933 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp) 4934 { 4935 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp); 4936 } 4937 4938 4939 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp) 4940 { 4941 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp); 4942 } 4943 4944 4945 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp) 4946 { 4947 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp); 4948 } 4949 4950 4951 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val) 4952 { 4953 u32 cval,nval; 4954 int ret; 4955 if (~msk) { 4956 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval); 4957 if (ret) return ret; 4958 nval = (cval & ~msk) | (val & msk); 4959 pvr2_trace(PVR2_TRACE_GPIO, 4960 "GPIO direction changing 0x%x:0x%x from 0x%x to 0x%x", 4961 msk,val,cval,nval); 4962 } else { 4963 nval = val; 4964 pvr2_trace(PVR2_TRACE_GPIO, 4965 "GPIO direction changing to 0x%x",nval); 4966 } 4967 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval); 4968 } 4969 4970 4971 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val) 4972 { 4973 u32 cval,nval; 4974 int ret; 4975 if (~msk) { 4976 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval); 4977 if (ret) return ret; 4978 nval = (cval & ~msk) | (val & msk); 4979 pvr2_trace(PVR2_TRACE_GPIO, 4980 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x", 4981 msk,val,cval,nval); 4982 } else { 4983 nval = val; 4984 pvr2_trace(PVR2_TRACE_GPIO, 4985 "GPIO output changing to 0x%x",nval); 4986 } 4987 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval); 4988 } 4989 4990 4991 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw) 4992 { 4993 struct v4l2_tuner *vtp = &hdw->tuner_signal_info; 4994 memset(vtp, 0, sizeof(*vtp)); 4995 vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ? 4996 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; 4997 hdw->tuner_signal_stale = 0; 4998 /* Note: There apparently is no replacement for VIDIOC_CROPCAP 4999 using v4l2-subdev - therefore we can't support that AT ALL right 5000 now. (Of course, no sub-drivers seem to implement it either. 5001 But now it's a a chicken and egg problem...) */ 5002 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp); 5003 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll type=%u strength=%u audio=0x%x cap=0x%x low=%u hi=%u", 5004 vtp->type, 5005 vtp->signal, vtp->rxsubchans, vtp->capability, 5006 vtp->rangelow, vtp->rangehigh); 5007 5008 /* We have to do this to avoid getting into constant polling if 5009 there's nobody to answer a poll of cropcap info. */ 5010 hdw->cropcap_stale = 0; 5011 } 5012 5013 5014 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw) 5015 { 5016 return hdw->input_avail_mask; 5017 } 5018 5019 5020 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw) 5021 { 5022 return hdw->input_allowed_mask; 5023 } 5024 5025 5026 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v) 5027 { 5028 if (hdw->input_val != v) { 5029 hdw->input_val = v; 5030 hdw->input_dirty = !0; 5031 } 5032 5033 /* Handle side effects - if we switch to a mode that needs the RF 5034 tuner, then select the right frequency choice as well and mark 5035 it dirty. */ 5036 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { 5037 hdw->freqSelector = 0; 5038 hdw->freqDirty = !0; 5039 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) || 5040 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) { 5041 hdw->freqSelector = 1; 5042 hdw->freqDirty = !0; 5043 } 5044 return 0; 5045 } 5046 5047 5048 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw, 5049 unsigned int change_mask, 5050 unsigned int change_val) 5051 { 5052 int ret = 0; 5053 unsigned int nv,m,idx; 5054 LOCK_TAKE(hdw->big_lock); 5055 do { 5056 nv = hdw->input_allowed_mask & ~change_mask; 5057 nv |= (change_val & change_mask); 5058 nv &= hdw->input_avail_mask; 5059 if (!nv) { 5060 /* No legal modes left; return error instead. */ 5061 ret = -EPERM; 5062 break; 5063 } 5064 hdw->input_allowed_mask = nv; 5065 if ((1 << hdw->input_val) & hdw->input_allowed_mask) { 5066 /* Current mode is still in the allowed mask, so 5067 we're done. */ 5068 break; 5069 } 5070 /* Select and switch to a mode that is still in the allowed 5071 mask */ 5072 if (!hdw->input_allowed_mask) { 5073 /* Nothing legal; give up */ 5074 break; 5075 } 5076 m = hdw->input_allowed_mask; 5077 for (idx = 0; idx < (sizeof(m) << 3); idx++) { 5078 if (!((1 << idx) & m)) continue; 5079 pvr2_hdw_set_input(hdw,idx); 5080 break; 5081 } 5082 } while (0); 5083 LOCK_GIVE(hdw->big_lock); 5084 return ret; 5085 } 5086 5087 5088 /* Find I2C address of eeprom */ 5089 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw) 5090 { 5091 int result; 5092 LOCK_TAKE(hdw->ctl_lock); do { 5093 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR; 5094 result = pvr2_send_request(hdw, 5095 hdw->cmd_buffer,1, 5096 hdw->cmd_buffer,1); 5097 if (result < 0) break; 5098 result = hdw->cmd_buffer[0]; 5099 } while(0); LOCK_GIVE(hdw->ctl_lock); 5100 return result; 5101 } 5102