1 /* 2 * 3 * 4 * Copyright (C) 2005 Mike Isely <isely@pobox.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * 19 */ 20 21 #include <linux/errno.h> 22 #include <linux/string.h> 23 #include <linux/slab.h> 24 #include <linux/module.h> 25 #include <linux/firmware.h> 26 #include <linux/videodev2.h> 27 #include <media/v4l2-common.h> 28 #include <media/tuner.h> 29 #include "pvrusb2.h" 30 #include "pvrusb2-std.h" 31 #include "pvrusb2-util.h" 32 #include "pvrusb2-hdw.h" 33 #include "pvrusb2-i2c-core.h" 34 #include "pvrusb2-eeprom.h" 35 #include "pvrusb2-hdw-internal.h" 36 #include "pvrusb2-encoder.h" 37 #include "pvrusb2-debug.h" 38 #include "pvrusb2-fx2-cmd.h" 39 #include "pvrusb2-wm8775.h" 40 #include "pvrusb2-video-v4l.h" 41 #include "pvrusb2-cx2584x-v4l.h" 42 #include "pvrusb2-cs53l32a.h" 43 #include "pvrusb2-audio.h" 44 45 #define TV_MIN_FREQ 55250000L 46 #define TV_MAX_FREQ 850000000L 47 48 /* This defines a minimum interval that the decoder must remain quiet 49 before we are allowed to start it running. */ 50 #define TIME_MSEC_DECODER_WAIT 50 51 52 /* This defines a minimum interval that the decoder must be allowed to run 53 before we can safely begin using its streaming output. */ 54 #define TIME_MSEC_DECODER_STABILIZATION_WAIT 300 55 56 /* This defines a minimum interval that the encoder must remain quiet 57 before we are allowed to configure it. */ 58 #define TIME_MSEC_ENCODER_WAIT 50 59 60 /* This defines the minimum interval that the encoder must successfully run 61 before we consider that the encoder has run at least once since its 62 firmware has been loaded. This measurement is in important for cases 63 where we can't do something until we know that the encoder has been run 64 at least once. */ 65 #define TIME_MSEC_ENCODER_OK 250 66 67 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL}; 68 static DEFINE_MUTEX(pvr2_unit_mtx); 69 70 static int ctlchg; 71 static int procreload; 72 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 }; 73 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 }; 74 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 }; 75 static int init_pause_msec; 76 77 module_param(ctlchg, int, S_IRUGO|S_IWUSR); 78 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value"); 79 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR); 80 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay"); 81 module_param(procreload, int, S_IRUGO|S_IWUSR); 82 MODULE_PARM_DESC(procreload, 83 "Attempt init failure recovery with firmware reload"); 84 module_param_array(tuner, int, NULL, 0444); 85 MODULE_PARM_DESC(tuner,"specify installed tuner type"); 86 module_param_array(video_std, int, NULL, 0444); 87 MODULE_PARM_DESC(video_std,"specify initial video standard"); 88 module_param_array(tolerance, int, NULL, 0444); 89 MODULE_PARM_DESC(tolerance,"specify stream error tolerance"); 90 91 /* US Broadcast channel 3 (61.25 MHz), to help with testing */ 92 static int default_tv_freq = 61250000L; 93 /* 104.3 MHz, a usable FM station for my area */ 94 static int default_radio_freq = 104300000L; 95 96 module_param_named(tv_freq, default_tv_freq, int, 0444); 97 MODULE_PARM_DESC(tv_freq, "specify initial television frequency"); 98 module_param_named(radio_freq, default_radio_freq, int, 0444); 99 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency"); 100 101 #define PVR2_CTL_WRITE_ENDPOINT 0x01 102 #define PVR2_CTL_READ_ENDPOINT 0x81 103 104 #define PVR2_GPIO_IN 0x9008 105 #define PVR2_GPIO_OUT 0x900c 106 #define PVR2_GPIO_DIR 0x9020 107 108 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__) 109 110 #define PVR2_FIRMWARE_ENDPOINT 0x02 111 112 /* size of a firmware chunk */ 113 #define FIRMWARE_CHUNK_SIZE 0x2000 114 115 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *, 116 struct v4l2_subdev *); 117 118 static const pvr2_subdev_update_func pvr2_module_update_functions[] = { 119 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update, 120 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update, 121 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update, 122 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update, 123 [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update, 124 }; 125 126 static const char *module_names[] = { 127 [PVR2_CLIENT_ID_MSP3400] = "msp3400", 128 [PVR2_CLIENT_ID_CX25840] = "cx25840", 129 [PVR2_CLIENT_ID_SAA7115] = "saa7115", 130 [PVR2_CLIENT_ID_TUNER] = "tuner", 131 [PVR2_CLIENT_ID_DEMOD] = "tuner", 132 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a", 133 [PVR2_CLIENT_ID_WM8775] = "wm8775", 134 }; 135 136 137 static const unsigned char *module_i2c_addresses[] = { 138 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63", 139 [PVR2_CLIENT_ID_DEMOD] = "\x43", 140 [PVR2_CLIENT_ID_MSP3400] = "\x40", 141 [PVR2_CLIENT_ID_SAA7115] = "\x21", 142 [PVR2_CLIENT_ID_WM8775] = "\x1b", 143 [PVR2_CLIENT_ID_CX25840] = "\x44", 144 [PVR2_CLIENT_ID_CS53L32A] = "\x11", 145 }; 146 147 148 static const char *ir_scheme_names[] = { 149 [PVR2_IR_SCHEME_NONE] = "none", 150 [PVR2_IR_SCHEME_29XXX] = "29xxx", 151 [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)", 152 [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)", 153 [PVR2_IR_SCHEME_ZILOG] = "Zilog", 154 }; 155 156 157 /* Define the list of additional controls we'll dynamically construct based 158 on query of the cx2341x module. */ 159 struct pvr2_mpeg_ids { 160 const char *strid; 161 int id; 162 }; 163 static const struct pvr2_mpeg_ids mpeg_ids[] = { 164 { 165 .strid = "audio_layer", 166 .id = V4L2_CID_MPEG_AUDIO_ENCODING, 167 },{ 168 .strid = "audio_bitrate", 169 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE, 170 },{ 171 /* Already using audio_mode elsewhere :-( */ 172 .strid = "mpeg_audio_mode", 173 .id = V4L2_CID_MPEG_AUDIO_MODE, 174 },{ 175 .strid = "mpeg_audio_mode_extension", 176 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION, 177 },{ 178 .strid = "audio_emphasis", 179 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS, 180 },{ 181 .strid = "audio_crc", 182 .id = V4L2_CID_MPEG_AUDIO_CRC, 183 },{ 184 .strid = "video_aspect", 185 .id = V4L2_CID_MPEG_VIDEO_ASPECT, 186 },{ 187 .strid = "video_b_frames", 188 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES, 189 },{ 190 .strid = "video_gop_size", 191 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE, 192 },{ 193 .strid = "video_gop_closure", 194 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE, 195 },{ 196 .strid = "video_bitrate_mode", 197 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE, 198 },{ 199 .strid = "video_bitrate", 200 .id = V4L2_CID_MPEG_VIDEO_BITRATE, 201 },{ 202 .strid = "video_bitrate_peak", 203 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK, 204 },{ 205 .strid = "video_temporal_decimation", 206 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION, 207 },{ 208 .strid = "stream_type", 209 .id = V4L2_CID_MPEG_STREAM_TYPE, 210 },{ 211 .strid = "video_spatial_filter_mode", 212 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE, 213 },{ 214 .strid = "video_spatial_filter", 215 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER, 216 },{ 217 .strid = "video_luma_spatial_filter_type", 218 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE, 219 },{ 220 .strid = "video_chroma_spatial_filter_type", 221 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE, 222 },{ 223 .strid = "video_temporal_filter_mode", 224 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE, 225 },{ 226 .strid = "video_temporal_filter", 227 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER, 228 },{ 229 .strid = "video_median_filter_type", 230 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE, 231 },{ 232 .strid = "video_luma_median_filter_top", 233 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP, 234 },{ 235 .strid = "video_luma_median_filter_bottom", 236 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM, 237 },{ 238 .strid = "video_chroma_median_filter_top", 239 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP, 240 },{ 241 .strid = "video_chroma_median_filter_bottom", 242 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM, 243 } 244 }; 245 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids) 246 247 248 static const char *control_values_srate[] = { 249 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz", 250 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz", 251 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz", 252 }; 253 254 255 256 static const char *control_values_input[] = { 257 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/ 258 [PVR2_CVAL_INPUT_DTV] = "dtv", 259 [PVR2_CVAL_INPUT_RADIO] = "radio", 260 [PVR2_CVAL_INPUT_SVIDEO] = "s-video", 261 [PVR2_CVAL_INPUT_COMPOSITE] = "composite", 262 }; 263 264 265 static const char *control_values_audiomode[] = { 266 [V4L2_TUNER_MODE_MONO] = "Mono", 267 [V4L2_TUNER_MODE_STEREO] = "Stereo", 268 [V4L2_TUNER_MODE_LANG1] = "Lang1", 269 [V4L2_TUNER_MODE_LANG2] = "Lang2", 270 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2", 271 }; 272 273 274 static const char *control_values_hsm[] = { 275 [PVR2_CVAL_HSM_FAIL] = "Fail", 276 [PVR2_CVAL_HSM_HIGH] = "High", 277 [PVR2_CVAL_HSM_FULL] = "Full", 278 }; 279 280 281 static const char *pvr2_state_names[] = { 282 [PVR2_STATE_NONE] = "none", 283 [PVR2_STATE_DEAD] = "dead", 284 [PVR2_STATE_COLD] = "cold", 285 [PVR2_STATE_WARM] = "warm", 286 [PVR2_STATE_ERROR] = "error", 287 [PVR2_STATE_READY] = "ready", 288 [PVR2_STATE_RUN] = "run", 289 }; 290 291 292 struct pvr2_fx2cmd_descdef { 293 unsigned char id; 294 unsigned char *desc; 295 }; 296 297 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = { 298 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"}, 299 {FX2CMD_MEM_READ_DWORD, "read encoder dword"}, 300 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"}, 301 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"}, 302 {FX2CMD_REG_WRITE, "write encoder register"}, 303 {FX2CMD_REG_READ, "read encoder register"}, 304 {FX2CMD_MEMSEL, "encoder memsel"}, 305 {FX2CMD_I2C_WRITE, "i2c write"}, 306 {FX2CMD_I2C_READ, "i2c read"}, 307 {FX2CMD_GET_USB_SPEED, "get USB speed"}, 308 {FX2CMD_STREAMING_ON, "stream on"}, 309 {FX2CMD_STREAMING_OFF, "stream off"}, 310 {FX2CMD_FWPOST1, "fwpost1"}, 311 {FX2CMD_POWER_OFF, "power off"}, 312 {FX2CMD_POWER_ON, "power on"}, 313 {FX2CMD_DEEP_RESET, "deep reset"}, 314 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"}, 315 {FX2CMD_GET_IR_CODE, "get IR code"}, 316 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"}, 317 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"}, 318 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"}, 319 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"}, 320 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"}, 321 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"}, 322 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"}, 323 }; 324 325 326 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v); 327 static void pvr2_hdw_state_sched(struct pvr2_hdw *); 328 static int pvr2_hdw_state_eval(struct pvr2_hdw *); 329 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long); 330 static void pvr2_hdw_worker_poll(struct work_struct *work); 331 static int pvr2_hdw_wait(struct pvr2_hdw *,int state); 332 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *); 333 static void pvr2_hdw_state_log_state(struct pvr2_hdw *); 334 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl); 335 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw); 336 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw); 337 static void pvr2_hdw_quiescent_timeout(unsigned long); 338 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long); 339 static void pvr2_hdw_encoder_wait_timeout(unsigned long); 340 static void pvr2_hdw_encoder_run_timeout(unsigned long); 341 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32); 342 static int pvr2_send_request_ex(struct pvr2_hdw *hdw, 343 unsigned int timeout,int probe_fl, 344 void *write_data,unsigned int write_len, 345 void *read_data,unsigned int read_len); 346 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw); 347 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw); 348 349 static void trace_stbit(const char *name,int val) 350 { 351 pvr2_trace(PVR2_TRACE_STBITS, 352 "State bit %s <-- %s", 353 name,(val ? "true" : "false")); 354 } 355 356 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp) 357 { 358 struct pvr2_hdw *hdw = cptr->hdw; 359 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) { 360 *vp = hdw->freqTable[hdw->freqProgSlot-1]; 361 } else { 362 *vp = 0; 363 } 364 return 0; 365 } 366 367 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v) 368 { 369 struct pvr2_hdw *hdw = cptr->hdw; 370 unsigned int slotId = hdw->freqProgSlot; 371 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) { 372 hdw->freqTable[slotId-1] = v; 373 /* Handle side effects correctly - if we're tuned to this 374 slot, then forgot the slot id relation since the stored 375 frequency has been changed. */ 376 if (hdw->freqSelector) { 377 if (hdw->freqSlotRadio == slotId) { 378 hdw->freqSlotRadio = 0; 379 } 380 } else { 381 if (hdw->freqSlotTelevision == slotId) { 382 hdw->freqSlotTelevision = 0; 383 } 384 } 385 } 386 return 0; 387 } 388 389 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp) 390 { 391 *vp = cptr->hdw->freqProgSlot; 392 return 0; 393 } 394 395 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v) 396 { 397 struct pvr2_hdw *hdw = cptr->hdw; 398 if ((v >= 0) && (v <= FREQTABLE_SIZE)) { 399 hdw->freqProgSlot = v; 400 } 401 return 0; 402 } 403 404 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp) 405 { 406 struct pvr2_hdw *hdw = cptr->hdw; 407 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision; 408 return 0; 409 } 410 411 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId) 412 { 413 unsigned freq = 0; 414 struct pvr2_hdw *hdw = cptr->hdw; 415 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0; 416 if (slotId > 0) { 417 freq = hdw->freqTable[slotId-1]; 418 if (!freq) return 0; 419 pvr2_hdw_set_cur_freq(hdw,freq); 420 } 421 if (hdw->freqSelector) { 422 hdw->freqSlotRadio = slotId; 423 } else { 424 hdw->freqSlotTelevision = slotId; 425 } 426 return 0; 427 } 428 429 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp) 430 { 431 *vp = pvr2_hdw_get_cur_freq(cptr->hdw); 432 return 0; 433 } 434 435 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr) 436 { 437 return cptr->hdw->freqDirty != 0; 438 } 439 440 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr) 441 { 442 cptr->hdw->freqDirty = 0; 443 } 444 445 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v) 446 { 447 pvr2_hdw_set_cur_freq(cptr->hdw,v); 448 return 0; 449 } 450 451 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left) 452 { 453 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 454 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 455 if (stat != 0) { 456 return stat; 457 } 458 *left = cap->bounds.left; 459 return 0; 460 } 461 462 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left) 463 { 464 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 465 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 466 if (stat != 0) { 467 return stat; 468 } 469 *left = cap->bounds.left; 470 if (cap->bounds.width > cptr->hdw->cropw_val) { 471 *left += cap->bounds.width - cptr->hdw->cropw_val; 472 } 473 return 0; 474 } 475 476 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top) 477 { 478 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 479 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 480 if (stat != 0) { 481 return stat; 482 } 483 *top = cap->bounds.top; 484 return 0; 485 } 486 487 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top) 488 { 489 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 490 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 491 if (stat != 0) { 492 return stat; 493 } 494 *top = cap->bounds.top; 495 if (cap->bounds.height > cptr->hdw->croph_val) { 496 *top += cap->bounds.height - cptr->hdw->croph_val; 497 } 498 return 0; 499 } 500 501 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width) 502 { 503 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 504 int stat, bleftend, cleft; 505 506 stat = pvr2_hdw_check_cropcap(cptr->hdw); 507 if (stat != 0) { 508 return stat; 509 } 510 bleftend = cap->bounds.left+cap->bounds.width; 511 cleft = cptr->hdw->cropl_val; 512 513 *width = cleft < bleftend ? bleftend-cleft : 0; 514 return 0; 515 } 516 517 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height) 518 { 519 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 520 int stat, btopend, ctop; 521 522 stat = pvr2_hdw_check_cropcap(cptr->hdw); 523 if (stat != 0) { 524 return stat; 525 } 526 btopend = cap->bounds.top+cap->bounds.height; 527 ctop = cptr->hdw->cropt_val; 528 529 *height = ctop < btopend ? btopend-ctop : 0; 530 return 0; 531 } 532 533 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val) 534 { 535 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 536 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 537 if (stat != 0) { 538 return stat; 539 } 540 *val = cap->bounds.left; 541 return 0; 542 } 543 544 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val) 545 { 546 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 547 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 548 if (stat != 0) { 549 return stat; 550 } 551 *val = cap->bounds.top; 552 return 0; 553 } 554 555 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val) 556 { 557 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 558 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 559 if (stat != 0) { 560 return stat; 561 } 562 *val = cap->bounds.width; 563 return 0; 564 } 565 566 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val) 567 { 568 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 569 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 570 if (stat != 0) { 571 return stat; 572 } 573 *val = cap->bounds.height; 574 return 0; 575 } 576 577 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val) 578 { 579 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 580 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 581 if (stat != 0) { 582 return stat; 583 } 584 *val = cap->defrect.left; 585 return 0; 586 } 587 588 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val) 589 { 590 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 591 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 592 if (stat != 0) { 593 return stat; 594 } 595 *val = cap->defrect.top; 596 return 0; 597 } 598 599 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val) 600 { 601 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 602 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 603 if (stat != 0) { 604 return stat; 605 } 606 *val = cap->defrect.width; 607 return 0; 608 } 609 610 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val) 611 { 612 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 613 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 614 if (stat != 0) { 615 return stat; 616 } 617 *val = cap->defrect.height; 618 return 0; 619 } 620 621 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val) 622 { 623 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 624 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 625 if (stat != 0) { 626 return stat; 627 } 628 *val = cap->pixelaspect.numerator; 629 return 0; 630 } 631 632 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val) 633 { 634 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info; 635 int stat = pvr2_hdw_check_cropcap(cptr->hdw); 636 if (stat != 0) { 637 return stat; 638 } 639 *val = cap->pixelaspect.denominator; 640 return 0; 641 } 642 643 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp) 644 { 645 /* Actual maximum depends on the video standard in effect. */ 646 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) { 647 *vp = 480; 648 } else { 649 *vp = 576; 650 } 651 return 0; 652 } 653 654 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp) 655 { 656 /* Actual minimum depends on device digitizer type. */ 657 if (cptr->hdw->hdw_desc->flag_has_cx25840) { 658 *vp = 75; 659 } else { 660 *vp = 17; 661 } 662 return 0; 663 } 664 665 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp) 666 { 667 *vp = cptr->hdw->input_val; 668 return 0; 669 } 670 671 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v) 672 { 673 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0; 674 } 675 676 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v) 677 { 678 return pvr2_hdw_set_input(cptr->hdw,v); 679 } 680 681 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr) 682 { 683 return cptr->hdw->input_dirty != 0; 684 } 685 686 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr) 687 { 688 cptr->hdw->input_dirty = 0; 689 } 690 691 692 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp) 693 { 694 unsigned long fv; 695 struct pvr2_hdw *hdw = cptr->hdw; 696 if (hdw->tuner_signal_stale) { 697 pvr2_hdw_status_poll(hdw); 698 } 699 fv = hdw->tuner_signal_info.rangehigh; 700 if (!fv) { 701 /* Safety fallback */ 702 *vp = TV_MAX_FREQ; 703 return 0; 704 } 705 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) { 706 fv = (fv * 125) / 2; 707 } else { 708 fv = fv * 62500; 709 } 710 *vp = fv; 711 return 0; 712 } 713 714 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp) 715 { 716 unsigned long fv; 717 struct pvr2_hdw *hdw = cptr->hdw; 718 if (hdw->tuner_signal_stale) { 719 pvr2_hdw_status_poll(hdw); 720 } 721 fv = hdw->tuner_signal_info.rangelow; 722 if (!fv) { 723 /* Safety fallback */ 724 *vp = TV_MIN_FREQ; 725 return 0; 726 } 727 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) { 728 fv = (fv * 125) / 2; 729 } else { 730 fv = fv * 62500; 731 } 732 *vp = fv; 733 return 0; 734 } 735 736 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr) 737 { 738 return cptr->hdw->enc_stale != 0; 739 } 740 741 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr) 742 { 743 cptr->hdw->enc_stale = 0; 744 cptr->hdw->enc_unsafe_stale = 0; 745 } 746 747 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp) 748 { 749 int ret; 750 struct v4l2_ext_controls cs; 751 struct v4l2_ext_control c1; 752 memset(&cs,0,sizeof(cs)); 753 memset(&c1,0,sizeof(c1)); 754 cs.controls = &c1; 755 cs.count = 1; 756 c1.id = cptr->info->v4l_id; 757 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs, 758 VIDIOC_G_EXT_CTRLS); 759 if (ret) return ret; 760 *vp = c1.value; 761 return 0; 762 } 763 764 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v) 765 { 766 int ret; 767 struct pvr2_hdw *hdw = cptr->hdw; 768 struct v4l2_ext_controls cs; 769 struct v4l2_ext_control c1; 770 memset(&cs,0,sizeof(cs)); 771 memset(&c1,0,sizeof(c1)); 772 cs.controls = &c1; 773 cs.count = 1; 774 c1.id = cptr->info->v4l_id; 775 c1.value = v; 776 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state, 777 hdw->state_encoder_run, &cs, 778 VIDIOC_S_EXT_CTRLS); 779 if (ret == -EBUSY) { 780 /* Oops. cx2341x is telling us it's not safe to change 781 this control while we're capturing. Make a note of this 782 fact so that the pipeline will be stopped the next time 783 controls are committed. Then go on ahead and store this 784 change anyway. */ 785 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state, 786 0, &cs, 787 VIDIOC_S_EXT_CTRLS); 788 if (!ret) hdw->enc_unsafe_stale = !0; 789 } 790 if (ret) return ret; 791 hdw->enc_stale = !0; 792 return 0; 793 } 794 795 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr) 796 { 797 struct v4l2_queryctrl qctrl; 798 struct pvr2_ctl_info *info; 799 qctrl.id = cptr->info->v4l_id; 800 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl); 801 /* Strip out the const so we can adjust a function pointer. It's 802 OK to do this here because we know this is a dynamically created 803 control, so the underlying storage for the info pointer is (a) 804 private to us, and (b) not in read-only storage. Either we do 805 this or we significantly complicate the underlying control 806 implementation. */ 807 info = (struct pvr2_ctl_info *)(cptr->info); 808 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) { 809 if (info->set_value) { 810 info->set_value = NULL; 811 } 812 } else { 813 if (!(info->set_value)) { 814 info->set_value = ctrl_cx2341x_set; 815 } 816 } 817 return qctrl.flags; 818 } 819 820 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp) 821 { 822 *vp = cptr->hdw->state_pipeline_req; 823 return 0; 824 } 825 826 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp) 827 { 828 *vp = cptr->hdw->master_state; 829 return 0; 830 } 831 832 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp) 833 { 834 int result = pvr2_hdw_is_hsm(cptr->hdw); 835 *vp = PVR2_CVAL_HSM_FULL; 836 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL; 837 if (result) *vp = PVR2_CVAL_HSM_HIGH; 838 return 0; 839 } 840 841 static int ctrl_stddetect_get(struct pvr2_ctrl *cptr, int *vp) 842 { 843 *vp = pvr2_hdw_get_detected_std(cptr->hdw); 844 return 0; 845 } 846 847 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp) 848 { 849 *vp = cptr->hdw->std_mask_avail; 850 return 0; 851 } 852 853 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v) 854 { 855 struct pvr2_hdw *hdw = cptr->hdw; 856 v4l2_std_id ns; 857 ns = hdw->std_mask_avail; 858 ns = (ns & ~m) | (v & m); 859 if (ns == hdw->std_mask_avail) return 0; 860 hdw->std_mask_avail = ns; 861 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail; 862 return 0; 863 } 864 865 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val, 866 char *bufPtr,unsigned int bufSize, 867 unsigned int *len) 868 { 869 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val); 870 return 0; 871 } 872 873 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr, 874 const char *bufPtr,unsigned int bufSize, 875 int *mskp,int *valp) 876 { 877 int ret; 878 v4l2_std_id id; 879 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize); 880 if (ret < 0) return ret; 881 if (mskp) *mskp = id; 882 if (valp) *valp = id; 883 return 0; 884 } 885 886 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp) 887 { 888 *vp = cptr->hdw->std_mask_cur; 889 return 0; 890 } 891 892 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v) 893 { 894 struct pvr2_hdw *hdw = cptr->hdw; 895 v4l2_std_id ns; 896 ns = hdw->std_mask_cur; 897 ns = (ns & ~m) | (v & m); 898 if (ns == hdw->std_mask_cur) return 0; 899 hdw->std_mask_cur = ns; 900 hdw->std_dirty = !0; 901 return 0; 902 } 903 904 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr) 905 { 906 return cptr->hdw->std_dirty != 0; 907 } 908 909 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr) 910 { 911 cptr->hdw->std_dirty = 0; 912 } 913 914 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp) 915 { 916 struct pvr2_hdw *hdw = cptr->hdw; 917 pvr2_hdw_status_poll(hdw); 918 *vp = hdw->tuner_signal_info.signal; 919 return 0; 920 } 921 922 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp) 923 { 924 int val = 0; 925 unsigned int subchan; 926 struct pvr2_hdw *hdw = cptr->hdw; 927 pvr2_hdw_status_poll(hdw); 928 subchan = hdw->tuner_signal_info.rxsubchans; 929 if (subchan & V4L2_TUNER_SUB_MONO) { 930 val |= (1 << V4L2_TUNER_MODE_MONO); 931 } 932 if (subchan & V4L2_TUNER_SUB_STEREO) { 933 val |= (1 << V4L2_TUNER_MODE_STEREO); 934 } 935 if (subchan & V4L2_TUNER_SUB_LANG1) { 936 val |= (1 << V4L2_TUNER_MODE_LANG1); 937 } 938 if (subchan & V4L2_TUNER_SUB_LANG2) { 939 val |= (1 << V4L2_TUNER_MODE_LANG2); 940 } 941 *vp = val; 942 return 0; 943 } 944 945 946 #define DEFINT(vmin,vmax) \ 947 .type = pvr2_ctl_int, \ 948 .def.type_int.min_value = vmin, \ 949 .def.type_int.max_value = vmax 950 951 #define DEFENUM(tab) \ 952 .type = pvr2_ctl_enum, \ 953 .def.type_enum.count = ARRAY_SIZE(tab), \ 954 .def.type_enum.value_names = tab 955 956 #define DEFBOOL \ 957 .type = pvr2_ctl_bool 958 959 #define DEFMASK(msk,tab) \ 960 .type = pvr2_ctl_bitmask, \ 961 .def.type_bitmask.valid_bits = msk, \ 962 .def.type_bitmask.bit_names = tab 963 964 #define DEFREF(vname) \ 965 .set_value = ctrl_set_##vname, \ 966 .get_value = ctrl_get_##vname, \ 967 .is_dirty = ctrl_isdirty_##vname, \ 968 .clear_dirty = ctrl_cleardirty_##vname 969 970 971 #define VCREATE_FUNCS(vname) \ 972 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \ 973 {*vp = cptr->hdw->vname##_val; return 0;} \ 974 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \ 975 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \ 976 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \ 977 {return cptr->hdw->vname##_dirty != 0;} \ 978 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \ 979 {cptr->hdw->vname##_dirty = 0;} 980 981 VCREATE_FUNCS(brightness) 982 VCREATE_FUNCS(contrast) 983 VCREATE_FUNCS(saturation) 984 VCREATE_FUNCS(hue) 985 VCREATE_FUNCS(volume) 986 VCREATE_FUNCS(balance) 987 VCREATE_FUNCS(bass) 988 VCREATE_FUNCS(treble) 989 VCREATE_FUNCS(mute) 990 VCREATE_FUNCS(cropl) 991 VCREATE_FUNCS(cropt) 992 VCREATE_FUNCS(cropw) 993 VCREATE_FUNCS(croph) 994 VCREATE_FUNCS(audiomode) 995 VCREATE_FUNCS(res_hor) 996 VCREATE_FUNCS(res_ver) 997 VCREATE_FUNCS(srate) 998 999 /* Table definition of all controls which can be manipulated */ 1000 static const struct pvr2_ctl_info control_defs[] = { 1001 { 1002 .v4l_id = V4L2_CID_BRIGHTNESS, 1003 .desc = "Brightness", 1004 .name = "brightness", 1005 .default_value = 128, 1006 DEFREF(brightness), 1007 DEFINT(0,255), 1008 },{ 1009 .v4l_id = V4L2_CID_CONTRAST, 1010 .desc = "Contrast", 1011 .name = "contrast", 1012 .default_value = 68, 1013 DEFREF(contrast), 1014 DEFINT(0,127), 1015 },{ 1016 .v4l_id = V4L2_CID_SATURATION, 1017 .desc = "Saturation", 1018 .name = "saturation", 1019 .default_value = 64, 1020 DEFREF(saturation), 1021 DEFINT(0,127), 1022 },{ 1023 .v4l_id = V4L2_CID_HUE, 1024 .desc = "Hue", 1025 .name = "hue", 1026 .default_value = 0, 1027 DEFREF(hue), 1028 DEFINT(-128,127), 1029 },{ 1030 .v4l_id = V4L2_CID_AUDIO_VOLUME, 1031 .desc = "Volume", 1032 .name = "volume", 1033 .default_value = 62000, 1034 DEFREF(volume), 1035 DEFINT(0,65535), 1036 },{ 1037 .v4l_id = V4L2_CID_AUDIO_BALANCE, 1038 .desc = "Balance", 1039 .name = "balance", 1040 .default_value = 0, 1041 DEFREF(balance), 1042 DEFINT(-32768,32767), 1043 },{ 1044 .v4l_id = V4L2_CID_AUDIO_BASS, 1045 .desc = "Bass", 1046 .name = "bass", 1047 .default_value = 0, 1048 DEFREF(bass), 1049 DEFINT(-32768,32767), 1050 },{ 1051 .v4l_id = V4L2_CID_AUDIO_TREBLE, 1052 .desc = "Treble", 1053 .name = "treble", 1054 .default_value = 0, 1055 DEFREF(treble), 1056 DEFINT(-32768,32767), 1057 },{ 1058 .v4l_id = V4L2_CID_AUDIO_MUTE, 1059 .desc = "Mute", 1060 .name = "mute", 1061 .default_value = 0, 1062 DEFREF(mute), 1063 DEFBOOL, 1064 }, { 1065 .desc = "Capture crop left margin", 1066 .name = "crop_left", 1067 .internal_id = PVR2_CID_CROPL, 1068 .default_value = 0, 1069 DEFREF(cropl), 1070 DEFINT(-129, 340), 1071 .get_min_value = ctrl_cropl_min_get, 1072 .get_max_value = ctrl_cropl_max_get, 1073 .get_def_value = ctrl_get_cropcapdl, 1074 }, { 1075 .desc = "Capture crop top margin", 1076 .name = "crop_top", 1077 .internal_id = PVR2_CID_CROPT, 1078 .default_value = 0, 1079 DEFREF(cropt), 1080 DEFINT(-35, 544), 1081 .get_min_value = ctrl_cropt_min_get, 1082 .get_max_value = ctrl_cropt_max_get, 1083 .get_def_value = ctrl_get_cropcapdt, 1084 }, { 1085 .desc = "Capture crop width", 1086 .name = "crop_width", 1087 .internal_id = PVR2_CID_CROPW, 1088 .default_value = 720, 1089 DEFREF(cropw), 1090 DEFINT(0, 864), 1091 .get_max_value = ctrl_cropw_max_get, 1092 .get_def_value = ctrl_get_cropcapdw, 1093 }, { 1094 .desc = "Capture crop height", 1095 .name = "crop_height", 1096 .internal_id = PVR2_CID_CROPH, 1097 .default_value = 480, 1098 DEFREF(croph), 1099 DEFINT(0, 576), 1100 .get_max_value = ctrl_croph_max_get, 1101 .get_def_value = ctrl_get_cropcapdh, 1102 }, { 1103 .desc = "Capture capability pixel aspect numerator", 1104 .name = "cropcap_pixel_numerator", 1105 .internal_id = PVR2_CID_CROPCAPPAN, 1106 .get_value = ctrl_get_cropcappan, 1107 }, { 1108 .desc = "Capture capability pixel aspect denominator", 1109 .name = "cropcap_pixel_denominator", 1110 .internal_id = PVR2_CID_CROPCAPPAD, 1111 .get_value = ctrl_get_cropcappad, 1112 }, { 1113 .desc = "Capture capability bounds top", 1114 .name = "cropcap_bounds_top", 1115 .internal_id = PVR2_CID_CROPCAPBT, 1116 .get_value = ctrl_get_cropcapbt, 1117 }, { 1118 .desc = "Capture capability bounds left", 1119 .name = "cropcap_bounds_left", 1120 .internal_id = PVR2_CID_CROPCAPBL, 1121 .get_value = ctrl_get_cropcapbl, 1122 }, { 1123 .desc = "Capture capability bounds width", 1124 .name = "cropcap_bounds_width", 1125 .internal_id = PVR2_CID_CROPCAPBW, 1126 .get_value = ctrl_get_cropcapbw, 1127 }, { 1128 .desc = "Capture capability bounds height", 1129 .name = "cropcap_bounds_height", 1130 .internal_id = PVR2_CID_CROPCAPBH, 1131 .get_value = ctrl_get_cropcapbh, 1132 },{ 1133 .desc = "Video Source", 1134 .name = "input", 1135 .internal_id = PVR2_CID_INPUT, 1136 .default_value = PVR2_CVAL_INPUT_TV, 1137 .check_value = ctrl_check_input, 1138 DEFREF(input), 1139 DEFENUM(control_values_input), 1140 },{ 1141 .desc = "Audio Mode", 1142 .name = "audio_mode", 1143 .internal_id = PVR2_CID_AUDIOMODE, 1144 .default_value = V4L2_TUNER_MODE_STEREO, 1145 DEFREF(audiomode), 1146 DEFENUM(control_values_audiomode), 1147 },{ 1148 .desc = "Horizontal capture resolution", 1149 .name = "resolution_hor", 1150 .internal_id = PVR2_CID_HRES, 1151 .default_value = 720, 1152 DEFREF(res_hor), 1153 DEFINT(19,720), 1154 },{ 1155 .desc = "Vertical capture resolution", 1156 .name = "resolution_ver", 1157 .internal_id = PVR2_CID_VRES, 1158 .default_value = 480, 1159 DEFREF(res_ver), 1160 DEFINT(17,576), 1161 /* Hook in check for video standard and adjust maximum 1162 depending on the standard. */ 1163 .get_max_value = ctrl_vres_max_get, 1164 .get_min_value = ctrl_vres_min_get, 1165 },{ 1166 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ, 1167 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000, 1168 .desc = "Audio Sampling Frequency", 1169 .name = "srate", 1170 DEFREF(srate), 1171 DEFENUM(control_values_srate), 1172 },{ 1173 .desc = "Tuner Frequency (Hz)", 1174 .name = "frequency", 1175 .internal_id = PVR2_CID_FREQUENCY, 1176 .default_value = 0, 1177 .set_value = ctrl_freq_set, 1178 .get_value = ctrl_freq_get, 1179 .is_dirty = ctrl_freq_is_dirty, 1180 .clear_dirty = ctrl_freq_clear_dirty, 1181 DEFINT(0,0), 1182 /* Hook in check for input value (tv/radio) and adjust 1183 max/min values accordingly */ 1184 .get_max_value = ctrl_freq_max_get, 1185 .get_min_value = ctrl_freq_min_get, 1186 },{ 1187 .desc = "Channel", 1188 .name = "channel", 1189 .set_value = ctrl_channel_set, 1190 .get_value = ctrl_channel_get, 1191 DEFINT(0,FREQTABLE_SIZE), 1192 },{ 1193 .desc = "Channel Program Frequency", 1194 .name = "freq_table_value", 1195 .set_value = ctrl_channelfreq_set, 1196 .get_value = ctrl_channelfreq_get, 1197 DEFINT(0,0), 1198 /* Hook in check for input value (tv/radio) and adjust 1199 max/min values accordingly */ 1200 .get_max_value = ctrl_freq_max_get, 1201 .get_min_value = ctrl_freq_min_get, 1202 },{ 1203 .desc = "Channel Program ID", 1204 .name = "freq_table_channel", 1205 .set_value = ctrl_channelprog_set, 1206 .get_value = ctrl_channelprog_get, 1207 DEFINT(0,FREQTABLE_SIZE), 1208 },{ 1209 .desc = "Streaming Enabled", 1210 .name = "streaming_enabled", 1211 .get_value = ctrl_streamingenabled_get, 1212 DEFBOOL, 1213 },{ 1214 .desc = "USB Speed", 1215 .name = "usb_speed", 1216 .get_value = ctrl_hsm_get, 1217 DEFENUM(control_values_hsm), 1218 },{ 1219 .desc = "Master State", 1220 .name = "master_state", 1221 .get_value = ctrl_masterstate_get, 1222 DEFENUM(pvr2_state_names), 1223 },{ 1224 .desc = "Signal Present", 1225 .name = "signal_present", 1226 .get_value = ctrl_signal_get, 1227 DEFINT(0,65535), 1228 },{ 1229 .desc = "Audio Modes Present", 1230 .name = "audio_modes_present", 1231 .get_value = ctrl_audio_modes_present_get, 1232 /* For this type we "borrow" the V4L2_TUNER_MODE enum from 1233 v4l. Nothing outside of this module cares about this, 1234 but I reuse it in order to also reuse the 1235 control_values_audiomode string table. */ 1236 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)| 1237 (1 << V4L2_TUNER_MODE_STEREO)| 1238 (1 << V4L2_TUNER_MODE_LANG1)| 1239 (1 << V4L2_TUNER_MODE_LANG2)), 1240 control_values_audiomode), 1241 },{ 1242 .desc = "Video Standards Available Mask", 1243 .name = "video_standard_mask_available", 1244 .internal_id = PVR2_CID_STDAVAIL, 1245 .skip_init = !0, 1246 .get_value = ctrl_stdavail_get, 1247 .set_value = ctrl_stdavail_set, 1248 .val_to_sym = ctrl_std_val_to_sym, 1249 .sym_to_val = ctrl_std_sym_to_val, 1250 .type = pvr2_ctl_bitmask, 1251 },{ 1252 .desc = "Video Standards In Use Mask", 1253 .name = "video_standard_mask_active", 1254 .internal_id = PVR2_CID_STDCUR, 1255 .skip_init = !0, 1256 .get_value = ctrl_stdcur_get, 1257 .set_value = ctrl_stdcur_set, 1258 .is_dirty = ctrl_stdcur_is_dirty, 1259 .clear_dirty = ctrl_stdcur_clear_dirty, 1260 .val_to_sym = ctrl_std_val_to_sym, 1261 .sym_to_val = ctrl_std_sym_to_val, 1262 .type = pvr2_ctl_bitmask, 1263 },{ 1264 .desc = "Video Standards Detected Mask", 1265 .name = "video_standard_mask_detected", 1266 .internal_id = PVR2_CID_STDDETECT, 1267 .skip_init = !0, 1268 .get_value = ctrl_stddetect_get, 1269 .val_to_sym = ctrl_std_val_to_sym, 1270 .sym_to_val = ctrl_std_sym_to_val, 1271 .type = pvr2_ctl_bitmask, 1272 } 1273 }; 1274 1275 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs) 1276 1277 1278 const char *pvr2_config_get_name(enum pvr2_config cfg) 1279 { 1280 switch (cfg) { 1281 case pvr2_config_empty: return "empty"; 1282 case pvr2_config_mpeg: return "mpeg"; 1283 case pvr2_config_vbi: return "vbi"; 1284 case pvr2_config_pcm: return "pcm"; 1285 case pvr2_config_rawvideo: return "raw video"; 1286 } 1287 return "<unknown>"; 1288 } 1289 1290 1291 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw) 1292 { 1293 return hdw->usb_dev; 1294 } 1295 1296 1297 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw) 1298 { 1299 return hdw->serial_number; 1300 } 1301 1302 1303 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw) 1304 { 1305 return hdw->bus_info; 1306 } 1307 1308 1309 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw) 1310 { 1311 return hdw->identifier; 1312 } 1313 1314 1315 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw) 1316 { 1317 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio; 1318 } 1319 1320 /* Set the currently tuned frequency and account for all possible 1321 driver-core side effects of this action. */ 1322 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val) 1323 { 1324 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { 1325 if (hdw->freqSelector) { 1326 /* Swing over to radio frequency selection */ 1327 hdw->freqSelector = 0; 1328 hdw->freqDirty = !0; 1329 } 1330 if (hdw->freqValRadio != val) { 1331 hdw->freqValRadio = val; 1332 hdw->freqSlotRadio = 0; 1333 hdw->freqDirty = !0; 1334 } 1335 } else { 1336 if (!(hdw->freqSelector)) { 1337 /* Swing over to television frequency selection */ 1338 hdw->freqSelector = 1; 1339 hdw->freqDirty = !0; 1340 } 1341 if (hdw->freqValTelevision != val) { 1342 hdw->freqValTelevision = val; 1343 hdw->freqSlotTelevision = 0; 1344 hdw->freqDirty = !0; 1345 } 1346 } 1347 } 1348 1349 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw) 1350 { 1351 return hdw->unit_number; 1352 } 1353 1354 1355 /* Attempt to locate one of the given set of files. Messages are logged 1356 appropriate to what has been found. The return value will be 0 or 1357 greater on success (it will be the index of the file name found) and 1358 fw_entry will be filled in. Otherwise a negative error is returned on 1359 failure. If the return value is -ENOENT then no viable firmware file 1360 could be located. */ 1361 static int pvr2_locate_firmware(struct pvr2_hdw *hdw, 1362 const struct firmware **fw_entry, 1363 const char *fwtypename, 1364 unsigned int fwcount, 1365 const char *fwnames[]) 1366 { 1367 unsigned int idx; 1368 int ret = -EINVAL; 1369 for (idx = 0; idx < fwcount; idx++) { 1370 ret = request_firmware(fw_entry, 1371 fwnames[idx], 1372 &hdw->usb_dev->dev); 1373 if (!ret) { 1374 trace_firmware("Located %s firmware: %s; uploading...", 1375 fwtypename, 1376 fwnames[idx]); 1377 return idx; 1378 } 1379 if (ret == -ENOENT) continue; 1380 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1381 "request_firmware fatal error with code=%d",ret); 1382 return ret; 1383 } 1384 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1385 "***WARNING*** Device %s firmware seems to be missing.", 1386 fwtypename); 1387 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1388 "Did you install the pvrusb2 firmware files in their proper location?"); 1389 if (fwcount == 1) { 1390 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1391 "request_firmware unable to locate %s file %s", 1392 fwtypename,fwnames[0]); 1393 } else { 1394 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1395 "request_firmware unable to locate one of the following %s files:", 1396 fwtypename); 1397 for (idx = 0; idx < fwcount; idx++) { 1398 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1399 "request_firmware: Failed to find %s", 1400 fwnames[idx]); 1401 } 1402 } 1403 return ret; 1404 } 1405 1406 1407 /* 1408 * pvr2_upload_firmware1(). 1409 * 1410 * Send the 8051 firmware to the device. After the upload, arrange for 1411 * device to re-enumerate. 1412 * 1413 * NOTE : the pointer to the firmware data given by request_firmware() 1414 * is not suitable for an usb transaction. 1415 * 1416 */ 1417 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw) 1418 { 1419 const struct firmware *fw_entry = NULL; 1420 void *fw_ptr; 1421 unsigned int pipe; 1422 unsigned int fwsize; 1423 int ret; 1424 u16 address; 1425 1426 if (!hdw->hdw_desc->fx2_firmware.cnt) { 1427 hdw->fw1_state = FW1_STATE_OK; 1428 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1429 "Connected device type defines no firmware to upload; ignoring firmware"); 1430 return -ENOTTY; 1431 } 1432 1433 hdw->fw1_state = FW1_STATE_FAILED; // default result 1434 1435 trace_firmware("pvr2_upload_firmware1"); 1436 1437 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller", 1438 hdw->hdw_desc->fx2_firmware.cnt, 1439 hdw->hdw_desc->fx2_firmware.lst); 1440 if (ret < 0) { 1441 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING; 1442 return ret; 1443 } 1444 1445 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f)); 1446 1447 pipe = usb_sndctrlpipe(hdw->usb_dev, 0); 1448 fwsize = fw_entry->size; 1449 1450 if ((fwsize != 0x2000) && 1451 (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) { 1452 if (hdw->hdw_desc->flag_fx2_16kb) { 1453 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1454 "Wrong fx2 firmware size (expected 8192 or 16384, got %u)", 1455 fwsize); 1456 } else { 1457 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1458 "Wrong fx2 firmware size (expected 8192, got %u)", 1459 fwsize); 1460 } 1461 release_firmware(fw_entry); 1462 return -ENOMEM; 1463 } 1464 1465 fw_ptr = kmalloc(0x800, GFP_KERNEL); 1466 if (fw_ptr == NULL){ 1467 release_firmware(fw_entry); 1468 return -ENOMEM; 1469 } 1470 1471 /* We have to hold the CPU during firmware upload. */ 1472 pvr2_hdw_cpureset_assert(hdw,1); 1473 1474 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes 1475 chunk. */ 1476 1477 ret = 0; 1478 for (address = 0; address < fwsize; address += 0x800) { 1479 memcpy(fw_ptr, fw_entry->data + address, 0x800); 1480 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address, 1481 0, fw_ptr, 0x800, HZ); 1482 } 1483 1484 trace_firmware("Upload done, releasing device's CPU"); 1485 1486 /* Now release the CPU. It will disconnect and reconnect later. */ 1487 pvr2_hdw_cpureset_assert(hdw,0); 1488 1489 kfree(fw_ptr); 1490 release_firmware(fw_entry); 1491 1492 trace_firmware("Upload done (%d bytes sent)",ret); 1493 1494 /* We should have written fwsize bytes */ 1495 if (ret == fwsize) { 1496 hdw->fw1_state = FW1_STATE_RELOAD; 1497 return 0; 1498 } 1499 1500 return -EIO; 1501 } 1502 1503 1504 /* 1505 * pvr2_upload_firmware2() 1506 * 1507 * This uploads encoder firmware on endpoint 2. 1508 * 1509 */ 1510 1511 int pvr2_upload_firmware2(struct pvr2_hdw *hdw) 1512 { 1513 const struct firmware *fw_entry = NULL; 1514 void *fw_ptr; 1515 unsigned int pipe, fw_len, fw_done, bcnt, icnt; 1516 int actual_length; 1517 int ret = 0; 1518 int fwidx; 1519 static const char *fw_files[] = { 1520 CX2341X_FIRM_ENC_FILENAME, 1521 }; 1522 1523 if (hdw->hdw_desc->flag_skip_cx23416_firmware) { 1524 return 0; 1525 } 1526 1527 trace_firmware("pvr2_upload_firmware2"); 1528 1529 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder", 1530 ARRAY_SIZE(fw_files), fw_files); 1531 if (ret < 0) return ret; 1532 fwidx = ret; 1533 ret = 0; 1534 /* Since we're about to completely reinitialize the encoder, 1535 invalidate our cached copy of its configuration state. Next 1536 time we configure the encoder, then we'll fully configure it. */ 1537 hdw->enc_cur_valid = 0; 1538 1539 /* Encoder is about to be reset so note that as far as we're 1540 concerned now, the encoder has never been run. */ 1541 del_timer_sync(&hdw->encoder_run_timer); 1542 if (hdw->state_encoder_runok) { 1543 hdw->state_encoder_runok = 0; 1544 trace_stbit("state_encoder_runok",hdw->state_encoder_runok); 1545 } 1546 1547 /* First prepare firmware loading */ 1548 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/ 1549 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/ 1550 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/ 1551 ret |= pvr2_hdw_cmd_deep_reset(hdw); 1552 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/ 1553 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/ 1554 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/ 1555 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/ 1556 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/ 1557 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/ 1558 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/ 1559 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/ 1560 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/ 1561 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/ 1562 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/ 1563 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/ 1564 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1); 1565 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16)); 1566 1567 if (ret) { 1568 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1569 "firmware2 upload prep failed, ret=%d",ret); 1570 release_firmware(fw_entry); 1571 goto done; 1572 } 1573 1574 /* Now send firmware */ 1575 1576 fw_len = fw_entry->size; 1577 1578 if (fw_len % sizeof(u32)) { 1579 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1580 "size of %s firmware must be a multiple of %zu bytes", 1581 fw_files[fwidx],sizeof(u32)); 1582 release_firmware(fw_entry); 1583 ret = -EINVAL; 1584 goto done; 1585 } 1586 1587 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL); 1588 if (fw_ptr == NULL){ 1589 release_firmware(fw_entry); 1590 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1591 "failed to allocate memory for firmware2 upload"); 1592 ret = -ENOMEM; 1593 goto done; 1594 } 1595 1596 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT); 1597 1598 fw_done = 0; 1599 for (fw_done = 0; fw_done < fw_len;) { 1600 bcnt = fw_len - fw_done; 1601 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE; 1602 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt); 1603 /* Usbsnoop log shows that we must swap bytes... */ 1604 /* Some background info: The data being swapped here is a 1605 firmware image destined for the mpeg encoder chip that 1606 lives at the other end of a USB endpoint. The encoder 1607 chip always talks in 32 bit chunks and its storage is 1608 organized into 32 bit words. However from the file 1609 system to the encoder chip everything is purely a byte 1610 stream. The firmware file's contents are always 32 bit 1611 swapped from what the encoder expects. Thus the need 1612 always exists to swap the bytes regardless of the endian 1613 type of the host processor and therefore swab32() makes 1614 the most sense. */ 1615 for (icnt = 0; icnt < bcnt/4 ; icnt++) 1616 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]); 1617 1618 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt, 1619 &actual_length, HZ); 1620 ret |= (actual_length != bcnt); 1621 if (ret) break; 1622 fw_done += bcnt; 1623 } 1624 1625 trace_firmware("upload of %s : %i / %i ", 1626 fw_files[fwidx],fw_done,fw_len); 1627 1628 kfree(fw_ptr); 1629 release_firmware(fw_entry); 1630 1631 if (ret) { 1632 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1633 "firmware2 upload transfer failure"); 1634 goto done; 1635 } 1636 1637 /* Finish upload */ 1638 1639 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/ 1640 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/ 1641 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16)); 1642 1643 if (ret) { 1644 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1645 "firmware2 upload post-proc failure"); 1646 } 1647 1648 done: 1649 if (hdw->hdw_desc->signal_routing_scheme == 1650 PVR2_ROUTING_SCHEME_GOTVIEW) { 1651 /* Ensure that GPIO 11 is set to output for GOTVIEW 1652 hardware. */ 1653 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0); 1654 } 1655 return ret; 1656 } 1657 1658 1659 static const char *pvr2_get_state_name(unsigned int st) 1660 { 1661 if (st < ARRAY_SIZE(pvr2_state_names)) { 1662 return pvr2_state_names[st]; 1663 } 1664 return "???"; 1665 } 1666 1667 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl) 1668 { 1669 /* Even though we really only care about the video decoder chip at 1670 this point, we'll broadcast stream on/off to all sub-devices 1671 anyway, just in case somebody else wants to hear the 1672 command... */ 1673 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s", 1674 (enablefl ? "on" : "off")); 1675 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl); 1676 v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl); 1677 if (hdw->decoder_client_id) { 1678 /* We get here if the encoder has been noticed. Otherwise 1679 we'll issue a warning to the user (which should 1680 normally never happen). */ 1681 return 0; 1682 } 1683 if (!hdw->flag_decoder_missed) { 1684 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1685 "WARNING: No decoder present"); 1686 hdw->flag_decoder_missed = !0; 1687 trace_stbit("flag_decoder_missed", 1688 hdw->flag_decoder_missed); 1689 } 1690 return -EIO; 1691 } 1692 1693 1694 int pvr2_hdw_get_state(struct pvr2_hdw *hdw) 1695 { 1696 return hdw->master_state; 1697 } 1698 1699 1700 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw) 1701 { 1702 if (!hdw->flag_tripped) return 0; 1703 hdw->flag_tripped = 0; 1704 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1705 "Clearing driver error statuss"); 1706 return !0; 1707 } 1708 1709 1710 int pvr2_hdw_untrip(struct pvr2_hdw *hdw) 1711 { 1712 int fl; 1713 LOCK_TAKE(hdw->big_lock); do { 1714 fl = pvr2_hdw_untrip_unlocked(hdw); 1715 } while (0); LOCK_GIVE(hdw->big_lock); 1716 if (fl) pvr2_hdw_state_sched(hdw); 1717 return 0; 1718 } 1719 1720 1721 1722 1723 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw) 1724 { 1725 return hdw->state_pipeline_req != 0; 1726 } 1727 1728 1729 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag) 1730 { 1731 int ret,st; 1732 LOCK_TAKE(hdw->big_lock); do { 1733 pvr2_hdw_untrip_unlocked(hdw); 1734 if ((!enable_flag) != !(hdw->state_pipeline_req)) { 1735 hdw->state_pipeline_req = enable_flag != 0; 1736 pvr2_trace(PVR2_TRACE_START_STOP, 1737 "/*--TRACE_STREAM--*/ %s", 1738 enable_flag ? "enable" : "disable"); 1739 } 1740 pvr2_hdw_state_sched(hdw); 1741 } while (0); LOCK_GIVE(hdw->big_lock); 1742 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret; 1743 if (enable_flag) { 1744 while ((st = hdw->master_state) != PVR2_STATE_RUN) { 1745 if (st != PVR2_STATE_READY) return -EIO; 1746 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret; 1747 } 1748 } 1749 return 0; 1750 } 1751 1752 1753 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config) 1754 { 1755 int fl; 1756 LOCK_TAKE(hdw->big_lock); 1757 if ((fl = (hdw->desired_stream_type != config)) != 0) { 1758 hdw->desired_stream_type = config; 1759 hdw->state_pipeline_config = 0; 1760 trace_stbit("state_pipeline_config", 1761 hdw->state_pipeline_config); 1762 pvr2_hdw_state_sched(hdw); 1763 } 1764 LOCK_GIVE(hdw->big_lock); 1765 if (fl) return 0; 1766 return pvr2_hdw_wait(hdw,0); 1767 } 1768 1769 1770 static int get_default_tuner_type(struct pvr2_hdw *hdw) 1771 { 1772 int unit_number = hdw->unit_number; 1773 int tp = -1; 1774 if ((unit_number >= 0) && (unit_number < PVR_NUM)) { 1775 tp = tuner[unit_number]; 1776 } 1777 if (tp < 0) return -EINVAL; 1778 hdw->tuner_type = tp; 1779 hdw->tuner_updated = !0; 1780 return 0; 1781 } 1782 1783 1784 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw) 1785 { 1786 int unit_number = hdw->unit_number; 1787 int tp = 0; 1788 if ((unit_number >= 0) && (unit_number < PVR_NUM)) { 1789 tp = video_std[unit_number]; 1790 if (tp) return tp; 1791 } 1792 return 0; 1793 } 1794 1795 1796 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw) 1797 { 1798 int unit_number = hdw->unit_number; 1799 int tp = 0; 1800 if ((unit_number >= 0) && (unit_number < PVR_NUM)) { 1801 tp = tolerance[unit_number]; 1802 } 1803 return tp; 1804 } 1805 1806 1807 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw) 1808 { 1809 /* Try a harmless request to fetch the eeprom's address over 1810 endpoint 1. See what happens. Only the full FX2 image can 1811 respond to this. If this probe fails then likely the FX2 1812 firmware needs be loaded. */ 1813 int result; 1814 LOCK_TAKE(hdw->ctl_lock); do { 1815 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR; 1816 result = pvr2_send_request_ex(hdw,HZ*1,!0, 1817 hdw->cmd_buffer,1, 1818 hdw->cmd_buffer,1); 1819 if (result < 0) break; 1820 } while(0); LOCK_GIVE(hdw->ctl_lock); 1821 if (result) { 1822 pvr2_trace(PVR2_TRACE_INIT, 1823 "Probe of device endpoint 1 result status %d", 1824 result); 1825 } else { 1826 pvr2_trace(PVR2_TRACE_INIT, 1827 "Probe of device endpoint 1 succeeded"); 1828 } 1829 return result == 0; 1830 } 1831 1832 struct pvr2_std_hack { 1833 v4l2_std_id pat; /* Pattern to match */ 1834 v4l2_std_id msk; /* Which bits we care about */ 1835 v4l2_std_id std; /* What additional standards or default to set */ 1836 }; 1837 1838 /* This data structure labels specific combinations of standards from 1839 tveeprom that we'll try to recognize. If we recognize one, then assume 1840 a specified default standard to use. This is here because tveeprom only 1841 tells us about available standards not the intended default standard (if 1842 any) for the device in question. We guess the default based on what has 1843 been reported as available. Note that this is only for guessing a 1844 default - which can always be overridden explicitly - and if the user 1845 has otherwise named a default then that default will always be used in 1846 place of this table. */ 1847 static const struct pvr2_std_hack std_eeprom_maps[] = { 1848 { /* PAL(B/G) */ 1849 .pat = V4L2_STD_B|V4L2_STD_GH, 1850 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G, 1851 }, 1852 { /* NTSC(M) */ 1853 .pat = V4L2_STD_MN, 1854 .std = V4L2_STD_NTSC_M, 1855 }, 1856 { /* PAL(I) */ 1857 .pat = V4L2_STD_PAL_I, 1858 .std = V4L2_STD_PAL_I, 1859 }, 1860 { /* SECAM(L/L') */ 1861 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC, 1862 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC, 1863 }, 1864 { /* PAL(D/D1/K) */ 1865 .pat = V4L2_STD_DK, 1866 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K, 1867 }, 1868 }; 1869 1870 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw) 1871 { 1872 char buf[40]; 1873 unsigned int bcnt; 1874 v4l2_std_id std1,std2,std3; 1875 1876 std1 = get_default_standard(hdw); 1877 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask; 1878 1879 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom); 1880 pvr2_trace(PVR2_TRACE_STD, 1881 "Supported video standard(s) reported available in hardware: %.*s", 1882 bcnt,buf); 1883 1884 hdw->std_mask_avail = hdw->std_mask_eeprom; 1885 1886 std2 = (std1|std3) & ~hdw->std_mask_avail; 1887 if (std2) { 1888 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2); 1889 pvr2_trace(PVR2_TRACE_STD, 1890 "Expanding supported video standards to include: %.*s", 1891 bcnt,buf); 1892 hdw->std_mask_avail |= std2; 1893 } 1894 1895 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail; 1896 1897 if (std1) { 1898 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1); 1899 pvr2_trace(PVR2_TRACE_STD, 1900 "Initial video standard forced to %.*s", 1901 bcnt,buf); 1902 hdw->std_mask_cur = std1; 1903 hdw->std_dirty = !0; 1904 return; 1905 } 1906 if (std3) { 1907 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3); 1908 pvr2_trace(PVR2_TRACE_STD, 1909 "Initial video standard (determined by device type): %.*s", 1910 bcnt, buf); 1911 hdw->std_mask_cur = std3; 1912 hdw->std_dirty = !0; 1913 return; 1914 } 1915 1916 { 1917 unsigned int idx; 1918 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) { 1919 if (std_eeprom_maps[idx].msk ? 1920 ((std_eeprom_maps[idx].pat ^ 1921 hdw->std_mask_eeprom) & 1922 std_eeprom_maps[idx].msk) : 1923 (std_eeprom_maps[idx].pat != 1924 hdw->std_mask_eeprom)) continue; 1925 bcnt = pvr2_std_id_to_str(buf,sizeof(buf), 1926 std_eeprom_maps[idx].std); 1927 pvr2_trace(PVR2_TRACE_STD, 1928 "Initial video standard guessed as %.*s", 1929 bcnt,buf); 1930 hdw->std_mask_cur = std_eeprom_maps[idx].std; 1931 hdw->std_dirty = !0; 1932 return; 1933 } 1934 } 1935 1936 } 1937 1938 1939 static unsigned int pvr2_copy_i2c_addr_list( 1940 unsigned short *dst, const unsigned char *src, 1941 unsigned int dst_max) 1942 { 1943 unsigned int cnt = 0; 1944 if (!src) return 0; 1945 while (src[cnt] && (cnt + 1) < dst_max) { 1946 dst[cnt] = src[cnt]; 1947 cnt++; 1948 } 1949 dst[cnt] = I2C_CLIENT_END; 1950 return cnt; 1951 } 1952 1953 1954 static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw) 1955 { 1956 /* 1957 Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness 1958 for cx25840 causes that module to correctly set up its video 1959 scaling. This is really a problem in the cx25840 module itself, 1960 but we work around it here. The problem has not been seen in 1961 ivtv because there VBI is supported and set up. We don't do VBI 1962 here (at least not yet) and thus we never attempted to even set 1963 it up. 1964 */ 1965 struct v4l2_format fmt; 1966 if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) { 1967 /* We're not using a cx25840 so don't enable the hack */ 1968 return; 1969 } 1970 1971 pvr2_trace(PVR2_TRACE_INIT, 1972 "Module ID %u: Executing cx25840 VBI hack", 1973 hdw->decoder_client_id); 1974 memset(&fmt, 0, sizeof(fmt)); 1975 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE; 1976 fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525; 1977 fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525; 1978 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id, 1979 vbi, s_sliced_fmt, &fmt.fmt.sliced); 1980 } 1981 1982 1983 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw, 1984 const struct pvr2_device_client_desc *cd) 1985 { 1986 const char *fname; 1987 unsigned char mid; 1988 struct v4l2_subdev *sd; 1989 unsigned int i2ccnt; 1990 const unsigned char *p; 1991 /* Arbitrary count - max # i2c addresses we will probe */ 1992 unsigned short i2caddr[25]; 1993 1994 mid = cd->module_id; 1995 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL; 1996 if (!fname) { 1997 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 1998 "Module ID %u for device %s has no name? The driver might have a configuration problem.", 1999 mid, 2000 hdw->hdw_desc->description); 2001 return -EINVAL; 2002 } 2003 pvr2_trace(PVR2_TRACE_INIT, 2004 "Module ID %u (%s) for device %s being loaded...", 2005 mid, fname, 2006 hdw->hdw_desc->description); 2007 2008 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list, 2009 ARRAY_SIZE(i2caddr)); 2010 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ? 2011 module_i2c_addresses[mid] : NULL) != NULL)) { 2012 /* Second chance: Try default i2c address list */ 2013 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p, 2014 ARRAY_SIZE(i2caddr)); 2015 if (i2ccnt) { 2016 pvr2_trace(PVR2_TRACE_INIT, 2017 "Module ID %u: Using default i2c address list", 2018 mid); 2019 } 2020 } 2021 2022 if (!i2ccnt) { 2023 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 2024 "Module ID %u (%s) for device %s: No i2c addresses. The driver might have a configuration problem.", 2025 mid, fname, hdw->hdw_desc->description); 2026 return -EINVAL; 2027 } 2028 2029 if (i2ccnt == 1) { 2030 pvr2_trace(PVR2_TRACE_INIT, 2031 "Module ID %u: Setting up with specified i2c address 0x%x", 2032 mid, i2caddr[0]); 2033 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap, 2034 fname, i2caddr[0], NULL); 2035 } else { 2036 pvr2_trace(PVR2_TRACE_INIT, 2037 "Module ID %u: Setting up with address probe list", 2038 mid); 2039 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap, 2040 fname, 0, i2caddr); 2041 } 2042 2043 if (!sd) { 2044 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 2045 "Module ID %u (%s) for device %s failed to load. Possible missing sub-device kernel module or initialization failure within module.", 2046 mid, fname, hdw->hdw_desc->description); 2047 return -EIO; 2048 } 2049 2050 /* Tag this sub-device instance with the module ID we know about. 2051 In other places we'll use that tag to determine if the instance 2052 requires special handling. */ 2053 sd->grp_id = mid; 2054 2055 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname); 2056 2057 2058 /* client-specific setup... */ 2059 switch (mid) { 2060 case PVR2_CLIENT_ID_CX25840: 2061 case PVR2_CLIENT_ID_SAA7115: 2062 hdw->decoder_client_id = mid; 2063 break; 2064 default: break; 2065 } 2066 2067 return 0; 2068 } 2069 2070 2071 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw) 2072 { 2073 unsigned int idx; 2074 const struct pvr2_string_table *cm; 2075 const struct pvr2_device_client_table *ct; 2076 int okFl = !0; 2077 2078 cm = &hdw->hdw_desc->client_modules; 2079 for (idx = 0; idx < cm->cnt; idx++) { 2080 request_module(cm->lst[idx]); 2081 } 2082 2083 ct = &hdw->hdw_desc->client_table; 2084 for (idx = 0; idx < ct->cnt; idx++) { 2085 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0; 2086 } 2087 if (!okFl) { 2088 hdw->flag_modulefail = !0; 2089 pvr2_hdw_render_useless(hdw); 2090 } 2091 } 2092 2093 2094 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw) 2095 { 2096 int ret; 2097 unsigned int idx; 2098 struct pvr2_ctrl *cptr; 2099 int reloadFl = 0; 2100 if (hdw->hdw_desc->fx2_firmware.cnt) { 2101 if (!reloadFl) { 2102 reloadFl = 2103 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints 2104 == 0); 2105 if (reloadFl) { 2106 pvr2_trace(PVR2_TRACE_INIT, 2107 "USB endpoint config looks strange; possibly firmware needs to be loaded"); 2108 } 2109 } 2110 if (!reloadFl) { 2111 reloadFl = !pvr2_hdw_check_firmware(hdw); 2112 if (reloadFl) { 2113 pvr2_trace(PVR2_TRACE_INIT, 2114 "Check for FX2 firmware failed; possibly firmware needs to be loaded"); 2115 } 2116 } 2117 if (reloadFl) { 2118 if (pvr2_upload_firmware1(hdw) != 0) { 2119 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 2120 "Failure uploading firmware1"); 2121 } 2122 return; 2123 } 2124 } 2125 hdw->fw1_state = FW1_STATE_OK; 2126 2127 if (!pvr2_hdw_dev_ok(hdw)) return; 2128 2129 hdw->force_dirty = !0; 2130 2131 if (!hdw->hdw_desc->flag_no_powerup) { 2132 pvr2_hdw_cmd_powerup(hdw); 2133 if (!pvr2_hdw_dev_ok(hdw)) return; 2134 } 2135 2136 /* Take the IR chip out of reset, if appropriate */ 2137 if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) { 2138 pvr2_issue_simple_cmd(hdw, 2139 FX2CMD_HCW_ZILOG_RESET | 2140 (1 << 8) | 2141 ((0) << 16)); 2142 } 2143 2144 // This step MUST happen after the earlier powerup step. 2145 pvr2_i2c_core_init(hdw); 2146 if (!pvr2_hdw_dev_ok(hdw)) return; 2147 2148 pvr2_hdw_load_modules(hdw); 2149 if (!pvr2_hdw_dev_ok(hdw)) return; 2150 2151 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw); 2152 2153 for (idx = 0; idx < CTRLDEF_COUNT; idx++) { 2154 cptr = hdw->controls + idx; 2155 if (cptr->info->skip_init) continue; 2156 if (!cptr->info->set_value) continue; 2157 cptr->info->set_value(cptr,~0,cptr->info->default_value); 2158 } 2159 2160 pvr2_hdw_cx25840_vbi_hack(hdw); 2161 2162 /* Set up special default values for the television and radio 2163 frequencies here. It's not really important what these defaults 2164 are, but I set them to something usable in the Chicago area just 2165 to make driver testing a little easier. */ 2166 2167 hdw->freqValTelevision = default_tv_freq; 2168 hdw->freqValRadio = default_radio_freq; 2169 2170 // Do not use pvr2_reset_ctl_endpoints() here. It is not 2171 // thread-safe against the normal pvr2_send_request() mechanism. 2172 // (We should make it thread safe). 2173 2174 if (hdw->hdw_desc->flag_has_hauppauge_rom) { 2175 ret = pvr2_hdw_get_eeprom_addr(hdw); 2176 if (!pvr2_hdw_dev_ok(hdw)) return; 2177 if (ret < 0) { 2178 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 2179 "Unable to determine location of eeprom, skipping"); 2180 } else { 2181 hdw->eeprom_addr = ret; 2182 pvr2_eeprom_analyze(hdw); 2183 if (!pvr2_hdw_dev_ok(hdw)) return; 2184 } 2185 } else { 2186 hdw->tuner_type = hdw->hdw_desc->default_tuner_type; 2187 hdw->tuner_updated = !0; 2188 hdw->std_mask_eeprom = V4L2_STD_ALL; 2189 } 2190 2191 if (hdw->serial_number) { 2192 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1, 2193 "sn-%lu", hdw->serial_number); 2194 } else if (hdw->unit_number >= 0) { 2195 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1, 2196 "unit-%c", 2197 hdw->unit_number + 'a'); 2198 } else { 2199 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1, 2200 "unit-??"); 2201 } 2202 hdw->identifier[idx] = 0; 2203 2204 pvr2_hdw_setup_std(hdw); 2205 2206 if (!get_default_tuner_type(hdw)) { 2207 pvr2_trace(PVR2_TRACE_INIT, 2208 "pvr2_hdw_setup: Tuner type overridden to %d", 2209 hdw->tuner_type); 2210 } 2211 2212 2213 if (!pvr2_hdw_dev_ok(hdw)) return; 2214 2215 if (hdw->hdw_desc->signal_routing_scheme == 2216 PVR2_ROUTING_SCHEME_GOTVIEW) { 2217 /* Ensure that GPIO 11 is set to output for GOTVIEW 2218 hardware. */ 2219 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0); 2220 } 2221 2222 pvr2_hdw_commit_setup(hdw); 2223 2224 hdw->vid_stream = pvr2_stream_create(); 2225 if (!pvr2_hdw_dev_ok(hdw)) return; 2226 pvr2_trace(PVR2_TRACE_INIT, 2227 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream); 2228 if (hdw->vid_stream) { 2229 idx = get_default_error_tolerance(hdw); 2230 if (idx) { 2231 pvr2_trace(PVR2_TRACE_INIT, 2232 "pvr2_hdw_setup: video stream %p setting tolerance %u", 2233 hdw->vid_stream,idx); 2234 } 2235 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev, 2236 PVR2_VID_ENDPOINT,idx); 2237 } 2238 2239 if (!pvr2_hdw_dev_ok(hdw)) return; 2240 2241 hdw->flag_init_ok = !0; 2242 2243 pvr2_hdw_state_sched(hdw); 2244 } 2245 2246 2247 /* Set up the structure and attempt to put the device into a usable state. 2248 This can be a time-consuming operation, which is why it is not done 2249 internally as part of the create() step. */ 2250 static void pvr2_hdw_setup(struct pvr2_hdw *hdw) 2251 { 2252 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw); 2253 do { 2254 pvr2_hdw_setup_low(hdw); 2255 pvr2_trace(PVR2_TRACE_INIT, 2256 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d", 2257 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok); 2258 if (pvr2_hdw_dev_ok(hdw)) { 2259 if (hdw->flag_init_ok) { 2260 pvr2_trace( 2261 PVR2_TRACE_INFO, 2262 "Device initialization completed successfully."); 2263 break; 2264 } 2265 if (hdw->fw1_state == FW1_STATE_RELOAD) { 2266 pvr2_trace( 2267 PVR2_TRACE_INFO, 2268 "Device microcontroller firmware (re)loaded; it should now reset and reconnect."); 2269 break; 2270 } 2271 pvr2_trace( 2272 PVR2_TRACE_ERROR_LEGS, 2273 "Device initialization was not successful."); 2274 if (hdw->fw1_state == FW1_STATE_MISSING) { 2275 pvr2_trace( 2276 PVR2_TRACE_ERROR_LEGS, 2277 "Giving up since device microcontroller firmware appears to be missing."); 2278 break; 2279 } 2280 } 2281 if (hdw->flag_modulefail) { 2282 pvr2_trace( 2283 PVR2_TRACE_ERROR_LEGS, 2284 "***WARNING*** pvrusb2 driver initialization failed due to the failure of one or more sub-device kernel modules."); 2285 pvr2_trace( 2286 PVR2_TRACE_ERROR_LEGS, 2287 "You need to resolve the failing condition before this driver can function. There should be some earlier messages giving more information about the problem."); 2288 break; 2289 } 2290 if (procreload) { 2291 pvr2_trace( 2292 PVR2_TRACE_ERROR_LEGS, 2293 "Attempting pvrusb2 recovery by reloading primary firmware."); 2294 pvr2_trace( 2295 PVR2_TRACE_ERROR_LEGS, 2296 "If this works, device should disconnect and reconnect in a sane state."); 2297 hdw->fw1_state = FW1_STATE_UNKNOWN; 2298 pvr2_upload_firmware1(hdw); 2299 } else { 2300 pvr2_trace( 2301 PVR2_TRACE_ERROR_LEGS, 2302 "***WARNING*** pvrusb2 device hardware appears to be jammed and I can't clear it."); 2303 pvr2_trace( 2304 PVR2_TRACE_ERROR_LEGS, 2305 "You might need to power cycle the pvrusb2 device in order to recover."); 2306 } 2307 } while (0); 2308 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw); 2309 } 2310 2311 2312 /* Perform second stage initialization. Set callback pointer first so that 2313 we can avoid a possible initialization race (if the kernel thread runs 2314 before the callback has been set). */ 2315 int pvr2_hdw_initialize(struct pvr2_hdw *hdw, 2316 void (*callback_func)(void *), 2317 void *callback_data) 2318 { 2319 LOCK_TAKE(hdw->big_lock); do { 2320 if (hdw->flag_disconnected) { 2321 /* Handle a race here: If we're already 2322 disconnected by this point, then give up. If we 2323 get past this then we'll remain connected for 2324 the duration of initialization since the entire 2325 initialization sequence is now protected by the 2326 big_lock. */ 2327 break; 2328 } 2329 hdw->state_data = callback_data; 2330 hdw->state_func = callback_func; 2331 pvr2_hdw_setup(hdw); 2332 } while (0); LOCK_GIVE(hdw->big_lock); 2333 return hdw->flag_init_ok; 2334 } 2335 2336 2337 /* Create, set up, and return a structure for interacting with the 2338 underlying hardware. */ 2339 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf, 2340 const struct usb_device_id *devid) 2341 { 2342 unsigned int idx,cnt1,cnt2,m; 2343 struct pvr2_hdw *hdw = NULL; 2344 int valid_std_mask; 2345 struct pvr2_ctrl *cptr; 2346 struct usb_device *usb_dev; 2347 const struct pvr2_device_desc *hdw_desc; 2348 __u8 ifnum; 2349 struct v4l2_queryctrl qctrl; 2350 struct pvr2_ctl_info *ciptr; 2351 2352 usb_dev = interface_to_usbdev(intf); 2353 2354 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info); 2355 2356 if (hdw_desc == NULL) { 2357 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create: No device description pointer, unable to continue."); 2358 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type, please contact Mike Isely <isely@pobox.com> to get it included in the driver\n"); 2359 goto fail; 2360 } 2361 2362 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL); 2363 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"", 2364 hdw,hdw_desc->description); 2365 pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s", 2366 hdw_desc->description); 2367 if (hdw_desc->flag_is_experimental) { 2368 pvr2_trace(PVR2_TRACE_INFO, "**********"); 2369 pvr2_trace(PVR2_TRACE_INFO, 2370 "WARNING: Support for this device (%s) is experimental.", 2371 hdw_desc->description); 2372 pvr2_trace(PVR2_TRACE_INFO, 2373 "Important functionality might not be entirely working."); 2374 pvr2_trace(PVR2_TRACE_INFO, 2375 "Please consider contacting the driver author to help with further stabilization of the driver."); 2376 pvr2_trace(PVR2_TRACE_INFO, "**********"); 2377 } 2378 if (!hdw) goto fail; 2379 2380 setup_timer(&hdw->quiescent_timer, pvr2_hdw_quiescent_timeout, 2381 (unsigned long)hdw); 2382 2383 setup_timer(&hdw->decoder_stabilization_timer, 2384 pvr2_hdw_decoder_stabilization_timeout, 2385 (unsigned long)hdw); 2386 2387 setup_timer(&hdw->encoder_wait_timer, pvr2_hdw_encoder_wait_timeout, 2388 (unsigned long)hdw); 2389 2390 setup_timer(&hdw->encoder_run_timer, pvr2_hdw_encoder_run_timeout, 2391 (unsigned long)hdw); 2392 2393 hdw->master_state = PVR2_STATE_DEAD; 2394 2395 init_waitqueue_head(&hdw->state_wait_data); 2396 2397 hdw->tuner_signal_stale = !0; 2398 cx2341x_fill_defaults(&hdw->enc_ctl_state); 2399 2400 /* Calculate which inputs are OK */ 2401 m = 0; 2402 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV; 2403 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) { 2404 m |= 1 << PVR2_CVAL_INPUT_DTV; 2405 } 2406 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO; 2407 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE; 2408 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO; 2409 hdw->input_avail_mask = m; 2410 hdw->input_allowed_mask = hdw->input_avail_mask; 2411 2412 /* If not a hybrid device, pathway_state never changes. So 2413 initialize it here to what it should forever be. */ 2414 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) { 2415 hdw->pathway_state = PVR2_PATHWAY_ANALOG; 2416 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) { 2417 hdw->pathway_state = PVR2_PATHWAY_DIGITAL; 2418 } 2419 2420 hdw->control_cnt = CTRLDEF_COUNT; 2421 hdw->control_cnt += MPEGDEF_COUNT; 2422 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt, 2423 GFP_KERNEL); 2424 if (!hdw->controls) goto fail; 2425 hdw->hdw_desc = hdw_desc; 2426 hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme; 2427 for (idx = 0; idx < hdw->control_cnt; idx++) { 2428 cptr = hdw->controls + idx; 2429 cptr->hdw = hdw; 2430 } 2431 for (idx = 0; idx < 32; idx++) { 2432 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx]; 2433 } 2434 for (idx = 0; idx < CTRLDEF_COUNT; idx++) { 2435 cptr = hdw->controls + idx; 2436 cptr->info = control_defs+idx; 2437 } 2438 2439 /* Ensure that default input choice is a valid one. */ 2440 m = hdw->input_avail_mask; 2441 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) { 2442 if (!((1 << idx) & m)) continue; 2443 hdw->input_val = idx; 2444 break; 2445 } 2446 2447 /* Define and configure additional controls from cx2341x module. */ 2448 hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT, 2449 sizeof(*(hdw->mpeg_ctrl_info)), 2450 GFP_KERNEL); 2451 if (!hdw->mpeg_ctrl_info) goto fail; 2452 for (idx = 0; idx < MPEGDEF_COUNT; idx++) { 2453 cptr = hdw->controls + idx + CTRLDEF_COUNT; 2454 ciptr = &(hdw->mpeg_ctrl_info[idx].info); 2455 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc; 2456 ciptr->name = mpeg_ids[idx].strid; 2457 ciptr->v4l_id = mpeg_ids[idx].id; 2458 ciptr->skip_init = !0; 2459 ciptr->get_value = ctrl_cx2341x_get; 2460 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags; 2461 ciptr->is_dirty = ctrl_cx2341x_is_dirty; 2462 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty; 2463 qctrl.id = ciptr->v4l_id; 2464 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl); 2465 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) { 2466 ciptr->set_value = ctrl_cx2341x_set; 2467 } 2468 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name, 2469 PVR2_CTLD_INFO_DESC_SIZE); 2470 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0; 2471 ciptr->default_value = qctrl.default_value; 2472 switch (qctrl.type) { 2473 default: 2474 case V4L2_CTRL_TYPE_INTEGER: 2475 ciptr->type = pvr2_ctl_int; 2476 ciptr->def.type_int.min_value = qctrl.minimum; 2477 ciptr->def.type_int.max_value = qctrl.maximum; 2478 break; 2479 case V4L2_CTRL_TYPE_BOOLEAN: 2480 ciptr->type = pvr2_ctl_bool; 2481 break; 2482 case V4L2_CTRL_TYPE_MENU: 2483 ciptr->type = pvr2_ctl_enum; 2484 ciptr->def.type_enum.value_names = 2485 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state, 2486 ciptr->v4l_id); 2487 for (cnt1 = 0; 2488 ciptr->def.type_enum.value_names[cnt1] != NULL; 2489 cnt1++) { } 2490 ciptr->def.type_enum.count = cnt1; 2491 break; 2492 } 2493 cptr->info = ciptr; 2494 } 2495 2496 // Initialize control data regarding video standard masks 2497 valid_std_mask = pvr2_std_get_usable(); 2498 for (idx = 0; idx < 32; idx++) { 2499 if (!(valid_std_mask & (1 << idx))) continue; 2500 cnt1 = pvr2_std_id_to_str( 2501 hdw->std_mask_names[idx], 2502 sizeof(hdw->std_mask_names[idx])-1, 2503 1 << idx); 2504 hdw->std_mask_names[idx][cnt1] = 0; 2505 } 2506 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL); 2507 if (cptr) { 2508 memcpy(&hdw->std_info_avail,cptr->info, 2509 sizeof(hdw->std_info_avail)); 2510 cptr->info = &hdw->std_info_avail; 2511 hdw->std_info_avail.def.type_bitmask.bit_names = 2512 hdw->std_mask_ptrs; 2513 hdw->std_info_avail.def.type_bitmask.valid_bits = 2514 valid_std_mask; 2515 } 2516 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR); 2517 if (cptr) { 2518 memcpy(&hdw->std_info_cur,cptr->info, 2519 sizeof(hdw->std_info_cur)); 2520 cptr->info = &hdw->std_info_cur; 2521 hdw->std_info_cur.def.type_bitmask.bit_names = 2522 hdw->std_mask_ptrs; 2523 hdw->std_info_cur.def.type_bitmask.valid_bits = 2524 valid_std_mask; 2525 } 2526 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDDETECT); 2527 if (cptr) { 2528 memcpy(&hdw->std_info_detect,cptr->info, 2529 sizeof(hdw->std_info_detect)); 2530 cptr->info = &hdw->std_info_detect; 2531 hdw->std_info_detect.def.type_bitmask.bit_names = 2532 hdw->std_mask_ptrs; 2533 hdw->std_info_detect.def.type_bitmask.valid_bits = 2534 valid_std_mask; 2535 } 2536 2537 hdw->cropcap_stale = !0; 2538 hdw->eeprom_addr = -1; 2539 hdw->unit_number = -1; 2540 hdw->v4l_minor_number_video = -1; 2541 hdw->v4l_minor_number_vbi = -1; 2542 hdw->v4l_minor_number_radio = -1; 2543 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL); 2544 if (!hdw->ctl_write_buffer) goto fail; 2545 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL); 2546 if (!hdw->ctl_read_buffer) goto fail; 2547 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL); 2548 if (!hdw->ctl_write_urb) goto fail; 2549 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL); 2550 if (!hdw->ctl_read_urb) goto fail; 2551 2552 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) { 2553 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 2554 "Error registering with v4l core, giving up"); 2555 goto fail; 2556 } 2557 mutex_lock(&pvr2_unit_mtx); 2558 do { 2559 for (idx = 0; idx < PVR_NUM; idx++) { 2560 if (unit_pointers[idx]) continue; 2561 hdw->unit_number = idx; 2562 unit_pointers[idx] = hdw; 2563 break; 2564 } 2565 } while (0); 2566 mutex_unlock(&pvr2_unit_mtx); 2567 2568 cnt1 = 0; 2569 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2"); 2570 cnt1 += cnt2; 2571 if (hdw->unit_number >= 0) { 2572 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c", 2573 ('a' + hdw->unit_number)); 2574 cnt1 += cnt2; 2575 } 2576 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1; 2577 hdw->name[cnt1] = 0; 2578 2579 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll); 2580 2581 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s", 2582 hdw->unit_number,hdw->name); 2583 2584 hdw->tuner_type = -1; 2585 hdw->flag_ok = !0; 2586 2587 hdw->usb_intf = intf; 2588 hdw->usb_dev = usb_dev; 2589 2590 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info)); 2591 2592 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber; 2593 usb_set_interface(hdw->usb_dev,ifnum,0); 2594 2595 mutex_init(&hdw->ctl_lock_mutex); 2596 mutex_init(&hdw->big_lock_mutex); 2597 2598 return hdw; 2599 fail: 2600 if (hdw) { 2601 del_timer_sync(&hdw->quiescent_timer); 2602 del_timer_sync(&hdw->decoder_stabilization_timer); 2603 del_timer_sync(&hdw->encoder_run_timer); 2604 del_timer_sync(&hdw->encoder_wait_timer); 2605 flush_work(&hdw->workpoll); 2606 usb_free_urb(hdw->ctl_read_urb); 2607 usb_free_urb(hdw->ctl_write_urb); 2608 kfree(hdw->ctl_read_buffer); 2609 kfree(hdw->ctl_write_buffer); 2610 kfree(hdw->controls); 2611 kfree(hdw->mpeg_ctrl_info); 2612 kfree(hdw); 2613 } 2614 return NULL; 2615 } 2616 2617 2618 /* Remove _all_ associations between this driver and the underlying USB 2619 layer. */ 2620 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw) 2621 { 2622 if (hdw->flag_disconnected) return; 2623 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw); 2624 if (hdw->ctl_read_urb) { 2625 usb_kill_urb(hdw->ctl_read_urb); 2626 usb_free_urb(hdw->ctl_read_urb); 2627 hdw->ctl_read_urb = NULL; 2628 } 2629 if (hdw->ctl_write_urb) { 2630 usb_kill_urb(hdw->ctl_write_urb); 2631 usb_free_urb(hdw->ctl_write_urb); 2632 hdw->ctl_write_urb = NULL; 2633 } 2634 if (hdw->ctl_read_buffer) { 2635 kfree(hdw->ctl_read_buffer); 2636 hdw->ctl_read_buffer = NULL; 2637 } 2638 if (hdw->ctl_write_buffer) { 2639 kfree(hdw->ctl_write_buffer); 2640 hdw->ctl_write_buffer = NULL; 2641 } 2642 hdw->flag_disconnected = !0; 2643 /* If we don't do this, then there will be a dangling struct device 2644 reference to our disappearing device persisting inside the V4L 2645 core... */ 2646 v4l2_device_disconnect(&hdw->v4l2_dev); 2647 hdw->usb_dev = NULL; 2648 hdw->usb_intf = NULL; 2649 pvr2_hdw_render_useless(hdw); 2650 } 2651 2652 void pvr2_hdw_set_v4l2_dev(struct pvr2_hdw *hdw, struct video_device *vdev) 2653 { 2654 vdev->v4l2_dev = &hdw->v4l2_dev; 2655 } 2656 2657 /* Destroy hardware interaction structure */ 2658 void pvr2_hdw_destroy(struct pvr2_hdw *hdw) 2659 { 2660 if (!hdw) return; 2661 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw); 2662 flush_work(&hdw->workpoll); 2663 del_timer_sync(&hdw->quiescent_timer); 2664 del_timer_sync(&hdw->decoder_stabilization_timer); 2665 del_timer_sync(&hdw->encoder_run_timer); 2666 del_timer_sync(&hdw->encoder_wait_timer); 2667 if (hdw->fw_buffer) { 2668 kfree(hdw->fw_buffer); 2669 hdw->fw_buffer = NULL; 2670 } 2671 if (hdw->vid_stream) { 2672 pvr2_stream_destroy(hdw->vid_stream); 2673 hdw->vid_stream = NULL; 2674 } 2675 pvr2_i2c_core_done(hdw); 2676 v4l2_device_unregister(&hdw->v4l2_dev); 2677 pvr2_hdw_remove_usb_stuff(hdw); 2678 mutex_lock(&pvr2_unit_mtx); 2679 do { 2680 if ((hdw->unit_number >= 0) && 2681 (hdw->unit_number < PVR_NUM) && 2682 (unit_pointers[hdw->unit_number] == hdw)) { 2683 unit_pointers[hdw->unit_number] = NULL; 2684 } 2685 } while (0); 2686 mutex_unlock(&pvr2_unit_mtx); 2687 kfree(hdw->controls); 2688 kfree(hdw->mpeg_ctrl_info); 2689 kfree(hdw); 2690 } 2691 2692 2693 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw) 2694 { 2695 return (hdw && hdw->flag_ok); 2696 } 2697 2698 2699 /* Called when hardware has been unplugged */ 2700 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw) 2701 { 2702 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw); 2703 LOCK_TAKE(hdw->big_lock); 2704 LOCK_TAKE(hdw->ctl_lock); 2705 pvr2_hdw_remove_usb_stuff(hdw); 2706 LOCK_GIVE(hdw->ctl_lock); 2707 LOCK_GIVE(hdw->big_lock); 2708 } 2709 2710 2711 /* Get the number of defined controls */ 2712 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw) 2713 { 2714 return hdw->control_cnt; 2715 } 2716 2717 2718 /* Retrieve a control handle given its index (0..count-1) */ 2719 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw, 2720 unsigned int idx) 2721 { 2722 if (idx >= hdw->control_cnt) return NULL; 2723 return hdw->controls + idx; 2724 } 2725 2726 2727 /* Retrieve a control handle given its index (0..count-1) */ 2728 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw, 2729 unsigned int ctl_id) 2730 { 2731 struct pvr2_ctrl *cptr; 2732 unsigned int idx; 2733 int i; 2734 2735 /* This could be made a lot more efficient, but for now... */ 2736 for (idx = 0; idx < hdw->control_cnt; idx++) { 2737 cptr = hdw->controls + idx; 2738 i = cptr->info->internal_id; 2739 if (i && (i == ctl_id)) return cptr; 2740 } 2741 return NULL; 2742 } 2743 2744 2745 /* Given a V4L ID, retrieve the control structure associated with it. */ 2746 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id) 2747 { 2748 struct pvr2_ctrl *cptr; 2749 unsigned int idx; 2750 int i; 2751 2752 /* This could be made a lot more efficient, but for now... */ 2753 for (idx = 0; idx < hdw->control_cnt; idx++) { 2754 cptr = hdw->controls + idx; 2755 i = cptr->info->v4l_id; 2756 if (i && (i == ctl_id)) return cptr; 2757 } 2758 return NULL; 2759 } 2760 2761 2762 /* Given a V4L ID for its immediate predecessor, retrieve the control 2763 structure associated with it. */ 2764 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw, 2765 unsigned int ctl_id) 2766 { 2767 struct pvr2_ctrl *cptr,*cp2; 2768 unsigned int idx; 2769 int i; 2770 2771 /* This could be made a lot more efficient, but for now... */ 2772 cp2 = NULL; 2773 for (idx = 0; idx < hdw->control_cnt; idx++) { 2774 cptr = hdw->controls + idx; 2775 i = cptr->info->v4l_id; 2776 if (!i) continue; 2777 if (i <= ctl_id) continue; 2778 if (cp2 && (cp2->info->v4l_id < i)) continue; 2779 cp2 = cptr; 2780 } 2781 return cp2; 2782 return NULL; 2783 } 2784 2785 2786 static const char *get_ctrl_typename(enum pvr2_ctl_type tp) 2787 { 2788 switch (tp) { 2789 case pvr2_ctl_int: return "integer"; 2790 case pvr2_ctl_enum: return "enum"; 2791 case pvr2_ctl_bool: return "boolean"; 2792 case pvr2_ctl_bitmask: return "bitmask"; 2793 } 2794 return ""; 2795 } 2796 2797 2798 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id, 2799 const char *name, int val) 2800 { 2801 struct v4l2_control ctrl; 2802 struct v4l2_subdev *sd; 2803 2804 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val); 2805 memset(&ctrl, 0, sizeof(ctrl)); 2806 ctrl.id = id; 2807 ctrl.value = val; 2808 2809 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) 2810 v4l2_s_ctrl(NULL, sd->ctrl_handler, &ctrl); 2811 } 2812 2813 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \ 2814 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \ 2815 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \ 2816 } 2817 2818 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw) 2819 { 2820 v4l2_std_id std; 2821 std = (v4l2_std_id)hdw->std_mask_avail; 2822 v4l2_device_call_all(&hdw->v4l2_dev, 0, 2823 video, querystd, &std); 2824 return std; 2825 } 2826 2827 /* Execute whatever commands are required to update the state of all the 2828 sub-devices so that they match our current control values. */ 2829 static void pvr2_subdev_update(struct pvr2_hdw *hdw) 2830 { 2831 struct v4l2_subdev *sd; 2832 unsigned int id; 2833 pvr2_subdev_update_func fp; 2834 2835 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update..."); 2836 2837 if (hdw->tuner_updated || hdw->force_dirty) { 2838 struct tuner_setup setup; 2839 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)", 2840 hdw->tuner_type); 2841 if (((int)(hdw->tuner_type)) >= 0) { 2842 memset(&setup, 0, sizeof(setup)); 2843 setup.addr = ADDR_UNSET; 2844 setup.type = hdw->tuner_type; 2845 setup.mode_mask = T_RADIO | T_ANALOG_TV; 2846 v4l2_device_call_all(&hdw->v4l2_dev, 0, 2847 tuner, s_type_addr, &setup); 2848 } 2849 } 2850 2851 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) { 2852 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard"); 2853 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { 2854 v4l2_device_call_all(&hdw->v4l2_dev, 0, 2855 tuner, s_radio); 2856 } else { 2857 v4l2_std_id vs; 2858 vs = hdw->std_mask_cur; 2859 v4l2_device_call_all(&hdw->v4l2_dev, 0, 2860 video, s_std, vs); 2861 pvr2_hdw_cx25840_vbi_hack(hdw); 2862 } 2863 hdw->tuner_signal_stale = !0; 2864 hdw->cropcap_stale = !0; 2865 } 2866 2867 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness); 2868 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast); 2869 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation); 2870 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue); 2871 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute); 2872 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume); 2873 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance); 2874 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass); 2875 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble); 2876 2877 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) { 2878 struct v4l2_tuner vt; 2879 memset(&vt, 0, sizeof(vt)); 2880 vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ? 2881 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; 2882 vt.audmode = hdw->audiomode_val; 2883 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt); 2884 } 2885 2886 if (hdw->freqDirty || hdw->force_dirty) { 2887 unsigned long fv; 2888 struct v4l2_frequency freq; 2889 fv = pvr2_hdw_get_cur_freq(hdw); 2890 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv); 2891 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw); 2892 memset(&freq, 0, sizeof(freq)); 2893 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) { 2894 /* ((fv * 1000) / 62500) */ 2895 freq.frequency = (fv * 2) / 125; 2896 } else { 2897 freq.frequency = fv / 62500; 2898 } 2899 /* tuner-core currently doesn't seem to care about this, but 2900 let's set it anyway for completeness. */ 2901 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { 2902 freq.type = V4L2_TUNER_RADIO; 2903 } else { 2904 freq.type = V4L2_TUNER_ANALOG_TV; 2905 } 2906 freq.tuner = 0; 2907 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, 2908 s_frequency, &freq); 2909 } 2910 2911 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) { 2912 struct v4l2_subdev_format format = { 2913 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 2914 }; 2915 2916 format.format.width = hdw->res_hor_val; 2917 format.format.height = hdw->res_ver_val; 2918 format.format.code = MEDIA_BUS_FMT_FIXED; 2919 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)", 2920 format.format.width, format.format.height); 2921 v4l2_device_call_all(&hdw->v4l2_dev, 0, pad, set_fmt, 2922 NULL, &format); 2923 } 2924 2925 if (hdw->srate_dirty || hdw->force_dirty) { 2926 u32 val; 2927 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d", 2928 hdw->srate_val); 2929 switch (hdw->srate_val) { 2930 default: 2931 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000: 2932 val = 48000; 2933 break; 2934 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100: 2935 val = 44100; 2936 break; 2937 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000: 2938 val = 32000; 2939 break; 2940 } 2941 v4l2_device_call_all(&hdw->v4l2_dev, 0, 2942 audio, s_clock_freq, val); 2943 } 2944 2945 /* Unable to set crop parameters; there is apparently no equivalent 2946 for VIDIOC_S_CROP */ 2947 2948 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) { 2949 id = sd->grp_id; 2950 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue; 2951 fp = pvr2_module_update_functions[id]; 2952 if (!fp) continue; 2953 (*fp)(hdw, sd); 2954 } 2955 2956 if (hdw->tuner_signal_stale || hdw->cropcap_stale) { 2957 pvr2_hdw_status_poll(hdw); 2958 } 2959 } 2960 2961 2962 /* Figure out if we need to commit control changes. If so, mark internal 2963 state flags to indicate this fact and return true. Otherwise do nothing 2964 else and return false. */ 2965 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw) 2966 { 2967 unsigned int idx; 2968 struct pvr2_ctrl *cptr; 2969 int value; 2970 int commit_flag = hdw->force_dirty; 2971 char buf[100]; 2972 unsigned int bcnt,ccnt; 2973 2974 for (idx = 0; idx < hdw->control_cnt; idx++) { 2975 cptr = hdw->controls + idx; 2976 if (!cptr->info->is_dirty) continue; 2977 if (!cptr->info->is_dirty(cptr)) continue; 2978 commit_flag = !0; 2979 2980 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue; 2981 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ", 2982 cptr->info->name); 2983 value = 0; 2984 cptr->info->get_value(cptr,&value); 2985 pvr2_ctrl_value_to_sym_internal(cptr,~0,value, 2986 buf+bcnt, 2987 sizeof(buf)-bcnt,&ccnt); 2988 bcnt += ccnt; 2989 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>", 2990 get_ctrl_typename(cptr->info->type)); 2991 pvr2_trace(PVR2_TRACE_CTL, 2992 "/*--TRACE_COMMIT--*/ %.*s", 2993 bcnt,buf); 2994 } 2995 2996 if (!commit_flag) { 2997 /* Nothing has changed */ 2998 return 0; 2999 } 3000 3001 hdw->state_pipeline_config = 0; 3002 trace_stbit("state_pipeline_config",hdw->state_pipeline_config); 3003 pvr2_hdw_state_sched(hdw); 3004 3005 return !0; 3006 } 3007 3008 3009 /* Perform all operations needed to commit all control changes. This must 3010 be performed in synchronization with the pipeline state and is thus 3011 expected to be called as part of the driver's worker thread. Return 3012 true if commit successful, otherwise return false to indicate that 3013 commit isn't possible at this time. */ 3014 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw) 3015 { 3016 unsigned int idx; 3017 struct pvr2_ctrl *cptr; 3018 int disruptive_change; 3019 3020 if (hdw->input_dirty && hdw->state_pathway_ok && 3021 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ? 3022 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) != 3023 hdw->pathway_state)) { 3024 /* Change of mode being asked for... */ 3025 hdw->state_pathway_ok = 0; 3026 trace_stbit("state_pathway_ok", hdw->state_pathway_ok); 3027 } 3028 if (!hdw->state_pathway_ok) { 3029 /* Can't commit anything until pathway is ok. */ 3030 return 0; 3031 } 3032 3033 /* Handle some required side effects when the video standard is 3034 changed.... */ 3035 if (hdw->std_dirty) { 3036 int nvres; 3037 int gop_size; 3038 if (hdw->std_mask_cur & V4L2_STD_525_60) { 3039 nvres = 480; 3040 gop_size = 15; 3041 } else { 3042 nvres = 576; 3043 gop_size = 12; 3044 } 3045 /* Rewrite the vertical resolution to be appropriate to the 3046 video standard that has been selected. */ 3047 if (nvres != hdw->res_ver_val) { 3048 hdw->res_ver_val = nvres; 3049 hdw->res_ver_dirty = !0; 3050 } 3051 /* Rewrite the GOP size to be appropriate to the video 3052 standard that has been selected. */ 3053 if (gop_size != hdw->enc_ctl_state.video_gop_size) { 3054 struct v4l2_ext_controls cs; 3055 struct v4l2_ext_control c1; 3056 memset(&cs, 0, sizeof(cs)); 3057 memset(&c1, 0, sizeof(c1)); 3058 cs.controls = &c1; 3059 cs.count = 1; 3060 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE; 3061 c1.value = gop_size; 3062 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs, 3063 VIDIOC_S_EXT_CTRLS); 3064 } 3065 } 3066 3067 /* The broadcast decoder can only scale down, so if 3068 * res_*_dirty && crop window < output format ==> enlarge crop. 3069 * 3070 * The mpeg encoder receives fields of res_hor_val dots and 3071 * res_ver_val halflines. Limits: hor<=720, ver<=576. 3072 */ 3073 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) { 3074 hdw->cropw_val = hdw->res_hor_val; 3075 hdw->cropw_dirty = !0; 3076 } else if (hdw->cropw_dirty) { 3077 hdw->res_hor_dirty = !0; /* must rescale */ 3078 hdw->res_hor_val = min(720, hdw->cropw_val); 3079 } 3080 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) { 3081 hdw->croph_val = hdw->res_ver_val; 3082 hdw->croph_dirty = !0; 3083 } else if (hdw->croph_dirty) { 3084 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576; 3085 hdw->res_ver_dirty = !0; 3086 hdw->res_ver_val = min(nvres, hdw->croph_val); 3087 } 3088 3089 /* If any of the below has changed, then we can't do the update 3090 while the pipeline is running. Pipeline must be paused first 3091 and decoder -> encoder connection be made quiescent before we 3092 can proceed. */ 3093 disruptive_change = 3094 (hdw->std_dirty || 3095 hdw->enc_unsafe_stale || 3096 hdw->srate_dirty || 3097 hdw->res_ver_dirty || 3098 hdw->res_hor_dirty || 3099 hdw->cropw_dirty || 3100 hdw->croph_dirty || 3101 hdw->input_dirty || 3102 (hdw->active_stream_type != hdw->desired_stream_type)); 3103 if (disruptive_change && !hdw->state_pipeline_idle) { 3104 /* Pipeline is not idle; we can't proceed. Arrange to 3105 cause pipeline to stop so that we can try this again 3106 later.... */ 3107 hdw->state_pipeline_pause = !0; 3108 return 0; 3109 } 3110 3111 if (hdw->srate_dirty) { 3112 /* Write new sample rate into control structure since 3113 * the master copy is stale. We must track srate 3114 * separate from the mpeg control structure because 3115 * other logic also uses this value. */ 3116 struct v4l2_ext_controls cs; 3117 struct v4l2_ext_control c1; 3118 memset(&cs,0,sizeof(cs)); 3119 memset(&c1,0,sizeof(c1)); 3120 cs.controls = &c1; 3121 cs.count = 1; 3122 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ; 3123 c1.value = hdw->srate_val; 3124 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS); 3125 } 3126 3127 if (hdw->active_stream_type != hdw->desired_stream_type) { 3128 /* Handle any side effects of stream config here */ 3129 hdw->active_stream_type = hdw->desired_stream_type; 3130 } 3131 3132 if (hdw->hdw_desc->signal_routing_scheme == 3133 PVR2_ROUTING_SCHEME_GOTVIEW) { 3134 u32 b; 3135 /* Handle GOTVIEW audio switching */ 3136 pvr2_hdw_gpio_get_out(hdw,&b); 3137 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { 3138 /* Set GPIO 11 */ 3139 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0); 3140 } else { 3141 /* Clear GPIO 11 */ 3142 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0); 3143 } 3144 } 3145 3146 /* Check and update state for all sub-devices. */ 3147 pvr2_subdev_update(hdw); 3148 3149 hdw->tuner_updated = 0; 3150 hdw->force_dirty = 0; 3151 for (idx = 0; idx < hdw->control_cnt; idx++) { 3152 cptr = hdw->controls + idx; 3153 if (!cptr->info->clear_dirty) continue; 3154 cptr->info->clear_dirty(cptr); 3155 } 3156 3157 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) && 3158 hdw->state_encoder_run) { 3159 /* If encoder isn't running or it can't be touched, then 3160 this will get worked out later when we start the 3161 encoder. */ 3162 if (pvr2_encoder_adjust(hdw) < 0) return !0; 3163 } 3164 3165 hdw->state_pipeline_config = !0; 3166 /* Hardware state may have changed in a way to cause the cropping 3167 capabilities to have changed. So mark it stale, which will 3168 cause a later re-fetch. */ 3169 trace_stbit("state_pipeline_config",hdw->state_pipeline_config); 3170 return !0; 3171 } 3172 3173 3174 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw) 3175 { 3176 int fl; 3177 LOCK_TAKE(hdw->big_lock); 3178 fl = pvr2_hdw_commit_setup(hdw); 3179 LOCK_GIVE(hdw->big_lock); 3180 if (!fl) return 0; 3181 return pvr2_hdw_wait(hdw,0); 3182 } 3183 3184 3185 static void pvr2_hdw_worker_poll(struct work_struct *work) 3186 { 3187 int fl = 0; 3188 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll); 3189 LOCK_TAKE(hdw->big_lock); do { 3190 fl = pvr2_hdw_state_eval(hdw); 3191 } while (0); LOCK_GIVE(hdw->big_lock); 3192 if (fl && hdw->state_func) { 3193 hdw->state_func(hdw->state_data); 3194 } 3195 } 3196 3197 3198 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state) 3199 { 3200 return wait_event_interruptible( 3201 hdw->state_wait_data, 3202 (hdw->state_stale == 0) && 3203 (!state || (hdw->master_state != state))); 3204 } 3205 3206 3207 /* Return name for this driver instance */ 3208 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw) 3209 { 3210 return hdw->name; 3211 } 3212 3213 3214 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw) 3215 { 3216 return hdw->hdw_desc->description; 3217 } 3218 3219 3220 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw) 3221 { 3222 return hdw->hdw_desc->shortname; 3223 } 3224 3225 3226 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw) 3227 { 3228 int result; 3229 LOCK_TAKE(hdw->ctl_lock); do { 3230 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED; 3231 result = pvr2_send_request(hdw, 3232 hdw->cmd_buffer,1, 3233 hdw->cmd_buffer,1); 3234 if (result < 0) break; 3235 result = (hdw->cmd_buffer[0] != 0); 3236 } while(0); LOCK_GIVE(hdw->ctl_lock); 3237 return result; 3238 } 3239 3240 3241 /* Execute poll of tuner status */ 3242 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw) 3243 { 3244 LOCK_TAKE(hdw->big_lock); do { 3245 pvr2_hdw_status_poll(hdw); 3246 } while (0); LOCK_GIVE(hdw->big_lock); 3247 } 3248 3249 3250 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw) 3251 { 3252 if (!hdw->cropcap_stale) { 3253 return 0; 3254 } 3255 pvr2_hdw_status_poll(hdw); 3256 if (hdw->cropcap_stale) { 3257 return -EIO; 3258 } 3259 return 0; 3260 } 3261 3262 3263 /* Return information about cropping capabilities */ 3264 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp) 3265 { 3266 int stat = 0; 3267 LOCK_TAKE(hdw->big_lock); 3268 stat = pvr2_hdw_check_cropcap(hdw); 3269 if (!stat) { 3270 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info)); 3271 } 3272 LOCK_GIVE(hdw->big_lock); 3273 return stat; 3274 } 3275 3276 3277 /* Return information about the tuner */ 3278 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp) 3279 { 3280 LOCK_TAKE(hdw->big_lock); do { 3281 if (hdw->tuner_signal_stale) { 3282 pvr2_hdw_status_poll(hdw); 3283 } 3284 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner)); 3285 } while (0); LOCK_GIVE(hdw->big_lock); 3286 return 0; 3287 } 3288 3289 3290 /* Get handle to video output stream */ 3291 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp) 3292 { 3293 return hp->vid_stream; 3294 } 3295 3296 3297 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw) 3298 { 3299 int nr = pvr2_hdw_get_unit_number(hdw); 3300 LOCK_TAKE(hdw->big_lock); 3301 do { 3302 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr); 3303 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status); 3304 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:"); 3305 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2"); 3306 pvr2_hdw_state_log_state(hdw); 3307 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr); 3308 } while (0); 3309 LOCK_GIVE(hdw->big_lock); 3310 } 3311 3312 3313 /* Grab EEPROM contents, needed for direct method. */ 3314 #define EEPROM_SIZE 8192 3315 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__) 3316 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw) 3317 { 3318 struct i2c_msg msg[2]; 3319 u8 *eeprom; 3320 u8 iadd[2]; 3321 u8 addr; 3322 u16 eepromSize; 3323 unsigned int offs; 3324 int ret; 3325 int mode16 = 0; 3326 unsigned pcnt,tcnt; 3327 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL); 3328 if (!eeprom) { 3329 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3330 "Failed to allocate memory required to read eeprom"); 3331 return NULL; 3332 } 3333 3334 trace_eeprom("Value for eeprom addr from controller was 0x%x", 3335 hdw->eeprom_addr); 3336 addr = hdw->eeprom_addr; 3337 /* Seems that if the high bit is set, then the *real* eeprom 3338 address is shifted right now bit position (noticed this in 3339 newer PVR USB2 hardware) */ 3340 if (addr & 0x80) addr >>= 1; 3341 3342 /* FX2 documentation states that a 16bit-addressed eeprom is 3343 expected if the I2C address is an odd number (yeah, this is 3344 strange but it's what they do) */ 3345 mode16 = (addr & 1); 3346 eepromSize = (mode16 ? EEPROM_SIZE : 256); 3347 trace_eeprom("Examining %d byte eeprom at location 0x%x using %d bit addressing", 3348 eepromSize, addr, 3349 mode16 ? 16 : 8); 3350 3351 msg[0].addr = addr; 3352 msg[0].flags = 0; 3353 msg[0].len = mode16 ? 2 : 1; 3354 msg[0].buf = iadd; 3355 msg[1].addr = addr; 3356 msg[1].flags = I2C_M_RD; 3357 3358 /* We have to do the actual eeprom data fetch ourselves, because 3359 (1) we're only fetching part of the eeprom, and (2) if we were 3360 getting the whole thing our I2C driver can't grab it in one 3361 pass - which is what tveeprom is otherwise going to attempt */ 3362 memset(eeprom,0,EEPROM_SIZE); 3363 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) { 3364 pcnt = 16; 3365 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt; 3366 offs = tcnt + (eepromSize - EEPROM_SIZE); 3367 if (mode16) { 3368 iadd[0] = offs >> 8; 3369 iadd[1] = offs; 3370 } else { 3371 iadd[0] = offs; 3372 } 3373 msg[1].len = pcnt; 3374 msg[1].buf = eeprom+tcnt; 3375 if ((ret = i2c_transfer(&hdw->i2c_adap, 3376 msg,ARRAY_SIZE(msg))) != 2) { 3377 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3378 "eeprom fetch set offs err=%d",ret); 3379 kfree(eeprom); 3380 return NULL; 3381 } 3382 } 3383 return eeprom; 3384 } 3385 3386 3387 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, 3388 int mode, 3389 int enable_flag) 3390 { 3391 int ret; 3392 u16 address; 3393 unsigned int pipe; 3394 LOCK_TAKE(hdw->big_lock); do { 3395 if ((hdw->fw_buffer == NULL) == !enable_flag) break; 3396 3397 if (!enable_flag) { 3398 pvr2_trace(PVR2_TRACE_FIRMWARE, 3399 "Cleaning up after CPU firmware fetch"); 3400 kfree(hdw->fw_buffer); 3401 hdw->fw_buffer = NULL; 3402 hdw->fw_size = 0; 3403 if (hdw->fw_cpu_flag) { 3404 /* Now release the CPU. It will disconnect 3405 and reconnect later. */ 3406 pvr2_hdw_cpureset_assert(hdw,0); 3407 } 3408 break; 3409 } 3410 3411 hdw->fw_cpu_flag = (mode != 2); 3412 if (hdw->fw_cpu_flag) { 3413 hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000; 3414 pvr2_trace(PVR2_TRACE_FIRMWARE, 3415 "Preparing to suck out CPU firmware (size=%u)", 3416 hdw->fw_size); 3417 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL); 3418 if (!hdw->fw_buffer) { 3419 hdw->fw_size = 0; 3420 break; 3421 } 3422 3423 /* We have to hold the CPU during firmware upload. */ 3424 pvr2_hdw_cpureset_assert(hdw,1); 3425 3426 /* download the firmware from address 0000-1fff in 2048 3427 (=0x800) bytes chunk. */ 3428 3429 pvr2_trace(PVR2_TRACE_FIRMWARE, 3430 "Grabbing CPU firmware"); 3431 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0); 3432 for(address = 0; address < hdw->fw_size; 3433 address += 0x800) { 3434 ret = usb_control_msg(hdw->usb_dev,pipe, 3435 0xa0,0xc0, 3436 address,0, 3437 hdw->fw_buffer+address, 3438 0x800,HZ); 3439 if (ret < 0) break; 3440 } 3441 3442 pvr2_trace(PVR2_TRACE_FIRMWARE, 3443 "Done grabbing CPU firmware"); 3444 } else { 3445 pvr2_trace(PVR2_TRACE_FIRMWARE, 3446 "Sucking down EEPROM contents"); 3447 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw); 3448 if (!hdw->fw_buffer) { 3449 pvr2_trace(PVR2_TRACE_FIRMWARE, 3450 "EEPROM content suck failed."); 3451 break; 3452 } 3453 hdw->fw_size = EEPROM_SIZE; 3454 pvr2_trace(PVR2_TRACE_FIRMWARE, 3455 "Done sucking down EEPROM contents"); 3456 } 3457 3458 } while (0); LOCK_GIVE(hdw->big_lock); 3459 } 3460 3461 3462 /* Return true if we're in a mode for retrieval CPU firmware */ 3463 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw) 3464 { 3465 return hdw->fw_buffer != NULL; 3466 } 3467 3468 3469 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs, 3470 char *buf,unsigned int cnt) 3471 { 3472 int ret = -EINVAL; 3473 LOCK_TAKE(hdw->big_lock); do { 3474 if (!buf) break; 3475 if (!cnt) break; 3476 3477 if (!hdw->fw_buffer) { 3478 ret = -EIO; 3479 break; 3480 } 3481 3482 if (offs >= hdw->fw_size) { 3483 pvr2_trace(PVR2_TRACE_FIRMWARE, 3484 "Read firmware data offs=%d EOF", 3485 offs); 3486 ret = 0; 3487 break; 3488 } 3489 3490 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs; 3491 3492 memcpy(buf,hdw->fw_buffer+offs,cnt); 3493 3494 pvr2_trace(PVR2_TRACE_FIRMWARE, 3495 "Read firmware data offs=%d cnt=%d", 3496 offs,cnt); 3497 ret = cnt; 3498 } while (0); LOCK_GIVE(hdw->big_lock); 3499 3500 return ret; 3501 } 3502 3503 3504 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw, 3505 enum pvr2_v4l_type index) 3506 { 3507 switch (index) { 3508 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video; 3509 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi; 3510 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio; 3511 default: return -1; 3512 } 3513 } 3514 3515 3516 /* Store a v4l minor device number */ 3517 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw, 3518 enum pvr2_v4l_type index,int v) 3519 { 3520 switch (index) { 3521 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;break; 3522 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;break; 3523 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;break; 3524 default: break; 3525 } 3526 } 3527 3528 3529 static void pvr2_ctl_write_complete(struct urb *urb) 3530 { 3531 struct pvr2_hdw *hdw = urb->context; 3532 hdw->ctl_write_pend_flag = 0; 3533 if (hdw->ctl_read_pend_flag) return; 3534 complete(&hdw->ctl_done); 3535 } 3536 3537 3538 static void pvr2_ctl_read_complete(struct urb *urb) 3539 { 3540 struct pvr2_hdw *hdw = urb->context; 3541 hdw->ctl_read_pend_flag = 0; 3542 if (hdw->ctl_write_pend_flag) return; 3543 complete(&hdw->ctl_done); 3544 } 3545 3546 3547 static void pvr2_ctl_timeout(unsigned long data) 3548 { 3549 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data; 3550 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) { 3551 hdw->ctl_timeout_flag = !0; 3552 if (hdw->ctl_write_pend_flag) 3553 usb_unlink_urb(hdw->ctl_write_urb); 3554 if (hdw->ctl_read_pend_flag) 3555 usb_unlink_urb(hdw->ctl_read_urb); 3556 } 3557 } 3558 3559 3560 /* Issue a command and get a response from the device. This extended 3561 version includes a probe flag (which if set means that device errors 3562 should not be logged or treated as fatal) and a timeout in jiffies. 3563 This can be used to non-lethally probe the health of endpoint 1. */ 3564 static int pvr2_send_request_ex(struct pvr2_hdw *hdw, 3565 unsigned int timeout,int probe_fl, 3566 void *write_data,unsigned int write_len, 3567 void *read_data,unsigned int read_len) 3568 { 3569 unsigned int idx; 3570 int status = 0; 3571 struct timer_list timer; 3572 if (!hdw->ctl_lock_held) { 3573 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3574 "Attempted to execute control transfer without lock!!"); 3575 return -EDEADLK; 3576 } 3577 if (!hdw->flag_ok && !probe_fl) { 3578 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3579 "Attempted to execute control transfer when device not ok"); 3580 return -EIO; 3581 } 3582 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) { 3583 if (!probe_fl) { 3584 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3585 "Attempted to execute control transfer when USB is disconnected"); 3586 } 3587 return -ENOTTY; 3588 } 3589 3590 /* Ensure that we have sane parameters */ 3591 if (!write_data) write_len = 0; 3592 if (!read_data) read_len = 0; 3593 if (write_len > PVR2_CTL_BUFFSIZE) { 3594 pvr2_trace( 3595 PVR2_TRACE_ERROR_LEGS, 3596 "Attempted to execute %d byte control-write transfer (limit=%d)", 3597 write_len,PVR2_CTL_BUFFSIZE); 3598 return -EINVAL; 3599 } 3600 if (read_len > PVR2_CTL_BUFFSIZE) { 3601 pvr2_trace( 3602 PVR2_TRACE_ERROR_LEGS, 3603 "Attempted to execute %d byte control-read transfer (limit=%d)", 3604 write_len,PVR2_CTL_BUFFSIZE); 3605 return -EINVAL; 3606 } 3607 if ((!write_len) && (!read_len)) { 3608 pvr2_trace( 3609 PVR2_TRACE_ERROR_LEGS, 3610 "Attempted to execute null control transfer?"); 3611 return -EINVAL; 3612 } 3613 3614 3615 hdw->cmd_debug_state = 1; 3616 if (write_len && write_data) 3617 hdw->cmd_debug_code = ((unsigned char *)write_data)[0]; 3618 else 3619 hdw->cmd_debug_code = 0; 3620 hdw->cmd_debug_write_len = write_len; 3621 hdw->cmd_debug_read_len = read_len; 3622 3623 /* Initialize common stuff */ 3624 init_completion(&hdw->ctl_done); 3625 hdw->ctl_timeout_flag = 0; 3626 hdw->ctl_write_pend_flag = 0; 3627 hdw->ctl_read_pend_flag = 0; 3628 setup_timer(&timer, pvr2_ctl_timeout, (unsigned long)hdw); 3629 timer.expires = jiffies + timeout; 3630 3631 if (write_len && write_data) { 3632 hdw->cmd_debug_state = 2; 3633 /* Transfer write data to internal buffer */ 3634 for (idx = 0; idx < write_len; idx++) { 3635 hdw->ctl_write_buffer[idx] = 3636 ((unsigned char *)write_data)[idx]; 3637 } 3638 /* Initiate a write request */ 3639 usb_fill_bulk_urb(hdw->ctl_write_urb, 3640 hdw->usb_dev, 3641 usb_sndbulkpipe(hdw->usb_dev, 3642 PVR2_CTL_WRITE_ENDPOINT), 3643 hdw->ctl_write_buffer, 3644 write_len, 3645 pvr2_ctl_write_complete, 3646 hdw); 3647 hdw->ctl_write_urb->actual_length = 0; 3648 hdw->ctl_write_pend_flag = !0; 3649 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL); 3650 if (status < 0) { 3651 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3652 "Failed to submit write-control URB status=%d", 3653 status); 3654 hdw->ctl_write_pend_flag = 0; 3655 goto done; 3656 } 3657 } 3658 3659 if (read_len) { 3660 hdw->cmd_debug_state = 3; 3661 memset(hdw->ctl_read_buffer,0x43,read_len); 3662 /* Initiate a read request */ 3663 usb_fill_bulk_urb(hdw->ctl_read_urb, 3664 hdw->usb_dev, 3665 usb_rcvbulkpipe(hdw->usb_dev, 3666 PVR2_CTL_READ_ENDPOINT), 3667 hdw->ctl_read_buffer, 3668 read_len, 3669 pvr2_ctl_read_complete, 3670 hdw); 3671 hdw->ctl_read_urb->actual_length = 0; 3672 hdw->ctl_read_pend_flag = !0; 3673 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL); 3674 if (status < 0) { 3675 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3676 "Failed to submit read-control URB status=%d", 3677 status); 3678 hdw->ctl_read_pend_flag = 0; 3679 goto done; 3680 } 3681 } 3682 3683 /* Start timer */ 3684 add_timer(&timer); 3685 3686 /* Now wait for all I/O to complete */ 3687 hdw->cmd_debug_state = 4; 3688 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) { 3689 wait_for_completion(&hdw->ctl_done); 3690 } 3691 hdw->cmd_debug_state = 5; 3692 3693 /* Stop timer */ 3694 del_timer_sync(&timer); 3695 3696 hdw->cmd_debug_state = 6; 3697 status = 0; 3698 3699 if (hdw->ctl_timeout_flag) { 3700 status = -ETIMEDOUT; 3701 if (!probe_fl) { 3702 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3703 "Timed out control-write"); 3704 } 3705 goto done; 3706 } 3707 3708 if (write_len) { 3709 /* Validate results of write request */ 3710 if ((hdw->ctl_write_urb->status != 0) && 3711 (hdw->ctl_write_urb->status != -ENOENT) && 3712 (hdw->ctl_write_urb->status != -ESHUTDOWN) && 3713 (hdw->ctl_write_urb->status != -ECONNRESET)) { 3714 /* USB subsystem is reporting some kind of failure 3715 on the write */ 3716 status = hdw->ctl_write_urb->status; 3717 if (!probe_fl) { 3718 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3719 "control-write URB failure, status=%d", 3720 status); 3721 } 3722 goto done; 3723 } 3724 if (hdw->ctl_write_urb->actual_length < write_len) { 3725 /* Failed to write enough data */ 3726 status = -EIO; 3727 if (!probe_fl) { 3728 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3729 "control-write URB short, expected=%d got=%d", 3730 write_len, 3731 hdw->ctl_write_urb->actual_length); 3732 } 3733 goto done; 3734 } 3735 } 3736 if (read_len && read_data) { 3737 /* Validate results of read request */ 3738 if ((hdw->ctl_read_urb->status != 0) && 3739 (hdw->ctl_read_urb->status != -ENOENT) && 3740 (hdw->ctl_read_urb->status != -ESHUTDOWN) && 3741 (hdw->ctl_read_urb->status != -ECONNRESET)) { 3742 /* USB subsystem is reporting some kind of failure 3743 on the read */ 3744 status = hdw->ctl_read_urb->status; 3745 if (!probe_fl) { 3746 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3747 "control-read URB failure, status=%d", 3748 status); 3749 } 3750 goto done; 3751 } 3752 if (hdw->ctl_read_urb->actual_length < read_len) { 3753 /* Failed to read enough data */ 3754 status = -EIO; 3755 if (!probe_fl) { 3756 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3757 "control-read URB short, expected=%d got=%d", 3758 read_len, 3759 hdw->ctl_read_urb->actual_length); 3760 } 3761 goto done; 3762 } 3763 /* Transfer retrieved data out from internal buffer */ 3764 for (idx = 0; idx < read_len; idx++) { 3765 ((unsigned char *)read_data)[idx] = 3766 hdw->ctl_read_buffer[idx]; 3767 } 3768 } 3769 3770 done: 3771 3772 hdw->cmd_debug_state = 0; 3773 if ((status < 0) && (!probe_fl)) { 3774 pvr2_hdw_render_useless(hdw); 3775 } 3776 return status; 3777 } 3778 3779 3780 int pvr2_send_request(struct pvr2_hdw *hdw, 3781 void *write_data,unsigned int write_len, 3782 void *read_data,unsigned int read_len) 3783 { 3784 return pvr2_send_request_ex(hdw,HZ*4,0, 3785 write_data,write_len, 3786 read_data,read_len); 3787 } 3788 3789 3790 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode) 3791 { 3792 int ret; 3793 unsigned int cnt = 1; 3794 unsigned int args = 0; 3795 LOCK_TAKE(hdw->ctl_lock); 3796 hdw->cmd_buffer[0] = cmdcode & 0xffu; 3797 args = (cmdcode >> 8) & 0xffu; 3798 args = (args > 2) ? 2 : args; 3799 if (args) { 3800 cnt += args; 3801 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu; 3802 if (args > 1) { 3803 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu; 3804 } 3805 } 3806 if (pvrusb2_debug & PVR2_TRACE_INIT) { 3807 unsigned int idx; 3808 unsigned int ccnt,bcnt; 3809 char tbuf[50]; 3810 cmdcode &= 0xffu; 3811 bcnt = 0; 3812 ccnt = scnprintf(tbuf+bcnt, 3813 sizeof(tbuf)-bcnt, 3814 "Sending FX2 command 0x%x",cmdcode); 3815 bcnt += ccnt; 3816 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) { 3817 if (pvr2_fx2cmd_desc[idx].id == cmdcode) { 3818 ccnt = scnprintf(tbuf+bcnt, 3819 sizeof(tbuf)-bcnt, 3820 " \"%s\"", 3821 pvr2_fx2cmd_desc[idx].desc); 3822 bcnt += ccnt; 3823 break; 3824 } 3825 } 3826 if (args) { 3827 ccnt = scnprintf(tbuf+bcnt, 3828 sizeof(tbuf)-bcnt, 3829 " (%u",hdw->cmd_buffer[1]); 3830 bcnt += ccnt; 3831 if (args > 1) { 3832 ccnt = scnprintf(tbuf+bcnt, 3833 sizeof(tbuf)-bcnt, 3834 ",%u",hdw->cmd_buffer[2]); 3835 bcnt += ccnt; 3836 } 3837 ccnt = scnprintf(tbuf+bcnt, 3838 sizeof(tbuf)-bcnt, 3839 ")"); 3840 bcnt += ccnt; 3841 } 3842 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf); 3843 } 3844 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0); 3845 LOCK_GIVE(hdw->ctl_lock); 3846 return ret; 3847 } 3848 3849 3850 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data) 3851 { 3852 int ret; 3853 3854 LOCK_TAKE(hdw->ctl_lock); 3855 3856 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */ 3857 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data); 3858 hdw->cmd_buffer[5] = 0; 3859 hdw->cmd_buffer[6] = (reg >> 8) & 0xff; 3860 hdw->cmd_buffer[7] = reg & 0xff; 3861 3862 3863 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0); 3864 3865 LOCK_GIVE(hdw->ctl_lock); 3866 3867 return ret; 3868 } 3869 3870 3871 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data) 3872 { 3873 int ret = 0; 3874 3875 LOCK_TAKE(hdw->ctl_lock); 3876 3877 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */ 3878 hdw->cmd_buffer[1] = 0; 3879 hdw->cmd_buffer[2] = 0; 3880 hdw->cmd_buffer[3] = 0; 3881 hdw->cmd_buffer[4] = 0; 3882 hdw->cmd_buffer[5] = 0; 3883 hdw->cmd_buffer[6] = (reg >> 8) & 0xff; 3884 hdw->cmd_buffer[7] = reg & 0xff; 3885 3886 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4); 3887 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0); 3888 3889 LOCK_GIVE(hdw->ctl_lock); 3890 3891 return ret; 3892 } 3893 3894 3895 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw) 3896 { 3897 if (!hdw->flag_ok) return; 3898 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3899 "Device being rendered inoperable"); 3900 if (hdw->vid_stream) { 3901 pvr2_stream_setup(hdw->vid_stream,NULL,0,0); 3902 } 3903 hdw->flag_ok = 0; 3904 trace_stbit("flag_ok",hdw->flag_ok); 3905 pvr2_hdw_state_sched(hdw); 3906 } 3907 3908 3909 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw) 3910 { 3911 int ret; 3912 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset..."); 3913 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL); 3914 if (ret == 0) { 3915 ret = usb_reset_device(hdw->usb_dev); 3916 usb_unlock_device(hdw->usb_dev); 3917 } else { 3918 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3919 "Failed to lock USB device ret=%d",ret); 3920 } 3921 if (init_pause_msec) { 3922 pvr2_trace(PVR2_TRACE_INFO, 3923 "Waiting %u msec for hardware to settle", 3924 init_pause_msec); 3925 msleep(init_pause_msec); 3926 } 3927 3928 } 3929 3930 3931 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val) 3932 { 3933 char *da; 3934 unsigned int pipe; 3935 int ret; 3936 3937 if (!hdw->usb_dev) return; 3938 3939 da = kmalloc(16, GFP_KERNEL); 3940 3941 if (da == NULL) { 3942 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3943 "Unable to allocate memory to control CPU reset"); 3944 return; 3945 } 3946 3947 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val); 3948 3949 da[0] = val ? 0x01 : 0x00; 3950 3951 /* Write the CPUCS register on the 8051. The lsb of the register 3952 is the reset bit; a 1 asserts reset while a 0 clears it. */ 3953 pipe = usb_sndctrlpipe(hdw->usb_dev, 0); 3954 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ); 3955 if (ret < 0) { 3956 pvr2_trace(PVR2_TRACE_ERROR_LEGS, 3957 "cpureset_assert(%d) error=%d",val,ret); 3958 pvr2_hdw_render_useless(hdw); 3959 } 3960 3961 kfree(da); 3962 } 3963 3964 3965 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw) 3966 { 3967 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET); 3968 } 3969 3970 3971 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw) 3972 { 3973 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON); 3974 } 3975 3976 3977 3978 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw) 3979 { 3980 pvr2_trace(PVR2_TRACE_INIT, 3981 "Requesting decoder reset"); 3982 if (hdw->decoder_client_id) { 3983 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id, 3984 core, reset, 0); 3985 pvr2_hdw_cx25840_vbi_hack(hdw); 3986 return 0; 3987 } 3988 pvr2_trace(PVR2_TRACE_INIT, 3989 "Unable to reset decoder: nothing attached"); 3990 return -ENOTTY; 3991 } 3992 3993 3994 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff) 3995 { 3996 hdw->flag_ok = !0; 3997 return pvr2_issue_simple_cmd(hdw, 3998 FX2CMD_HCW_DEMOD_RESETIN | 3999 (1 << 8) | 4000 ((onoff ? 1 : 0) << 16)); 4001 } 4002 4003 4004 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff) 4005 { 4006 hdw->flag_ok = !0; 4007 return pvr2_issue_simple_cmd(hdw,(onoff ? 4008 FX2CMD_ONAIR_DTV_POWER_ON : 4009 FX2CMD_ONAIR_DTV_POWER_OFF)); 4010 } 4011 4012 4013 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw, 4014 int onoff) 4015 { 4016 return pvr2_issue_simple_cmd(hdw,(onoff ? 4017 FX2CMD_ONAIR_DTV_STREAMING_ON : 4018 FX2CMD_ONAIR_DTV_STREAMING_OFF)); 4019 } 4020 4021 4022 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl) 4023 { 4024 int cmode; 4025 /* Compare digital/analog desired setting with current setting. If 4026 they don't match, fix it... */ 4027 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG); 4028 if (cmode == hdw->pathway_state) { 4029 /* They match; nothing to do */ 4030 return; 4031 } 4032 4033 switch (hdw->hdw_desc->digital_control_scheme) { 4034 case PVR2_DIGITAL_SCHEME_HAUPPAUGE: 4035 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl); 4036 if (cmode == PVR2_PATHWAY_ANALOG) { 4037 /* If moving to analog mode, also force the decoder 4038 to reset. If no decoder is attached, then it's 4039 ok to ignore this because if/when the decoder 4040 attaches, it will reset itself at that time. */ 4041 pvr2_hdw_cmd_decoder_reset(hdw); 4042 } 4043 break; 4044 case PVR2_DIGITAL_SCHEME_ONAIR: 4045 /* Supposedly we should always have the power on whether in 4046 digital or analog mode. But for now do what appears to 4047 work... */ 4048 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl); 4049 break; 4050 default: break; 4051 } 4052 4053 pvr2_hdw_untrip_unlocked(hdw); 4054 hdw->pathway_state = cmode; 4055 } 4056 4057 4058 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff) 4059 { 4060 /* change some GPIO data 4061 * 4062 * note: bit d7 of dir appears to control the LED, 4063 * so we shut it off here. 4064 * 4065 */ 4066 if (onoff) { 4067 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481); 4068 } else { 4069 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401); 4070 } 4071 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000); 4072 } 4073 4074 4075 typedef void (*led_method_func)(struct pvr2_hdw *,int); 4076 4077 static led_method_func led_methods[] = { 4078 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge, 4079 }; 4080 4081 4082 /* Toggle LED */ 4083 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff) 4084 { 4085 unsigned int scheme_id; 4086 led_method_func fp; 4087 4088 if ((!onoff) == (!hdw->led_on)) return; 4089 4090 hdw->led_on = onoff != 0; 4091 4092 scheme_id = hdw->hdw_desc->led_scheme; 4093 if (scheme_id < ARRAY_SIZE(led_methods)) { 4094 fp = led_methods[scheme_id]; 4095 } else { 4096 fp = NULL; 4097 } 4098 4099 if (fp) (*fp)(hdw,onoff); 4100 } 4101 4102 4103 /* Stop / start video stream transport */ 4104 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl) 4105 { 4106 int ret; 4107 4108 /* If we're in analog mode, then just issue the usual analog 4109 command. */ 4110 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) { 4111 return pvr2_issue_simple_cmd(hdw, 4112 (runFl ? 4113 FX2CMD_STREAMING_ON : 4114 FX2CMD_STREAMING_OFF)); 4115 /*Note: Not reached */ 4116 } 4117 4118 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) { 4119 /* Whoops, we don't know what mode we're in... */ 4120 return -EINVAL; 4121 } 4122 4123 /* To get here we have to be in digital mode. The mechanism here 4124 is unfortunately different for different vendors. So we switch 4125 on the device's digital scheme attribute in order to figure out 4126 what to do. */ 4127 switch (hdw->hdw_desc->digital_control_scheme) { 4128 case PVR2_DIGITAL_SCHEME_HAUPPAUGE: 4129 return pvr2_issue_simple_cmd(hdw, 4130 (runFl ? 4131 FX2CMD_HCW_DTV_STREAMING_ON : 4132 FX2CMD_HCW_DTV_STREAMING_OFF)); 4133 case PVR2_DIGITAL_SCHEME_ONAIR: 4134 ret = pvr2_issue_simple_cmd(hdw, 4135 (runFl ? 4136 FX2CMD_STREAMING_ON : 4137 FX2CMD_STREAMING_OFF)); 4138 if (ret) return ret; 4139 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl); 4140 default: 4141 return -EINVAL; 4142 } 4143 } 4144 4145 4146 /* Evaluate whether or not state_pathway_ok can change */ 4147 static int state_eval_pathway_ok(struct pvr2_hdw *hdw) 4148 { 4149 if (hdw->state_pathway_ok) { 4150 /* Nothing to do if pathway is already ok */ 4151 return 0; 4152 } 4153 if (!hdw->state_pipeline_idle) { 4154 /* Not allowed to change anything if pipeline is not idle */ 4155 return 0; 4156 } 4157 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV); 4158 hdw->state_pathway_ok = !0; 4159 trace_stbit("state_pathway_ok",hdw->state_pathway_ok); 4160 return !0; 4161 } 4162 4163 4164 /* Evaluate whether or not state_encoder_ok can change */ 4165 static int state_eval_encoder_ok(struct pvr2_hdw *hdw) 4166 { 4167 if (hdw->state_encoder_ok) return 0; 4168 if (hdw->flag_tripped) return 0; 4169 if (hdw->state_encoder_run) return 0; 4170 if (hdw->state_encoder_config) return 0; 4171 if (hdw->state_decoder_run) return 0; 4172 if (hdw->state_usbstream_run) return 0; 4173 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) { 4174 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0; 4175 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) { 4176 return 0; 4177 } 4178 4179 if (pvr2_upload_firmware2(hdw) < 0) { 4180 hdw->flag_tripped = !0; 4181 trace_stbit("flag_tripped",hdw->flag_tripped); 4182 return !0; 4183 } 4184 hdw->state_encoder_ok = !0; 4185 trace_stbit("state_encoder_ok",hdw->state_encoder_ok); 4186 return !0; 4187 } 4188 4189 4190 /* Evaluate whether or not state_encoder_config can change */ 4191 static int state_eval_encoder_config(struct pvr2_hdw *hdw) 4192 { 4193 if (hdw->state_encoder_config) { 4194 if (hdw->state_encoder_ok) { 4195 if (hdw->state_pipeline_req && 4196 !hdw->state_pipeline_pause) return 0; 4197 } 4198 hdw->state_encoder_config = 0; 4199 hdw->state_encoder_waitok = 0; 4200 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok); 4201 /* paranoia - solve race if timer just completed */ 4202 del_timer_sync(&hdw->encoder_wait_timer); 4203 } else { 4204 if (!hdw->state_pathway_ok || 4205 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) || 4206 !hdw->state_encoder_ok || 4207 !hdw->state_pipeline_idle || 4208 hdw->state_pipeline_pause || 4209 !hdw->state_pipeline_req || 4210 !hdw->state_pipeline_config) { 4211 /* We must reset the enforced wait interval if 4212 anything has happened that might have disturbed 4213 the encoder. This should be a rare case. */ 4214 if (timer_pending(&hdw->encoder_wait_timer)) { 4215 del_timer_sync(&hdw->encoder_wait_timer); 4216 } 4217 if (hdw->state_encoder_waitok) { 4218 /* Must clear the state - therefore we did 4219 something to a state bit and must also 4220 return true. */ 4221 hdw->state_encoder_waitok = 0; 4222 trace_stbit("state_encoder_waitok", 4223 hdw->state_encoder_waitok); 4224 return !0; 4225 } 4226 return 0; 4227 } 4228 if (!hdw->state_encoder_waitok) { 4229 if (!timer_pending(&hdw->encoder_wait_timer)) { 4230 /* waitok flag wasn't set and timer isn't 4231 running. Check flag once more to avoid 4232 a race then start the timer. This is 4233 the point when we measure out a minimal 4234 quiet interval before doing something to 4235 the encoder. */ 4236 if (!hdw->state_encoder_waitok) { 4237 hdw->encoder_wait_timer.expires = 4238 jiffies + msecs_to_jiffies( 4239 TIME_MSEC_ENCODER_WAIT); 4240 add_timer(&hdw->encoder_wait_timer); 4241 } 4242 } 4243 /* We can't continue until we know we have been 4244 quiet for the interval measured by this 4245 timer. */ 4246 return 0; 4247 } 4248 pvr2_encoder_configure(hdw); 4249 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0; 4250 } 4251 trace_stbit("state_encoder_config",hdw->state_encoder_config); 4252 return !0; 4253 } 4254 4255 4256 /* Return true if the encoder should not be running. */ 4257 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw) 4258 { 4259 if (!hdw->state_encoder_ok) { 4260 /* Encoder isn't healthy at the moment, so stop it. */ 4261 return !0; 4262 } 4263 if (!hdw->state_pathway_ok) { 4264 /* Mode is not understood at the moment (i.e. it wants to 4265 change), so encoder must be stopped. */ 4266 return !0; 4267 } 4268 4269 switch (hdw->pathway_state) { 4270 case PVR2_PATHWAY_ANALOG: 4271 if (!hdw->state_decoder_run) { 4272 /* We're in analog mode and the decoder is not 4273 running; thus the encoder should be stopped as 4274 well. */ 4275 return !0; 4276 } 4277 break; 4278 case PVR2_PATHWAY_DIGITAL: 4279 if (hdw->state_encoder_runok) { 4280 /* This is a funny case. We're in digital mode so 4281 really the encoder should be stopped. However 4282 if it really is running, only kill it after 4283 runok has been set. This gives a chance for the 4284 onair quirk to function (encoder must run 4285 briefly first, at least once, before onair 4286 digital streaming can work). */ 4287 return !0; 4288 } 4289 break; 4290 default: 4291 /* Unknown mode; so encoder should be stopped. */ 4292 return !0; 4293 } 4294 4295 /* If we get here, we haven't found a reason to stop the 4296 encoder. */ 4297 return 0; 4298 } 4299 4300 4301 /* Return true if the encoder should be running. */ 4302 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw) 4303 { 4304 if (!hdw->state_encoder_ok) { 4305 /* Don't run the encoder if it isn't healthy... */ 4306 return 0; 4307 } 4308 if (!hdw->state_pathway_ok) { 4309 /* Don't run the encoder if we don't (yet) know what mode 4310 we need to be in... */ 4311 return 0; 4312 } 4313 4314 switch (hdw->pathway_state) { 4315 case PVR2_PATHWAY_ANALOG: 4316 if (hdw->state_decoder_run && hdw->state_decoder_ready) { 4317 /* In analog mode, if the decoder is running, then 4318 run the encoder. */ 4319 return !0; 4320 } 4321 break; 4322 case PVR2_PATHWAY_DIGITAL: 4323 if ((hdw->hdw_desc->digital_control_scheme == 4324 PVR2_DIGITAL_SCHEME_ONAIR) && 4325 !hdw->state_encoder_runok) { 4326 /* This is a quirk. OnAir hardware won't stream 4327 digital until the encoder has been run at least 4328 once, for a minimal period of time (empiricially 4329 measured to be 1/4 second). So if we're on 4330 OnAir hardware and the encoder has never been 4331 run at all, then start the encoder. Normal 4332 state machine logic in the driver will 4333 automatically handle the remaining bits. */ 4334 return !0; 4335 } 4336 break; 4337 default: 4338 /* For completeness (unknown mode; encoder won't run ever) */ 4339 break; 4340 } 4341 /* If we get here, then we haven't found any reason to run the 4342 encoder, so don't run it. */ 4343 return 0; 4344 } 4345 4346 4347 /* Evaluate whether or not state_encoder_run can change */ 4348 static int state_eval_encoder_run(struct pvr2_hdw *hdw) 4349 { 4350 if (hdw->state_encoder_run) { 4351 if (!state_check_disable_encoder_run(hdw)) return 0; 4352 if (hdw->state_encoder_ok) { 4353 del_timer_sync(&hdw->encoder_run_timer); 4354 if (pvr2_encoder_stop(hdw) < 0) return !0; 4355 } 4356 hdw->state_encoder_run = 0; 4357 } else { 4358 if (!state_check_enable_encoder_run(hdw)) return 0; 4359 if (pvr2_encoder_start(hdw) < 0) return !0; 4360 hdw->state_encoder_run = !0; 4361 if (!hdw->state_encoder_runok) { 4362 hdw->encoder_run_timer.expires = jiffies + 4363 msecs_to_jiffies(TIME_MSEC_ENCODER_OK); 4364 add_timer(&hdw->encoder_run_timer); 4365 } 4366 } 4367 trace_stbit("state_encoder_run",hdw->state_encoder_run); 4368 return !0; 4369 } 4370 4371 4372 /* Timeout function for quiescent timer. */ 4373 static void pvr2_hdw_quiescent_timeout(unsigned long data) 4374 { 4375 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data; 4376 hdw->state_decoder_quiescent = !0; 4377 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent); 4378 hdw->state_stale = !0; 4379 schedule_work(&hdw->workpoll); 4380 } 4381 4382 4383 /* Timeout function for decoder stabilization timer. */ 4384 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data) 4385 { 4386 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data; 4387 hdw->state_decoder_ready = !0; 4388 trace_stbit("state_decoder_ready", hdw->state_decoder_ready); 4389 hdw->state_stale = !0; 4390 schedule_work(&hdw->workpoll); 4391 } 4392 4393 4394 /* Timeout function for encoder wait timer. */ 4395 static void pvr2_hdw_encoder_wait_timeout(unsigned long data) 4396 { 4397 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data; 4398 hdw->state_encoder_waitok = !0; 4399 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok); 4400 hdw->state_stale = !0; 4401 schedule_work(&hdw->workpoll); 4402 } 4403 4404 4405 /* Timeout function for encoder run timer. */ 4406 static void pvr2_hdw_encoder_run_timeout(unsigned long data) 4407 { 4408 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data; 4409 if (!hdw->state_encoder_runok) { 4410 hdw->state_encoder_runok = !0; 4411 trace_stbit("state_encoder_runok",hdw->state_encoder_runok); 4412 hdw->state_stale = !0; 4413 schedule_work(&hdw->workpoll); 4414 } 4415 } 4416 4417 4418 /* Evaluate whether or not state_decoder_run can change */ 4419 static int state_eval_decoder_run(struct pvr2_hdw *hdw) 4420 { 4421 if (hdw->state_decoder_run) { 4422 if (hdw->state_encoder_ok) { 4423 if (hdw->state_pipeline_req && 4424 !hdw->state_pipeline_pause && 4425 hdw->state_pathway_ok) return 0; 4426 } 4427 if (!hdw->flag_decoder_missed) { 4428 pvr2_decoder_enable(hdw,0); 4429 } 4430 hdw->state_decoder_quiescent = 0; 4431 hdw->state_decoder_run = 0; 4432 /* paranoia - solve race if timer(s) just completed */ 4433 del_timer_sync(&hdw->quiescent_timer); 4434 /* Kill the stabilization timer, in case we're killing the 4435 encoder before the previous stabilization interval has 4436 been properly timed. */ 4437 del_timer_sync(&hdw->decoder_stabilization_timer); 4438 hdw->state_decoder_ready = 0; 4439 } else { 4440 if (!hdw->state_decoder_quiescent) { 4441 if (!timer_pending(&hdw->quiescent_timer)) { 4442 /* We don't do something about the 4443 quiescent timer until right here because 4444 we also want to catch cases where the 4445 decoder was already not running (like 4446 after initialization) as opposed to 4447 knowing that we had just stopped it. 4448 The second flag check is here to cover a 4449 race - the timer could have run and set 4450 this flag just after the previous check 4451 but before we did the pending check. */ 4452 if (!hdw->state_decoder_quiescent) { 4453 hdw->quiescent_timer.expires = 4454 jiffies + msecs_to_jiffies( 4455 TIME_MSEC_DECODER_WAIT); 4456 add_timer(&hdw->quiescent_timer); 4457 } 4458 } 4459 /* Don't allow decoder to start again until it has 4460 been quiesced first. This little detail should 4461 hopefully further stabilize the encoder. */ 4462 return 0; 4463 } 4464 if (!hdw->state_pathway_ok || 4465 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) || 4466 !hdw->state_pipeline_req || 4467 hdw->state_pipeline_pause || 4468 !hdw->state_pipeline_config || 4469 !hdw->state_encoder_config || 4470 !hdw->state_encoder_ok) return 0; 4471 del_timer_sync(&hdw->quiescent_timer); 4472 if (hdw->flag_decoder_missed) return 0; 4473 if (pvr2_decoder_enable(hdw,!0) < 0) return 0; 4474 hdw->state_decoder_quiescent = 0; 4475 hdw->state_decoder_ready = 0; 4476 hdw->state_decoder_run = !0; 4477 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) { 4478 hdw->decoder_stabilization_timer.expires = 4479 jiffies + msecs_to_jiffies( 4480 TIME_MSEC_DECODER_STABILIZATION_WAIT); 4481 add_timer(&hdw->decoder_stabilization_timer); 4482 } else { 4483 hdw->state_decoder_ready = !0; 4484 } 4485 } 4486 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent); 4487 trace_stbit("state_decoder_run",hdw->state_decoder_run); 4488 trace_stbit("state_decoder_ready", hdw->state_decoder_ready); 4489 return !0; 4490 } 4491 4492 4493 /* Evaluate whether or not state_usbstream_run can change */ 4494 static int state_eval_usbstream_run(struct pvr2_hdw *hdw) 4495 { 4496 if (hdw->state_usbstream_run) { 4497 int fl = !0; 4498 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) { 4499 fl = (hdw->state_encoder_ok && 4500 hdw->state_encoder_run); 4501 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) && 4502 (hdw->hdw_desc->flag_digital_requires_cx23416)) { 4503 fl = hdw->state_encoder_ok; 4504 } 4505 if (fl && 4506 hdw->state_pipeline_req && 4507 !hdw->state_pipeline_pause && 4508 hdw->state_pathway_ok) { 4509 return 0; 4510 } 4511 pvr2_hdw_cmd_usbstream(hdw,0); 4512 hdw->state_usbstream_run = 0; 4513 } else { 4514 if (!hdw->state_pipeline_req || 4515 hdw->state_pipeline_pause || 4516 !hdw->state_pathway_ok) return 0; 4517 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) { 4518 if (!hdw->state_encoder_ok || 4519 !hdw->state_encoder_run) return 0; 4520 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) && 4521 (hdw->hdw_desc->flag_digital_requires_cx23416)) { 4522 if (!hdw->state_encoder_ok) return 0; 4523 if (hdw->state_encoder_run) return 0; 4524 if (hdw->hdw_desc->digital_control_scheme == 4525 PVR2_DIGITAL_SCHEME_ONAIR) { 4526 /* OnAir digital receivers won't stream 4527 unless the analog encoder has run first. 4528 Why? I have no idea. But don't even 4529 try until we know the analog side is 4530 known to have run. */ 4531 if (!hdw->state_encoder_runok) return 0; 4532 } 4533 } 4534 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0; 4535 hdw->state_usbstream_run = !0; 4536 } 4537 trace_stbit("state_usbstream_run",hdw->state_usbstream_run); 4538 return !0; 4539 } 4540 4541 4542 /* Attempt to configure pipeline, if needed */ 4543 static int state_eval_pipeline_config(struct pvr2_hdw *hdw) 4544 { 4545 if (hdw->state_pipeline_config || 4546 hdw->state_pipeline_pause) return 0; 4547 pvr2_hdw_commit_execute(hdw); 4548 return !0; 4549 } 4550 4551 4552 /* Update pipeline idle and pipeline pause tracking states based on other 4553 inputs. This must be called whenever the other relevant inputs have 4554 changed. */ 4555 static int state_update_pipeline_state(struct pvr2_hdw *hdw) 4556 { 4557 unsigned int st; 4558 int updatedFl = 0; 4559 /* Update pipeline state */ 4560 st = !(hdw->state_encoder_run || 4561 hdw->state_decoder_run || 4562 hdw->state_usbstream_run || 4563 (!hdw->state_decoder_quiescent)); 4564 if (!st != !hdw->state_pipeline_idle) { 4565 hdw->state_pipeline_idle = st; 4566 updatedFl = !0; 4567 } 4568 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) { 4569 hdw->state_pipeline_pause = 0; 4570 updatedFl = !0; 4571 } 4572 return updatedFl; 4573 } 4574 4575 4576 typedef int (*state_eval_func)(struct pvr2_hdw *); 4577 4578 /* Set of functions to be run to evaluate various states in the driver. */ 4579 static const state_eval_func eval_funcs[] = { 4580 state_eval_pathway_ok, 4581 state_eval_pipeline_config, 4582 state_eval_encoder_ok, 4583 state_eval_encoder_config, 4584 state_eval_decoder_run, 4585 state_eval_encoder_run, 4586 state_eval_usbstream_run, 4587 }; 4588 4589 4590 /* Process various states and return true if we did anything interesting. */ 4591 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw) 4592 { 4593 unsigned int i; 4594 int state_updated = 0; 4595 int check_flag; 4596 4597 if (!hdw->state_stale) return 0; 4598 if ((hdw->fw1_state != FW1_STATE_OK) || 4599 !hdw->flag_ok) { 4600 hdw->state_stale = 0; 4601 return !0; 4602 } 4603 /* This loop is the heart of the entire driver. It keeps trying to 4604 evaluate various bits of driver state until nothing changes for 4605 one full iteration. Each "bit of state" tracks some global 4606 aspect of the driver, e.g. whether decoder should run, if 4607 pipeline is configured, usb streaming is on, etc. We separately 4608 evaluate each of those questions based on other driver state to 4609 arrive at the correct running configuration. */ 4610 do { 4611 check_flag = 0; 4612 state_update_pipeline_state(hdw); 4613 /* Iterate over each bit of state */ 4614 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) { 4615 if ((*eval_funcs[i])(hdw)) { 4616 check_flag = !0; 4617 state_updated = !0; 4618 state_update_pipeline_state(hdw); 4619 } 4620 } 4621 } while (check_flag && hdw->flag_ok); 4622 hdw->state_stale = 0; 4623 trace_stbit("state_stale",hdw->state_stale); 4624 return state_updated; 4625 } 4626 4627 4628 static unsigned int print_input_mask(unsigned int msk, 4629 char *buf,unsigned int acnt) 4630 { 4631 unsigned int idx,ccnt; 4632 unsigned int tcnt = 0; 4633 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) { 4634 if (!((1 << idx) & msk)) continue; 4635 ccnt = scnprintf(buf+tcnt, 4636 acnt-tcnt, 4637 "%s%s", 4638 (tcnt ? ", " : ""), 4639 control_values_input[idx]); 4640 tcnt += ccnt; 4641 } 4642 return tcnt; 4643 } 4644 4645 4646 static const char *pvr2_pathway_state_name(int id) 4647 { 4648 switch (id) { 4649 case PVR2_PATHWAY_ANALOG: return "analog"; 4650 case PVR2_PATHWAY_DIGITAL: return "digital"; 4651 default: return "unknown"; 4652 } 4653 } 4654 4655 4656 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which, 4657 char *buf,unsigned int acnt) 4658 { 4659 switch (which) { 4660 case 0: 4661 return scnprintf( 4662 buf,acnt, 4663 "driver:%s%s%s%s%s <mode=%s>", 4664 (hdw->flag_ok ? " <ok>" : " <fail>"), 4665 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"), 4666 (hdw->flag_disconnected ? " <disconnected>" : 4667 " <connected>"), 4668 (hdw->flag_tripped ? " <tripped>" : ""), 4669 (hdw->flag_decoder_missed ? " <no decoder>" : ""), 4670 pvr2_pathway_state_name(hdw->pathway_state)); 4671 4672 case 1: 4673 return scnprintf( 4674 buf,acnt, 4675 "pipeline:%s%s%s%s", 4676 (hdw->state_pipeline_idle ? " <idle>" : ""), 4677 (hdw->state_pipeline_config ? 4678 " <configok>" : " <stale>"), 4679 (hdw->state_pipeline_req ? " <req>" : ""), 4680 (hdw->state_pipeline_pause ? " <pause>" : "")); 4681 case 2: 4682 return scnprintf( 4683 buf,acnt, 4684 "worker:%s%s%s%s%s%s%s", 4685 (hdw->state_decoder_run ? 4686 (hdw->state_decoder_ready ? 4687 "<decode:run>" : " <decode:start>") : 4688 (hdw->state_decoder_quiescent ? 4689 "" : " <decode:stop>")), 4690 (hdw->state_decoder_quiescent ? 4691 " <decode:quiescent>" : ""), 4692 (hdw->state_encoder_ok ? 4693 "" : " <encode:init>"), 4694 (hdw->state_encoder_run ? 4695 (hdw->state_encoder_runok ? 4696 " <encode:run>" : 4697 " <encode:firstrun>") : 4698 (hdw->state_encoder_runok ? 4699 " <encode:stop>" : 4700 " <encode:virgin>")), 4701 (hdw->state_encoder_config ? 4702 " <encode:configok>" : 4703 (hdw->state_encoder_waitok ? 4704 "" : " <encode:waitok>")), 4705 (hdw->state_usbstream_run ? 4706 " <usb:run>" : " <usb:stop>"), 4707 (hdw->state_pathway_ok ? 4708 " <pathway:ok>" : "")); 4709 case 3: 4710 return scnprintf( 4711 buf,acnt, 4712 "state: %s", 4713 pvr2_get_state_name(hdw->master_state)); 4714 case 4: { 4715 unsigned int tcnt = 0; 4716 unsigned int ccnt; 4717 4718 ccnt = scnprintf(buf, 4719 acnt, 4720 "Hardware supported inputs: "); 4721 tcnt += ccnt; 4722 tcnt += print_input_mask(hdw->input_avail_mask, 4723 buf+tcnt, 4724 acnt-tcnt); 4725 if (hdw->input_avail_mask != hdw->input_allowed_mask) { 4726 ccnt = scnprintf(buf+tcnt, 4727 acnt-tcnt, 4728 "; allowed inputs: "); 4729 tcnt += ccnt; 4730 tcnt += print_input_mask(hdw->input_allowed_mask, 4731 buf+tcnt, 4732 acnt-tcnt); 4733 } 4734 return tcnt; 4735 } 4736 case 5: { 4737 struct pvr2_stream_stats stats; 4738 if (!hdw->vid_stream) break; 4739 pvr2_stream_get_stats(hdw->vid_stream, 4740 &stats, 4741 0); 4742 return scnprintf( 4743 buf,acnt, 4744 "Bytes streamed=%u URBs: queued=%u idle=%u ready=%u processed=%u failed=%u", 4745 stats.bytes_processed, 4746 stats.buffers_in_queue, 4747 stats.buffers_in_idle, 4748 stats.buffers_in_ready, 4749 stats.buffers_processed, 4750 stats.buffers_failed); 4751 } 4752 case 6: { 4753 unsigned int id = hdw->ir_scheme_active; 4754 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id, 4755 (id >= ARRAY_SIZE(ir_scheme_names) ? 4756 "?" : ir_scheme_names[id])); 4757 } 4758 default: break; 4759 } 4760 return 0; 4761 } 4762 4763 4764 /* Generate report containing info about attached sub-devices and attached 4765 i2c clients, including an indication of which attached i2c clients are 4766 actually sub-devices. */ 4767 static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw, 4768 char *buf, unsigned int acnt) 4769 { 4770 struct v4l2_subdev *sd; 4771 unsigned int tcnt = 0; 4772 unsigned int ccnt; 4773 struct i2c_client *client; 4774 const char *p; 4775 unsigned int id; 4776 4777 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n"); 4778 tcnt += ccnt; 4779 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) { 4780 id = sd->grp_id; 4781 p = NULL; 4782 if (id < ARRAY_SIZE(module_names)) p = module_names[id]; 4783 if (p) { 4784 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p); 4785 tcnt += ccnt; 4786 } else { 4787 ccnt = scnprintf(buf + tcnt, acnt - tcnt, 4788 " (unknown id=%u):", id); 4789 tcnt += ccnt; 4790 } 4791 client = v4l2_get_subdevdata(sd); 4792 if (client) { 4793 ccnt = scnprintf(buf + tcnt, acnt - tcnt, 4794 " %s @ %02x\n", client->name, 4795 client->addr); 4796 tcnt += ccnt; 4797 } else { 4798 ccnt = scnprintf(buf + tcnt, acnt - tcnt, 4799 " no i2c client\n"); 4800 tcnt += ccnt; 4801 } 4802 } 4803 return tcnt; 4804 } 4805 4806 4807 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw, 4808 char *buf,unsigned int acnt) 4809 { 4810 unsigned int bcnt,ccnt,idx; 4811 bcnt = 0; 4812 LOCK_TAKE(hdw->big_lock); 4813 for (idx = 0; ; idx++) { 4814 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt); 4815 if (!ccnt) break; 4816 bcnt += ccnt; acnt -= ccnt; buf += ccnt; 4817 if (!acnt) break; 4818 buf[0] = '\n'; ccnt = 1; 4819 bcnt += ccnt; acnt -= ccnt; buf += ccnt; 4820 } 4821 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt); 4822 bcnt += ccnt; acnt -= ccnt; buf += ccnt; 4823 LOCK_GIVE(hdw->big_lock); 4824 return bcnt; 4825 } 4826 4827 4828 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw) 4829 { 4830 char buf[256]; 4831 unsigned int idx, ccnt; 4832 unsigned int lcnt, ucnt; 4833 4834 for (idx = 0; ; idx++) { 4835 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf)); 4836 if (!ccnt) break; 4837 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf); 4838 } 4839 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf)); 4840 if (ccnt >= sizeof(buf)) 4841 ccnt = sizeof(buf); 4842 4843 ucnt = 0; 4844 while (ucnt < ccnt) { 4845 lcnt = 0; 4846 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) { 4847 lcnt++; 4848 } 4849 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt); 4850 ucnt += lcnt + 1; 4851 } 4852 } 4853 4854 4855 /* Evaluate and update the driver's current state, taking various actions 4856 as appropriate for the update. */ 4857 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw) 4858 { 4859 unsigned int st; 4860 int state_updated = 0; 4861 int callback_flag = 0; 4862 int analog_mode; 4863 4864 pvr2_trace(PVR2_TRACE_STBITS, 4865 "Drive state check START"); 4866 if (pvrusb2_debug & PVR2_TRACE_STBITS) { 4867 pvr2_hdw_state_log_state(hdw); 4868 } 4869 4870 /* Process all state and get back over disposition */ 4871 state_updated = pvr2_hdw_state_update(hdw); 4872 4873 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL); 4874 4875 /* Update master state based upon all other states. */ 4876 if (!hdw->flag_ok) { 4877 st = PVR2_STATE_DEAD; 4878 } else if (hdw->fw1_state != FW1_STATE_OK) { 4879 st = PVR2_STATE_COLD; 4880 } else if ((analog_mode || 4881 hdw->hdw_desc->flag_digital_requires_cx23416) && 4882 !hdw->state_encoder_ok) { 4883 st = PVR2_STATE_WARM; 4884 } else if (hdw->flag_tripped || 4885 (analog_mode && hdw->flag_decoder_missed)) { 4886 st = PVR2_STATE_ERROR; 4887 } else if (hdw->state_usbstream_run && 4888 (!analog_mode || 4889 (hdw->state_encoder_run && hdw->state_decoder_run))) { 4890 st = PVR2_STATE_RUN; 4891 } else { 4892 st = PVR2_STATE_READY; 4893 } 4894 if (hdw->master_state != st) { 4895 pvr2_trace(PVR2_TRACE_STATE, 4896 "Device state change from %s to %s", 4897 pvr2_get_state_name(hdw->master_state), 4898 pvr2_get_state_name(st)); 4899 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN); 4900 hdw->master_state = st; 4901 state_updated = !0; 4902 callback_flag = !0; 4903 } 4904 if (state_updated) { 4905 /* Trigger anyone waiting on any state changes here. */ 4906 wake_up(&hdw->state_wait_data); 4907 } 4908 4909 if (pvrusb2_debug & PVR2_TRACE_STBITS) { 4910 pvr2_hdw_state_log_state(hdw); 4911 } 4912 pvr2_trace(PVR2_TRACE_STBITS, 4913 "Drive state check DONE callback=%d",callback_flag); 4914 4915 return callback_flag; 4916 } 4917 4918 4919 /* Cause kernel thread to check / update driver state */ 4920 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw) 4921 { 4922 if (hdw->state_stale) return; 4923 hdw->state_stale = !0; 4924 trace_stbit("state_stale",hdw->state_stale); 4925 schedule_work(&hdw->workpoll); 4926 } 4927 4928 4929 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp) 4930 { 4931 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp); 4932 } 4933 4934 4935 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp) 4936 { 4937 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp); 4938 } 4939 4940 4941 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp) 4942 { 4943 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp); 4944 } 4945 4946 4947 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val) 4948 { 4949 u32 cval,nval; 4950 int ret; 4951 if (~msk) { 4952 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval); 4953 if (ret) return ret; 4954 nval = (cval & ~msk) | (val & msk); 4955 pvr2_trace(PVR2_TRACE_GPIO, 4956 "GPIO direction changing 0x%x:0x%x from 0x%x to 0x%x", 4957 msk,val,cval,nval); 4958 } else { 4959 nval = val; 4960 pvr2_trace(PVR2_TRACE_GPIO, 4961 "GPIO direction changing to 0x%x",nval); 4962 } 4963 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval); 4964 } 4965 4966 4967 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val) 4968 { 4969 u32 cval,nval; 4970 int ret; 4971 if (~msk) { 4972 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval); 4973 if (ret) return ret; 4974 nval = (cval & ~msk) | (val & msk); 4975 pvr2_trace(PVR2_TRACE_GPIO, 4976 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x", 4977 msk,val,cval,nval); 4978 } else { 4979 nval = val; 4980 pvr2_trace(PVR2_TRACE_GPIO, 4981 "GPIO output changing to 0x%x",nval); 4982 } 4983 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval); 4984 } 4985 4986 4987 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw) 4988 { 4989 struct v4l2_tuner *vtp = &hdw->tuner_signal_info; 4990 memset(vtp, 0, sizeof(*vtp)); 4991 vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ? 4992 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV; 4993 hdw->tuner_signal_stale = 0; 4994 /* Note: There apparently is no replacement for VIDIOC_CROPCAP 4995 using v4l2-subdev - therefore we can't support that AT ALL right 4996 now. (Of course, no sub-drivers seem to implement it either. 4997 But now it's a a chicken and egg problem...) */ 4998 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp); 4999 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll type=%u strength=%u audio=0x%x cap=0x%x low=%u hi=%u", 5000 vtp->type, 5001 vtp->signal, vtp->rxsubchans, vtp->capability, 5002 vtp->rangelow, vtp->rangehigh); 5003 5004 /* We have to do this to avoid getting into constant polling if 5005 there's nobody to answer a poll of cropcap info. */ 5006 hdw->cropcap_stale = 0; 5007 } 5008 5009 5010 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw) 5011 { 5012 return hdw->input_avail_mask; 5013 } 5014 5015 5016 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw) 5017 { 5018 return hdw->input_allowed_mask; 5019 } 5020 5021 5022 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v) 5023 { 5024 if (hdw->input_val != v) { 5025 hdw->input_val = v; 5026 hdw->input_dirty = !0; 5027 } 5028 5029 /* Handle side effects - if we switch to a mode that needs the RF 5030 tuner, then select the right frequency choice as well and mark 5031 it dirty. */ 5032 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) { 5033 hdw->freqSelector = 0; 5034 hdw->freqDirty = !0; 5035 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) || 5036 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) { 5037 hdw->freqSelector = 1; 5038 hdw->freqDirty = !0; 5039 } 5040 return 0; 5041 } 5042 5043 5044 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw, 5045 unsigned int change_mask, 5046 unsigned int change_val) 5047 { 5048 int ret = 0; 5049 unsigned int nv,m,idx; 5050 LOCK_TAKE(hdw->big_lock); 5051 do { 5052 nv = hdw->input_allowed_mask & ~change_mask; 5053 nv |= (change_val & change_mask); 5054 nv &= hdw->input_avail_mask; 5055 if (!nv) { 5056 /* No legal modes left; return error instead. */ 5057 ret = -EPERM; 5058 break; 5059 } 5060 hdw->input_allowed_mask = nv; 5061 if ((1 << hdw->input_val) & hdw->input_allowed_mask) { 5062 /* Current mode is still in the allowed mask, so 5063 we're done. */ 5064 break; 5065 } 5066 /* Select and switch to a mode that is still in the allowed 5067 mask */ 5068 if (!hdw->input_allowed_mask) { 5069 /* Nothing legal; give up */ 5070 break; 5071 } 5072 m = hdw->input_allowed_mask; 5073 for (idx = 0; idx < (sizeof(m) << 3); idx++) { 5074 if (!((1 << idx) & m)) continue; 5075 pvr2_hdw_set_input(hdw,idx); 5076 break; 5077 } 5078 } while (0); 5079 LOCK_GIVE(hdw->big_lock); 5080 return ret; 5081 } 5082 5083 5084 /* Find I2C address of eeprom */ 5085 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw) 5086 { 5087 int result; 5088 LOCK_TAKE(hdw->ctl_lock); do { 5089 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR; 5090 result = pvr2_send_request(hdw, 5091 hdw->cmd_buffer,1, 5092 hdw->cmd_buffer,1); 5093 if (result < 0) break; 5094 result = hdw->cmd_buffer[0]; 5095 } while(0); LOCK_GIVE(hdw->ctl_lock); 5096 return result; 5097 } 5098